STA Timing Report

[vijayank88]

@jjcherry56 @maliberty
One of fpga design has custom SDC constraints.

set_input_delay 0.0  -clock [get_clocks config_clk_i] [get_ports config_shift_i]

In the final STA report

Startpoint: config_shift_i (input port clocked by config_clk_i)
Endpoint: _3723_ (rising edge-triggered flip-flop clocked by config_clk_i)
Path Group: config_clk_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock config_clk_i (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          0.00    0.00 ^ input external delay
                  0.04    0.02    0.02 ^ config_shift_i (in)
     1    0.00                           config_shift_i (net)
                  0.04    0.00    0.02 ^ hold2/A (sky130_fd_sc_hd__dlygate4sd3_1)
                  0.05    0.49    0.51 ^ hold2/X (sky130_fd_sc_hd__dlygate4sd3_1)
     1    0.00                           net11 (net)
                  0.05    0.00    0.51 ^ hold1/A (sky130_fd_sc_hd__dlygate4sd3_1)
                  0.05    0.50    1.01 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
     1    0.00                           net10 (net)
                  0.05    0.00    1.01 ^ _3723_/D (sky130_fd_sc_hd__dfxtp_1)
                                  1.01   data arrival time

                          0.00    0.00   clock config_clk_i (rise edge)
                          0.00    0.00   clock source latency
                  0.47    0.34    0.34 ^ config_clk_i (in)
     1    0.04                           config_clk_i (net)
                  0.47    0.00    0.34 ^ clkbuf_0_config_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
                  0.09    0.29    0.63 ^ clkbuf_0_config_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.07                           clknet_0_config_clk_i (net)
                  0.09    0.00    0.63 ^ clkbuf_2_1__f_config_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
                  0.11    0.21    0.84 ^ clkbuf_2_1__f_config_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
     7    0.09                           clknet_2_1__leaf_config_clk_i (net)
                  0.11    0.00    0.85 ^ clkbuf_leaf_6_config_clk_i/A (sky130_fd_sc_hd__clkbuf_16)
                  0.08    0.19    1.04 ^ clkbuf_leaf_6_config_clk_i/X (sky130_fd_sc_hd__clkbuf_16)
    21    0.06                           clknet_leaf_6_config_clk_i (net)
                  0.08    0.00    1.04 ^ _3723_/CLK (sky130_fd_sc_hd__dfxtp_1)
                          0.00    1.04   clock reconvergence pessimism
                         -0.03    1.01   library hold time
                                  1.01   data required time
-----------------------------------------------------------------------------
                                  1.01   data required time
                                 -1.01   data arrival time
-----------------------------------------------------------------------------
                                  0.00   slack (VIOLATED)

Due to this flow fails with below error in OpenLane:

[ERROR]: There are hold violations in the design at the typical corner. Please refer to 'reports/signoff/25-rcx_sta.min.rpt'.

Is that must value > 0.00 required to print slack MET?

[maliberty]

My guess is that it is something like -0.001 which when rounded to two digits for display appears as zero but is in fact negative. Try -digits 10 to see.

[vijayank88]

yes. Its negative value only.

-------------------------------------------------------------------------------------------------------------
                                                          1.0099427700   data required time
                                                         -1.0052579641   data arrival time
-------------------------------------------------------------------------------------------------------------
                                                         -0.0046848082   slack (VIOLATED)