Global routing issue with IO pads on horizontal sides

[LucaMartis00]

I encountered an issue during the global routing phase when using IO pads placed on the horizontal sides (top and bottom) of the chip.

Pads on the vertical sides (left and right) do not cause any problems, but when IO pads are placed on the horizontal edges, the global router seems to fail or produce invalid results.

[maliberty]

Can you provide a test case? Are the power rings blocking the pins?

[LucaMartis00]

Yes, apparently, the power ring is obstructing the horizontal pin.
Here is the script used to place the pad and generate the power distribution network (PDN)

make_io_sites -horizontal_site sg13g2_ioSite \
    -vertical_site sg13g2_ioSite \
    -corner_site sg13g2_ioSite \
    -offset 0 \
    -rotation_horizontal R0 \
    -rotation_vertical R0 \
    -rotation_corner R0

set padD    180; # pad depth (edge to core)
set padW     80; # pad width (beachfront)

set chipH  2090; # left/right (height)
set chipW  2145; # top/bottom (width)


set offset 215;
set width 80;
set space_between_pad 10;


place_pad -row IO_NORTH   -location [expr $offset + 0*($width + $space_between_pad)]                     "pad_vssio0"; # pin no:  1
place_pad -row IO_NORTH   -location [expr $offset  + 1*($width + $space_between_pad)]                    "pad_vddio0"; # pin no:  2
place_pad -row IO_NORTH   -location [expr $chipH - $offset - $width - 0*($width + $space_between_pad)]   "pad_vss0"; # pin no: 15
place_pad -row IO_NORTH   -location [expr $chipH - $offset - $width - 1*($width + $space_between_pad)]   "pad_vdd0"; # pin no: 16
place_pad -row IO_SOUTH  -location [expr $offset  + 0*($width + $space_between_pad)]                    "pad_vssio1"       ; # pin no:  1
place_pad -row IO_SOUTH  -location [expr $offset  + 1*($width + $space_between_pad)]                    "pad_vddio1"       ; # pin no:  2
place_pad -row IO_SOUTH  -location [expr $chipH - $offset - $width - 0*($width + $space_between_pad)]   "pad_vss1"; # pin no: 15
place_pad -row IO_SOUTH  -location [expr $chipH - $offset - $width - 1*($width + $space_between_pad)]   "pad_vdd1"; # pin no: 16



place_pad -row IO_EAST  -location [expr $offset  + 2*($width + $space_between_pad)]                  "pad_i_flash_miso" ; 
place_pad -row IO_EAST  -location [expr $offset  + 3*($width + $space_between_pad)]                  "pad_o_flash_ss" ; 
place_pad -row IO_EAST   -location [expr $offset  + 4*($width + $space_between_pad)]                  "pad_o_flash_sck" ; 
place_pad -row IO_EAST  -location [expr $offset  + 5*($width + $space_between_pad)]                  "pad_o_flash_mosi" ;
place_pad -row IO_EAST  -location [expr $offset  + 6*($width + $space_between_pad)]                  "pad_wb_clk" ; 
place_pad -row IO_EAST  -location [expr $offset  + 7*($width + $space_between_pad)]                  "pad_wb_rst" ;
place_pad -row IO_EAST  -location [expr $offset  + 8*($width + $space_between_pad)]                  "pad_timer_clk" ; 
place_pad -row IO_EAST  -location [expr $offset  + 9*($width + $space_between_pad)]                  "pad_o_txd" ; 

place_pad -row IO_SOUTH  -location [expr $offset  + 9*($width + $space_between_pad)]                  "pad_enb_debug" ; 
place_pad -row IO_SOUTH  -location [expr $offset  + 10*($width + $space_between_pad)]                  "pad_output_buffer_wr_en_debug" ;
place_pad -row IO_SOUTH  -location [expr $offset  + 11*($width + $space_between_pad)]                 "pad_buttons_0" ; 
place_pad -row IO_SOUTH  -location [expr $offset  + 12*($width + $space_between_pad)]                 "pad_buttons_1" ; 
place_pad -row IO_SOUTH  -location [expr $offset  + 13*($width + $space_between_pad)]                 "pad_buttons_2" ; 




set iocorner sg13g2_Corner
set iofill [ list sg13g2_Filler10000 sg13g2_Filler4000 sg13g2_Filler2000 sg13g2_Filler1000 sg13g2_Filler400 sg13g2_Filler200 ]

place_corners $iocorner

place_io_fill -row IO_NORTH {*}$iofill
place_io_fill -row IO_SOUTH {*}$iofill
place_io_fill -row IO_WEST  {*}$iofill
place_io_fill -row IO_EAST  {*}$iofill

connect_by_abutment
#place_bondpad -bond bondpad_70x70 -offset {5.0 -70.0} pad_*
place_io_terminals pad_*/pad
remove_io_rows




################################################################      POWER DISTRIBUTION NETWORK                           #####################################################
####################################
# global connections
####################################
# standard cells
add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -pin_pattern {^VSSE$}
# I/O pads
add_global_connection -net {VDD} -pin_pattern {^vdd$} -power
add_global_connection -net {VSS} -pin_pattern {^vss$} -ground
global_connect
# rams
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDDARRAY} -power
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDDARRAY!} -power
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {VDD!} -power
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {VSS!} -ground

####################################
# voltage domains
####################################
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}

##########################################################################
##  Power settings
##########################################################################
# Core Power Ring
## Space between pads and core -> used for power ring
set PowRingSpace  35
## Spacing must meet TM2 rules
set pgcrSpacing 6
## Width must meet TM2 rules
set pgcrWidth 10
## Offset from core to power ring
set pgcrOffset [expr ($PowRingSpace - $pgcrSpacing - 2 * $pgcrWidth) / 2]

# TopMetal2 Core Power Grid
set tpg2Width     6; # arbitrary number
set tpg2Pitch   204; # multiple of pad-pitch
set tpg2Spacing  60; # big enough to skip over a pad
set tpg2Offset   97; # offset from leftX of core

# Macro Power Rings -> M3 and M2
## Spacing must be larger than pitch of M2/M3
set mprSpacing 0.6
## Width
set mprWidth 2
## Offset from Macro to power ring
set mprOffsetX 2.4
set mprOffsetY 0.6

# macro power grid (stripes on TopMetal1/TopMetal2 depending on orientation)
set mpgWidth 6
set mpgSpacing 4
set mpgOffset 20; # arbitrary

##########################################################################
##  SRAM power rings
##########################################################################
proc sram_power { name macro } {
    global mprWidth mprSpacing mprOffsetX mprOffsetY mpgWidth mpgSpacing mpgOffset
    # Macro Grid and Rings
    define_pdn_grid -macro -cells $macro -name ${name}_grid -orient "R0 R180 MY MX" \
        -grid_over_boundary -voltage_domains {CORE} \
        -halo {1 1}

    add_pdn_ring -grid ${name}_grid \
        -layer        {Metal3 Metal4} \
        -widths       "$mprWidth $mprWidth" \
        -spacings     "$mprSpacing $mprSpacing" \
        -core_offsets "$mprOffsetX $mprOffsetY" \
        -add_connect

    set sram  [[ord::get_db] findMaster $macro]
    set sramHeight  [ord::dbu_to_microns [$sram getHeight]]
    set stripe_dist [expr $sramHeight - 2*$mpgOffset - $mpgWidth - $mpgSpacing]
    utl::report "stripe_dist of $macro: $stripe_dist"

    # for the large macros there is enough space for an additional stripe
    if {$stripe_dist > 100} {
        set stripe_dist [expr $stripe_dist/2]
    }

    add_pdn_stripe -grid ${name}_grid -layer {TopMetal1} -width $mpgWidth -spacing $mpgSpacing \
                   -pitch $stripe_dist -offset $mpgOffset -extend_to_core_ring -starts_with POWER -snap_to_grid

    # Connection of Macro Power Ring to standard-cell rails
    add_pdn_connect -grid ${name}_grid -layers {Metal3 Metal1}
    # Connection of Stripes on Macro to Macro Power Ring
    add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal3}
    add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal4}
    # Connection of Stripes on Macro to Macro Power Pins
    # add_pdn_connect -grid ${name}_grid -layers {TopMetal1 Metal4}
    # Connection of Stripes on Macro to Core Power Stripes
    add_pdn_connect -grid ${name}_grid -layers {TopMetal2 TopMetal1}
}


##########################################################################
##  Core Power
##########################################################################
# Top 1 - Top 2
define_pdn_grid -name {core_grid} -voltage_domains {CORE}

add_pdn_ring -grid {core_grid} \
   -layer        {TopMetal1 TopMetal2} \
   -widths       "$pgcrWidth $pgcrWidth" \
   -spacings     "$pgcrSpacing $pgcrSpacing" \
   -pad_offsets  "6 6" \
   -add_connect                        \
   -connect_to_pads                    \
   -connect_to_pad_layers TopMetal2

# M1 Standardcell Rows (tracks)
add_pdn_stripe -grid {core_grid} -layer {Metal1} -width {0.44} -offset {0} \
               -followpins -extend_to_core_ring


# SRAMS
sram_power "grid_256x64" "RM_IHPSG13_1P_256x64_c2_bm_bist"          
sram_power "grid_256x48" "RM_IHPSG13_1P_256x48_c2_bm_bist"              
sram_power "grid_wmem"   "RM_IHPSG13_1P_2048x64_c2_bm_bist"
sram_power "grid_ram"    "RM_IHPSG13_1P_1024x64_c2_bm_bist"  

# Top power grid
# Top 2 Stripe
add_pdn_stripe -grid {core_grid} -layer {TopMetal2} -width $tpg2Width \
               -pitch $tpg2Pitch -spacing $tpg2Spacing -offset $tpg2Offset \
               -extend_to_core_ring -snap_to_grid 

# "The add_pdn_connect command is used to define which layers in the power grid are to be connected together. 
#  During power grid generation, vias will be added for overlapping power nets and overlapping ground nets."
# M1 is declared vertical but tracks still horizontal
# vertical TopMetal2 to below horizonals (M1 has horizontal power tracks)
add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal1}
add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal2}
add_pdn_connect -grid {core_grid} -layers {TopMetal2 Metal4}
# add_pdn_connect -grid {core_grid} -layers {TopMetal2 TopMetal1}
# power ring to standard cell rails
add_pdn_connect -grid {core_grid} -layers {Metal3 Metal1}
add_pdn_connect -grid {core_grid} -layers {Metal3 Metal2}`

[LucaMartis00]

[LucaMartis00]

violation type: Horizontal congestion
	srcs: net:i_flash_miso_i
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 432.0000) - (1915.2000, 439.2000) on Layer -
violation type: Horizontal congestion
	srcs: net:o_flash_ss_i
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 518.4000) - (1915.2000, 525.6000) on Layer -
violation type: Horizontal congestion
	srcs: net:o_flash_sck_i
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 612.0000) - (1915.2000, 619.2000) on Layer -
violation type: Horizontal congestion
	srcs: net:o_flash_mosi_i
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 698.4000) - (1915.2000, 705.6000) on Layer -
violation type: Horizontal congestion
	srcs: net:gating_cell.CK
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 792.0000) - (1915.2000, 799.2000) on Layer -
violation type: Horizontal congestion
	srcs: net:service_ihp.acc_top.aif.i_wb_rst
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 878.4000) - (1915.2000, 885.6000) on Layer -
violation type: Horizontal congestion
	srcs: net:service_ihp.servant.timer_clk
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 972.0000) - (1915.2000, 979.2000) on Layer -
violation type: Horizontal congestion
	srcs: net:o_txd_i
	comment: capacity:0 usage:1 overflow:1
	bbox = (1908.0000, 1058.4000) - (1915.2000, 1065.6000) on Layer -

[maliberty]

Looking at https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/b434ab0f9eaa83373567f1bb5f067e9707d4e02d/flow/designs/ihp-sg13g2/i2c-gpio-expander/pdn.tcl#L27 I see he used Metal5 and TopMetal1 which looks like it wouldn't block the pins.

[LucaMartis00]

Thank you very much, I think I’ve solved it.
I believe the issue was related to my old version of OpenROAD.
I ran my design with that PDN and got the same error; then I tried running the example itself and encountered the same issue.
After downloading the latest versions of OpenROAD, Yosys, and the OpenROAD flow scripts, the problem was resolved.