From 3d87c10d2db76f59a84603db315d5200081f77f4 Mon Sep 17 00:00:00 2001 From: ThreepwoodLeBrush <59653481+ThreepwoodLeBrush@users.noreply.github.com> Date: Sun, 15 Dec 2024 18:09:49 +0100 Subject: [PATCH] Fixed Typo --- names.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/names.csv b/names.csv index 3752426..7cf5efd 100644 --- a/names.csv +++ b/names.csv @@ -181,7 +181,7 @@ SuperJacob ;Super Jacob ;SuperJacob:1 | | | | | | | | | | | | | | | | | | | | | | | | | | | ADCTest ;ADC Input Test ;ADCTest:18_Common_EU ;ADCTest:18_Common_EU ;ADCTest:18_Common_EU ;ADCTest:18_Common_EU ;ADCTest:18_Common_EU ;ADC Input and Signal Test ;ADCTest:28_Common_EU ;ADCTest:28_Common_EU ;ADCTest:28_Common_EU ;ADCTest:28_Common_EU ;ADCTest:28_Common_EU ;ADCTest:28_Common_EU InputTest ;Input Test ;InputTest:18_Common_EU ;InputTest:18_Common_EU ;InputTest:18_Common_EU ;InputTest:18_Common_EU ;InputTest:18_Common_EU ;Controller Input Tester ;InputTest:28_Common_EU ;InputTest:28_Common_EU ;InputTest:28_Common_EU ;InputTest:28_Common_EU ;InputTest:28_Common_EU ;InputTest:28_Common_EU -InputTest_Sinden ;Input Test (S) ;InputTest:18_Common_EU ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;Controller Input Tester ;InputTest:28_Common_EU ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP +InputTest_Sinden ;Input Test (S) ;InputTest_Sinden:18_Common_EU ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;InputTest_Sinden:18_Common_JP ;Controller Input Tester ;InputTest_Sinden:28_Common_EU ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP ;InputTest_Sinden:28_Common_JP jtsdram48 ;SDRAM Test 48 MHz ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;jtsdram48:18_Common_EU ;Jotego SDRAM Test 48 MHz ;jtsdram48:28_Manufacturer_EU ;jtsdram48:28_Manufacturer_EU ;jtsdram48:28_Manufacturer_EU jtsdram96 ;SDRAM Test 96 MHz ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;jtsdram96:18_Common_EU ;Jotego SDRAM Test 96 MHz ;jtsdram96:28_Manufacturer_EU ;jtsdram96:28_Manufacturer_EU ;jtsdram96:28_Manufacturer_EU memtest ;SDRAM Test ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU ;memtest:18_Common_EU