@@ -102,6 +102,45 @@ def test_memblock_added_default_named(self):
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self .assertIs (pyrtl .working_block ().get_memblock_by_name (mem .name ), mem )
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+ class RTLMemBlockErrorTests (unittest .TestCase ):
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+ def setUp (self ):
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+ pyrtl .reset_working_block ()
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+
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+ def test_negative_bitwidth (self ):
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ pyrtl .MemBlock (bitwidth = - 1 , addrwidth = 1 )
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+
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+ def test_negative_addrwidth (self ):
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ pyrtl .MemBlock (bitwidth = 1 , addrwidth = - 1 )
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+
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+ def test_memindex_bitwidth_greater_than_addrwidth (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 1 , addrwidth = 1 )
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+ mem_addr = pyrtl .Input (2 , 'mem_addr' )
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+ mem_out = pyrtl .Output (1 , 'mem_out' )
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ mem_out <<= mem [mem_addr ]
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+
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+ def test_memblock_write_data_larger_than_memory_bitwidth (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 1 , addrwidth = 1 )
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+ mem_addr = pyrtl .Input (1 , 'mem_addr' )
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+ mem_in = pyrtl .Input (2 , 'mem_in' )
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ mem [mem_addr ] <<= mem_in
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+
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+ def test_memblock_enable_signal_not_1_bit (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 1 , addrwidth = 1 )
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+ mem_addr = pyrtl .Input (1 , 'mem_addr' )
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+ mem_in = pyrtl .Input (1 , 'mem_in' )
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ mem [mem_addr ] <<= pyrtl .MemBlock .EnabledWrite (mem_in , enable = pyrtl .Input (2 ))
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+
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+ def test_read_ports_exception (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 1 , addrwidth = 1 )
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+ with self .assertRaises (pyrtl .PyrtlError ):
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+ mem .read_ports ()
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+
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+
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class MemIndexedTests (unittest .TestCase ):
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def setUp (self ):
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pyrtl .reset_working_block ()
@@ -229,6 +268,51 @@ def test_write_memindexed_ior(self):
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self .assertEqual (self .mem1 .num_read_ports , 1 )
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self .assertEqual (self .mem2 .num_write_ports , 1 )
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+ def test_memindexed_len (self ):
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+ self .mem = pyrtl .MemBlock (bitwidth = 8 , addrwidth = 1 )
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+ self .assertEqual (len (self .mem [0 ]), 8 )
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+ self .mem_2 = pyrtl .MemBlock (bitwidth = 16 , addrwidth = 1 )
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+ self .assertEqual (len (self .mem_2 [0 ]), 16 )
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+
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+ def test_memindexed_getitem (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 8 , addrwidth = 1 , max_read_ports = None )
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+ mem_addr = pyrtl .Input (1 , 'mem_addr' )
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+ mem_out_array = [pyrtl .Output (8 , 'mem_out_' + str (i )) for i in range (8 )]
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+ for i in range (8 ):
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+ mem_out_array [i ] <<= mem [mem_addr ][i ]
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+ mem_value_map = {mem : {0 : 7 , 1 : 5 }}
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+ sim = pyrtl .Simulation (memory_value_map = mem_value_map )
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+ sim .step ({mem_addr : 0 })
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+ binary = bin (mem_value_map [mem ][0 ])[2 :].zfill (8 )
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+ self .assertEqual ([sim .inspect (mem_out_array [j ]) for j in range (8 )],
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+ [int (binary [7 - j ]) for j in range (8 )])
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+
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+ def test_memindexed_sign_extended (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 8 , addrwidth = 1 )
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+ mem_addr = pyrtl .Input (1 , 'mem_addr' )
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+ mem_out = pyrtl .Output (16 , 'mem_out' )
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+ mem_out <<= mem [mem_addr ].sign_extended (16 )
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+ mem_value_map = {mem : {0 : 0b00101101 , 1 : 0b10011011 }}
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+ mem_value_map_sign_extended = [0b0000000000101101 , 0b1111111110011011 ]
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+ sim = pyrtl .Simulation (memory_value_map = mem_value_map )
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+ sim .step ({mem_addr : 0 })
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+ self .assertEqual (sim .inspect (mem_out ), mem_value_map_sign_extended [0 ])
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+ sim .step ({mem_addr : 1 })
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+ self .assertEqual (sim .inspect (mem_out ), mem_value_map_sign_extended [1 ])
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+
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+ def test_memindexed_zero_extended (self ):
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+ mem = pyrtl .MemBlock (bitwidth = 8 , addrwidth = 1 )
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+ mem_addr = pyrtl .Input (1 , 'mem_addr' )
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+ mem_out = pyrtl .Output (16 , 'mem_out' )
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+ mem_out <<= mem [mem_addr ].zero_extended (16 )
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+ mem_value_map = {mem : {0 : 0b00101101 , 1 : 0b10011011 }}
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+ mem_value_map_zero_extended = [0b0000000000101101 , 0b0000000010011011 ]
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+ sim = pyrtl .Simulation (memory_value_map = mem_value_map )
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+ sim .step ({mem_addr : 0 })
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+ self .assertEqual (sim .inspect (mem_out ), mem_value_map_zero_extended [0 ])
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+ sim .step ({mem_addr : 1 })
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+ self .assertEqual (sim .inspect (mem_out ), mem_value_map_zero_extended [1 ])
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+
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class RTLRomBlockWiring (unittest .TestCase ):
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data = list (range (2 ** 5 ))
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