Skip to content

Commit 5b282f3

Browse files
authored
Add more tests for MemBlock and _MemIndexed (#461)
* Add more tests for MemBlock and _MemIndexed
1 parent 5077c24 commit 5b282f3

File tree

1 file changed

+84
-0
lines changed

1 file changed

+84
-0
lines changed

tests/test_memblock.py

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,45 @@ def test_memblock_added_default_named(self):
102102
self.assertIs(pyrtl.working_block().get_memblock_by_name(mem.name), mem)
103103

104104

105+
class RTLMemBlockErrorTests(unittest.TestCase):
106+
def setUp(self):
107+
pyrtl.reset_working_block()
108+
109+
def test_negative_bitwidth(self):
110+
with self.assertRaises(pyrtl.PyrtlError):
111+
pyrtl.MemBlock(bitwidth=-1, addrwidth=1)
112+
113+
def test_negative_addrwidth(self):
114+
with self.assertRaises(pyrtl.PyrtlError):
115+
pyrtl.MemBlock(bitwidth=1, addrwidth=-1)
116+
117+
def test_memindex_bitwidth_greater_than_addrwidth(self):
118+
mem = pyrtl.MemBlock(bitwidth=1, addrwidth=1)
119+
mem_addr = pyrtl.Input(2, 'mem_addr')
120+
mem_out = pyrtl.Output(1, 'mem_out')
121+
with self.assertRaises(pyrtl.PyrtlError):
122+
mem_out <<= mem[mem_addr]
123+
124+
def test_memblock_write_data_larger_than_memory_bitwidth(self):
125+
mem = pyrtl.MemBlock(bitwidth=1, addrwidth=1)
126+
mem_addr = pyrtl.Input(1, 'mem_addr')
127+
mem_in = pyrtl.Input(2, 'mem_in')
128+
with self.assertRaises(pyrtl.PyrtlError):
129+
mem[mem_addr] <<= mem_in
130+
131+
def test_memblock_enable_signal_not_1_bit(self):
132+
mem = pyrtl.MemBlock(bitwidth=1, addrwidth=1)
133+
mem_addr = pyrtl.Input(1, 'mem_addr')
134+
mem_in = pyrtl.Input(1, 'mem_in')
135+
with self.assertRaises(pyrtl.PyrtlError):
136+
mem[mem_addr] <<= pyrtl.MemBlock.EnabledWrite(mem_in, enable=pyrtl.Input(2))
137+
138+
def test_read_ports_exception(self):
139+
mem = pyrtl.MemBlock(bitwidth=1, addrwidth=1)
140+
with self.assertRaises(pyrtl.PyrtlError):
141+
mem.read_ports()
142+
143+
105144
class MemIndexedTests(unittest.TestCase):
106145
def setUp(self):
107146
pyrtl.reset_working_block()
@@ -229,6 +268,51 @@ def test_write_memindexed_ior(self):
229268
self.assertEqual(self.mem1.num_read_ports, 1)
230269
self.assertEqual(self.mem2.num_write_ports, 1)
231270

271+
def test_memindexed_len(self):
272+
self.mem = pyrtl.MemBlock(bitwidth=8, addrwidth=1)
273+
self.assertEqual(len(self.mem[0]), 8)
274+
self.mem_2 = pyrtl.MemBlock(bitwidth=16, addrwidth=1)
275+
self.assertEqual(len(self.mem_2[0]), 16)
276+
277+
def test_memindexed_getitem(self):
278+
mem = pyrtl.MemBlock(bitwidth=8, addrwidth=1, max_read_ports=None)
279+
mem_addr = pyrtl.Input(1, 'mem_addr')
280+
mem_out_array = [pyrtl.Output(8, 'mem_out_' + str(i)) for i in range(8)]
281+
for i in range(8):
282+
mem_out_array[i] <<= mem[mem_addr][i]
283+
mem_value_map = {mem: {0: 7, 1: 5}}
284+
sim = pyrtl.Simulation(memory_value_map=mem_value_map)
285+
sim.step({mem_addr: 0})
286+
binary = bin(mem_value_map[mem][0])[2:].zfill(8)
287+
self.assertEqual([sim.inspect(mem_out_array[j]) for j in range(8)],
288+
[int(binary[7 - j]) for j in range(8)])
289+
290+
def test_memindexed_sign_extended(self):
291+
mem = pyrtl.MemBlock(bitwidth=8, addrwidth=1)
292+
mem_addr = pyrtl.Input(1, 'mem_addr')
293+
mem_out = pyrtl.Output(16, 'mem_out')
294+
mem_out <<= mem[mem_addr].sign_extended(16)
295+
mem_value_map = {mem: {0: 0b00101101, 1: 0b10011011}}
296+
mem_value_map_sign_extended = [0b0000000000101101, 0b1111111110011011]
297+
sim = pyrtl.Simulation(memory_value_map=mem_value_map)
298+
sim.step({mem_addr: 0})
299+
self.assertEqual(sim.inspect(mem_out), mem_value_map_sign_extended[0])
300+
sim.step({mem_addr: 1})
301+
self.assertEqual(sim.inspect(mem_out), mem_value_map_sign_extended[1])
302+
303+
def test_memindexed_zero_extended(self):
304+
mem = pyrtl.MemBlock(bitwidth=8, addrwidth=1)
305+
mem_addr = pyrtl.Input(1, 'mem_addr')
306+
mem_out = pyrtl.Output(16, 'mem_out')
307+
mem_out <<= mem[mem_addr].zero_extended(16)
308+
mem_value_map = {mem: {0: 0b00101101, 1: 0b10011011}}
309+
mem_value_map_zero_extended = [0b0000000000101101, 0b0000000010011011]
310+
sim = pyrtl.Simulation(memory_value_map=mem_value_map)
311+
sim.step({mem_addr: 0})
312+
self.assertEqual(sim.inspect(mem_out), mem_value_map_zero_extended[0])
313+
sim.step({mem_addr: 1})
314+
self.assertEqual(sim.inspect(mem_out), mem_value_map_zero_extended[1])
315+
232316

233317
class RTLRomBlockWiring(unittest.TestCase):
234318
data = list(range(2**5))

0 commit comments

Comments
 (0)