Remove more Python 2 legacy code (explicit inheritance from object, importing collections.Mapping).

Author: fdxmw

examples/example5-introspection.py

@@ -10,7 +10,7 @@
 # stages, and new members with names not starting with "_" are to be registered
 # for the next stage.
 
-class SimplePipeline(object):
+class SimplePipeline:
     """ Pipeline builder with auto generation of pipeline registers. """
 
     def __init__(self):

ipynb-examples/example5-introspection.ipynb

@@ -38,7 +38,7 @@
     "\n",
     "pyrtl.reset_working_block()\n",
     "\n",
-    "class SimplePipeline(object):\n",
+    "class SimplePipeline:\n",
     "    def __init__(self):\n",
     "        self._pipeline_register_map = {}\n",
     "        self._current_stage_num = 0\n",

pyrtl/analysis.py

@@ -135,7 +135,7 @@ def _bits_ports_and_isrom_from_memory(mem):
 #    |  |  |  | | | \| \__>     /    \| \| /~~\ |_  |   .__/ |  .__/
 #
 
-class TimingAnalysis(object):
+class TimingAnalysis:
     """Timing analysis estimates the timing delays in the block
 
     TimingAnalysis has an :py:attr:`~.TimingAnalysis.timing_map` object that

pyrtl/compilesim.py

@@ -8,6 +8,7 @@
 import platform
 import sys
 import _ctypes
+from collections.abc import Mapping
 
 from .core import working_block, Block
 from .wire import Input, Output, Const, WireVector, Register
@@ -16,11 +17,6 @@
 from .simulation import SimulationTrace, _trace_sort_key
 from .helperfuncs import infer_val_and_bitwidth
 
-try:
-    from collections.abc import Mapping
-except ImportError:
-    from collections import Mapping
-
 
 __all__ = ['CompiledSimulation']
 
@@ -56,7 +52,7 @@ def __eq__(self, other):
         return all(self[x] == other.get(x, 0) for x in self)
 
 
-class CompiledSimulation(object):
+class CompiledSimulation:
     """Simulate a block, compiling to C for efficiency.
 
     This module provides significant speed improvements over

pyrtl/conditional.py

@@ -185,7 +185,7 @@ def currently_under_condition() -> bool:
 # `conditional_assignment` and `otherwise`, both visible in the pyrtl module, are
 # defined as instances (hopefully the only and unchanging instances) of the following
 # two types.
-class _ConditionalAssignment(object):
+class _ConditionalAssignment:
     def __init__(self):
         self.defaults = {}
 
@@ -208,7 +208,7 @@ def __exit__(self, *exc_info):
             _reset_conditional_state()  # sets _depth back to 0
 
 
-class _Otherwise(object):
+class _Otherwise:
     def __enter__(self):
         _push_condition(otherwise)
 

pyrtl/core.py

@@ -232,7 +232,7 @@ def _compare_error(self, other):
     __ge__ = _compare_error
 
 
-class Block(object):
+class Block:
     """Block encapsulates a netlist.
 
     A Block in PyRTL is the class that stores a netlist and provides basic
@@ -977,7 +977,7 @@ def reset_working_block():
     _singleton_block = Block()
 
 
-class set_working_block(object):
+class set_working_block:
     """ Set the working block to be the block passed as argument.
     Compatible with the `with` statement.
 
@@ -1037,7 +1037,7 @@ def set_debug_mode(debug=True):
 _py_regex = r'^[^\d\W]\w*\Z'
 
 
-class _NameIndexer(object):
+class _NameIndexer:
     """ Provides internal names that are based on a prefix and an index. """
     def __init__(self, internal_prefix='_sani_temp'):
         self.internal_prefix = internal_prefix

pyrtl/helperfuncs.py

@@ -891,7 +891,7 @@ def find_loop(block=None):
     wires_left, logic_left = result
     import random
 
-    class _FilteringState(object):
+    class _FilteringState:
         def __init__(self, dst_w):
             self.dst_w = dst_w
             self.arg_num = -1
@@ -987,7 +987,7 @@ def _print_netlist_latex(netlist):
     display(Latex(out))
 
 
-class _NetCount(object):
+class _NetCount:
     """ Helper class to track when to stop an iteration that depends on number of nets
 
     Mainly useful for iterations that are for optimization

pyrtl/memory.py

@@ -86,7 +86,7 @@ def name(self, n):
         as_wires(self).name = n
 
 
-class MemBlock(object):
+class MemBlock:
     """MemBlock is the object for specifying block memories. It can be indexed like an
     array for both reading and writing. Writes under a conditional are automatically
     converted to enabled writes. Consider the following examples where ``addr``,

pyrtl/passes.py

@@ -208,7 +208,7 @@ def _optimize_inverter_chains(block, skip_sanity_check=False):
         block.sanity_check()
 
 
-class _ProducerList(object):
+class _ProducerList:
     """  Maps from wire to its immediate producer and finds ultimate producers. """
     def __init__(self):
         self.dict = {}  # map from wirevector to its direct producer wirevector

pyrtl/rtllib/aes.py

@@ -46,7 +46,7 @@
 #    full independent hardware units) would be a plus as well
 
 
-class AES(object):
+class AES:
     def __init__(self):
         self.memories_built = False
         self._key_len = 128

pyrtl/rtllib/matrix.py

@@ -9,7 +9,7 @@
 from ..helperfuncs import formatted_str_to_val
 
 
-class Matrix(object):
+class Matrix:
     ''' Class for making a Matrix using PyRTL.
 
     Provides the ability to perform different matrix operations.

pyrtl/rtllib/muxes.py

@@ -105,7 +105,7 @@ def _sparse_mux(sel, vals):
     return pyrtl.select(sel[-1], falsecase=false_result, truecase=true_result)
 
 
-class MultiSelector(object):
+class MultiSelector:
     """ The MultiSelector allows you to specify multiple wire value results
     for a single select wire.
 

pyrtl/simulation.py

@@ -9,6 +9,7 @@
 import re
 import sys
 import typing
+from collections.abc import Mapping
 
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
 from .core import working_block, PostSynthBlock, _PythonSanitizer, Block
@@ -18,19 +19,14 @@
 from .helperfuncs import val_to_signed_integer, infer_val_and_bitwidth
 from .importexport import _VerilogSanitizer
 
-try:
-    from collections.abc import Mapping
-except ImportError:
-    from collections import Mapping
-
 # ----------------------------------------------------------------
 #    __                         ___    __
 #   /__` |  |\/| |  | |     /\   |  | /  \ |\ |
 #   .__/ |  |  | \__/ |___ /~~\  |  | \__/ | \|
 #
 
 
-class Simulation(object):
+class Simulation:
     """A class for simulating blocks of logic step by step.
 
     A Simulation step works as follows:
@@ -488,7 +484,7 @@ def _mem_update(self, net):
 #
 
 
-class FastSimulation(object):
+class FastSimulation:
     """A class for running JIT-to-python implementations of blocks.
 
     A Simulation step works as follows:
@@ -994,7 +990,7 @@ def make_split(
 #     |  |  \ /~~\ \__, |___
 #
 
-class WaveRenderer(object):
+class WaveRenderer:
     """Render a SimulationTrace to the terminal.
 
     See ``examples/renderer-demo.py``, which renders traces with various
@@ -1460,7 +1456,7 @@ def __getitem__(self, key):
         return self.__data[key]
 
 
-class SimulationTrace(object):
+class SimulationTrace:
     """ Storage and presentation of simulation waveforms. """
 
     def __init__(self, wires_to_track: list[WireVector] = None,

pyrtl/wire.py

@@ -58,7 +58,7 @@ def next_tempvar_name(name=""):
 WireVectorLike = Union["WireVector", int, str, bool]
 
 
-class WireVector(object):
+class WireVector:
     """The main class for describing the connections between operators.
 
     ``WireVectors`` act much like a list of wires, except that there is no "contained"
@@ -1244,7 +1244,7 @@ class Register(WireVector):
     #     reg <<= 5       # error
     #     a <<= reg.next  # error
     #     reg.next = 5    # error
-    class _Next(object):
+    class _Next:
         """Type returned by the ``Register.next`` property.
 
         This class allows unconditional assignments (``<<=``, ``__ilshift__``) and