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lfsr increased randomness
1 parent 467db36 commit 16f6485

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2 files changed

+11
-10
lines changed

2 files changed

+11
-10
lines changed

src/dino_game_top.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ module tt_um_uwasic_dinogame #(parameter CONV = 2) (
3737

3838
wire [7:0] rng;
3939

40-
lfsr #(.NUM_BITS(8)) lfsr_inst (
40+
lfsr #(.NUM_BITS(15)) lfsr_inst (
4141
.clk(clk),
4242
.enable(ena),
4343
.lfsr_data(rng)

src/lfsr.v

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -6,9 +6,10 @@ module lfsr
66
(
77
input wire clk,
88
input wire enable,
9-
output wire [NUM_BITS-1:0] lfsr_data
9+
output wire [7:0] lfsr_data
1010
);
11-
reg [NUM_BITS:1] r_lfsr = {NUM_BITS/2{2'b01}}; // 010101 ...
11+
// reg [NUM_BITS:1] r_lfsr = {NUM_BITS/2{2'b01}}; // 010101 ...
12+
reg [NUM_BITS:1] r_lfsr = 15'b0101010101010101; // 010101 ...
1213
wire r_xnor;
1314

1415
// Create Feedback Polynomials. Based on Application Note:
@@ -20,25 +21,25 @@ module lfsr
2021
5: begin : gen_poly assign r_xnor = r_lfsr[5] ^~ r_lfsr[3]; end
2122
6: begin : gen_poly assign r_xnor = r_lfsr[6] ^~ r_lfsr[5]; end
2223
7: begin : gen_poly assign r_xnor = r_lfsr[7] ^~ r_lfsr[6]; end
23-
8: begin : gen_poly assign r_xnor = r_lfsr[8] ^~ r_lfsr[6] ^~ r_lfsr[5] ^~ r_lfsr[4]; end
24+
8: begin : gen_poly assign r_xnor = ~(r_lfsr[8] ^ r_lfsr[6] ^ r_lfsr[5] ^ r_lfsr[4]); end
2425
9: begin : gen_poly assign r_xnor = r_lfsr[9] ^~ r_lfsr[5]; end
2526
10: begin : gen_poly assign r_xnor = r_lfsr[10] ^~ r_lfsr[7]; end
2627
11: begin : gen_poly assign r_xnor = r_lfsr[11] ^~ r_lfsr[9]; end
27-
12: begin : gen_poly assign r_xnor = r_lfsr[12] ^~ r_lfsr[6] ^~ r_lfsr[4] ^~ r_lfsr[1]; end
28-
13: begin : gen_poly assign r_xnor = r_lfsr[13] ^~ r_lfsr[4] ^~ r_lfsr[3] ^~ r_lfsr[1]; end
29-
14: begin : gen_poly assign r_xnor = r_lfsr[14] ^~ r_lfsr[5] ^~ r_lfsr[3] ^~ r_lfsr[1]; end
28+
12: begin : gen_poly assign r_xnor = ~(r_lfsr[12] ^ r_lfsr[6] ^ r_lfsr[4] ^ r_lfsr[1]); end
29+
13: begin : gen_poly assign r_xnor = ~(r_lfsr[13] ^ r_lfsr[4] ^ r_lfsr[3] ^ r_lfsr[1]); end
30+
14: begin : gen_poly assign r_xnor = ~(r_lfsr[14] ^ r_lfsr[5] ^ r_lfsr[3] ^ r_lfsr[1]); end
3031
15: begin : gen_poly assign r_xnor = r_lfsr[15] ^~ r_lfsr[14]; end
31-
16: begin : gen_poly assign r_xnor = r_lfsr[16] ^~ r_lfsr[15] ^~ r_lfsr[13] ^~ r_lfsr[4]; end
32+
16: begin : gen_poly assign r_xnor = ~(r_lfsr[16] ^ r_lfsr[15] ^ r_lfsr[13] ^ r_lfsr[4]); end
3233
endcase // case (NUM_BITS)
3334
endgenerate
3435

3536
always @(posedge clk) begin
3637
if (enable == 1'b1)
3738
r_lfsr <= {r_lfsr[NUM_BITS-1:1], r_xnor};
3839
else
39-
r_lfsr <= {NUM_BITS/2{2'b01}};
40+
r_lfsr <= 15'b0101010101010101;
4041
end
4142

42-
assign lfsr_data = r_lfsr[NUM_BITS:1];
43+
assign lfsr_data = r_lfsr[8:1];
4344
endmodule
4445

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