From 647d0ce939a30c4d82690137ce474f8ce07612ea Mon Sep 17 00:00:00 2001 From: umarcor Date: Mon, 25 Oct 2021 19:44:11 +0200 Subject: [PATCH] revert "vunit/sim_if: Active-HDL supports VHDL 2019 (#755)" This reverts commit 3aa1c05a22b47f4738fe5b1614297ce038279b81. --- vunit/sim_if/activehdl.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vunit/sim_if/activehdl.py b/vunit/sim_if/activehdl.py index 8782ae2b0..c496a350d 100644 --- a/vunit/sim_if/activehdl.py +++ b/vunit/sim_if/activehdl.py @@ -109,7 +109,7 @@ def _std_str(vhdl_standard): """ Convert standard to format of Active-HDL command line flag """ - if vhdl_standard <= VHDL.STD_2019: + if vhdl_standard <= VHDL.STD_2008: return f"-{vhdl_standard!s}" raise ValueError(f"Invalid VHDL standard {vhdl_standard!s}")