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mmickommicko
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Use extra tile information from chip database
1 parent 8f91f95 commit d3bbdc8

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5 files changed

+58
-46
lines changed

5 files changed

+58
-46
lines changed

‎himbaechel/uarch/gatemate/bitstream.cc

Lines changed: 26 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -40,21 +40,6 @@ struct BitstreamBackend
4040
BitstreamBackend(Context *ctx, GateMateImpl *uarch, const std::string &device, std::ostream &out)
4141
: ctx(ctx), uarch(uarch), device(device), out(out) {};
4242

43-
void get_bitstream_tile(int x, int y, int &b_x, int &b_y)
44-
{
45-
// Edge blocks are bit bigger
46-
if (x == -2)
47-
x++;
48-
if (x == 163)
49-
x--;
50-
if (y == -2)
51-
y++;
52-
if (y == 131)
53-
y--;
54-
b_x = (x + 1) / 2;
55-
b_y = (y + 1) / 2;
56-
}
57-
5843
std::vector<bool> int_to_bitvector(int val, int size)
5944
{
6045
std::vector<bool> bv;
@@ -76,28 +61,16 @@ struct BitstreamBackend
7661
return bv;
7762
}
7863

79-
CfgLoc getConfigLoc(Context *ctx, int tile)
64+
CfgLoc getConfigLoc(int tile)
8065
{
81-
int x0, y0;
82-
int bx, by;
83-
tile_xy(ctx->chip_info, tile, x0, y0);
84-
get_bitstream_tile(x0 - 2, y0 - 2, bx, by);
66+
auto ti = *uarch->tile_extra_data(tile);
8567
CfgLoc loc;
86-
loc.die = 0;
87-
loc.x = bx;
88-
loc.y = by;
68+
loc.die = ti.die;
69+
loc.x = ti.bit_x;
70+
loc.y = ti.bit_y;
8971
return loc;
9072
}
9173

92-
int getInTileIndex(Context *ctx, int tile)
93-
{
94-
int x0, y0;
95-
tile_xy(ctx->chip_info, tile, x0, y0);
96-
x0 -= 2 - 1;
97-
y0 -= 2 - 1;
98-
return (x0 % 2) * 2 + (y0 % 2) + 1;
99-
}
100-
10174
void write_bitstream()
10275
{
10376
ChipConfig cc;
@@ -111,7 +84,7 @@ struct BitstreamBackend
11184
cc.configs[0].add_word("GPIO.BANK_W1", int_to_bitvector(1, 1));
11285
cc.configs[0].add_word("GPIO.BANK_W2", int_to_bitvector(1, 1));
11386
for (auto &cell : ctx->cells) {
114-
CfgLoc loc = getConfigLoc(ctx, cell.second.get()->bel.tile);
87+
CfgLoc loc = getConfigLoc(cell.second.get()->bel.tile);
11588
auto &params = cell.second.get()->params;
11689
switch (cell.second->type.index) {
11790
case id_CC_IBUF.index:
@@ -127,9 +100,9 @@ struct BitstreamBackend
127100
}
128101
break;
129102
case id_CPE.index: {
130-
int x = getInTileIndex(ctx, cell.second.get()->bel.tile);
103+
int id = uarch->tile_extra_data(cell.second.get()->bel.tile)->prim_id;
131104
for (auto &p : params) {
132-
cc.tiles[loc].add_word(stringf("CPE%d.%s", x, p.first.c_str(ctx)), p.second.as_bits());
105+
cc.tiles[loc].add_word(stringf("CPE%d.%s", id, p.first.c_str(ctx)), p.second.as_bits());
133106
}
134107
} break;
135108
case id_BUFG.index:
@@ -169,20 +142,28 @@ struct BitstreamBackend
169142
chip_pip_info(ctx->chip_info, pip).extra_data.get());
170143
if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) {
171144
IdString name = IdString(extra_data.name);
172-
CfgLoc loc = getConfigLoc(ctx, pip.tile);
145+
CfgLoc loc = getConfigLoc(pip.tile);
173146
std::string word = name.c_str(ctx);
174147
if (extra_data.flags & MUX_CONFIG) {
175-
cc.configs[loc.die].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits));
148+
cc.configs[loc.die].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits));
176149
} else {
177-
int x = getInTileIndex(ctx, pip.tile);
150+
int id = uarch->tile_extra_data(pip.tile)->prim_id;
178151
if (boost::starts_with(word, "IM."))
179-
boost::replace_all(word, "IM.", stringf("IM%d.", x));
180-
if (boost::starts_with(word, "OM."))
181-
boost::replace_all(word, "OM.", stringf("OM%d.", x));
182-
if (boost::starts_with(word, "IOES."))
183-
boost::replace_all(word, "IOES.", "IOES1.");
184-
if (boost::starts_with(word, "CPE."))
185-
boost::replace_all(word, "CPE.", stringf("CPE%d.", x));
152+
boost::replace_all(word, "IM.", stringf("IM%d.", id));
153+
else if (boost::starts_with(word, "OM."))
154+
boost::replace_all(word, "OM.", stringf("OM%d.", id));
155+
else if (boost::starts_with(word, "CPE."))
156+
boost::replace_all(word, "CPE.", stringf("CPE%d.", id));
157+
else if (boost::starts_with(word, "IOES."))
158+
boost::replace_all(word, "IOES.", stringf("IOES%d.", id));
159+
else if (boost::starts_with(word, "LES."))
160+
boost::replace_all(word, "LES.", stringf("LES%d.", id));
161+
else if (boost::starts_with(word, "BES."))
162+
boost::replace_all(word, "BES.", stringf("BES%d.", id));
163+
else if (boost::starts_with(word, "RES."))
164+
boost::replace_all(word, "RES.", stringf("RES%d.", id));
165+
else if (boost::starts_with(word, "TES."))
166+
boost::replace_all(word, "TES.", stringf("TES%d.", id));
186167
cc.tiles[loc].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits));
187168
}
188169
}

‎himbaechel/uarch/gatemate/extra_data.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,13 @@
2424

2525
NEXTPNR_NAMESPACE_BEGIN
2626

27+
NPNR_PACKED_STRUCT(struct GateMateTileExtraDataPOD {
28+
uint8_t die;
29+
uint8_t bit_x;
30+
uint8_t bit_y;
31+
uint8_t prim_id;
32+
});
33+
2734
NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD {
2835
int32_t name;
2936
uint8_t bits;

‎himbaechel/uarch/gatemate/gatemate.cc

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -267,6 +267,11 @@ bool GateMateImpl::isValidBelForCellType(IdString cell_type, BelId bel) const
267267
return (bel_type == cell_type);
268268
}
269269

270+
const GateMateTileExtraDataPOD *GateMateImpl::tile_extra_data(int tile) const
271+
{
272+
return reinterpret_cast<const GateMateTileExtraDataPOD *>(ctx->chip_info->tile_insts[tile].extra_data.get());
273+
}
274+
270275
struct GateMateArch : HimbaechelArch
271276
{
272277
GateMateArch() : HimbaechelArch("gatemate") {};

‎himbaechel/uarch/gatemate/gatemate.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,7 @@ struct GateMateImpl : HimbaechelAPI
6363
const auto &extra_data = *reinterpret_cast<const GateMatePipExtraDataPOD*>(chip_pip_info(ctx->chip_info, pip).extra_data.get());
6464
return extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_INVERT);
6565
}
66+
const GateMateTileExtraDataPOD *tile_extra_data(int tile) const;
6667

6768
pool<PipId> blocked_pips;
6869
};

‎himbaechel/uarch/gatemate/gen/arch_gen.py

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,21 @@
4343
import chip
4444
import die
4545

46+
@dataclass
47+
class TileExtraData(BBAStruct):
48+
die : int = 0
49+
bit_x: int = 0
50+
bit_y: int = 0
51+
prim_id : int = 0
52+
53+
def serialise_lists(self, context: str, bba: BBAWriter):
54+
pass
55+
def serialise(self, context: str, bba: BBAWriter):
56+
bba.u8(self.die)
57+
bba.u8(self.bit_x)
58+
bba.u8(self.bit_y)
59+
bba.u8(self.prim_id)
60+
4661
@dataclass
4762
class PipExtraData(BBAStruct):
4863
pip_type: int
@@ -218,7 +233,10 @@ def main():
218233
# Setup tile grid
219234
for x in range(dev.max_col() + 3):
220235
for y in range(dev.max_row() + 3):
221-
ch.set_tile_type(x, y, dev.get_tile_type(x - 2,y - 2))
236+
ti = ch.set_tile_type(x, y, dev.get_tile_type(x - 2,y - 2))
237+
tileinfo = dev.get_tile_info(x - 2,y - 2)
238+
ti.extra_data = TileExtraData(tileinfo.die, tileinfo.bit_x, tileinfo.bit_y, tileinfo.prim_index)
239+
222240
# Create nodes between tiles
223241
for _,nodes in dev.get_connections():
224242
node = []

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