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Commit f52ceb2

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mmickommicko
committed
better MX2
1 parent 96350e3 commit f52ceb2

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3 files changed

+27
-38
lines changed

3 files changed

+27
-38
lines changed

‎himbaechel/uarch/gatemate/gatemate.cc

+7-33
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919

2020
#include "gatemate.h"
2121
#include "design_utils.h"
22+
#include "placer_heap.h"
2223

2324
#define GEN_INIT_CONSTIDS
2425
#define HIMBAECHEL_CONSTIDS "uarch/gatemate/constids.inc"
@@ -241,7 +242,6 @@ void GateMateImpl::postRoute()
241242
}
242243
for (auto &cell : ctx->cells) {
243244
if (cell.second->type.in(id_CPE_HALF_U)) {
244-
//log_info("Checking id_CPE_HALF_U %s\n", cell.second->name.c_str(ctx));
245245
uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
246246
if (func != C_MX4) {
247247
updateLUT(ctx, cell.second.get(), id_IN1, id_INIT_L00);
@@ -271,38 +271,6 @@ void GateMateImpl::postRoute()
271271
updateINV(ctx, cell.second.get(), id_SR, id_C_CPE_RES);
272272
}
273273
}
274-
/*
275-
276-
for (auto &cell : ctx->cells) {
277-
if (cell.second->type == id_CPE) {
278-
// if LUT part used
279-
uint8_t func = int_or_default(cell.second->params, id_C_FUNCTION, 0);
280-
if (func != C_MX4) {
281-
updateLUT(ctx, cell.second.get(), id_IN1, id_INIT_L00);
282-
updateLUT(ctx, cell.second.get(), id_IN2, id_INIT_L00);
283-
updateLUT(ctx, cell.second.get(), id_IN3, id_INIT_L01);
284-
updateLUT(ctx, cell.second.get(), id_IN4, id_INIT_L01);
285-
} else {
286-
updateMUX_INV(ctx, cell.second.get(), id_IN1, id_INIT_L11, 0);
287-
updateMUX_INV(ctx, cell.second.get(), id_IN2, id_INIT_L11, 1);
288-
updateMUX_INV(ctx, cell.second.get(), id_IN3, id_INIT_L11, 2);
289-
updateMUX_INV(ctx, cell.second.get(), id_IN4, id_INIT_L11, 3);
290-
}
291-
292-
updateLUT(ctx, cell.second.get(), id_IN5, id_INIT_L02);
293-
updateLUT(ctx, cell.second.get(), id_IN6, id_INIT_L02);
294-
updateLUT(ctx, cell.second.get(), id_IN7, id_INIT_L03);
295-
updateLUT(ctx, cell.second.get(), id_IN8, id_INIT_L03);
296-
updateINV(ctx, cell.second.get(), id_CLK, id_C_CPE_CLK);
297-
updateINV(ctx, cell.second.get(), id_EN, id_C_CPE_EN);
298-
bool set = int_or_default(cell.second->params, id_C_EN_SR, 0) == 1;
299-
if (set)
300-
updateSR_INV(ctx, cell.second.get(), id_SR, id_C_CPE_SET);
301-
else
302-
updateSR_INV(ctx, cell.second.get(), id_SR, id_C_CPE_RES);
303-
}
304-
}
305-
*/
306274
print_utilisation(ctx);
307275

308276
const ArchArgs &args = ctx->args;
@@ -311,6 +279,12 @@ void GateMateImpl::postRoute()
311279
}
312280
}
313281

282+
void GateMateImpl::configurePlacerHeap(PlacerHeapCfg &cfg)
283+
{
284+
//cfg.beta = 0.5;
285+
cfg.placeAllAtOnce = true;
286+
}
287+
314288
void GateMateImpl::prePlace()
315289
{
316290
assign_cell_info();

‎himbaechel/uarch/gatemate/gatemate.h

+2
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,8 @@ struct GateMateImpl : HimbaechelAPI
6161
bool isValidBelForCellType(IdString cell_type, BelId bel) const override;
6262
BelBucketId getBelBucketForBel(BelId bel) const override;
6363

64+
void configurePlacerHeap(PlacerHeapCfg &cfg) override;
65+
6466
bool isPipInverting(PipId pip) const override {
6567
const auto &extra_data = *reinterpret_cast<const GateMatePipExtraDataPOD*>(chip_pip_info(ctx->chip_info, pip).extra_data.get());
6668
return extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_INVERT);

‎himbaechel/uarch/gatemate/pack.cc

+18-5
Original file line numberDiff line numberDiff line change
@@ -387,7 +387,7 @@ void GateMatePacker::pack_cpe()
387387
std::vector<CellInfo *> l2t5_list;
388388
for (auto &cell : ctx->cells) {
389389
CellInfo &ci = *cell.second;
390-
if (!ci.type.in(id_CC_L2T4, id_CC_L2T5, id_CC_LUT2, id_CC_LUT1))
390+
if (!ci.type.in(id_CC_L2T4, id_CC_L2T5, id_CC_LUT2, id_CC_LUT1, id_CC_MX2))
391391
continue;
392392
if (ci.type == id_CC_L2T5) {
393393
l2t5_list.push_back(&ci);
@@ -400,6 +400,21 @@ void GateMatePacker::pack_cpe()
400400

401401
ci.params[id_C_O] = Property(0b11, 2);
402402
ci.type = id_CPE_HALF_L;
403+
} else if (ci.type == id_CC_MX2) {
404+
ci.params[id_C_O] = Property(0b11, 2);
405+
ci.renamePort(id_D1, id_IN1);
406+
NetInfo *sel = ci.getPort(id_S0);
407+
ci.renamePort(id_S0, id_IN2);
408+
ci.ports[id_IN3].name = id_IN3;
409+
ci.ports[id_IN3].type = PORT_IN;
410+
ci.connectPort(id_IN3, sel);
411+
ci.renamePort(id_D0, id_IN4);
412+
ci.disconnectPort(id_D1);
413+
ci.params[id_INIT_L00] = Property(0b1000, 4); // AND
414+
ci.params[id_INIT_L01] = Property(0b0100, 4); // AND inv D0
415+
ci.params[id_INIT_L10] = Property(0b1110, 4); // OR
416+
ci.renamePort(id_Y, id_OUT);
417+
ci.type = id_CPE_HALF;
403418
} else {
404419
ci.renamePort(id_I0, id_IN1);
405420
ci.renamePort(id_I1, id_IN2);
@@ -451,7 +466,7 @@ void GateMatePacker::pack_cpe()
451466
std::vector<CellInfo *> mux_list;
452467
for (auto &cell : ctx->cells) {
453468
CellInfo &ci = *cell.second;
454-
if (!ci.type.in(id_CC_MX2, id_CC_MX4))
469+
if (!ci.type.in(id_CC_MX4))
455470
continue;
456471
mux_list.push_back(&ci);
457472
}
@@ -479,8 +494,7 @@ void GateMatePacker::pack_cpe()
479494
}
480495
ci.params[id_C_FUNCTION] = Property(C_MX4, 3);
481496
ci.params[id_INIT_L02] = Property(0b1100, 4); // IN6
482-
if (ci.type == id_CC_MX4)
483-
ci.params[id_INIT_L03] = Property(0b1100, 4); // IN8
497+
ci.params[id_INIT_L03] = Property(0b1100, 4); // IN8
484498
//ci.params[id_INIT_L11] = Property(invert, 4); // Inversion bits
485499
ci.params[id_INIT_L20] = Property(0b1100, 4); // Always D1
486500
ci.params[id_C_O] = Property(0b11, 2);
@@ -496,7 +510,6 @@ void GateMatePacker::pack_cpe()
496510

497511
ci.movePortTo(id_D0, upper, id_IN1);
498512
ci.movePortTo(id_D1, upper, id_IN2);
499-
// Only for CC_MX4
500513
ci.movePortTo(id_D2, upper, id_IN3);
501514
ci.movePortTo(id_D3, upper, id_IN4);
502515
ci.constr_children.push_back(upper);

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