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gcc-zippatch.patch
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diff -Naur '--exclude=*.swp' gcc-10.3.0/config.sub gcc-10.3.0-zip/config.sub
--- gcc-10.3.0/config.sub 2021-04-08 07:56:27.573734691 -0400
+++ gcc-10.3.0-zip/config.sub 2021-04-12 16:19:47.027596647 -0400
@@ -629,6 +629,11 @@
basic_machine=ymp-cray
os=unicos
;;
+ zip)
+ basic_machine=zip
+ vendor=gqtech
+ os=none
+ ;;
*)
basic_machine=$1
os=
@@ -916,6 +921,9 @@
cpu=sparc
vendor=`echo "$basic_machine" | sed 's/-.*//'`
;;
+ zip*)
+ cpu=zip
+ ;;
*-*)
# shellcheck disable=SC2162
@@ -1250,7 +1258,7 @@
| x86 | x86_64 | xc16x | xgate | xps100 \
| xstormy16 | xtensa* \
| ymp \
- | z8k | z80)
+ | z8k | z80 | zip)
;;
*)
@@ -1511,6 +1519,8 @@
;;
*-eabi)
;;
+ zip*)
+ ;;
*)
echo Invalid configuration \`"$1"\': system \`"$os"\' not recognized 1>&2
exit 1
diff -Naur '--exclude=*.swp' gcc-10.3.0/configure gcc-10.3.0-zip/configure
--- gcc-10.3.0/configure 2021-04-08 07:56:27.581734786 -0400
+++ gcc-10.3.0-zip/configure 2021-05-10 15:57:39.959087492 -0400
@@ -3404,6 +3404,11 @@
ft32-*-*)
noconfigdirs="$noconfigdirs target-libstdc++-v3"
;;
+ zip*)
+ noconfigdirs="$noconfigdirs ${libgcj}}"
+ noconfigdirs="$noconfigdirs target-boehm-gc"
+ noconfigdirs="$noconfigdirs target-libgfortran"
+ ;;
esac
fi
@@ -3614,6 +3619,9 @@
bpf-*-*)
noconfigdirs="$noconfigdirs target-libgo"
;;
+ zip*)
+ noconfigdirs="$noconfigdirs target-libgo"
+ ;;
esac
fi
@@ -4023,6 +4031,9 @@
wasm32-*-*)
noconfigdirs="$noconfigdirs ld"
;;
+ zip*)
+ noconfigdirs="$noconfigdirs target-libobjc target-libssp target-libffi target-boehm-gc gdb gprof"
+ ;;
esac
# If we aren't building newlib, then don't build libgloss, since libgloss
@@ -6938,7 +6949,7 @@
# CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
if test "x$CFLAGS_FOR_TARGET" = x; then
if test "x${is_cross_compiler}" = xyes; then
- CFLAGS_FOR_TARGET="-g -O2"
+ CFLAGS_FOR_TARGET="-O3"
else
CFLAGS_FOR_TARGET=$CFLAGS
case " $CFLAGS " in
@@ -6955,7 +6966,7 @@
if test "x$CXXFLAGS_FOR_TARGET" = x; then
if test "x${is_cross_compiler}" = xyes; then
- CXXFLAGS_FOR_TARGET="-g -O2"
+ CXXFLAGS_FOR_TARGET="-O3"
else
CXXFLAGS_FOR_TARGET=$CXXFLAGS
case " $CXXFLAGS " in
diff -Naur '--exclude=*.swp' gcc-10.3.0/configure.ac gcc-10.3.0-zip/configure.ac
--- gcc-10.3.0/configure.ac 2021-04-08 07:56:27.581734786 -0400
+++ gcc-10.3.0-zip/configure.ac 2021-04-12 15:13:12.907436010 -0400
@@ -889,6 +889,9 @@
bpf-*-*)
noconfigdirs="$noconfigdirs target-libgo"
;;
+ zip*)
+ noconfigdirs="$noconfigdirs target-libgo"
+ ;;
esac
fi
diff -Naur '--exclude=*.swp' gcc-10.3.0/gcc/common/config/zip/zip-common.c gcc-10.3.0-zip/gcc/common/config/zip/zip-common.c
--- gcc-10.3.0/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
+++ gcc-10.3.0-zip/gcc/common/config/zip/zip-common.c 2025-01-18 17:59:20.285130520 -0500
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: sw/gcc-10.3.0-zip/gcc/common/config/zip/zip-common.c
+// {{{
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
+//
+// Purpose: To eliminate the frame register automatically.
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Copyright (C) 2016-2025, Gisselquist Technology, LLC
+// {{{
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+// }}}
+// License: GPL, v3, as defined and found on www.gnu.org,
+// {{{
+// http://www.gnu.org/licenses/gpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+
+static const struct default_options zip_option_optimization_table[] =
+ {
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff -Naur '--exclude=*.swp' gcc-10.3.0/gcc/compare-elim.c gcc-10.3.0-zip/gcc/compare-elim.c
--- gcc-10.3.0/gcc/compare-elim.c 2021-04-08 07:56:28.029740197 -0400
+++ gcc-10.3.0-zip/gcc/compare-elim.c 2021-05-23 18:18:43.674541504 -0400
@@ -254,8 +254,12 @@
comparison code that is outer to the actual flags use. */
loc = DF_REF_LOC (use);
x = PATTERN (insn);
+
if (GET_CODE (x) == PARALLEL)
x = XVECEXP (x, 0, 0);
+ if (GET_CODE (x) == UNSPEC_VOLATILE)
+ goto fail;
+
x = SET_SRC (x);
if (GET_CODE (x) == IF_THEN_ELSE)
x = XEXP (x, 0);
diff -Naur '--exclude=*.swp' gcc-10.3.0/gcc/config/zip/genzipops.c gcc-10.3.0-zip/gcc/config/zip/genzipops.c
--- gcc-10.3.0/gcc/config/zip/genzipops.c 1969-12-31 19:00:00.000000000 -0500
+++ gcc-10.3.0-zip/gcc/config/zip/genzipops.c 2025-01-18 17:59:00.705498854 -0500
@@ -0,0 +1,702 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: sw/gcc-10.3.0-zip/gcc/config/zip/genzipops.c
+// {{{
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
+//
+// Purpose: This program generates the zip-ops.md machine description file.
+//
+// While I understand that this is not GCC's preferred method of generating
+// machine description files, there were just so many instructions to
+// generate, and so many forms of them, and the GCC infrastructure didn't
+// support the conditional execution model of the ZipCPU that ... I built
+// it this way.
+//
+// As of this writing, building zip-ops.md is not an automatic part of
+// making GCC. To build genzipops, just type:
+//
+// g++ genzipops.c -o genzipops
+//
+// And to run it, type:
+//
+// genzipops > zip-ops.md
+//
+// genzipops takes no arguments, and does nothing but write the machine
+// descriptions to the standard output.
+//
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Copyright (C) 2017-2025, Gisselquist Technology, LLC
+// {{{
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+// }}}
+// License: GPL, v3, as defined and found on www.gnu.org,
+// {{{
+// http://www.gnu.org/licenses/gpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// }}}
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+// legal(FILE *fp)
+// {{{
+void legal(FILE *fp) {
+ fprintf(fp, ""
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";;\n"
+";; Filename: zip-ops.md\n"
+";; {{{\n"
+";; Project: Zip CPU -- a small, lightweight, RISC CPU soft core\n"
+";;\n"
+";; Purpose: This is a computer generated machine description of the\n"
+";; ZipCPU\'s operations. It is computer generated simply for\n"
+";; two reasons. First, I can\'t seem to find a way to generate this\n"
+";; information within GCC\'s current constructs. Specifically, the\n"
+";; CPU\'s instructions normally set the condition codes, unless they\n"
+";; are conditional instructions when they don\'t. Second, the ZipCPU is\n"
+";; actually quite regular. Almost all of the instructions have the same\n"
+";; form. This form turns into many, many RTL instructions. Because the\n"
+";; CPU doesn\'t match any of the others within GCC, that means either\n"
+";; I have a *lot* of cut, copy, paste, and edit to do to create the file\n"
+";; and upon any and every edit, or I need to build a program to generate\n"
+";; the remaining .md constructs. Hence, I chose the latter to minimize\n"
+";; the amount of work I needed to do.\n"
+";;\n"
+";;\n"
+";; Creator: Dan Gisselquist, Ph.D.\n"
+";; Gisselquist Technology, LLC\n"
+";;\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";; }}}\n"
+";; Copyright (C) 2017-2024, Gisselquist Technology, LLC\n"
+";; {{{\n"
+";; This program is free software (firmware): you can redistribute it and/or\n"
+";; modify it under the terms of the GNU General Public License as published\n"
+";; by the Free Software Foundation, either version 3 of the License, or (at\n"
+";; your option) any later version.\n"
+";;\n"
+";; This program is distributed in the hope that it will be useful, but WITHOUT\n"
+";; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
+";; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\n"
+";; for more details.\n"
+";; }}}\n"
+";; License: GPL, v3, as defined and found on www.gnu.org,\n"
+";; {{{\n"
+";; http://www.gnu.org/licenses/gpl.html\n"
+";;\n"
+";;\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";;\n"
+";;\n");
+}
+// }}}
+// }}}
+
+// gen_heading(FILE *fp, heading)
+// {{{
+void gen_heading(FILE *fp, const char *heading) {
+ fprintf(fp, ";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n"
+"; %s\n"
+"; {{{\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n;\n", heading);
+}
+// }}}
+// }}}
+
+// genzip_condop -- generate a conditional operation definition
+// {{{
+void genzip_condop_off(FILE *fp, const char *md_opname,
+ const char *rtxstr, const char *insn_cond,
+ const char *zip_op,
+ const char *rtx_cond, const char *zip_cond, int offset) {
+ char defineinsn[2048], *ptr;
+
+ // First definition via if-then-else
+ // {{{
+ sprintf(defineinsn, "(define_insn \"%s_%s\"\n"
+"\t[(set (match_operand:SI 0 \"register_operand\" \"=r,\?r\")\n"
+"\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n\t\t",
+ md_opname, rtx_cond, rtx_cond);
+ if (offset) {
+ sprintf(&defineinsn[strlen(defineinsn)], rtxstr,
+ "match_operand:SI 1 \"register_operand\" \"0,r\"",
+ "plus:SI (match_operand:SI 2 \"register_operand\" \"r,r\")\n"
+ "\t\t\t(match_operand:SI 3 \"zip_opb_immv_p\" \"N,N\")");
+ } else {
+ sprintf(&defineinsn[strlen(defineinsn)], rtxstr,
+ "match_operand:SI 1 \"register_operand\" \"0,r\"",
+ "match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO,r\"");
+ }
+ strcat(defineinsn, "\n\t\t(match_dup 1)))]\n");
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\"%s\"\t; Condition\n", insn_cond);
+
+ strcat(defineinsn, "\t{\n"
+ "\t\tif (REGNO(operands[0])!=REGNO(operands[1])) {\n");
+ if (offset) {
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\tif (REG_P(operands[2]))\n"
+ "\t\t\t\tgcc_assert(REGNO(operands[0])!=REGNO(operands[2]));\n");
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\treturn \"MOV.%s\\t%%1,%%0\\n\"\n"
+ "\t\t\t\t\"\\t%s.%s\\t%%3+%%2,%%0\\t; %s_%s\";\n"
+ "\t\t} else\n"
+ "\t\t\treturn \"%s.%s\\t%%3+%%2,%%0\t; %s_%s\";\n"
+ "\t}\n",
+ zip_cond, zip_op, zip_cond, md_opname, rtx_cond,
+ zip_op, zip_cond, md_opname, rtx_cond);
+ } else {
+ if (strcmp(zip_op, "SUB") == 0 || strcmp(zip_op, "DIVS") == 0
+ || strcmp(zip_op, "DIVU") == 0
+ || strcmp(zip_op, "LSR") == 0
+ || strcmp(zip_op, "LSL") == 0
+ || strcmp(zip_op, "ASR") == 0)
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\tif (REG_P(operands[2]))\n"
+ "\t\t\t\tgcc_assert(REGNO(operands[0])!=REGNO(operands[2]));\n"
+ "\t\t\treturn \"MOV.%s\\t%%1,%%0\\n\\t%s.%s\\t%%2,%%0\\t; %s_%s (mov-first)\";\n"
+ "\t\t} else\n",
+ zip_cond, zip_op, zip_cond, md_opname, rtx_cond);
+ else
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\tif (REG_P(operands[2]) && REGNO(operands[0]) == REGNO(operands[2]))\n"
+ "\t\t\t\treturn \"%s.%s\\t%%1,%%0\\t; %s_%s (swapped)\";\n"
+ "\t\t\telse\n"
+ "\t\t\t\treturn \"MOV.%s\\t%%1,%%0\\n\\t%s.%s\\t%%2,%%0\\t; %s_%s (pre-move)\";\n"
+ "\t\t} else\n",
+ zip_op, zip_cond, md_opname, rtx_cond,
+ zip_cond, zip_op, zip_cond, md_opname, rtx_cond);
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\treturn \"%s.%s\\t%%2,%%0\t; %s_%s (primary)\";\n"
+ "\t}\n",
+ zip_op, zip_cond, md_opname, rtx_cond);
+ }
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t[(set_attr \"predicable\" \"no\") "
+ "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n");
+
+ fputs(defineinsn, fp);
+ // }}}
+
+ // Second definition via cond-exec
+ // {{{
+ sprintf(defineinsn, "(define_insn \"%s_c%s\"\n"
+"\t[(cond_exec (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t(set (match_operand:SI 0 \"register_operand\" \"=r,\?r\")\n\t\t",
+ md_opname, rtx_cond, rtx_cond);
+
+ if (offset) {
+ sprintf(&defineinsn[strlen(defineinsn)], rtxstr,
+ "match_operand:SI 1 \"register_operand\" \"0,r\"",
+ "plus:SI (match_operand:SI 2 \"register_operand\" \"r,r\")\n"
+ "\t\t\t(match_operand:SI 3 \"zip_opb_immv_p\" \"N,N\")");
+ } else {
+ sprintf(&defineinsn[strlen(defineinsn)], rtxstr,
+ "match_operand:SI 1 \"register_operand\" \"0,r\"",
+ "match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO,r\"");
+ }
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "))]\n\t\"%s\"\t; Condition\n", insn_cond);
+
+ strcat(defineinsn, "\t{\n"
+ "\t\tif (REGNO(operands[0])!=REGNO(operands[1])) {\n"
+ "\t\t\tif (REG_P(operands[2]))\n"
+ "\t\t\t\tgcc_assert(REGNO(operands[0])!=REGNO(operands[2]));\n");
+ if (offset) {
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\treturn \"MOV.%s\\t%%1,%%0\\n\"\n"
+ "\t\t\t\t\"\\t%s.%s\\t%%3+%%2,%%0\\t; %s_c%s\";\n"
+ "\t\t} else\n"
+ "\t\t\treturn \"%s.%s\\t%%3+%%2,%%0\t; %s_c%s\";\n"
+ "\t}\n",
+ zip_cond, zip_op, zip_cond, md_opname, rtx_cond,
+ zip_op, zip_cond, md_opname, rtx_cond);
+ } else {
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\t\treturn \"MOV.%s\\t%%1,%%0\\n\\t%s.%s\\t%%2,%%0\\t; %s_%s\";\n"
+ "\t\t} else\n"
+ "\t\t\treturn \"%s.%s\\t%%2,%%0\t; %s_c%s\";\n"
+ "\t}\n",
+ zip_cond, zip_op, zip_cond, md_opname, rtx_cond,
+ zip_op, zip_cond, md_opname, rtx_cond);
+ }
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t[(set_attr \"predicable\" \"no\") "
+ "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n");
+
+ fputs(defineinsn, fp);
+ // }}}
+}
+
+void genzip_condop(FILE *fp, const char *md_opname,
+ const char *rtxstr, const char *insn_cond,
+ const char *zip_op,
+ const char *rtx_cond, const char *zip_cond) {
+
+ genzip_condop_off(fp, md_opname, rtxstr, insn_cond,
+ zip_op, rtx_cond, zip_cond, 0);
+}
+
+// }}}
+
+// genzipop_long
+// {{{
+void genzipop_long(FILE *fp, const char *md_opname, const char *insn_rtx,
+ const char *insn_cond, const char *zip_op) {
+ char heading[128], defineinsn[1024], *ptr;
+
+ sprintf(heading, "%s (genzipop_long)", zip_op);
+ // {{{
+ fprintf(fp, "; }}}\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n"
+"; %s (genzipop_long)\n"
+"; {{{\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n;\n", zip_op);
+ // }}}
+
+ //
+ // First time through, we clobber the CC register
+ //
+ sprintf(defineinsn, "(define_insn \"%s\"\n"
+"\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n\t\t", md_opname);
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx,
+ "match_operand:SI 1 \"register_operand\" \"0\"",
+ "match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\"");
+ strcat(defineinsn, ")\n\t(clobber (reg:CC CC_REG))]\n");
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\"%s\"\n"
+ "\t\"%s\\t%%2,%%0\t; %s (from genzipop_long)\"\n"
+ "\t[(set_attr \"predicable\" \"yes\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
+ insn_cond, zip_op, md_opname);
+ fputs(defineinsn, fp);
+
+ //
+ // Second version sets the CC register
+ //
+ sprintf(defineinsn, "(define_insn \"%s_raw\"\n"
+"\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n\t\t", md_opname);
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx,
+ "match_operand:SI 1 \"register_operand\" \"0\"",
+ "match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\"");
+ strcat(defineinsn, ")\n"
+ "\t(set (reg:CC CC_REG) (compare:CC\n\t\t");
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx, "match_dup 1",
+ "match_dup 2");
+ strcat(defineinsn, " (const_int 0)))]\n");
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ "\t\"%s\"\n"
+ "\t\"%s\\t%%2,%%0\t; %s (from genzipop_long)\"\n"
+ "\t[(set_attr \"predicable\" \"yes\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
+ insn_cond, zip_op, md_opname);
+
+ fputs(defineinsn, fp);
+
+
+ //
+ // Now repeat the above, w/o setting CC, for all possible conditions
+ //
+
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "eq", "Z");
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "ne", "NZ");
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "lt", "LT");
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "ge", "GE");
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "ltu", "C");
+ genzip_condop(fp, md_opname, insn_rtx, insn_cond, zip_op, "geu", "NC");
+}
+// }}}
+
+// genzipop_long_offset (long operation, but with an offset)
+// {{{
+void genzipop_long_offset(FILE *fp, const char *md_opname,
+ const char *insn_rtx, const char *insn_cond,
+ const char *zip_op) {
+ char heading[128], defineinsn[4096];
+
+ sprintf(heading, "%s (genzipop_long_offset)", zip_op);
+ // {{{
+ fprintf(fp, "; }}}\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n"
+"; %s (genzipop_long_offset)\n"
+"; {{{\n"
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
+";\n;\n", zip_op);
+ // }}}
+
+ // As before, the first time through we clobber the CC register
+ sprintf(defineinsn, "(define_insn \"%s\"\n"
+"\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n\t\t", md_opname);
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx,
+ "match_operand:SI 1 \"register_operand\" \"0\"",
+ "plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
+ "\t\t\t(match_operand:SI 3 \"zip_opb_immv_p\" \"N\")");
+
+ sprintf(&defineinsn[strlen(defineinsn)],
+ ")\n\t(clobber (reg:CC CC_REG))]\n"
+ "\t\"%s\"\n"
+ "\t\"%s\\t%%3+%%2,%%0\t; %s from genzipop_long_offset\"\n"
+"\t[(set_attr \"predicable\" \"yes\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
+ insn_cond, zip_op, md_opname);
+
+ fputs(defineinsn, fp);
+
+
+ sprintf(defineinsn, "(define_insn \"%s_raw\"\n"
+"\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n\t\t", md_opname);
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx,
+ "match_operand:SI 1 \"register_operand\" \"0\"",
+ "plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
+ "\t\t\t(match_operand:SI 3 \"zip_opb_immv_p\" \"N\")");
+ sprintf(&defineinsn[strlen(defineinsn)], ")\n"
+ "\t(set (reg:CC CC_REG) (compare:CC\n\t\t");
+ sprintf(&defineinsn[strlen(defineinsn)], insn_rtx,
+ "match_dup 1", "plus:SI (match_dup 2) (match_dup 3)");
+ sprintf(&defineinsn[strlen(defineinsn)], "\n\t\t(const_int 0)))]\n"
+"\t\"%s\"\n"
+"\t\"%s\\t%%2+%%1,%%0\t; %s_raw from genzipop_long_offset\"\n"
+"\t[(set_attr \"predicable\" \"yes\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
+ insn_cond, zip_op, md_opname);
+
+ fputs(defineinsn, fp);
+
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "eq", "Z", 1);
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "ne", "NZ", 1);
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "lt", "LT", 1);
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "ge", "GE", 1);
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "ltu", "C", 1);
+ genzip_condop_off(fp, md_opname, insn_rtx, insn_cond, zip_op, "geu", "NC", 1);
+}
+// }}}
+
+// genzipop
+// {{{
+void genzipop(FILE *fp, const char *md_opname, const char *rtx_name, const char *insn_cond, const char *zip_op) {
+ char rtxstr[512], altname[64];
+
+ sprintf(rtxstr, "(%s (%%s)\n\t\t(%%s))", rtx_name);
+/*
+ sprintf(splitstr,
+ "(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))", rtx_name);
+*/
+
+ genzipop_long(fp, md_opname, rtxstr, insn_cond, zip_op);
+
+/*
+ sprintf(rtxstr, "(%s (%%s)\n\t\t\t(plus:SI (%%s)\n"
+ "\t\t\t\t(%%s)))", rtx_name);
+*/
+ sprintf(altname, "%s_off", md_opname);
+
+ genzipop_long_offset(fp, altname, rtxstr, insn_cond, zip_op);
+}
+// }}}
+
+// gencmov -- generate for a conditional move
+// {{{
+void gencmov(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"nonimmediate_operand\" \"=r,r,r,Q\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(match_operand:SI 1 \"general_operand\" \"r,Q,i,r\")\n"
+ "\t\t\t(match_operand:SI 2 \"nonimmediate_operand\" \"0,0,0,0\")))]\n"
+ "\t\"\"\n"
+ "\t\"@\n"
+ "\tMOV.%s\t%%1,%%0\t; cmov\n"
+ "\tLW.%s\t%%1,%%0\t; cmov\n"
+ "\tLDI.%s\t%%1,%%0\t; cmov\n"
+ "\tSW.%s\t%%1,%%0\t; cmov\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond, zip_cond, zip_cond, zip_cond, zip_cond);
+
+}
+// }}}
+
+// gencadd
+// {{{
+void gencadd(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r,?r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(plus:SI (match_operand:SI 1 \"register_operand\" \"0,r\")\n"
+ "\t\t\t\t(match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO,O\"))\n"
+ "\t\t\t(match_operand:SI 3 \"register_operand\" \"0,r\")))]\n"
+ "\t\"\"\n"
+ "\t{\n"
+ "\t\tif (REGNO(operands[0])!=REGNO(operands[1])) {\n"
+ "\t\t\tif (REG_P(operands[2]))\n"
+ "\t\t\t\tgcc_assert(REGNO(operands[0])!=REGNO(operands[2]));\n"
+ "\t\t\treturn \"MOV.%s\\t%%1,%%0\\n"
+ "ADD.%s\\t%%2,%%0\\t; %s_%s\";\n"
+ "\t\t} else\n"
+ "\t\t\treturn \"ADD.%s\\t%%2,%%0\t; %s_%s\";\n"
+ "\t}\n"
+ // "\t\"ADD.%s\t%%2,%%0\t; cadd\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond,
+ zip_cond, zip_cond, md_opname, md_cond,
+ zip_cond, md_opname, md_cond);
+}
+// }}}
+
+// gencnot -- a conditional unary not operand
+// {{{
+void gencnot(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(xor:SI (match_operand:SI 1 \"register_operand\" \"0\")\n"
+ "\t\t\t\t(const_int -1))\n"
+ "\t\t\t(match_operand:SI 2 \"register_operand\" \"0\")))]\n"
+ "\t\"\"\n"
+ "\t\"NOT.%s\t%%0\t; cnot\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond, zip_cond);
+}
+// }}}
+
+// gencneg -- a conditional negate
+// {{{
+void gencneg(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(neg:SI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
+ "\t\t\t(match_operand:SI 2 \"register_operand\" \"0\")))]\n"
+ "\t\"\"\n"
+ "\t\"NEG.%s\t%%0\t; cneg\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")\n\t\t(set_attr \"cost\" \"2\")])\n",
+ md_opname, md_cond, md_cond, zip_cond);
+}
+// }}}
+
+// gencand -- a conditional bit-wise AND
+// {{{
+void gencand(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(and:SI (match_operand:SI 1 \"register_operand\" \"0\") (match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\"))\n"
+ "\t\t\t(match_operand:SI 3 \"register_operand\" \"0\")))]\n"
+ "\t\"\"\n"
+ "\t\"AND.%s\t%%2,%%0\t; cand\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond, zip_cond);
+}
+// }}}
+
+// gencior -- conditional bit-wise OR
+// {{{
+void gencior(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(ior:SI (match_operand:SI 1 \"register_operand\" \"0\") (match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\"))\n"
+ "\t\t\t(match_operand:SI 3 \"register_operand\" \"0\")))]\n"
+ "\t\"\"\n"
+ "\t\"OR.%s\t%%2,%%0\t; cior\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond, zip_cond);
+}
+// }}}
+
+// gencxor -- conditional XOR
+// {{{
+void gencxor(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
+ fprintf(fp, ";\n;\n"
+"(define_insn \"%s_%s\"\n"
+ "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
+ "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
+ "\t\t\t(xor:SI (match_operand:SI 1 \"register_operand\" \"0\") (match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\"))\n"
+ "\t\t\t(match_operand:SI 3 \"register_operand\" \"0\")))]\n"
+ "\t\"\"\n"
+ "\t\"XOR.%s\t%%2,%%0\t; cxor\"\n"
+ "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
+ md_opname, md_cond, md_cond, zip_cond);
+}
+// }}}
+
+// usage()
+// {{{
+void usage(void) {
+ printf("USAGE: genzipops <new-zip-ops.md filename>\n");
+}
+// }}}
+
+const char *TMPPATH = ".zip-ops.md";
+const char *TAILPATH = "zip-ops.md";
+
+// main
+// {{{
+int main(int argc, char **argv) {
+ FILE *fp = fopen(TMPPATH, "w");
+ const char *newname = TAILPATH;
+
+ // Argument handling
+ // {{{
+ if ((argc>1)&&(argv[1][0] == '-')) {
+ usage();
+ exit(EXIT_FAILURE);
+ }
+
+ if (argc>1) {
+ if ((strlen(argv[1])>=strlen(TAILPATH))
+ &&(strcmp(&argv[1][strlen(argv[1])-strlen(TAILPATH)],
+ TAILPATH)==0)
+ &&(access(argv[1], F_OK)==0))
+ unlink(argv[1]);
+ newname = argv[1];
+ }
+ // }}}
+
+ legal(fp);
+ genzipop(fp, "addsi3", "plus:SI", "", "ADD");
+ genzipop(fp, "subsi3", "minus:SI", "", "SUB");
+ genzipop(fp, "mulsi3", "mult:SI", "", "MPY");
+ genzipop(fp, "divsi3", "div:SI", "(ZIP_DIVIDE)", "DIVS");
+ genzipop(fp, "udivsi3", "udiv:SI", "(ZIP_DIVIDE)", "DIVU");
+ genzipop(fp, "andsi3", "and:SI", "", "AND");
+ genzipop(fp, "iorsi3", "ior:SI", "", "OR");
+ genzipop(fp, "xorsi3", "xor:SI", "", "XOR");
+ genzipop(fp, "ashrsi3", "ashiftrt:SI","", "ASR");
+ genzipop(fp, "ashlsi3", "ashift:SI", "", "LSL");
+ genzipop(fp, "lshrsi3", "lshiftrt:SI","", "LSR");
+
+ genzipop_long(fp, "smulsi_highpart",
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
+ "\t\t(sign_extend:DI (%s))\n"
+ "\t\t\t(sign_extend:DI (%s)))\n"
+ "\t\t\t(const_int 32)))",
+ "(ZIP_HAS_DI)",
+ "MPYSHI");
+ genzipop_long(fp, "umulsi_highpart",
+ "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
+ "\t\t\t(zero_extend:DI (%s))\n"
+ "\t\t\t(zero_extend:DI (%s)))\n"
+ "\t\t\t(const_int 32)))",
+ "(ZIP_HAS_DI)",
+ "MPYUHI");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional move instructions");
+
+ gencmov(fp, "cmov", "eq", "Z");
+ gencmov(fp, "cmov", "ne", "NZ");
+ gencmov(fp, "cmov", "lt", "LT");
+ gencmov(fp, "cmov", "ge", "GE");
+ gencmov(fp, "cmov", "ltu", "C");
+ gencmov(fp, "cmov", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional add instructions");
+
+ gencadd(fp, "cadd", "eq", "Z");
+ gencadd(fp, "cadd", "ne", "NZ");
+ gencadd(fp, "cadd", "lt", "LT");
+ gencadd(fp, "cadd", "ge", "GE");
+ gencadd(fp, "cadd", "ltu", "C");
+ gencadd(fp, "cadd", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional not instructions");
+
+ gencnot(fp, "cnot", "eq", "Z");
+ gencnot(fp, "cnot", "ne", "NZ");
+ gencnot(fp, "cnot", "lt", "LT");
+ gencnot(fp, "cnot", "ge", "GE");
+ gencnot(fp, "cnot", "ltu", "C");
+ gencnot(fp, "cnot", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional negate instructions");
+
+ gencneg(fp, "cneg", "eq", "Z");
+ gencneg(fp, "cneg", "ne", "NZ");
+ gencneg(fp, "cneg", "lt", "LT");
+ gencneg(fp, "cneg", "ge", "GE");
+ gencneg(fp, "cneg", "ltu", "C");
+ gencneg(fp, "cneg", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional and instructions");
+
+ gencand(fp, "cand", "eq", "Z");
+ gencand(fp, "cand", "ne", "NZ");
+ gencand(fp, "cand", "lt", "LT");
+ gencand(fp, "cand", "ge", "GE");
+ gencand(fp, "cand", "ltu", "C");
+ gencand(fp, "cand", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional ior instructions");
+
+ gencior(fp, "cior", "eq", "Z");
+ gencior(fp, "cior", "ne", "NZ");
+ gencior(fp, "cior", "lt", "LT");
+ gencior(fp, "cior", "ge", "GE");
+ gencior(fp, "cior", "ltu", "C");
+ gencior(fp, "cior", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ gen_heading(fp, "Conditional xor instructions");
+
+ gencxor(fp, "cxor", "eq", "Z");
+ gencxor(fp, "cxor", "ne", "NZ");
+ gencxor(fp, "cxor", "lt", "LT");
+ gencxor(fp, "cxor", "ge", "GE");
+ gencxor(fp, "cxor", "ltu", "C");
+ gencxor(fp, "cxor", "geu", "NC");
+
+ // {{{
+ fprintf(fp, "; }}}\n");
+ fclose(fp);
+
+ if (rename(TMPPATH, newname) != 0) {
+ fprintf(stderr, "ERR: Could not create %s, leaving results in %s\n", newname, TMPPATH);
+ exit(EXIT_FAILURE);
+ } exit(EXIT_SUCCESS);
+}
+// }}}
diff -Naur '--exclude=*.swp' gcc-10.3.0/gcc/config/zip/zip.c gcc-10.3.0-zip/gcc/config/zip/zip.c
--- gcc-10.3.0/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
+++ gcc-10.3.0-zip/gcc/config/zip/zip.c 2025-01-27 14:21:33.566386291 -0500
@@ -0,0 +1,3513 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: sw/gcc-10.3.0-zip/gcc/config/zip/zip.c
+// {{{
+// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
+//
+// Purpose:
+//
+// Creator: Dan Gisselquist, Ph.D.
+// Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Copyright (C) 2016-2025, Gisselquist Technology, LLC
+// {{{
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program. (It's in the $(ROOT)/doc directory. Run make with no
+// target there if the PDF file isn't present.) If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+// }}}
+// License: GPL, v3, as defined and found on www.gnu.org,
+// {{{
+// http://www.gnu.org/licenses/gpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Includes
+// {{{
+#define IN_TARGET_CODE 1
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "rtl.h"
+#include "function.h"
+#include "dominance.h"
+#include "cfg.h"
+#include "cfgrtl.h"
+#include "cfganal.h"
+#include "lcm.h"
+#include "cfgbuild.h"
+#include "cfgcleanup.h"
+#include "predict.h"
+#include "basic-block.h"
+#include "bitmap.h"
+#include "df.h"
+#include "hashtab.h"
+#include "hash-set.h"
+#include "machmode.h"
+#include "symtab.h"
+#include "rtlhash.h"
+#include "tree.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "expr.h"
+#include "function.h"
+#include "recog.h"
+#include "toplev.h"
+#include "ggc.h"
+#include "builtins.h"
+#include "calls.h"
+#include "langhooks.h"
+#include "memmodel.h"
+#include "optabs.h"
+#include "explow.h"
+#include "emit-rtl.h"
+#include "ifcvt.h"
+#include "genrtl.h"
+#include "stor-layout.h"
+#include "stringpool.h"
+#include "attribs.h"
+
+// #include "tmp_p.h"
+#include "target.h"
+#include "target-def.h"
+// #include "tm-constrs.h"
+#include "tm-preds.h"
+
+#include "diagnostic.h"
+// #include "integrate.h"
+
+#include "zip-protos.h"
+// }}}
+
+// Function prototypes
+// {{{
+static bool zip_return_in_memory(const_tree, const_tree);
+static bool zip_frame_pointer_required(void);
+
+static void zip_function_arg_advance(cumulative_args_t ca,
+ const function_arg_info &arg);