Support for Huawei Matebook E Go (sc8280xp tablet with mipi-dsi panel)

[matalama80td3l]

This issue is approximately about sc8280xp's dsi support.
ACPI tables here: matebook-e-go-acpi-tables.

It is a tablet with a dual-dsi panel CSOT PPC357DB1(driven by himax hx83121 chip). Sadly there is no mdss-dsi description in sc8280xp.dtsi until now in mainline linux. So I tried to merge mdss-dsi descriptions from sm8350.dtsi into sc8280xp.dtsi and it didnt work.

---

WHAT I HAD DONE

source from steev/linux/lenovo-x13s-6.4.y

1. Try to add dsi support in sc8280xp.dtsi, code can be found here.
2. Create a new dts for matebook-e-go based on x13s's dts, code here.
3. Because PPC357DB1 panel is also used in Samsung galaxy tab s7 FE, get its source and trans it to a panel driver using lmdpdg. Driver code here.

---

PROBLEMS

Boot from a usb hdd.
Kernel is booted successfully because dmesg and syslog appear in /var/log. Screen keeps black with a little backlight after grub. Push power button twice can turn the device off.

errors occured and some attempts to fix them

Error:

efifb: invalid framebuffer address  

So there's no kernel boot info being printed to screen. Ignored because syslog can be viewed.

---

Error:

msm_dsi_host_init: get config failed   
msm_dsi: probe of ae94000.dsi failed with error -22  

This is because msm_dsi_host_init gets sc8280xp dsi version 0x20050001 that is not configured in drivers/gpu/drm/msm/dsi/dsi_cfg.h. Then I add it into dsi_cfg.h and dsi_cfg.c.

Fix attempts:

Add

#define MSM_DSI_6G_VER_MINOR_V2_5_1 0x20050001

into dsi_cfg.h

Add

{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_1, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}  

into dsi_cfg_handlers[]

I'm not sure if using sc7280_dsi_cfg is proper.

It seems work and then ...

---

Error:

dsi_link_clk_set_rate_6g: Failed to set rate pixel clk, -22

I tried to trace the rate settings of the pixel clk's clock tree. Log here:

[    0.947206] kernel: dsi_get_pclk_rate: pixel clock rate now is 281848000
[    0.947301] kernel: dsi_mgr_phy_enable: single dsi, id is 0
[    0.948407] kernel: dsi_get_pclk_rate: pixel clock rate now is 281848000
[    0.948410] kernel: dsi_get_pclk_rate: pixel clock rate now is 281848000
[    0.948811] kernel: dsi_7nm_pll_restore_state:set dsi_pll rate when restore
[    0.948813] kernel: dsi_pll_7nm_vco_set_rate:DSI PLL0 rate=0, parent's=19200000
[    0.949200] kernel: clk_calc_new_rates: now calc clk: disp0_cc_mdss_byte0_clk, its parent clk: disp0_cc_mdss_byte0_clk_src, its rate: 0, its req_rate:105693000
[    0.949204] kernel: clk_calc_new_rates: disp0_cc_mdss_byte0_clk pass-through clock with adjustable parent
[    0.949205] kernel: clk_calc_new_rates: now calc clk: disp0_cc_mdss_byte0_clk_src, its parent clk: dsi0_phy_pll_out_byteclk, its rate: 0, its req_rate:105693000
[    0.949207] kernel: clk_calc_new_rates: disp0_cc_mdss_byte0_clk_src clk_core_can_round is TRUE
[    0.949210] kernel: clk_calc_new_rates: disp0_cc_mdss_byte0_clk_src new rate is 105693000, req.rate is 105693000 and parent is dsi0_phy_pll_out_byteclk
[    0.949226] kernel: clk_calc_new_rates: set disp0_cc_mdss_byte0_clk_src parent dsi0_phy_pll_out_byteclk rate: 105693000
[    0.949227] kernel: clk_calc_new_rates: now calc clk: dsi0_phy_pll_out_byteclk, its parent clk: dsi0_pll_bit_clk, its rate: 0, its req_rate:105693000
[    0.949229] kernel: clk_calc_new_rates: dsi0_phy_pll_out_byteclk clk_core_can_round is TRUE
[    0.949232] kernel: clk_calc_new_rates: dsi0_phy_pll_out_byteclk new rate is 105693000, req.rate is 105693000 and parent is dsi0_pll_bit_clk
[    0.949234] kernel: clk_calc_new_rates: set dsi0_phy_pll_out_byteclk parent dsi0_pll_bit_clk rate: 739851000
[    0.949235] kernel: clk_calc_new_rates: now calc clk: dsi0_pll_bit_clk, its parent clk: dsi0_pll_out_div_clk, its rate: 0, its req_rate:739851000
[    0.949237] kernel: clk_calc_new_rates: dsi0_pll_bit_clk clk_core_can_round is TRUE
[    0.949240] kernel: clk_calc_new_rates: dsi0_pll_bit_clk new rate is 739851000, req.rate is 739851000 and parent is dsi0_pll_out_div_clk
[    0.949241] kernel: clk_calc_new_rates: set dsi0_pll_bit_clk parent dsi0_pll_out_div_clk rate: 739851000
[    0.949242] kernel: clk_calc_new_rates: now calc clk: dsi0_pll_out_div_clk, its parent clk: dsi0vco_clk, its rate: 0, its req_rate:739851000
[    0.949244] kernel: clk_calc_new_rates: dsi0_pll_out_div_clk clk_core_can_round is TRUE
[    0.949245] kernel: clk_calc_new_rates: dsi0_pll_out_div_clk new rate is 739851000, req.rate is 739851000 and parent is dsi0vco_clk
[    0.949246] kernel: clk_calc_new_rates: set dsi0_pll_out_div_clk parent dsi0vco_clk rate: 739851000
[    0.949247] kernel: clk_calc_new_rates: now calc clk: dsi0vco_clk, its parent clk: bi_tcxo, its rate: 0, its req_rate:739851000
[    0.949250] kernel: clk_calc_new_rates: dsi0vco_clk clk_core_can_round is TRUE
[    0.949250] kernel: clk_calc_new_rates: dsi0vco_clk new rate is 739851000, req.rate is 739851000 and parent is bi_tcxo
[    0.949289] kernel: dsi_pll_7nm_vco_set_rate:DSI PLL0 rate=739851000, parent's=19200000
[    0.949389] kernel: clk_calc_new_rates: now calc clk: disp0_cc_mdss_pclk0_clk, its parent clk: disp0_cc_mdss_pclk0_clk_src, its rate: 14092400, its req_rate:281848000
[    0.949391] kernel: clk_calc_new_rates: disp0_cc_mdss_pclk0_clk pass-through clock with adjustable parent
[    0.949392] kernel: clk_calc_new_rates: now calc clk: disp0_cc_mdss_pclk0_clk_src, its parent clk: dsi0_phy_pll_out_dsiclk, its rate: 14092400, its req_rate:281848000
[    0.949394] kernel: clk_calc_new_rates: disp0_cc_mdss_pclk0_clk_src clk_core_can_round is TRUE
[    0.949395] kernel: clk_calc_new_rates: disp0_cc_mdss_pclk0_clk_src clk_core_determine_round_nolock is error -22

I added some debug info and hope you could understand :(
When setting disp0_cc_mdss_pclk0_clk_src's rate, clk_core_determine_round_nolock returns error -22.

If I comment the return of clk_core_determine_round_nolock and let it goes on:

[    1.411392] kernel: dsi_cmds2buf_tx: cmd dma tx failed, type=0x39, data0=0xb1, len=36, ret=-110
[    1.411430] kernel: panel-hx83121-ppc357db11-wqxga ae94000.dsi.0: sending command 0xb1 failed: -110
[    1.411436] kernel: panel-hx83121-ppc357db11-wqxga ae94000.dsi.0: Failed to initialize panel: -110

Full log here. Ignore all those "pixel clock from ...".

I doubt that sc8280xp's dsi controller/phy is not the same address as sm8350's. But it can get the dsi version 0x20050001. I'm quite confused.

Any help is appreciated!

[chenyu0329]

https://gitlab.freedesktop.org/drm/msm/-/issues
They seem to be discussing the panel issue as well?