how to add STM32G07x series?

[laszlokovacs25]

hi,

I'm working on a project where I would like to program an STM32G07x chip with ESP32 but this STM family is not supported now.
Is there a way to add it easily?

I have extended the model here:
struct {
uint32_t mcuid;
const char *name;
} _stm32_devices[] = {
{0x413, "STM32F405xx/07xx and STM32F415xx/17xx"},
{0x419, "STM32F42xxx and STM32F43xxx"},
{0x431, "STM32F411xC/E"},
{0x441, "STM32F412"},
{0x460, "STM32G07x"},
};

but it says:
12:14:47.014 -> Connecting...
12:14:47.014 -> Adafruit Generic CMSIS-DAP Adapter 123456 v0.1 (S)
12:14:47.014 -> No STM32 device found!

thanks

[hathach]

I'm working on a project where I would like to program an STM32G07x chip with ESP32 but this STM family is not supported now. Is there a way to add it easily?

there is only way to add new port: read manual + codebase then update + test it out. Should you get it working, please consider to make an PR

[laszlokovacs25]

thanks for quick answer, I tried few things with the commands and addresses but if you could advice me where and how in the code is the best to start the mods, that would be great.
I tried to find the addresses of the "DAP_DBGMCU_IDCODE " and "STM32_FLASHSIZE " for the stm32f and stm32g families from the data sheet because I think the ID code and the Flash size are under different address on the G family but no succsess.

I'm stuck in this routine, I guess I have to configure this part of the code to be able to discover the G family:

`bool Adafruit_DAP_STM32::select(uint32_t *found_id) {
uint32_t mcuid;

dap_target_prepare();

// Stop the core
dap_write_word(DHCSR, 0xa05f0003);
dap_write_word(DEMCR, 0x00000001);
dap_write_word(AIRCR, 0x05fa0004);

target_device.flash_size = (dap_read_word(STM32_FLASHSIZE) >> 16) * 1024;

*found_id = mcuid = (dap_read_word(DAP_DBGMCU_IDCODE) & 0xFFFUL);
for (int i = 0; i < STM32_DEVICES_COUNT; i++) {
if (mcuid == _stm32_devices[i].mcuid) {
target_device.name = _stm32_devices[i].name;
break;
}
}

if (target_device.name == NULL)
return false;

return true;
}`

[laszlokovacs25]

I have further progress.
If I don't connect the rst pin, the ESP32 can find the STM32G chip.

I can not program it because G family has different FLASH organization.
These are the F family registers, I need to modify these for the G family:

[laszlokovacs25]

New progress, until the nRST pin is connected, the ESP32 can not find the STM, as soon as the nRST pin is disconnected, ESP32 can find the target.

furthermore, these regs must be changed for the G family:

how the flash size been calculated, is different as well:

with these mods, the target is recognised but can't be programed because the programing sequence is different too.
I will need help how to program it.

09:05:59.030 -> Opening file: /G070CB.hex
09:05:59.076 -> Connecting...
09:05:59.076 -> Adafruit Generic CMSIS-DAP Adapter 123456 v0.1 (S)
09:05:59.076 -> Found Target STM32G07x
09:05:59.076 -> Flash size 128 KBs
09:05:59.076 -> Preparing ... done in 146 ms
09:05:59.218 -> Programming 248647 bytes ...invalid response while writing the block
09:06:01.085 -> 4
09:06:01.085 -> invalid response writing to reg 5 (count = 0, value = 4)

the mod needs to be here:

can someone help?

[laszlokovacs25]

New progress, I can flash the STM32G family with the ESP32 but the last 4 bytes are missing every time:

I upload more than 80kb or 5kb the last 4bytes are not written into STM32.

[testerHerbert]

Hi @laszlokovacs25 laszlokovacs25
Could you tell me your solution for the problem in "dap_write_block" which you mentioned on your penultimate post? I am getting the exact same issue (getting a 4 as a response there).
Of course it would also be interesting if you have solved the problem with the last 4 bytes not being written.

[laszlokovacs25]

hi @testerHerbert
I couldn't find the solution in the dap files, I've cheated, I add extra 4bytes to the hex file before I upload it to the STM.
:)

[testerHerbert]

Hi @laszlokovacs25 ,
thanks for the fast answer. I understand the part with the 4 extra bytes as a fix, but how did you solve that issue one post before that the buf[2] is "4"? I get the same issue when trying to write directly in the first sector.

I am talking about that screenshot from you:

[laszlokovacs25]

hi @testerHerbert

the only file what need to be modified is the Adafruit_DAP_STM32.cpp
what is the chip number you want to flash? I added only the STM32G07x family but with this mods you will lose the F4 family support. If you want to keep the F4 families you have to rename the definitions and later make is selectable. I didn't bother because I needed only the G0 family.

---

1. you have to add the necessary definitions

//STM32F4
//#define DAP_DBGMCU_IDCODE 0xE0042000
//#define STM32_FLASHSIZE 0x1FFF7A22
//STM32G0
#define DAP_DBGMCU_IDCODE 0x40015800 //0x1FFF7590
#define STM32_FLASHSIZE 0x1FFF75E0

#define FLASH_BANK2_START_PAGE 256U

// Flash Interface Registers*STM32F4
//#define FLASH_R_BASE 0x40023C00UL
//#define FLASH_ACR (FLASH_R_BASE + 0x00)
//#define FLASH_KEYR (FLASH_R_BASE + 0x04)
//#define FLASH_OPTKEYR (FLASH_R_BASE + 0x08)
//#define FLASH_SR (FLASH_R_BASE + 0x0C)
//#define FLASH_CR (FLASH_R_BASE + 0x10)
//#define FLASH_OPTCR (FLASH_R_BASE + 0x14)
//#define FLASH_OPTCR1 (FLASH_R_BASE + 0x18)

// Flash Interface Registers*STM32G0
#define FLASH_R_BASE 0x40022000UL
#define FLASH_ACR (FLASH_R_BASE + 0x000)
#define FLASH_ACR_EMPTY (1U << 16U)
#define FLASH_KEYR (FLASH_R_BASE + 0x008)
#define FLASH_OPTKEYR (FLASH_R_BASE + 0x00C)
#define FLASH_SR (FLASH_R_BASE + 0x010)
#define FLASH_CR (FLASH_R_BASE + 0x014)
#define FLASH_OPTCR (FLASH_R_BASE + 0x020)
//#define FLASH_OPTCR1 (FLASH_R_BASE + 0x18)

///******************* Bits definition for FLASH_SR register STM32F4**************/
//#define FLASH_SR_EOP_Pos (0U)
//#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 /
//#define FLASH_SR_EOP FLASH_SR_EOP_Msk
//#define FLASH_SR_SOP_Pos (1U)
//#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /!< 0x00000002 /
//#define FLASH_SR_SOP FLASH_SR_SOP_Msk
//#define FLASH_SR_WRPERR_Pos (4U)
//#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /!< 0x00000010 /
//#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
//#define FLASH_SR_PGAERR_Pos (5U)
//#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /!< 0x00000020 /
//#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
//#define FLASH_SR_PGPERR_Pos (6U)
//#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /!< 0x00000040 /
//#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
//#define FLASH_SR_PGSERR_Pos (7U)
//#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /!< 0x00000080 /
//#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
//#define FLASH_SR_BSY_Pos (16U)
//#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /!< 0x00010000 */
//#define FLASH_SR_BSY FLASH_SR_BSY_Msk

/******************* Bits definition for FLASH_SR register STM32G0**************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 /
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_SOP_Pos (1U)
#define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos) /!< 0x00000002 /
#define FLASH_SR_SOP FLASH_SR_SOP_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /!< 0x00000010 /
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /!< 0x00000020 /
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
//#define FLASH_SR_PGPERR_Pos (6U)
//#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /!< 0x00000040 /
//#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_BSY2 (1U << 17U)
#define FLASH_SR_BSY1 (1U << 16U)
#define FLASH_SR_BSY_MASK (FLASH_SR_BSY2 | FLASH_SR_BSY1)

///******************* Bits definition for FLASH_CR register STM32F4**************/
//#define FLASH_CR_PG_Pos (0U)
//#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 /
//#define FLASH_CR_PG FLASH_CR_PG_Msk
//#define FLASH_CR_SER_Pos (1U)
//#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /!< 0x00000002 /
//#define FLASH_CR_SER FLASH_CR_SER_Msk
//#define FLASH_CR_MER_Pos (2U)
//#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /!< 0x00000004 /
//#define FLASH_CR_MER FLASH_CR_MER_Msk
//#define FLASH_CR_SNB_Pos (3U)
//#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /!< 0x000000F8 /
//#define FLASH_CR_SNB FLASH_CR_SNB_Msk
//#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /!< 0x00000008 /
//#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /!< 0x00000010 /
//#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /!< 0x00000020 /
//#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /!< 0x00000040 /
//#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /!< 0x00000080 /
//#define FLASH_CR_PSIZE_Pos (8U)
//#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /!< 0x00000300 /
//#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
//#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /!< 0x00000100 /
//#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /!< 0x00000200 /
//#define FLASH_CR_STRT_Pos (16U)
//#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /!< 0x00010000 /
//#define FLASH_CR_STRT FLASH_CR_STRT_Msk
//#define FLASH_CR_EOPIE_Pos (24U)
//#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /!< 0x01000000 /
//#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
//#define FLASH_CR_LOCK_Pos (31U)
//#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /!< 0x80000000 */
//#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk

/******************* Bits definition for FLASH_CR register STM32G0**************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 /
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_SER_Pos (1U)
#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /!< 0x00000002 /
#define FLASH_CR_SER FLASH_CR_SER_Msk
#define FLASH_CR_MER_Pos (2U)
#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /!< 0x00000004 /
#define FLASH_CR_MER FLASH_CR_MER_Msk
#define FLASH_CR_SNB_Pos (3U)
#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /!< 0x000000F8 /
#define FLASH_CR_SNB FLASH_CR_SNB_Msk
#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /!< 0x00000008 /
#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /!< 0x00000010 /
#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /!< 0x00000020 /
#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /!< 0x00000040 /
#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /!< 0x00000080 /
#define FLASH_CR_PSIZE_Pos (8U)
#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /!< 0x00000300 /
#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /!< 0x00000100 /
#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /!< 0x00000200 /
#define FLASH_CR_BKER (1U << 13U)
#define FLASH_CR_MER2 (1U << 15U)
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /!< 0x00010000 /
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /!< 0x01000000 /
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define FLASH_CR_PSIZE_WORD (2UL << FLASH_CR_PSIZE_Pos)
// Look up table for MCU ID
struct {
uint32_t mcuid;
const char *name;
} _stm32_devices[] = {
{0x413, "STM32F405xx/07xx and STM32F415xx/17xx"},
{0x419, "STM32F42xxx and STM32F43xxx"},
{0x431, "STM32F411xC/E"},
{0x441, "STM32F412"},
{0x460, "STM32G07x"},
};

---

2. change flash size reading in the "select" bool

// target_device.flash_size = (dap_read_word(STM32_FLASHSIZE) >> 16) * 1024;
target_device.flash_size = (dap_read_word(STM32_FLASHSIZE) & 0xFFFUL) * 1024;

---

3. change the "flash_busy" bool

// return dap_read_word(FLASH_SR) & FLASH_SR_BSY;
return dap_read_word(FLASH_SR) & FLASH_SR_BSY_MASK;

---

4. change the "erase" void

// dap_write_word(FLASH_CR, FLASH_CR_MER | FLASH_CR_STRT | FLASH_CR_PSIZE_WORD);
dap_write_word(FLASH_CR, FLASH_CR_MER | FLASH_CR_MER2 | FLASH_CR_STRT);

---

5. change the "program_start" uint32_t

const uint32_t flash_sectors[] = {
// Bank 0 : sector 0-3 : 16 KB, sector 4: 64 KB, sector 5-11: 128 KB
// 16, 16, 16, 16, 64, 128, 128, 128, 128, 128, 128, 128,
//
// // Bank 1 : sector 0-3 : 16 KB, sector 4: 64 KB, sector 5-11: 128 KB
// 16, 16, 16, 16, 64, 128, 128, 128, 128, 128, 128, 128,

// Bank 0 : sector 0-3 : 16 KB, sector 4: 64 KB, sector 5-11: 128 KB
2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2, 2, 2, 2, 2, 2, 2, 2, 2, 2,2,2,0};

---

---

// Set SER, Sector Number, and PSize and Start bit
// dap_write_word(FLASH_CR, FLASH_CR_SER | FLASH_CR_STRT | (i << FLASH_CR_SNB_Pos) | FLASH_CR_PSIZE_WORD);

const uint32_t ctrl = (sector_count << FLASH_CR_SNB_Pos) | FLASH_CR_SER | (sector_count >= FLASH_BANK2_START_PAGE ? FLASH_CR_BKER : 0);
dap_write_word(FLASH_CR, ctrl);
dap_write_word(FLASH_CR, ctrl | FLASH_CR_STRT);

---

6. change the "programBlock" void

//dap_write_word(FLASH_CR, FLASH_CR_PG | FLASH_CR_PSIZE_WORD);
dap_write_word(FLASH_CR, FLASH_CR_PG);

---

after all those changes:
Don't connect the nRST pin
Add the 4 extra byte to the end of the hex otherwise the verification will fail.