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‎latest/embedded-designs/agilex-7/f-series/soc/rsu/ug-rsu-multiqspi-agx7f-soc/index.html‎

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Redirecting to <a href="../../../../../../../rel-24.2/embedded-designs/agilex-7/f-series/soc/rsu/ug-rsu-multiqspi-agx7f-soc/">../../../../../../../rel-24.2/embedded-designs/agilex-7/f-series/soc/rsu/ug-rsu-multiqspi-agx7f-soc/</a>...
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Agilex™ 7 SoC HPS Multi-QSPI Remote System Update Example
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<title>Linux driver template - Altera-FPGA Site</title>
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<title>**Host Attach DFL FPGA Management Engine IP Driver** - Altera-FPGA Site</title>
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**Host Attach DFL FPGA Management Engine IP Driver**
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<!--This template provides an outline for you to create your Linux driver page. Below each guidance comment there is an example for your to reference.-->
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<h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
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<!--Add this date comment below to include date document was last changed-->
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<p>Last updated: <strong>September 03, 2024</strong> </p>
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<!--Note whether your driver is upstreamed or not. If it is upstreamed, provide linux kernel link-->
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<p>Last updated: <strong>September 23, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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<!--Note devices supported-->
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<p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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<p>This set of drivers is designed to support FME functionality, as implemented under FPGA Device Feature List (DFL) framework. It is used to expose FME capabilities.</p>
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<!--If this is an OFS Driver include this table that notes the driver, what it maps to, the source and whether the driver is optional or not for DFL.-->
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<!--If there are multiple drivers, you can create a driver dependency chart using mermaid. Below is an example; to learn more about mermaid see https://mermaid.js.org/ -->
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<pre class="mermaid"><code>graph TD;
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A[dfl-fme]--&gt;B[dfl-fme-mgr];
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<!--Describe the IP(s) that the driver controls, provide a block diagram and link to any user guide documentation. -->
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<h2 id="fpga-management-engine-ip"><strong>FPGA Management Engine IP</strong><a class="headerlink" href="#fpga-management-engine-ip" title="Permanent link">&para;</a></h2>
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<p>The FPGA Management Engine IP provides management features for the platform and controls reset and loading of the AFU into the partial reconfiguration region of the FPGA. Implementation of a PR region is optional.</p>
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<p>Each FME feature exposes its capability to host software drivers through a device feature header (DFH) register found at the beginning of its control status register (CSR) space. The FME CSR maps to physical function 0 (PF0) Base address register 0 (BAR0) so that software can access it through a single PCIe link. For more information about DFHs, refer to the <a href="https://ofs.github.io/latest/hw/d5005/reference_manuals/ofs_fim/mnl_fim_ofs_d5005/#721-device-feature-header-dfh-structure">Device Feature Header (DFH) structure</a>.</p>
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<h2 id="driver-sources"><strong>Driver Sources</strong><a class="headerlink" href="#driver-sources" title="Permanent link">&para;</a></h2>
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<p>The source code for these drivers can be found at https://github.com/OFS/linux-dfl/tree/master/drivers/fpga, where branches labelled fpga-ofs-dev-*-lts correspond with the latest developmental versions of the DFL driver suite on that specific kernel version.</p>
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<p>This driver set is a DFL specific implementation of generic FPGA drivers available in the kernel. <code>dfl-fme-mgr</code> is a DFL specific instantiation of the generic FPGA manager (drivers/linux/fpga/fpga-mgr.c), <code>dfl-fme-br</code> builds on top of a generic FPGA bridge (drivers/fpga/fpga-bridge.c), and <code>dfl-fme-region</code> instantiates an FPGA region. All three supplementary DFL Drivers depend on <code>dfl-fme</code>.</p>
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<p>The DFL FME driver is a feature device implemented under the Device Feature List (DFL) framework. It enables the platform driver for the FME IP and implements all FPGA platform level management features. Only one FME is created per DFL based FPGA device. The DFL Bridge, Manager, and Region drivers are only required when attempting to configure a PR region in the FIM.</p>
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<p>The FPGA Management Engine IP is included as a part of the FIM design for <a href="https://github.com/OFS/ofs-agx7-pcie-attach">PCIe Attach supporting DFL</a>, <a href="https://github.com/OFS/ofs-d5005.git">Stratix 10 PCIe Attach</a>, and <a href="https://github.com/OFS/ofs-f2000x-pl">SoC Attach</a>. Please refer to <a href="https://ofs.github.io/">site</a> for more information about these designs.</p>
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