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‎rel-24.3/common/templates/linux_driver_template/index.html‎

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<h1 id="host-attach-dfl-fpga-management-engine-ip-driver"><strong>Host Attach DFL FPGA Management Engine IP Driver</strong><a class="headerlink" href="#host-attach-dfl-fpga-management-engine-ip-driver" title="Permanent link">&para;</a></h1>
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<p>Last updated: <strong>December 08, 2024</strong> </p>
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<p>Last updated: <strong>December 09, 2024</strong> </p>
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<p><strong>Upstream Status</strong>: <a href="https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/fpga?h=master">Upstreamed</a></p>
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<p><strong>Devices supported</strong>: Stratix 10, Agilex 7</p>
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<h2 id="introduction"><strong>Introduction</strong><a class="headerlink" href="#introduction" title="Permanent link">&para;</a></h2>
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‎rel-24.3/ed-demo-list/ed-list/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/common/virtual-platforms/linux-gsrd/ug-linux-gsrd-agilex5-virtual-platforms/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/modular/gsrd/ug-gsrd-agx5e-modular/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/premium/gsrd/ug-gsrd-agx5e-premium/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/premium/remote-debug/ug-remote-debug-agx5e-premium/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/premium/rsu/ug-rsu-agx5e-soc/index.html‎

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‎rel-24.3/embedded-designs/agilex-5/e-series/premium/tsn/rgmii-hps/ug-tsncfg1-agx5e-premium/index.html‎

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<h5>Generating Latency Plot Using Excel</h5>
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<p>Import 'afpkt-rxtstamps.txt' and 'afxdp-rxtstamps.txt' to excel in 2 seperate sheets.</p>
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<p><a class="glightbox" href="/rel-24.3/docs/embedded-designs/doc_modules/tsn/images/1_excelview.png" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img src="/rel-24.3/docs/embedded-designs/doc_modules/tsn/images/1_excelview.png" alt="Import .txt File" width="800"></a></p>
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<p><a class="glightbox" href="https://altera-fpga.github.io/rel-24.3/embedded-designs/doc_modules/tsn/images/1_excelview.png" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img src="https://altera-fpga.github.io/rel-24.3/embedded-designs/doc_modules/tsn/images/1_excelview.png" alt="Import.txt File" width="800"></a></p>
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<p>Plot Column 1 for each sheets using Scatter chart,</p>
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<p><a class="glightbox" href="/rel-24.3/docs/embedded-designs/doc_modules/tsn/images2_excelview.png" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img src="/rel-24.3/docs/embedded-designs/doc_modules/tsn/images2_excelview.png" alt="Plot Scatter Chart" width="800"></a></p>
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<p><a class="glightbox" href="https://altera-fpga.github.io/rel-24.3/embedded-designs/doc_modules/tsn/images/2_excelview.png" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img src="https://altera-fpga.github.io/rel-24.3/embedded-designs/doc_modules/tsn/images/2_excelview.png" alt="Plot Scatter Chart" width="800"></a></p>
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<p>This will generate plot for AFPKT and AFXDP with latency(on Y-axis) against packet count (on X-axis).</p>
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<p>The latency for this design example can be seen as below:
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<a class="glightbox" href="../images/cfg1_ag5-pdk_af_latency.jpg" data-type="image" data-width="100%" data-height="auto" data-desc-position="bottom"><img alt="" src="../images/cfg1_ag5-pdk_af_latency.jpg" /></a></p>
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