File tree 2 files changed +5
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2 files changed +5
-2
lines changed Original file line number Diff line number Diff line change @@ -438,7 +438,7 @@ def sim_test():
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self .assertEqual ((yield dut .bus .sel ), 0b1111 )
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self .assertEqual ((yield dut .bus .we ), 1 )
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self .assertEqual ((yield dut .bus .dat_w ), 0x12345678 )
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- self .assertEqual ((yield dut .bus .lock ), 1 )
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+ self .assertEqual ((yield dut .bus .lock ), 0 )
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self .assertEqual ((yield dut .bus .cti ), CycleType .CLASSIC .value )
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self .assertEqual ((yield dut .bus .bte ), BurstTypeExt .LINEAR .value )
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self .assertEqual ((yield intr_1 .dat_r ), 0xabcdef01 )
Original file line number Diff line number Diff line change @@ -99,6 +99,9 @@ class Interface(Record):
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Optional. Corresponds to Wishbone signal ``STALL_I`` (initiator) or ``STALL_O`` (target).
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lock : Signal()
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Optional. Corresponds to Wishbone signal ``LOCK_O`` (initiator) or ``LOCK_I`` (target).
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+ nmigen-soc Wishbone support assumes that initiators that don't want bus arbitration to happen in
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+ between two transactions need to use ``lock`` feature to guarantee this. An initiator without
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+ the ``lock`` feature may be arbitrated in between two transactions even if ``cyc`` is kept high.
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cti : Signal()
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Optional. Corresponds to Wishbone signal ``CTI_O`` (initiator) or ``CTI_I`` (target).
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bte : Signal()
@@ -414,7 +417,7 @@ def elaborate(self, platform):
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]
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m .d .comb += self .bus .cyc .eq (intr_bus .cyc )
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if hasattr (self .bus , "lock" ):
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- m .d .comb += self .bus .lock .eq (getattr (intr_bus , "lock" , 1 ))
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+ m .d .comb += self .bus .lock .eq (getattr (intr_bus , "lock" , 0 ))
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if hasattr (self .bus , "cti" ):
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m .d .comb += self .bus .cti .eq (getattr (intr_bus , "cti" , CycleType .CLASSIC ))
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if hasattr (self .bus , "bte" ):
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