Rename nMigen to Amaranth HDL.

whitequark · whitequark · commit 217d4ea76ad3 · 2021-12-10T08:30:44.000Z
diff --git a/.coveragerc b/.coveragerc
@@ -1,9 +1,9 @@
 [run]
 branch = True
 include =
-  nmigen_soc/*
+  amaranth_soc/*
 omit =
-  nmigen_soc/test/*
+  amaranth_soc/test/*
   */__init__.py
 
 [report]
diff --git a/LICENSE.txt b/LICENSE.txt
@@ -1,5 +1,4 @@
-Copyright (C) 2019-2020 whitequark
-Copyright (C) 2019 M-Labs Limited
+Copyright (C) 2019-2021 Amaranth HDL contributors
 
 Redistribution and use in source and binary forms, with or without modification,
 are permitted provided that the following conditions are met:
diff --git a/README.md b/README.md
@@ -1,11 +1,9 @@
-# System on Chip toolkit for nMigen
+# System on Chip toolkit for Amaranth HDL
 
-## CPU and peripheral building blocks
+TODO
 
-TBD
+## License
 
-### License
-
-nMigen is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use nMigen for closed-source proprietary designs.
+Amaranth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use Amaranth for closed-source proprietary designs.
 
 See [LICENSE.txt](LICENSE.txt) file for full copyright and license info.
diff --git a/amaranth_soc/__init__.py b/amaranth_soc/__init__.py
@@ -0,0 +1,11 @@
+try:
+    try:
+        from importlib import metadata as importlib_metadata # py3.8+ stdlib
+    except ImportError:
+        import importlib_metadata # py3.7- shim
+    __version__ = importlib_metadata.version(__package__)
+except ImportError:
+    # No importlib_metadata. This shouldn't normally happen, but some people prefer not installing
+    # packages via pip at all, instead using PYTHONPATH directly or copying the package files into
+    # `lib/pythonX.Y/site-packages`. Although not a recommended way, we still try to support it.
+    __version__ = "unknown" # :nocov:
diff --git a/amaranth_soc/csr/__init__.py b/amaranth_soc/csr/__init__.py
diff --git a/amaranth_soc/csr/bus.py b/amaranth_soc/csr/bus.py
@@ -1,6 +1,6 @@
 import enum
-from nmigen import *
-from nmigen.utils import log2_int
+from amaranth import *
+from amaranth.utils import log2_int
 
 from ..memory import MemoryMap
 
diff --git a/amaranth_soc/csr/event.py b/amaranth_soc/csr/event.py
@@ -1,6 +1,6 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
-from nmigen import *
+from amaranth import *
 
 from . import Element, Multiplexer
 from .. import event
diff --git a/amaranth_soc/csr/wishbone.py b/amaranth_soc/csr/wishbone.py
@@ -1,5 +1,5 @@
-from nmigen import *
-from nmigen.utils import log2_int
+from amaranth import *
+from amaranth.utils import log2_int
 
 from . import Interface as CSRInterface
 from ..wishbone import Interface as WishboneInterface
diff --git a/amaranth_soc/event.py b/amaranth_soc/event.py
@@ -1,7 +1,7 @@
 import enum
 from collections import OrderedDict
 
-from nmigen import *
+from amaranth import *
 
 
 __all__ = ["Source", "EventMap", "Monitor"]
diff --git a/amaranth_soc/memory.py b/amaranth_soc/memory.py
@@ -1,6 +1,6 @@
 import bisect
 
-from nmigen.utils import bits_for
+from amaranth.utils import bits_for
 
 
 __all__ = ["ResourceInfo", "MemoryMap"]
diff --git a/amaranth_soc/periph.py b/amaranth_soc/periph.py
@@ -1,7 +1,7 @@
 from collections import OrderedDict
 from collections.abc import Mapping
 
-from nmigen.utils import bits_for
+from amaranth.utils import bits_for
 
 from .memory import MemoryMap
 from . import event
diff --git a/amaranth_soc/test/__init__.py b/amaranth_soc/test/__init__.py
diff --git a/amaranth_soc/test/test_csr_bus.py b/amaranth_soc/test/test_csr_bus.py
@@ -1,9 +1,9 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.hdl.rec import Layout
-from nmigen.back.pysim import *
+from amaranth import *
+from amaranth.hdl.rec import Layout
+from amaranth.back.pysim import *
 
 from ..csr.bus import *
 from ..memory import MemoryMap
diff --git a/amaranth_soc/test/test_csr_event.py b/amaranth_soc/test/test_csr_event.py
@@ -1,8 +1,8 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.back.pysim import *
+from amaranth import *
+from amaranth.back.pysim import *
 
 from ..csr import *
 from .. import event
diff --git a/amaranth_soc/test/test_csr_wishbone.py b/amaranth_soc/test/test_csr_wishbone.py
@@ -1,8 +1,8 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.back.pysim import *
+from amaranth import *
+from amaranth.back.pysim import *
 
 from .. import csr
 from ..csr.wishbone import *
diff --git a/amaranth_soc/test/test_event.py b/amaranth_soc/test/test_event.py
@@ -1,8 +1,8 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.back.pysim import *
+from amaranth import *
+from amaranth.back.pysim import *
 
 from ..event import *
 
diff --git a/amaranth_soc/test/test_memory.py b/amaranth_soc/test/test_memory.py
@@ -283,7 +283,7 @@ def test_add_window_wrong_frozen(self):
         memory_map.freeze()
         with self.assertRaisesRegex(ValueError,
                 r"Memory map has been frozen. Cannot add window "
-                r"<nmigen_soc\.memory\.MemoryMap object at .+?>"):
+                r"<amaranth_soc\.memory\.MemoryMap object at .+?>"):
             memory_map.add_window(MemoryMap(addr_width=1, data_width=8))
 
     def test_add_window_wrong_window(self):
@@ -325,15 +325,15 @@ def test_add_window_wrong_overlap(self):
         memory_map.add_window(MemoryMap(addr_width=10, data_width=8))
         with self.assertRaisesRegex(ValueError,
                 r"Address range 0x200\.\.0x600 overlaps with window "
-                r"<nmigen_soc\.memory\.MemoryMap object at .+?> at 0x0\.\.0x400"):
+                r"<amaranth_soc\.memory\.MemoryMap object at .+?> at 0x0\.\.0x400"):
             memory_map.add_window(MemoryMap(addr_width=10, data_width=8), addr=0x200)
 
     def test_add_window_wrong_twice(self):
         memory_map = MemoryMap(addr_width=16, data_width=8)
         window = MemoryMap(addr_width=10, data_width=8)
         memory_map.add_window(window)
         with self.assertRaisesRegex(ValueError,
-                r"Window <nmigen_soc\.memory\.MemoryMap object at .+?> is already added "
+                r"Window <amaranth_soc\.memory\.MemoryMap object at .+?> is already added "
                 r"at address range 0x0\.\.0x400"):
             memory_map.add_window(window)
 
diff --git a/amaranth_soc/test/test_periph.py b/amaranth_soc/test/test_periph.py
diff --git a/amaranth_soc/test/test_wishbone_bus.py b/amaranth_soc/test/test_wishbone_bus.py
@@ -1,9 +1,9 @@
-# nmigen: UnusedElaboratable=no
+# amaranth: UnusedElaboratable=no
 
 import unittest
-from nmigen import *
-from nmigen.hdl.rec import *
-from nmigen.back.pysim import *
+from amaranth import *
+from amaranth.hdl.rec import *
+from amaranth.back.pysim import *
 
 from ..wishbone.bus import *
 from ..memory import MemoryMap
diff --git a/amaranth_soc/wishbone/__init__.py b/amaranth_soc/wishbone/__init__.py
diff --git a/amaranth_soc/wishbone/bus.py b/amaranth_soc/wishbone/bus.py
@@ -1,7 +1,7 @@
 from enum import Enum
-from nmigen import *
-from nmigen.hdl.rec import Direction
-from nmigen.utils import log2_int
+from amaranth import *
+from amaranth.hdl.rec import Direction
+from amaranth.utils import log2_int
 
 from ..memory import MemoryMap
 
@@ -72,7 +72,7 @@ class Interface(Record):
 
     Attributes
     ----------
-    The correspondence between the nMigen-SoC signals and the Wishbone signals changes depending
+    The correspondence between the Amaranth-SoC signals and the Wishbone signals changes depending
     on whether the interface acts as an initiator or a target.
 
     adr : Signal(addr_width)
@@ -99,7 +99,7 @@ class Interface(Record):
         Optional. Corresponds to Wishbone signal ``STALL_I`` (initiator) or ``STALL_O`` (target).
     lock : Signal()
         Optional. Corresponds to Wishbone signal ``LOCK_O`` (initiator) or ``LOCK_I`` (target).
-        nmigen-soc Wishbone support assumes that initiators that don't want bus arbitration to happen in
+        amaranth-soc Wishbone support assumes that initiators that don't want bus arbitration to happen in
         between two transactions need to use ``lock`` feature to guarantee this. An initiator without
         the ``lock`` feature may be arbitrated in between two transactions even if ``cyc`` is kept high.
     cti : Signal()
diff --git a/nmigen_soc/__init__.py b/nmigen_soc/__init__.py
diff --git a/setup.py b/setup.py
@@ -15,18 +15,21 @@ def local_scheme(version):
 
 
 setup(
-    name="nmigen-soc",
+    name="amaranth-soc",
     use_scm_version=scm_version(),
     author="whitequark",
     author_email="whitequark@whitequark.org",
-    description="System on Chip toolkit for nMigen",
+    description="System on Chip toolkit for Amaranth HDL",
     #long_description="""TODO""",
     license="BSD",
     setup_requires=["wheel", "setuptools", "setuptools_scm"],
-    install_requires=["nmigen>=0.2,<0.5"],
+    install_requires=[
+        "amaranth>=0.2,<0.5",
+        "importlib_metadata; python_version<'3.8'",
+    ],
     packages=find_packages(),
     project_urls={
-        "Source Code": "https://github.com/nmigen/nmigen-soc",
-        "Bug Tracker": "https://github.com/nmigen/nmigen-soc/issues",
+        "Source Code": "https://github.com/amaranth-lang/amaranth-soc",
+        "Bug Tracker": "https://github.com/amaranth-lang/amaranth-soc/issues",
     },
 )
