@@ -414,6 +414,16 @@ class FooRegister(Register, access="r"):
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self .assertEqual (reg .element .access , Element .Access .R )
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self .assertEqual (reg .element .width , 2 )
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+ def test_fields_single (self ):
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+ reg = Register (Field (action .R , unsigned (1 )), access = "r" )
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+
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+ field_r_u1 = Field (action .R , unsigned (1 )).create ()
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+
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+ self .assertTrue (_compatible_fields (reg .f , field_r_u1 ))
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+
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+ self .assertEqual (reg .element .access , Element .Access .R )
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+ self .assertEqual (reg .element .width , 1 )
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+
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def test_wrong_access (self ):
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with self .assertRaisesRegex (ValueError , r"'foo' is not a valid Element.Access" ):
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Register ({"a" : Field (action .R , unsigned (1 ))}, access = "foo" )
@@ -450,7 +460,7 @@ def test_wrong_fields(self):
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class FooRegister (Register , access = "w" ):
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pass
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with self .assertRaisesRegex (TypeError ,
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- r"Field collection must be a dict or a list , not 'foo'" ):
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+ r"Field collection must be a dict, list, or Field , not 'foo'" ):
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FooRegister (fields = "foo" )
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def test_annotations_conflict (self ):
@@ -497,6 +507,12 @@ class FooRegister(Register, access="rw"):
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(("e" , 1 ), reg .f .e [1 ]),
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])
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+ def test_iter_single (self ):
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+ reg = Register (Field (action .R , unsigned (1 )), access = "rw" )
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+ self .assertEqual (list (reg ), [
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+ ((), reg .f ),
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+ ])
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+
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def test_sim (self ):
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class FooRegister (Register , access = "rw" ):
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a : Field (action .R , unsigned (1 ))
@@ -629,6 +645,44 @@ def process():
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with sim .write_vcd (vcd_file = open ("test.vcd" , "w" )):
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sim .run ()
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+ def test_sim_single (self ):
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+ dut = Register (Field (action .RW , unsigned (1 ), init = 1 ), access = "rw" )
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+
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+ def process ():
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+ # Check init values:
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+
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+ self .assertEqual ((yield dut .f .data ), 1 )
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+ self .assertEqual ((yield dut .f .port .r_data ), 1 )
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+
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+ # Initiator read:
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+
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+ yield dut .element .r_stb .eq (1 )
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+ yield Delay ()
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+
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+ self .assertEqual ((yield dut .f .port .r_stb ), 1 )
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+
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+ yield dut .element .r_stb .eq (0 )
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+
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+ # Initiator write:
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+
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+ yield dut .element .w_stb .eq (1 )
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+ yield dut .element .w_data .eq (0 )
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+ yield Delay ()
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+
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+ self .assertEqual ((yield dut .f .port .w_stb ), 1 )
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+ self .assertEqual ((yield dut .f .port .w_data ), 0 )
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+
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+ yield Tick ()
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+ yield dut .element .w_stb .eq (0 )
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+ yield Delay ()
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+
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+ self .assertEqual ((yield dut .f .data ), 0 )
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+
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+ sim = Simulator (dut )
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+ sim .add_clock (1e-6 )
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+ sim .add_testbench (process )
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+ with sim .write_vcd (vcd_file = open ("test.vcd" , "w" )):
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+ sim .run ()
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class _MockRegister (Register , access = "rw" ):
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def __init__ (self , name , width = 1 ):
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