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kivikakkjfng
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wishbone: sram: allow SPRAM by disabling read port on write.
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amaranth_soc/wishbone/sram.py

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Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ def elaborate(self, platform):
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with m.Elif(self.wb_bus.cyc & self.wb_bus.stb):
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if self.writable:
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m.d.comb += write_port.en.eq(Mux(self.wb_bus.we, self.wb_bus.sel, 0))
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m.d.comb += read_port.en.eq(~self.wb_bus.we)
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m.d.sync += self.wb_bus.ack.eq(1)
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return m

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