@@ -369,7 +369,7 @@ def elaborate(self, platform):
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produce_dec = m .submodules .produce_dec = \
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GrayDecoder (self ._ctr_bits )
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m .d .comb += produce_dec .i .eq (produce_r_gry ),
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- m .d [ self . _r_domain ] += produce_r_bin .eq (produce_dec .o )
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+ m .d . comb += produce_r_bin .eq (produce_dec .o )
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w_full = Signal ()
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r_empty = Signal ()
@@ -381,7 +381,7 @@ def elaborate(self, platform):
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]
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m .d [self ._w_domain ] += self .w_level .eq ((produce_w_bin - consume_w_bin )[:self ._ctr_bits - 1 ])
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- m .d [ self . _r_domain ] += self .r_level .eq ((produce_r_bin - consume_r_bin )[:self ._ctr_bits - 1 ])
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+ m .d . comb += self .r_level .eq ((produce_r_bin - consume_r_bin )[:self ._ctr_bits - 1 ])
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storage = Memory (width = self .width , depth = self .depth )
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w_port = m .submodules .w_port = storage .write_port (domain = self ._w_domain )
@@ -509,12 +509,13 @@ def elaborate(self, platform):
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self .w_level .eq (fifo .w_level ),
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]
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+ m .d [self ._r_domain ] += self .r_level .eq (fifo .r_level + self .r_rdy - self .r_en )
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+
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with m .If (self .r_en | ~ self .r_rdy ):
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m .d [self ._r_domain ] += [
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self .r_data .eq (fifo .r_data ),
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self .r_rdy .eq (fifo .r_rdy ),
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self .r_rst .eq (fifo .r_rst ),
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- self .r_level .eq (fifo .r_level ),
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]
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m .d .comb += [
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fifo .r_en .eq (1 )
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