diff --git a/.github/labeler.yml b/.github/labeler.yml index 95552ac61b0..a44984bdb92 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -9,7 +9,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. # (now owned by Analog Devices, Inc.), - # Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software # is proprietary to Analog Devices, Inc. and its licensors. # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -50,6 +50,13 @@ - '**/Libraries/PeriphDrivers/max32570_files.mk' - '**/Libraries/PeriphDrivers/Include/MAX32570/**/*' +'MAX32572': +- '**/*me55*.*' +- '**/Libraries/Boards/MAX32572/**/*' +- '**/Libraries/CMSIS/Device/Maxim/MAX32572/**/*' +- '**/Libraries/PeriphDrivers/max32572_files.mk' +- '**/Libraries/PeriphDrivers/Include/MAX32572/**/*' + 'MAX32650': - '**/Examples/MAX32650/**/*' - '**/*me10*.*' diff --git a/Libraries/Boards/MAX32572/EvKit_V1/Include/board.h b/Libraries/Boards/MAX32572/EvKit_V1/Include/board.h index b8ce105e79c..4d47ebc74f3 100644 --- a/Libraries/Boards/MAX32572/EvKit_V1/Include/board.h +++ b/Libraries/Boards/MAX32572/EvKit_V1/Include/board.h @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,15 +54,15 @@ extern "C" { #define CONSOLE_BAUD 115200 /// Console baud rate #endif -#ifndef MX25_BAUD -#define MX25_BAUD 3000000 -#endif +#define EXT_FLASH_SPIXFC_BAUD 3000000 +#define EXT_FLASH_SPIXFM_BAUD 24000000 -// #define MX25_SPI MXC_SPIXC -// #define MX25_SSEL 0 -// // #define SPI_CHAR_BITS 8 +#define SPIXFC_CMD_VAL 0x0B +#define SPIXFM_BUS_IDLE_VAL 0x1000 -// const spixc_cfg_t mx25_spixc_cfg; +#define TS_I2C MXC_I2C0 +#define TS_I2C_FREQ MXC_I2C_STD_MODE +#define TS_I2C_TARGET_ADDR 0x48 /** * \brief Initialize the BSP and board interfaces. @@ -90,40 +90,35 @@ int Console_Shutdown(void); int Console_PrepForSleep(void); /** - * \brief Initialize the SPI peripheral to use for MX25 - * \returns #E_NO_ERROR if everything is successful + * @brief Writes data to external flash. + * @note This function must be executed from RAM. + * @param address Address in external flash to start writing from. + * @param length Number of bytes to be written. + * @param buffer Pointer to data to be written to external flash. + * @return #EF_E_SUCCESS If function is successful. + * @note make sure to disable SFCC and interrupts; before running this function */ -int MX25_Board_Init(void); +int MXC_Ext_Write(uint32_t address, uint32_t length, uint8_t *buffer); /** - * \brief Translation function to implement SPI Read transaction - * @param read Pointer to where master will store data. - * @param len Number of characters to send. - * @param deassert Deassert slave select at the end of the transaction. - * @param width spi_width_t for how many data lines to use - * \returns #E_NO_ERROR if successful, !=0 otherwise + * @brief Reads data from external flash + * @note This function must be executed from RAM. + * @param[in] address The address to read from + * @param buffer The buffer to read the data into + * @param[in] len The length of the buffer + * @return #EF_E_SUCCESS If function is successful. + * @note make sure to disable SFCC and interrupts; before running this function */ - -int MX25_Board_Read(uint8_t *read, unsigned len, unsigned deassert, mxc_spixf_width_t width); -/** - * \brief Translation function to implement SPI Write transaction - * @param write Pointer to data master will write. - * @param len Number of characters to send. - * @param deassert Deassert slave select at the end of the transaction. - * @param width spi_width_t for how many data lines to use - * \returns #E_NO_ERROR if successful, !=0 otherwise - */ - -int MX25_Board_Write(const uint8_t *write, unsigned len, unsigned deassert, - mxc_spixf_width_t width); +int MXC_Ext_Read(int address, uint8_t *buffer, int len); /** - * \brief Send clocks on SCLK. - * @param len Number of characters to send. - * @param deassert Deassert slave select at the end of the transaction. - * \returns #E_NO_ERROR if successful, !=0 otherwise + * @brief Erases the sector of external flash at the specified address. + * @note This function must be executed from RAM. + * @param address Any address within the sector to erase. + * @return #EF_E_SUCCESS If function is successful. + * @note make sure to disable SFCC and interrupts; before running this function */ -int MX25_Clock(unsigned len, unsigned deassert); +int MXC_Ext_SectorErase(int address); #ifdef __cplusplus } diff --git a/Libraries/Boards/MAX32572/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32572/EvKit_V1/Source/board.c index 24d0a166e48..82bc158c9a6 100644 --- a/Libraries/Boards/MAX32572/EvKit_V1/Source/board.c +++ b/Libraries/Boards/MAX32572/EvKit_V1/Source/board.c @@ -31,6 +31,10 @@ #include "pb.h" #include "spixf.h" #include "i2c.h" +#include "Ext_Flash.h" +#include "spi.h" +#include "tft_ssd2119.h" +#include "tsc2007.h" /***** Global Variables *****/ mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(CONSOLE_UART); @@ -49,6 +53,65 @@ const mxc_gpio_cfg_t led_pin[] = { const unsigned int num_leds = (sizeof(led_pin) / sizeof(mxc_gpio_cfg_t)); // clang-format on +/******************************************************************************/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int ext_flash_board_init(void) +{ + int err; + err = MXC_SPIXF_Init(SPIXFC_CMD_VAL, EXT_FLASH_SPIXFC_BAUD); + if (err == E_NO_ERROR) { + MXC_SPIXF_Enable(); + } + return err; +} + +/******************************************************************************/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int ext_flash_board_read(uint8_t *read, unsigned len, unsigned deassert, + Ext_Flash_DataLine_t width) +{ + mxc_spixf_req_t req = { deassert, 0, NULL, read, (mxc_spixf_width_t)width, len, 0, 0, NULL }; + if (MXC_SPIXF_Transaction(&req) != len) { + return E_COMM_ERR; + } + return E_NO_ERROR; +} + +/******************************************************************************/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int ext_flash_board_write(const uint8_t *write, unsigned len, unsigned deassert, + Ext_Flash_DataLine_t width) +{ + mxc_spixf_req_t req = { deassert, 0, write, NULL, (mxc_spixf_width_t)width, len, 0, 0, NULL }; + if (MXC_SPIXF_Transaction(&req) != len) { + return E_COMM_ERR; + } + return E_NO_ERROR; +} + +/******************************************************************************/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int ext_flash_clock(unsigned len, unsigned deassert) +{ + return MXC_SPIXF_Clocks(len, deassert); +} + /******************************************************************************/ void mxc_assert(const char *expr, const char *file, int line) { @@ -77,6 +140,108 @@ __weak void GPIO1_IRQHandler(void) MXC_GPIO_Handler(MXC_GPIO_GET_IDX(MXC_GPIO1)); } +void TS_I2C_Init(void) +{ + MXC_I2C_Init(TS_I2C, 1, 0); + MXC_I2C_SetFrequency(TS_I2C, TS_I2C_FREQ); +} + +void TS_I2C_Transmit(uint8_t datain, uint16_t *dataout) +{ + uint8_t rx[2] = { 0, 0 }; + mxc_i2c_req_t request; + + request.i2c = TS_I2C; + request.addr = TS_I2C_TARGET_ADDR; + request.tx_buf = (uint8_t *)(&datain); + request.rx_buf = NULL; + request.tx_len = 1; + request.rx_len = 0; + request.restart = 0; + request.callback = NULL; + + // send command + MXC_I2C_MasterTransaction(&request); + + request.tx_buf = NULL; + request.rx_buf = (uint8_t *)(rx); + request.tx_len = 0; + request.rx_len = 2; + + // receive value + MXC_I2C_MasterTransaction(&request); + + // convert 16 bits to 12 bits + if (dataout != NULL) { + *dataout = (rx[1] | (rx[0] << 8)) >> 4; + } +} + +/******************************************************************************/ +int Board_Init(void) +{ + int err; + // callback functions for external flash driver + Ext_Flash_Config_t exf_cfg = { .init = ext_flash_board_init, + .read = ext_flash_board_read, + .write = ext_flash_board_write, + .clock = ext_flash_clock }; + + // configure callback functions for external flash driver + if ((err = Ext_Flash_Configure(&exf_cfg)) != E_NO_ERROR) { + return err; + } + + if ((err = Console_Init()) < E_NO_ERROR) { + return err; + } + + if ((err = PB_Init()) != E_NO_ERROR) { + MXC_ASSERT_FAIL(); + return err; + } + + if ((err = LED_Init()) != E_NO_ERROR) { + MXC_ASSERT_FAIL(); + return err; + } + + /* TFT SPI */ + mxc_tft_spi_config tft_spi_config = { + .regs = MXC_SPI0, + .gpio = { MXC_GPIO0, MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5, + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }, + .freq = 12000000, + .ss_idx = 0, + }; + + /* TFT reset and backlight signal */ + mxc_gpio_cfg_t tft_reset_pin = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_OUT, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; + mxc_gpio_cfg_t tft_bl_pin = { MXC_GPIO0, MXC_GPIO_PIN_6, MXC_GPIO_FUNC_OUT, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; + + /* Initialize TFT display */ + MXC_TFT_PreInit(&tft_spi_config, &tft_reset_pin, &tft_bl_pin); + + /* Touch screen controller I2C */ + mxc_ts_i2c_config ts_i2c_config = { + .regs = MXC_I2C0, + .gpio = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }, + .freq = MXC_I2C_STD_MODE, + }; + + /* Touch screen controller interrupt signal */ + mxc_gpio_cfg_t ts_int_pin = { MXC_GPIO1, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; + + /* Pre-Initialize Touch Screen controller */ + MXC_TS_PreInit(&ts_i2c_config, &ts_int_pin); + + return E_NO_ERROR; +} + /******************************************************************************/ int Console_Init(void) { @@ -99,6 +264,115 @@ int Console_Shutdown(void) return E_NO_ERROR; } +/******************************************************************************/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +/** + * @brief Configurations for SPIXFM (XiP) + */ +void SPIXFM_Config() +{ + MXC_SPIXF_SetSPIFrequency(EXT_FLASH_SPIXFM_BAUD); + MXC_SPIXF_SetMode(MXC_SPIXF_MODE_0); + MXC_SPIXF_SetSSPolActiveLow(); + MXC_SPIXF_SetSSActiveTime(MXC_SPIXF_SYS_CLOCKS_2); + MXC_SPIXF_SetSSInactiveTime(MXC_SPIXF_SYS_CLOCKS_9); + + MXC_SPIXF_SetBusIdle(SPIXFM_BUS_IDLE_VAL); + + MXC_SPIXF_SetCmdValue(EXT_FLASH_CMD_QREAD); + MXC_SPIXF_SetModeData(MXC_SPIXF_MODE_0); + MXC_SPIXF_SetCmdWidth(MXC_SPIXF_SINGLE_SDIO); + MXC_SPIXF_SetAddrWidth(MXC_SPIXF_QUAD_SDIO); + MXC_SPIXF_SetDataWidth(MXC_SPIXF_WIDTH_4); + MXC_SPIXF_SetModeClk(EXT_FLASH_QREAD_DUMMY); + + MXC_SPIXF_Set3ByteAddr(); + MXC_SPIXF_SCKFeedbackEnable(); + MXC_SPIXF_SetSCKNonInverted(); +} + +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int MXC_Ext_Write(uint32_t address, uint32_t length, uint8_t *buffer) +{ + int err = E_NO_ERROR; + // reset SPIXF peripheral (both SPIXFC and SPIXFM) + MXC_GCR->rst1 |= MXC_F_GCR_RST1_SPIXIPM | MXC_F_GCR_RST1_SPIXIP; + // initialize spixfc + MXC_SPIXF_Init(SPIXFC_CMD_VAL, EXT_FLASH_SPIXFC_BAUD); + // enable spixfc + MXC_SPIXF_Enable(); + + // write to external flash + err = Ext_Flash_Program_Page(address, buffer, length, Ext_Flash_DataLine_Single); + + // disable spixfc + MXC_SPIXF_Disable(); + // re-config SPIXF for XiP + SPIXFM_Config(); + + return err; +} + +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int MXC_Ext_Read(int address, uint8_t *buffer, int len) +{ + int err = E_NO_ERROR; + // reset SPIXF peripheral (both SPIXFC and SPIXFM) + MXC_GCR->rst1 |= MXC_F_GCR_RST1_SPIXIPM | MXC_F_GCR_RST1_SPIXIP; + // initialize spixfc + MXC_SPIXF_Init(SPIXFC_CMD_VAL, EXT_FLASH_SPIXFC_BAUD); + // enable spixfc + MXC_SPIXF_Enable(); + + // read from external flash + err = Ext_Flash_Read(address, buffer, len, Ext_Flash_DataLine_Single); + + // disable spixfc + MXC_SPIXF_Disable(); + // re-config SPIXF for XiP + SPIXFM_Config(); + + return err; +} + +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int MXC_Ext_SectorErase(int address) +{ + int err = E_NO_ERROR; + // reset SPIXF peripheral (both SPIXFC and SPIXFM) + MXC_GCR->rst1 |= MXC_F_GCR_RST1_SPIXIPM | MXC_F_GCR_RST1_SPIXIP; + // initialize spixfc + MXC_SPIXF_Init(SPIXFC_CMD_VAL, EXT_FLASH_SPIXFC_BAUD); + // enable spixfc + MXC_SPIXF_Enable(); + + // erase 4KB from flash which corresponds to a sector + err = Ext_Flash_Erase(address, Ext_Flash_Erase_4K); + + // disable spixfc + MXC_SPIXF_Disable(); + // re-config SPIXF for XiP + SPIXFM_Config(); + + return err; +} + /******************************************************************************/ __weak void NMI_Handler(void) { diff --git a/Libraries/Boards/MAX32572/EvKit_V1/board.mk b/Libraries/Boards/MAX32572/EvKit_V1/board.mk index 1a269d1cef7..223dde4de6d 100644 --- a/Libraries/Boards/MAX32572/EvKit_V1/board.mk +++ b/Libraries/Boards/MAX32572/EvKit_V1/board.mk @@ -2,7 +2,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. # (now owned by Analog Devices, Inc.), - # Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software # is proprietary to Analog Devices, Inc. and its licensors. # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,10 +27,15 @@ endif SRCS += board.c SRCS += stdio.c SRCS += led.c +SRCS += is25.c SRCS += pb.c -SRCS += tsc2046.c +SRCS += tsc2007.c SRCS += tft_ssd2119.c +PROJ_CFLAGS+=-DSPIXF_RAM +PROJ_CFLAGS+=-DEXT_FLASH_IS25 +PROJ_CFLAGS+=-DTS_TSC2007 + MISC_DRIVERS_DIR ?= $(MAXIM_PATH)/Libraries/MiscDrivers # Where to find BSP source files @@ -38,6 +43,7 @@ VPATH += $(BOARD_DIR)/Source VPATH += $(MISC_DRIVERS_DIR) VPATH += $(MISC_DRIVERS_DIR)/LED VPATH += $(MISC_DRIVERS_DIR)/PushButton +VPATH += $(MISC_DRIVERS_DIR)/ExtMemory VPATH += $(MISC_DRIVERS_DIR)/Display VPATH += $(MISC_DRIVERS_DIR)/Touchscreen @@ -46,5 +52,6 @@ IPATH += $(BOARD_DIR)/Include IPATH += $(MISC_DRIVERS_DIR) IPATH += $(MISC_DRIVERS_DIR)/LED IPATH += $(MISC_DRIVERS_DIR)/PushButton +IPATH += $(MISC_DRIVERS_DIR)/ExtMemory IPATH += $(MISC_DRIVERS_DIR)/Display IPATH += $(MISC_DRIVERS_DIR)/Touchscreen diff --git a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h index 021ddaea4c0..f05f9506884 100644 --- a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h +++ b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * - * Portions Copyright (C) 2022-2023 Analog Devices, Inc. + * Portions Copyright (C) 2022-2024 Analog Devices, Inc. * * SPDX-License-Identifier: Apache-2.0 * @@ -318,14 +318,19 @@ typedef struct { /*@} end of group CMSIS_NVIC */ -#define MXC_BASE_INTR ((uint32_t)0xE5070000UL) -//#define MXC_BASE_INTR ((uint32_t)0xE5000000UL) +/* For MCUs with extra RISCV core (RISCV1) */ +#ifdef __riscv1 +#define MXC_BASE_INTR ((uint32_t)0xE5170000UL) +#define MXC_BASE_EVENT ((uint32_t)0xE5170020UL) +#define MXC_BASE_SLEEP ((uint32_t)0xE5170040UL) +#else +#define MXC_BASE_INTR ((uint32_t)0xE5070000UL) +#define MXC_BASE_EVENT ((uint32_t)0xE5070020UL) +#define MXC_BASE_SLEEP ((uint32_t)0xE5070040UL) +#endif + #define MXC_INTR ((mxc_intr_regs_t *)MXC_BASE_INTR) -#define MXC_BASE_EVENT ((uint32_t)0xE5070020UL) -//#define MXC_BASE_EVENT ((uint32_t)0xE5000020UL) #define MXC_EVENT ((mxc_event_regs_t *)MXC_BASE_EVENT) -#define MXC_BASE_SLEEP ((uint32_t)0xE5070040UL) -//#define MXC_BASE_SLEEP ((uint32_t)0xE5000040UL) #define MXC_SLEEP ((mxc_sleep_regs_t *)MXC_BASE_SLEEP) /******************************************************************************* diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32572.h b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32572.h index edec8aa48cd..714481d3e37 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32572.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Include/max32572.h @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -283,6 +283,7 @@ typedef enum { #define MXC_ROM_MEM_SIZE MXC_ROM0_MEM_SIZE #define MXC_XIP_MEM_BASE 0x08000000UL #define MXC_XIP_MEM_SIZE 0x08000000UL +#define MXC_XIP_SECTOR_SIZE 0x00001000UL #define MXC_SRAM_MEM_BASE 0x20000000UL #define MXC_SRAM_MEM_SIZE 0x0006C000UL #define MXC_OTP_MEM_BASE 0x400C0000UL @@ -367,9 +368,7 @@ typedef enum { #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : (i) == 1 ? MXC_GPIO1 : 0) -#ifndef __riscv #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (i) == 1 ? GPIO1_IRQn : 0) -#endif /******************************************************************************/ /* Magstripe Reader ADC */ @@ -396,7 +395,6 @@ typedef enum { #define MXC_BASE_TMR5 ((uint32_t)0x40115000UL) #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5) -#ifndef __riscv #define MXC_TMR_GET_IRQ(i) \ (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ (i) == 1 ? TMR1_IRQn : \ @@ -405,9 +403,6 @@ typedef enum { (i) == 4 ? TMR4_IRQn : \ (i) == 5 ? TMR5_IRQn : \ 0) -#else -#define MXC_TMR_GET_IRQ(i) ((i) == 5 ? TMR5_IRQn : 0) -#endif #define MXC_TMR_GET_BASE(i) \ ((i) == 0 ? MXC_BASE_TMR0 : \ @@ -453,9 +448,7 @@ typedef enum { #define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) #define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1) -#ifndef __riscv #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0) -#endif #define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0) @@ -640,14 +633,12 @@ typedef enum { #define MXC_BASE_UART3 ((uint32_t)0x40045000UL) #define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3) -#ifndef __riscv #define MXC_UART_GET_IRQ(i) \ (IRQn_Type)((i) == 0 ? UART0_IRQn : \ (i) == 1 ? UART1_IRQn : \ (i) == 2 ? UART2_IRQn : \ (i) == 3 ? UART3_IRQn : \ 0) -#endif #define MXC_UART_GET_BASE(i) \ ((i) == 0 ? MXC_BASE_UART0 : \ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572.ld b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572.ld index 154fbec941e..a634e2b0249 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572.ld @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +26,6 @@ MEMORY { SRAM_RV (rwx) : ORIGIN = 0x20060000, LENGTH = 0x0000C000 } -/* Added Oct 9, 2018 to go to correct reset vector. */ ENTRY(Reset_Handler) PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24))); PROVIDE_HIDDEN( _SLA_Size = __end_image - __end_header ); @@ -76,6 +75,16 @@ SECTIONS { _etext = .; } > SPIX + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > SPIX + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -88,7 +97,7 @@ SECTIONS { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; - } > ROM + } > SPIX /* This section will keep the SPIX data until loaded into the external device */ /* Upon initialization of SPIX (user code needs to do this) */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_emulator.ld b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_sla.ld similarity index 56% rename from Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_emulator.ld rename to Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_sla.ld index efeb4ce458f..a228426bbfc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_emulator.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/GCC/max32572_sla.ld @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,15 +17,30 @@ * See the License for the specific language governing permissions and * limitations under the License. * - ******************************************************************************/ + ******************************************************************************/ MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB "ROM" */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 1M /* 256kB "FLASH" */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x000BE000 /* 760kB SRAM */ + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 64K + SPIX (rx) : ORIGIN = 0x08000000, LENGTH = 128M + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* Total: 432kB SRAM */ + SRAM_RV (rwx) : ORIGIN = 0x20060000, LENGTH = 0x0000C000 } +/* Added Oct 9, 2018 to go to correct reset vector. */ +ENTRY(Reset_Handler) +PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24))); +PROVIDE_HIDDEN( _SLA_Size = __end_image - __end_header ); +PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24))); + SECTIONS { + .sla_header : ALIGN(4) + { + FILL(0xFF); + KEEP(*(.sb_sla_header)) /* Header for ROM code */ + __end_header = .; + . = ALIGN(512); + } > SPIX + .rom : { KEEP(*(.rom_vector)) @@ -45,7 +60,22 @@ SECTIONS { /* C++ Exception handling */ KEEP(*(.eh_frame*)) _etext = .; - } > FLASH + } > SPIX + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > SPIX + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > SPIX /* it's used for C++ exception handling */ /* we need to keep this to avoid overlapping */ @@ -54,14 +84,23 @@ SECTIONS { __exidx_start = .; *(.ARM.exidx*) __exidx_end = .; - } > FLASH + } > SPIX + + /* This section will keep the SPIX data until loaded into the external device */ + /* Upon initialization of SPIX (user code needs to do this) */ + .xip_section : + { + KEEP(*(.xip_section*)) + } > SPIX AT>SPIX + __load_start_xip = LOADADDR(.xip_section); + __load_length_xip = SIZEOF(.xip_section); .data : { _data = ALIGN(., 4); - *(.data*) /*read-write initialized data: initialized global variable*/ + *(vtable) + *(.data*) /* read-write initialized data: initialized global variable */ *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ - *(.flashprog*) /* Flash program */ /* These array sections are used by __libc_init_array to call static C++ constructors */ . = ALIGN(4); @@ -85,14 +124,39 @@ SECTIONS { PROVIDE_HIDDEN (__fini_array_end = .); _edata = ALIGN(., 4); - } > SRAM AT>FLASH + } > SRAM AT>SPIX __load_data = LOADADDR(.data); + __end_data = LOADADDR(.data)+SIZEOF(.data); + + .sram_rv : + { + _data_rv = ALIGN(., 4); + *(.sram_rv*) + _edata_rv = ALIGN(., 4); + } > SRAM_RV + + .sb_sla_trailer : AT(__end_data) + { + KEEP(*(.sb_sla_trailer)) + /* Align image with 16-byte boundary to conform to flash encryption block size. */ + FILL(0xDEADC0DE); + /* NOTE: The FILL and ALIGN will not work unless something is written to the section. So, we use LONG. */ + LONG(0xDEADC0DE); + . = ALIGN(16); + } > SPIX + __end_image = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer); + + .sig : + { + KEEP(*(.sig)) + LONG(0xDEADBEEF); + } > SPIX .bss : { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /* read-write zero-initialized data: uninitialized global variable */ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c index f2332bf297e..4ae420a9e1b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,8 @@ extern unsigned int _start_SWAP; extern unsigned int _SLA_Size_SWAP; typedef enum { - MagicH = 0x44495357, + // MSB should be 0x48 to indicate ECDSA. + MagicH = 0x48495357, MagicL = 0x45444744, } enum_magic_t; @@ -63,7 +64,7 @@ const flash_app_header_t sb_header = { }, .RomVersion = SWAP(ROM_A1_VERSION), - .LoadAddr = SWAP(0x10000000), + .LoadAddr = SWAP(0x08000000), .SLA_CodeSize = (unsigned int)&_SLA_Size_SWAP, // Trick to get constant defined at link time .JumpAddr = &_start_SWAP, .ArgSize = 0, diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header.c b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header.c deleted file mode 100644 index 33b306e98fc..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header.c +++ /dev/null @@ -1,89 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#define SWAP(x) \ - (((x) >> 24) | (((x)&0x00FF0000) >> 8) | (((x)&0x0000FF00) << 8) | (((x)&0x000000FF) << 24)) - -typedef enum { - ROM_A1_VERSION = 0x01000000, - LESS_THAN_ROM_A1_VERSION = 0x00000001, - GREATER_THAN_ROM_A1_VERSION = 0x01000001, -} enum_rom_version_t; - -typedef enum { - APP_VERSION = 0x01000000, - LESS_THAN_APP_VERSION = 0x00AA0055, - GREATER_THAN_APP_VERSION = 0x010000CC, -} enum_app_version_t; - -//#ifdef __SLA_FWK__ -/***** Includes *****/ -#include -#include - -extern unsigned int _start_SWAP; -extern unsigned int _SLA_Size_SWAP; - -typedef enum { - MagicH = 0x48495357, - MagicL = 0x45444744, -} enum_magic_t; - -typedef struct { - enum_magic_t MagicHigh; //> SLA Header magic - enum_magic_t MagicLow; //> SLA Header magic -} magic_t; - -typedef struct { - magic_t Magic; - enum_rom_version_t RomVersion; //> ROM version - unsigned int LoadAddr; //> Relocation address. - unsigned int SLA_CodeSize; //> SLA code size in bytes - unsigned int *JumpAddr; //> Rom code will jump at this address - unsigned int ArgSize; //> Size of the Argument - unsigned int AppVersionNumber; //> Version of this application -} flash_app_header_t; - -extern uint32_t _FLASH; - -__attribute__((section(".sb_sla_header"))) __attribute__((__used__)) -const flash_app_header_t sb_header = -{ - .Magic = - { - .MagicHigh = SWAP(MagicH), - .MagicLow = SWAP(MagicL), - }, - - .RomVersion = SWAP(ROM_A1_VERSION), -// .RomVersion = SWAP(LESS_THAN_ROM_A1_VERSION), -// .RomVersion = SWAP(GREATER_THAN_ROM_A1_VERSION), - .LoadAddr = SWAP(0x08000000), -// .LoadAddr = SWAP(0x1007FC00), - .SLA_CodeSize = (unsigned int)&_SLA_Size_SWAP, // Trick to get constant defined at link time - .JumpAddr = &_start_SWAP, - .ArgSize = 0, - .AppVersionNumber = SWAP(APP_VERSION), // 0xAABBCCCC for version AA.BB.CCCC -// .AppVersionNumber = SWAP(LESS_THAN_APP_VERSION), -// .AppVersionNumber = SWAP(GREATER_THAN_APP_VERSION), -}; - -//__attribute__ ((section(".sb_sla_trailer"))) __attribute__ ((__used__)) -//const unsigned int dummy_signature=0xCAFEFADE; - -//#endif //__SLA_FWK__ diff --git a/Libraries/CMSIS/Include/core_rv32.h b/Libraries/CMSIS/Include/core_rv32.h index 716a3d7c907..018cf074475 100644 --- a/Libraries/CMSIS/Include/core_rv32.h +++ b/Libraries/CMSIS/Include/core_rv32.h @@ -1,23 +1,22 @@ -/****************************************************************************** +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. - * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software - * is proprietary to Analog Devices, Inc. and its licensors. + * Portions Copyright (C) 2022-2024 Analog Devices, Inc. * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - ******************************************************************************/ + */ #ifndef LIBRARIES_CMSIS_INCLUDE_CORE_RV32_H_ #define LIBRARIES_CMSIS_INCLUDE_CORE_RV32_H_ @@ -310,14 +309,19 @@ typedef struct { /*@} end of group CMSIS_NVIC */ +/* For MCUs with extra RISCV core (RISCV1) */ +#ifdef __riscv1 +#define MXC_BASE_INTR ((uint32_t)0xE5170000UL) +#define MXC_BASE_EVENT ((uint32_t)0xE5170020UL) +#define MXC_BASE_SLEEP ((uint32_t)0xE5170040UL) +#else #define MXC_BASE_INTR ((uint32_t)0xE5070000UL) -//#define MXC_BASE_INTR ((uint32_t)0xE5000000UL) -#define MXC_INTR ((mxc_intr_regs_t *)MXC_BASE_INTR) #define MXC_BASE_EVENT ((uint32_t)0xE5070020UL) -//#define MXC_BASE_EVENT ((uint32_t)0xE5000020UL) -#define MXC_EVENT ((mxc_event_regs_t *)MXC_BASE_EVENT) #define MXC_BASE_SLEEP ((uint32_t)0xE5070040UL) -//#define MXC_BASE_SLEEP ((uint32_t)0xE5000040UL) +#endif + +#define MXC_INTR ((mxc_intr_regs_t *)MXC_BASE_INTR) +#define MXC_EVENT ((mxc_event_regs_t *)MXC_BASE_EVENT) #define MXC_SLEEP ((mxc_sleep_regs_t *)MXC_BASE_SLEEP) /******************************************************************************* diff --git a/Libraries/MAXUSB/Makefile b/Libraries/MAXUSB/Makefile index cef0db68b0c..3a4769d383e 100644 --- a/Libraries/MAXUSB/Makefile +++ b/Libraries/MAXUSB/Makefile @@ -2,7 +2,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. # (now owned by Analog Devices, Inc.), - # Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + # Copyright (C) 2023-2024Analog Devices, Inc. All Rights Reserved. This software # is proprietary to Analog Devices, Inc. and its licensors. # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -48,6 +48,9 @@ CMSIS_ROOT=../CMSIS endif # Select Full Speed or High Speed Library +ifeq "$(TARGET_UC)" "MAX32572" +TARGET_USB=MUSBHSFC +endif ifeq "$(TARGET_UC)" "MAX32650" TARGET_USB=MUSBHSFC endif diff --git a/Libraries/MAXUSB/maxusb.mk b/Libraries/MAXUSB/maxusb.mk index 90a96d8627a..71c963d114d 100644 --- a/Libraries/MAXUSB/maxusb.mk +++ b/Libraries/MAXUSB/maxusb.mk @@ -2,7 +2,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. # (now owned by Analog Devices, Inc.), - # Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software # is proprietary to Analog Devices, Inc. and its licensors. # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,6 +49,9 @@ export PROJ_LDFLAGS LIBS += ${MAXUSB_BUILD_DIR}/maxusb.a # Select Full Speed or High Speed Library +ifeq "$(TARGET_UC)" "MAX32572" +TARGET_USB=MUSBHSFC +endif ifeq "$(TARGET_UC)" "MAX32650" TARGET_USB=MUSBHSFC endif diff --git a/Libraries/MiscDrivers/Display/tft_ssd2119.c b/Libraries/MiscDrivers/Display/tft_ssd2119.c index ddb9a01f3a1..73dcf3892a4 100644 --- a/Libraries/MiscDrivers/Display/tft_ssd2119.c +++ b/Libraries/MiscDrivers/Display/tft_ssd2119.c @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -494,7 +494,7 @@ static void tft_spi_init(void) int numSlaves = 2; int ssPol = 0; -#if defined(OLD_SPI_API) // Defined in spi.h file if the driver if first version +#if defined(OLD_SPI_API_FUNCTIONS) // Defined in spi.h file if the driver if first version MXC_SPI_Init((mxc_spi_regs_t *)spi, master, quadMode, numSlaves, ssPol, tft_spi_freq); // Todo: diff --git a/Libraries/MiscDrivers/Display/tft_ssd2119.h b/Libraries/MiscDrivers/Display/tft_ssd2119.h index fababbbdc87..0b7f648c779 100644 --- a/Libraries/MiscDrivers/Display/tft_ssd2119.h +++ b/Libraries/MiscDrivers/Display/tft_ssd2119.h @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,7 +32,11 @@ #include #include +#if defined(TS_TSC2007) +#include "tsc2007.h" +#else #include "tsc2046.h" +#endif #ifdef __cplusplus extern "C" { diff --git a/Libraries/MiscDrivers/ExtMemory/Ext_Flash.h b/Libraries/MiscDrivers/ExtMemory/Ext_Flash.h index 58c16fcd570..19341b8f30c 100644 --- a/Libraries/MiscDrivers/ExtMemory/Ext_Flash.h +++ b/Libraries/MiscDrivers/ExtMemory/Ext_Flash.h @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -52,7 +52,7 @@ extern "C" { #define EXT_FLASH_NAME "MX25" -#define EXT_FLASH_Read_DUMMY \ +#define EXT_FLASH_READ_DUMMY \ 8 /**< Dummy byte sent on a standard read command per the MX25 datasheet. */ #define EXT_FLASH_DREAD_DUMMY \ 4 /**< Dummy data sent on a fast-read (Dual) read command per the MX25 datasheet. */ @@ -69,7 +69,7 @@ extern "C" { #define EXT_FLASH_NAME "W25" -#define EXT_FLASH_Read_DUMMY \ +#define EXT_FLASH_READ_DUMMY \ 8 /**< Dummy byte sent on a standard read command per the W25 datasheet. */ #define EXT_FLASH_DREAD_DUMMY \ 4 /**< Dummy data sent on a fast-read (Dual) read command per the W25 datasheet. */ @@ -86,7 +86,7 @@ extern "C" { #define EXT_FLASH_NAME "MX25_64MB" -#define EXT_FLASH_Read_DUMMY \ +#define EXT_FLASH_READ_DUMMY \ 8 /**< Dummy byte sent on a standard read command per the MX25 datasheet. */ #define EXT_FLASH_DREAD_DUMMY \ 4 /**< Dummy data sent on a fast-read (Dual) read command per the MX25 datasheet. */ @@ -99,6 +99,28 @@ extern "C" { #define EXT_FLASH_CMD_DREAD 0xBB /**< Dual SPI Read */ #define EXT_FLASH_CMD_QREAD 0xEB /**< Quad SPI Read */ +#elif defined(EXT_FLASH_IS25) + +#define EXT_FLASH_NAME "IS25" + +#define EXT_FLASH_READ_DUMMY \ + 8 /**< Dummy byte sent on a standard read command per the IS25 datasheet. */ +#define EXT_FLASH_DREAD_DUMMY \ + 4 /**< Dummy data sent on a fast-read (Dual) read command per the IS25 datasheet. */ +#define EXT_FLASH_QREAD_DUMMY \ + 6 /**< Dummy data sent on a fast-read (Quad) read command per the IS25 datasheet. */ + +#define EXT_FLASH_EXP_ID 0x009D7018 + +#define EXT_FLASH_CMD_READ 0x0B /**< Read */ +#define EXT_FLASH_CMD_DREAD 0xBB /**< Dual SPI Read */ +#define EXT_FLASH_CMD_QREAD 0xEB /**< Quad SPI Read */ + +#endif + +#ifdef EXT_FLASH_READ_DUMMY +// Deprecated name. Please use EXT_FLASH_READ_DUMMY +#define EXT_FLASH_Read_DUMMY EXT_FLASH_READ_DUMMY #endif /** diff --git a/Libraries/MiscDrivers/ExtMemory/is25.c b/Libraries/MiscDrivers/ExtMemory/is25.c new file mode 100644 index 00000000000..0cf8068c27b --- /dev/null +++ b/Libraries/MiscDrivers/ExtMemory/is25.c @@ -0,0 +1,626 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file is25.c + * @brief Board layer Driver for the ISSI IS25 Serial Multi-I/O Flash Memory. +*/ + +/* **** Includes **** */ +#include +#include +#include "Ext_Flash.h" + +/** + * @ingroup is25 + * @{ + */ + +/* **** Definitions **** */ +#define IS25_ID_LEN (3) + +#define IS25_WIP_MASK 0x01 /**< Status Reg-1: Work In Progress */ +#define IS25_WEL_MASK 0x02 /**< Status Reg-1: Write Enable Latch mask */ +#define IS25_QE_MASK 0x40 /**< Status Reg-2: Quad-SPI enable mask */ + +#define IS25_DEVICE_SIZE 0x1000000 +#define IS25_BLOCK_SIZE 0x10000 +#define IS25_PAGE_SIZE 256 + +#define IS25_CMD_RST_EN 0x66 /**< Reset Enable */ +#define IS25_CMD_RST_MEM 0x99 /**< Reset Memory */ +#define IS25_CMD_ID 0x9F /**< ID */ +#define IS25_CMD_WRITE_EN 0x06 /**< Write Enable */ +#define IS25_CMD_WRITE_DIS 0x04 /**< Write Disable */ + +#define IS25_CMD_READ_SR 0x05 /**< Read Status Register 1 */ +#define IS25_CMD_WRITE_SR 0x01 /**< Write Status Register 1 */ + +#define IS25_CMD_PPROG 0x02 /**< Page Program */ +#define IS25_CMD_QUAD_PROG 0X32 /**< Quad (4 x I/O) Page Program */ + +#define IS25_CMD_4K_ERASE 0x20 /**< Page Erase */ +#define IS25_CMD_32K_ERASE 0x52 /**< Sector Type 2 (32KB) Erase */ +#define IS25_CMD_64K_ERASE 0xD8 /**< Sector Type 3 (64KB) Erase */ +#define IS25_CMD_BULK_ERASE 0xC7 /**< Bulk Erase */ + +/* **** Globals **** */ + +static Ext_Flash_Config_t g_cfg; +static uint8_t g_is_configured = 0; + +/* **** Static Functions **** */ + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int flash_busy() +{ + uint8_t buf; + + Ext_Flash_Read_SR(&buf, Ext_Flash_StatusReg_1); + + if (buf & IS25_WIP_MASK) { + return EF_E_BUSY; + } else { + return EF_E_SUCCESS; + } +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int write_enable() +{ + int err = EF_E_SUCCESS; + uint8_t cmd = IS25_CMD_WRITE_EN; + uint8_t buf = 0; + + // Send the command + if ((err = g_cfg.write(&cmd, 1, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + if ((err = Ext_Flash_Read_SR(&buf, Ext_Flash_StatusReg_1)) != EF_E_SUCCESS) { + return err; + } + + if (buf & IS25_WEL_MASK) { + return EF_E_SUCCESS; + } + + return EF_E_BAD_STATE; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int inline read_reg(uint8_t cmd, uint8_t *buf) +{ + int err = EF_E_SUCCESS; + + if (!buf) { + return EF_E_BAD_PARAM; + } + + // Send the command + if ((err = g_cfg.write(&cmd, 1, 0, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + // Read the data + if ((err = g_cfg.read(buf, 1, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +static int inline write_reg(uint8_t *buf, unsigned len) +{ + int err = EF_E_SUCCESS; + + if (!buf || (len == 0)) { + return EF_E_BAD_PARAM; + } + + if ((err = write_enable()) != EF_E_SUCCESS) { + return err; + } + + // Send the command and data + if ((err = g_cfg.write(buf, len, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + return EF_E_SUCCESS; +} + +/* **** Functions **** */ + +int Ext_Flash_Configure(Ext_Flash_Config_t *cfg) +{ + int err = EF_E_SUCCESS; + + if (cfg == NULL) { + return EF_E_BAD_PARAM; + } + + g_cfg = *cfg; + g_is_configured = 1; + + return err; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Init(void) +{ + if (!g_is_configured) { + return EF_E_BAD_STATE; + } + + return g_cfg.init(); +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Reset(void) +{ + int err = EF_E_SUCCESS; + int busy_count = 0; + uint8_t cmd = IS25_CMD_RST_EN; + + // Send the Reset command + if ((err = g_cfg.write(&cmd, 1, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + cmd = IS25_CMD_RST_MEM; + if ((err = g_cfg.write(&cmd, 1, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) { + busy_count++; + if (busy_count > 20000) { + return EF_E_TIME_OUT; + } + } + + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +uint32_t Ext_Flash_ID(void) +{ + int err = EF_E_SUCCESS; + uint8_t cmd = IS25_CMD_ID; + uint8_t id[IS25_ID_LEN]; + + // Send the command + if ((err = g_cfg.write(&cmd, 1, 0, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + // Read the data + if ((err = g_cfg.read(id, IS25_ID_LEN, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + return ((uint32_t)(id[2] | (id[1] << 8) | (id[0] << 16))); +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Quad(int enable) +{ + int err = EF_E_SUCCESS; + uint8_t pre_buf = 0; + uint8_t post_buf = 0; + + // Enable QSPI mode + if ((err = Ext_Flash_Read_SR(&pre_buf, Ext_Flash_StatusReg_1)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) {} + + if (enable) { + if (pre_buf & IS25_QE_MASK) { + return EF_E_SUCCESS; + } + pre_buf |= IS25_QE_MASK; + } else { + if (!(pre_buf & IS25_QE_MASK)) { + return EF_E_SUCCESS; + } + pre_buf &= ~IS25_QE_MASK; + } + + if (write_enable() != EF_E_SUCCESS) { + return EF_E_BAD_STATE; + } + + if ((err = Ext_Flash_Write_SR(pre_buf, Ext_Flash_StatusReg_1)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) {} + + if ((err = Ext_Flash_Read_SR(&post_buf, Ext_Flash_StatusReg_1)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) {} + + if (enable) { + if (!(post_buf & IS25_QE_MASK)) { + return EF_E_ERROR; + } + } else { + if (post_buf & IS25_QE_MASK) { + return EF_E_ERROR; + } + } + + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Read(uint32_t address, uint8_t *rx_buf, uint32_t rx_len, Ext_Flash_DataLine_t d_line) +{ + int err = EF_E_SUCCESS; + uint8_t cmd[4] = { 0 }; + uint8_t dummy_bits = 0; + + if (flash_busy()) { + return EF_E_BUSY; + } + + cmd[1] = (address >> 16) & 0xFF; + cmd[2] = (address >> 8) & 0xFF; + cmd[3] = address & 0xFF; + + // Select approriate command for the desired read mode + if (d_line == Ext_Flash_DataLine_Single) { + cmd[0] = EXT_FLASH_CMD_READ; + dummy_bits = EXT_FLASH_READ_DUMMY; + } else if (d_line == Ext_Flash_DataLine_Dual) { + cmd[0] = EXT_FLASH_CMD_DREAD; + dummy_bits = EXT_FLASH_DREAD_DUMMY; + } else { + cmd[0] = EXT_FLASH_CMD_QREAD; + dummy_bits = EXT_FLASH_QREAD_DUMMY; + } + + // Send command + if ((err = g_cfg.write(&cmd[0], 1, 0, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + // Send starting address of the read + if ((err = g_cfg.write(&cmd[1], 3, 0, d_line)) != EF_E_SUCCESS) { + return err; + } + + // Send dummy bits + g_cfg.clock(dummy_bits, 0); + + // Receive the data + if ((err = g_cfg.read(rx_buf, rx_len, 1, d_line)) != EF_E_SUCCESS) { + return err; + } + + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Program_Page(uint32_t address, uint8_t *tx_buf, uint32_t tx_len, + Ext_Flash_DataLine_t d_line) +{ + int err = EF_E_SUCCESS; + volatile int timeout = 0; + uint8_t cmd[4] = { 0 }; + uint32_t len = 0; + uint32_t next_page = 0; + uint8_t *pWrite_Data = NULL; + + if (tx_buf == NULL) { + return EF_E_BAD_PARAM; + } + + // if flash address is out-of-range + if ((address >= IS25_DEVICE_SIZE) || ((address + tx_len) > IS25_DEVICE_SIZE)) { + return EF_E_BAD_PARAM; // attempt to write outside flash memory size + } + + // Device only supports page program in Standard and Quad modes + if (d_line == Ext_Flash_DataLine_Dual) { + return EF_E_ERROR; + } + + pWrite_Data = tx_buf; // note our starting source data address + + if (flash_busy()) { + return EF_E_BUSY; + } + + // Now write out as many pages of flash as required to fulfil the request + while (tx_len > 0) { + while (write_enable()) { + timeout++; + if (timeout > 100) { + return EF_E_TIME_OUT; + } + } + + cmd[1] = (address >> 16) & 0xFF; + cmd[2] = (address >> 8) & 0xFF; + cmd[3] = address & 0xFF; + + // Send the command and dummy bits + if (d_line == Ext_Flash_DataLine_Quad) { + cmd[0] = IS25_CMD_QUAD_PROG; + } else { + cmd[0] = IS25_CMD_PPROG; + } + + if ((err = g_cfg.write(&cmd[0], 1, 0, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + // Send the address + if ((err = g_cfg.write(&cmd[1], 3, 0, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + // calculate the next flash page boundary from our starting address + next_page = ((address & ~(IS25_PAGE_SIZE - 1)) + IS25_PAGE_SIZE); + + // Now check for how much data to write on this page of flash + if ((address + tx_len) < next_page) { + len = tx_len; // no page boundary is crossed + } else { + len = next_page - address; // adjust length of this write to say within the current page + } + + // Write the data + if ((err = g_cfg.write(pWrite_Data, len, 1, d_line)) != EF_E_SUCCESS) { + return err; + } + + if (tx_len >= len) { + tx_len -= len; // what's left to write + } + + // if there is more to write + if (tx_len > 0) { + address += len; // calculate new starting flash_address + pWrite_Data += len; // and source data address + } + + timeout = 0; + while (flash_busy()) { + timeout++; + if (timeout > 10000) { + return EF_E_TIME_OUT; + } + } + } + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Bulk_Erase(void) +{ + int err = EF_E_SUCCESS; + uint8_t cmd = IS25_CMD_BULK_ERASE; + volatile int timeout = 0; + + if (flash_busy()) { + return EF_E_BUSY; + } + + if (write_enable() != 0) { + return EF_E_BAD_STATE; + } + + // Send the command + if ((err = g_cfg.write(&cmd, 1, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) { + timeout++; + if (timeout > 100000000) { + return EF_E_TIME_OUT; + } + } + + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Erase(uint32_t address, Ext_Flash_Erase_t size) +{ + int err = EF_E_SUCCESS; + uint8_t cmd[4] = { 0 }; + volatile int timeout = 0; + + if (flash_busy()) { + return EF_E_BUSY; + } + + while (write_enable()) { + timeout++; + if (timeout > 100) { + return EF_E_BAD_STATE; + } + } + + switch (size) { + case Ext_Flash_Erase_4K: + default: + cmd[0] = IS25_CMD_4K_ERASE; + break; + case Ext_Flash_Erase_32K: + cmd[0] = IS25_CMD_32K_ERASE; + break; + case Ext_Flash_Erase_64K: + cmd[0] = IS25_CMD_64K_ERASE; + break; + } + + cmd[1] = (address >> 16) & 0xFF; + cmd[2] = (address >> 8) & 0xFF; + cmd[3] = address & 0xFF; + + // Send the command and the address + if ((err = g_cfg.write(&cmd[0], 4, 1, Ext_Flash_DataLine_Single)) != EF_E_SUCCESS) { + return err; + } + + while (flash_busy()) { + timeout++; + if (timeout > 1000000000) { + return EF_E_TIME_OUT; + } + } + return EF_E_SUCCESS; +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Read_SR(uint8_t *buf, Ext_Flash_StatusReg_t reg_num) +{ + uint8_t cmd = 0; + + if (buf == NULL) { + return EF_E_BAD_PARAM; + } + + switch (reg_num) { + case Ext_Flash_StatusReg_1: + cmd = IS25_CMD_READ_SR; + break; + default: + return EF_E_BAD_PARAM; + } + + return read_reg(cmd, buf); +} + +/* ************************************************************************* */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif +int Ext_Flash_Write_SR(uint8_t value, Ext_Flash_StatusReg_t reg_num) +{ + uint8_t cmd = 0; + + switch (reg_num) { + case Ext_Flash_StatusReg_1: + cmd = IS25_CMD_WRITE_SR; + break; + default: + return EF_E_BAD_PARAM; + } + + uint8_t cmd_seq[2] = { cmd, value }; + + return write_reg(cmd_seq, 2); +} + +/* ************************************************************************* */ +int Ext_Flash_Block_WP(uint32_t addr, uint32_t begin) +{ + // not implemented yet + return EF_E_BAD_PARAM; +} + +/* ************************************************************************* */ +Ext_Flash_Unblk_t Ext_Flash_GetAvailableFlash(void) +{ + // not implemented yet + Ext_Flash_Unblk_t free_flash; + free_flash.start_addr = 0; + free_flash.end_addr = 0; + + return free_flash; +} +/**@} end of ingroup is25 */ diff --git a/Libraries/MiscDrivers/ExtMemory/mx25.c b/Libraries/MiscDrivers/ExtMemory/mx25.c index ac8cd399d12..770bb26155c 100644 --- a/Libraries/MiscDrivers/ExtMemory/mx25.c +++ b/Libraries/MiscDrivers/ExtMemory/mx25.c @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -290,7 +290,7 @@ int Ext_Flash_Read(uint32_t address, uint8_t *rx_buf, uint32_t rx_len, Ext_Flash // Select approriate command for the desired read mode if (d_line == Ext_Flash_DataLine_Single) { cmd[0] = EXT_FLASH_CMD_READ; - dummy_bits = EXT_FLASH_Read_DUMMY; + dummy_bits = EXT_FLASH_READ_DUMMY; } else if (d_line == Ext_Flash_DataLine_Dual) { cmd[0] = EXT_FLASH_CMD_DREAD; dummy_bits = EXT_FLASH_DREAD_DUMMY; diff --git a/Libraries/MiscDrivers/ExtMemory/mx25_64MB.c b/Libraries/MiscDrivers/ExtMemory/mx25_64MB.c index b711fa3eeac..1ac8af433e3 100644 --- a/Libraries/MiscDrivers/ExtMemory/mx25_64MB.c +++ b/Libraries/MiscDrivers/ExtMemory/mx25_64MB.c @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -291,7 +291,7 @@ int Ext_Flash_Read(uint32_t address, uint8_t *rx_buf, uint32_t rx_len, Ext_Flash // Select approriate command for the desired read mode if (d_line == Ext_Flash_DataLine_Single) { cmd[0] = EXT_FLASH_CMD_READ; - dummy_bits = EXT_FLASH_Read_DUMMY; + dummy_bits = EXT_FLASH_READ_DUMMY; } else if (d_line == Ext_Flash_DataLine_Dual) { cmd[0] = EXT_FLASH_CMD_DREAD; dummy_bits = EXT_FLASH_DREAD_DUMMY; diff --git a/Libraries/MiscDrivers/ExtMemory/w25.c b/Libraries/MiscDrivers/ExtMemory/w25.c index a9477eb8959..1063573bc3a 100644 --- a/Libraries/MiscDrivers/ExtMemory/w25.c +++ b/Libraries/MiscDrivers/ExtMemory/w25.c @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -327,7 +327,7 @@ int Ext_Flash_Read(uint32_t address, uint8_t *rx_buf, uint32_t rx_len, Ext_Flash // Select approriate command for the desired read mode if (d_line == Ext_Flash_DataLine_Single) { cmd[0] = EXT_FLASH_CMD_READ; - dummy_bits = EXT_FLASH_Read_DUMMY; + dummy_bits = EXT_FLASH_READ_DUMMY; } else if (d_line == Ext_Flash_DataLine_Dual) { cmd[0] = EXT_FLASH_CMD_DREAD; dummy_bits = EXT_FLASH_DREAD_DUMMY; diff --git a/Libraries/MiscDrivers/Touchscreen/tsc2007.c b/Libraries/MiscDrivers/Touchscreen/tsc2007.c new file mode 100644 index 00000000000..6c9c3d816ce --- /dev/null +++ b/Libraries/MiscDrivers/Touchscreen/tsc2007.c @@ -0,0 +1,303 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "mxc_device.h" +#include "mxc_delay.h" +#include "tsc2007.h" + +/************************************ DEFINES ********************************/ +#ifndef FLIP_SCREEN +#define FLIP_SCREEN 0 +#endif +#ifndef SWAP_XY +#define SWAP_XY 0 +#endif +#ifndef ROTATE_SCREEN +#define ROTATE_SCREEN 0 +#endif +#define X_RES_T 320 +#define Y_RES_T 240 + +#define ADC_Z_THRESHOLD 0x7F0 +#define ADC_X_MIN 232 +#define ADC_X_MAX 3888 +#define ADC_Y_MIN 375 +#define ADC_Y_MAX 3799 + +#define NOT_IN_BOX 0 +#define IN_BOX 1 + +/******************************* TYPE DEFINITIONS ****************************/ +typedef struct _TS_Buttons_t { + int x0; + int y0; + int x1; + int y1; + int key_code; +} TS_Buttons_t; + +static TS_Buttons_t ts_buttons[TS_MAX_BUTTONS]; +static int pressed_key = 0; +static mxc_i2c_regs_t *t_i2c; +static unsigned int t_i2c_freq; +static mxc_gpio_cfg_t int_gpio; +static mxc_gpio_cfg_t t_i2c_gpio; +unsigned int g_x, g_y = 0; +// Global touchscreen event flag that can be polled by applications if needed. +// The application should clear it to 0 if used. +// It is set to 1 eve +int ts_event = false; + +uint16_t tsX, tsY, tsZ1; + +static uint8_t tsConstructCommand(mxc_ts_cmd_func_t function, mxc_ts_cmd_pdown_t pdown, + mxc_ts_cmd_mode_t mode) +{ + // Bits D7-D4: C3-C0 => converter function select bits + // Bits D3-D2: PD1-PD0 => power-down bits + // Bits D1: M => mode bit + // Bits D0: X => don't care + uint8_t command = (uint8_t)function << 4; + command |= (uint8_t)pdown << 2; + command |= (uint8_t)mode << 1; + return command; +} + +static int isInBox(int x, int y, int x0, int y0, int x1, int y1) +{ + if ((x >= x0) && (x <= x1) && (y >= y0) && (y <= y1)) { + return IN_BOX; + } + + return NOT_IN_BOX; +} + +static int tsGetXY(uint16_t *x, uint16_t *y) +{ + int ret; + + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_Z1, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), &tsZ1); + if (tsZ1 & ADC_Z_THRESHOLD) { +#if (SWAP_XY == 1) + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_Y, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), &tsX); + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_X, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), &tsY); +#else + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_Y, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), &tsY); + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_X, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), &tsX); +#endif + + // Wait Release + do { + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_Z1, TSC_ADC_ON_IRQ_DIS_0, TSC_12_BIT), + &tsZ1); + } while (tsZ1 & ADC_Z_THRESHOLD); + + *x = (((tsX - ADC_X_MIN) * X_RES_T) / (ADC_X_MAX - ADC_X_MIN)); + *y = (((tsY - ADC_Y_MIN) * Y_RES_T) / (ADC_Y_MAX - ADC_Y_MIN)); + +#if (FLIP_SCREEN == 1) + *x = X_RES_T - *x; + *y = Y_RES_T - *y; +#elif (ROTATE_SCREEN == 1) + uint16_t swap = *x; + *x = Y_RES_T - *y - 1; + *y = swap; +#endif + ret = 1; + + } else { +#if (FLIP_SCREEN == 1) + *x = X_RES_T; + *y = Y_RES_T; +#elif (ROTATE_SCREEN == 1) + *x = Y_RES_T; + *y = X_RES_T; +#else + *x = 0; + *y = 0; +#endif + + ret = 0; + } + + // power down ADC and enable IRQ for next touch + TS_I2C_Transmit(tsConstructCommand(TSC_MEASURE_TEMP0, TSC_POWER_DOWN_IRQ_EN, TSC_12_BIT), NULL); + + return ret; +} + +static void tsHandler(void) +{ + uint32_t i; + + MXC_TS_Stop(); + + if (tsGetXY((uint16_t *)&g_x, (uint16_t *)&g_y)) { + ts_event = true; + if (pressed_key == 0) { // wait until prev key process + for (i = 0; i < TS_MAX_BUTTONS; i++) { + if (ts_buttons[i].key_code != TS_INVALID_KEY_CODE) { + if (isInBox(g_x, g_y, ts_buttons[i].x0, ts_buttons[i].y0, ts_buttons[i].x1, + ts_buttons[i].y1)) { + // pressed key + pressed_key = ts_buttons[i].key_code; + break; + } + } + } + } + } + MXC_GPIO_ClearFlags(int_gpio.port, int_gpio.mask); + MXC_TS_Start(); +} + +int MXC_TS_AssignInterruptPin(mxc_gpio_cfg_t pin) +{ + if (pin.port) { + int_gpio = pin; + return E_NO_ERROR; + } else { + return E_BAD_PARAM; + } +} + +int MXC_TS_PreInit(mxc_ts_i2c_config *i2c_config, mxc_gpio_cfg_t *int_pin) +{ + int result = E_NO_ERROR; + + if ((int_pin == NULL) || (i2c_config == NULL)) { + return E_NULL_PTR; + } + + t_i2c = i2c_config->regs; + t_i2c_freq = i2c_config->freq; + int_gpio = *int_pin; + t_i2c_gpio = i2c_config->gpio; + + return result; +} + +int MXC_TS_Init(void) +{ + int result = E_NO_ERROR; + + // Touchscreen interrupt pin + MXC_GPIO_Config(&int_gpio); + MXC_GPIO_RegisterCallback(&int_gpio, (mxc_gpio_callback_fn)tsHandler, NULL); + MXC_GPIO_IntConfig(&int_gpio, MXC_GPIO_INT_FALLING); + + // Configure I2C Pins + TS_I2C_Init(); + + MXC_TS_RemoveAllButton(); + + // Configure touchscreen interrupt +#ifndef __riscv + NVIC_SetPriority(MXC_GPIO_GET_IRQ(MXC_GPIO_GET_IDX(int_gpio.port)), 5); +#endif + NVIC_EnableIRQ(MXC_GPIO_GET_IRQ(MXC_GPIO_GET_IDX(int_gpio.port))); + + MXC_TS_Stop(); + + return result; +} + +void MXC_TS_Start(void) +{ + MXC_GPIO_EnableInt(int_gpio.port, int_gpio.mask); +} + +void MXC_TS_Stop(void) +{ + MXC_GPIO_DisableInt(int_gpio.port, int_gpio.mask); +} + +void MXC_TS_GetXY(unsigned int *x, unsigned int *y) +{ + *x = g_x; + *y = g_y; +} + +int MXC_TS_GetTSEvent() +{ + return ts_event; +} + +void MXC_TS_ClearTSEvent() +{ + ts_event = false; +} + +int MXC_TS_AddButton(int x0, int y0, int x1, int y1, int on_press_expected_code) +{ + int index; + + for (index = TS_MAX_BUTTONS - 1; index >= 0; index--) { + if (ts_buttons[index].key_code == TS_INVALID_KEY_CODE) { + ts_buttons[index].x0 = x0; + ts_buttons[index].y0 = y0; + ts_buttons[index].x1 = x1; + ts_buttons[index].y1 = y1; + ts_buttons[index].key_code = on_press_expected_code; + break; + } + } + + return index; +} + +void MXC_TS_RemoveButton(int x0, int y0, int x1, int y1) +{ + int i; + + for (i = 0; i < TS_MAX_BUTTONS; i++) { + if (ts_buttons[i].key_code != TS_INVALID_KEY_CODE) { + if (isInBox(x0, y0, ts_buttons[i].x0, ts_buttons[i].y0, ts_buttons[i].x1, + ts_buttons[i].y1)) { + // clear flag + ts_buttons[i].key_code = TS_INVALID_KEY_CODE; + } + } + } +} + +void MXC_TS_RemoveAllButton(void) +{ + int i; + + for (i = 0; i < TS_MAX_BUTTONS; i++) { + ts_buttons[i].key_code = TS_INVALID_KEY_CODE; + } +} + +int MXC_TS_GetKey(void) +{ + int key; + + key = pressed_key; + pressed_key = 0; + + return key; +} diff --git a/Libraries/MiscDrivers/Touchscreen/tsc2007.h b/Libraries/MiscDrivers/Touchscreen/tsc2007.h new file mode 100644 index 00000000000..b94a7614018 --- /dev/null +++ b/Libraries/MiscDrivers/Touchscreen/tsc2007.h @@ -0,0 +1,161 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_MISCDRIVERS_TOUCHSCREEN_TSC2007_H_ +#define LIBRARIES_MISCDRIVERS_TOUCHSCREEN_TSC2007_H_ + +#include +#include + +#ifndef TS_MAX_BUTTONS +#define TS_MAX_BUTTONS 16 +#endif +#define TS_INVALID_KEY_CODE -1 + +#define TSC2007_I2C_TARGET_ADDRESS 0x48 + +typedef enum { + TSC_MEASURE_TEMP0 = 0b0000, + TSC_MEASURE_AUX = 0b0010, + TSC_MEASURE_TEMP1 = 0b0100, + TSC_ACTIVATE_X_NEGATIVE = 0b1000, + TSC_ACTIVATE_Y_NEGATIVE = 0b1001, + TSC_ACTIVATE_Y_POSITIVE_X_NEGATIVE = 0b1010, + TSC_SETUP_COMMAND = 0b1011, + TSC_MEASURE_X = 0b1100, + TSC_MEASURE_Y = 0b1101, + TSC_MEASURE_Z1 = 0b1110, + TSC_MEASURE_Z2 = 0b1111 +} mxc_ts_cmd_func_t; + +typedef enum { + TSC_POWER_DOWN_IRQ_EN = 0b00, + TSC_ADC_ON_IRQ_DIS_0 = 0b01, + TSC_ADC_OFF_IRQ_EN = 0b10, + TSC_ADC_ON_IRQ_DIS_1 = 0b11 +} mxc_ts_cmd_pdown_t; + +typedef enum { TSC_12_BIT = 0b0, TSC_8_BIT = 0b1 } mxc_ts_cmd_mode_t; + +typedef struct { + mxc_i2c_regs_t *regs; // The I2C instance the touchscreen controller is connected to + mxc_gpio_cfg_t gpio; // The I2C pins: SDA and SCL, must define all them + unsigned int freq; // The I2C frequency +} mxc_ts_i2c_config; + +/************************************************************************************/ + +// I2C Transport layer functions + +/** + * @brief Initialize the I2C instance connected to the TouchScreen driver. + * Board files must implement this. + */ +extern void TS_I2C_Init(void); + +/** + * @brief Send a byte of data to the TouchScreen driver over I2C. + * Board files must implement this. + * + * @param datain Input value to write + * @param[out] dataout Output pointer. This function will decode and save + * the I2C response to this pointer. + */ +extern void TS_I2C_Transmit(uint8_t datain, uint16_t *dataout); + +/************************************************************************************/ + +int MXC_TS_AssignInterruptPin(mxc_gpio_cfg_t pin); + +/** + * @brief Used to register hw related configuration, need to be called before MXC_TS_Init() + * + * @param i2c_config Touch screen I2C configuration + * @param int_pin The GPIO pin configuration for the touchscreen controller's interrupt pin + * + * @return See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TS_PreInit(mxc_ts_i2c_config *i2c_config, mxc_gpio_cfg_t *int_pin); + +/** + * @brief Initialize the touchscreen controller + * + * @return See \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TS_Init(void); + +/** + * @brief Enables touch interrupts + * + */ +void MXC_TS_Start(void); + +/** + * @brief Disables touch interrupts + * + */ +void MXC_TS_Stop(void); + +/** + * @brief Get the x,y coordinates of the last touchscreen press + * + * @param[out] x (Output) Where to save the x coordinate + * @param[out] y (Output) Where to save the y coordinate + */ +void MXC_TS_GetXY(unsigned int *x, unsigned int *y); + +/** + * @brief Returns true if there is a touchscreen event pending, + * otherwise returns false. + */ +int MXC_TS_GetTSEvent(); + +/** + * @brief Clears the pending touchscreen event flag. + */ +void MXC_TS_ClearTSEvent(); + +/** + * @brief Register a button + * +* @param x0, y0, x1, y1 location of button +* @param on_press_expected_code expected keycode when touch related point area + */ +int MXC_TS_AddButton(int x0, int y0, int x1, int y1, int on_press_expected_code); + +/** + * @brief Remove a button + * + * @param x0, y0, x1, y1 location of button + */ +void MXC_TS_RemoveButton(int x0, int y0, int x1, int y1); + +/** + * @brief Remove all registered keys + * + */ +void MXC_TS_RemoveAllButton(void); + +/** + * @brief Read pressed key + * + */ +int MXC_TS_GetKey(void); + +#endif // LIBRARIES_MISCDRIVERS_TOUCHSCREEN_TSC2007_H_ diff --git a/Libraries/MiscDrivers/Touchscreen/tsc2046.c b/Libraries/MiscDrivers/Touchscreen/tsc2046.c index c8f83bbb67c..0b40ec4ae50 100644 --- a/Libraries/MiscDrivers/Touchscreen/tsc2046.c +++ b/Libraries/MiscDrivers/Touchscreen/tsc2046.c @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,6 +20,7 @@ ******************************************************************************/ #include +#include #include #include #include diff --git a/Libraries/PeriphDrivers/Include/MAX32520/i2c.h b/Libraries/PeriphDrivers/Include/MAX32520/i2c.h index 2671ecee3f2..fd96f348762 100644 --- a/Libraries/PeriphDrivers/Include/MAX32520/i2c.h +++ b/Libraries/PeriphDrivers/Include/MAX32520/i2c.h @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -168,7 +168,6 @@ typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_ /** * @brief Initialize and enable I2C peripheral. - * * @param i2c Pointer to I2C registers (selects the I2C block used.) * @param masterMode Whether to put the device in master or slave mode. Use diff --git a/Libraries/PeriphDrivers/Include/MAX32572/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32572/mxc_pins.h index b76b1259d60..92a12924453 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/mxc_pins.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/mxc_pins.h @@ -108,4 +108,6 @@ extern const mxc_gpio_cfg_t gpio_cfg_adc_ain5; extern const mxc_gpio_cfg_t gpio_cfg_adc_ain6; extern const mxc_gpio_cfg_t gpio_cfg_adc_ain7; +extern const mxc_gpio_cfg_t gpio_cfg_skbd_P2; + #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_MXC_PINS_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32572/sfcc.h b/Libraries/PeriphDrivers/Include/MAX32572/sfcc.h new file mode 100644 index 00000000000..e8fd3ac3fc5 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32572/sfcc.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file sfcc.h + * @brief SPI Flash Controller Cache(SFCC) function prototypes and data types. + */ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_SFCC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_SFCC_H_ + +/* **** Includes **** */ +#include +#include "sfcc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sfcc SFCC + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for the Cache ID Register + */ +typedef enum { + SFCC_INFO_RELNUM, ///< Identifies the Release Number + SFCC_INFO_PARTNUM, ///< Specifies the value of Cache ID Part Number + SFCC_INFO_ID ///< Specifies the value of Cache ID +} mxc_sfcc_info_t; + +/** + * @brief Reads the data from the Cache Id Register. + * @param cid Enumeration type for Cache Id Register. + * @retval Returns the contents of Cache Id Register. + */ +int MXC_SFCC_ID(mxc_sfcc_info_t cid); + +/** + * @brief Enable the instruction cache controller. + */ +void MXC_SFCC_Enable(void); + +/** + * @brief Disable the instruction cache controller. + */ +void MXC_SFCC_Disable(void); + +/** + * @brief Flush the instruction cache controller. + */ +void MXC_SFCC_Flush(void); + +/**@} end of group sfcc */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32572_SFCC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32572/skbd.h b/Libraries/PeriphDrivers/Include/MAX32572/skbd.h index 5ae9ca3cd70..9388b4973cc 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/skbd.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/skbd.h @@ -7,7 +7,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -130,6 +130,21 @@ typedef enum { MXC_SKBD_KBDIO9 = (0x01 << 9), ///< SKBD pin 9 } mxc_skbd_io_pins_t; +/** + * @brief Keypad Debounce Time + * + */ +typedef enum { + MXC_SKBD_DBTM_TIME4MS = MXC_V_SKBD_CTRL1_DBTM_TIME4MS, ///< SKBD Debounce Time 4ms + MXC_SKBD_DBTM_TIME5MS = MXC_V_SKBD_CTRL1_DBTM_TIME5MS, ///< SKBD Debounce Time 5ms + MXC_SKBD_DBTM_TIME6MS = MXC_V_SKBD_CTRL1_DBTM_TIME6MS, ///< SKBD Debounce Time 6ms + MXC_SKBD_DBTM_TIME7MS = MXC_V_SKBD_CTRL1_DBTM_TIME7MS, ///< SKBD Debounce Time 7ms + MXC_SKBD_DBTM_TIME8MS = MXC_V_SKBD_CTRL1_DBTM_TIME8MS, ///< SKBD Debounce Time 8ms + MXC_SKBD_DBTM_TIME10MS = MXC_V_SKBD_CTRL1_DBTM_TIME10MS, ///< SKBD Debounce Time 10ms + MXC_SKBD_DBTM_TIME11MS = MXC_V_SKBD_CTRL1_DBTM_TIME11MS, ///< SKBD Debounce Time 11ms + MXC_SKBD_DBTM_TIME12MS = MXC_V_SKBD_CTRL1_DBTM_TIME12MS, ///< SKBD Debounce Time 12ms +} mxc_skbd_debounce_time_t; + /** * @brief Keypad IRQ handler function * diff --git a/Libraries/PeriphDrivers/Include/MAX32572/wdt.h b/Libraries/PeriphDrivers/Include/MAX32572/wdt.h index e70619a15c5..775edf71255 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/wdt.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/wdt.h @@ -4,11 +4,10 @@ */ /****************************************************************************** - * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/PeriphDrivers/Source/AES/aeskeys_reva.svd b/Libraries/PeriphDrivers/Source/AES/aeskeys_reva.svd new file mode 100644 index 00000000000..b28aa59155f --- /dev/null +++ b/Libraries/PeriphDrivers/Source/AES/aeskeys_reva.svd @@ -0,0 +1,33 @@ + + + + + AESKEYS + AES Keys. + 0x40005000 + + 0x00 + 0x400 + registers + + + + SRAM_KEY + AES SRAM KEY + 0x00 + 32 + + + CODE_KEY + AES CODE Key + 0x20 + + + DATA_KEY + AES DATA KEY + 0x40 + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/AES/aeskeys_revb.svd b/Libraries/PeriphDrivers/Source/AES/aeskeys_revb.svd new file mode 100644 index 00000000000..877efe87928 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/AES/aeskeys_revb.svd @@ -0,0 +1,65 @@ + + + + + AESKEYS + AES Key Registers. + 0x40007800 + + 0x00 + 0x400 + registers + + + + KEY0 + AES Key 0. + 0x00 + 32 + + + KEY1 + AES Key 1. + 0x04 + 32 + + + KEY2 + AES Key 2. + 0x08 + 32 + + + KEY3 + AES Key 3. + 0x0C + 32 + + + KEY4 + AES Key 4. + 0x10 + 32 + + + KEY5 + AES Key 5. + 0x14 + 32 + + + KEY6 + AES Key 6. + 0x18 + 32 + + + KEY7 + AES Key 7. + 0x1C + 32 + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me55.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me55.c index 3b0c7c43b9d..20135329b67 100644 --- a/Libraries/PeriphDrivers/Source/RTC/rtc_me55.c +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me55.c @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -63,7 +63,8 @@ int MXC_RTC_Stop(void) int MXC_RTC_Init(uint32_t sec, uint16_t ssec) { - MXC_MCR->clkctrl |= MXC_F_MCR_CLKCTRL_ERTCO_EN; + MXC_MCR->ctrl |= MXC_F_MCR_CLKCTRL_ERTCO_EN; + MXC_MCR->clkctrl &= ~(MXC_F_MCR_CLKCTRL_ERTCO_PD); return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_SSEC)); } diff --git a/Libraries/PeriphDrivers/Source/SFCC/sfcc_me55.c b/Libraries/PeriphDrivers/Source/SFCC/sfcc_me55.c new file mode 100644 index 00000000000..c6e9a1aa02d --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SFCC/sfcc_me55.c @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "sfcc.h" +#include "sfcc_reva.h" + +int MXC_SFCC_ID(mxc_sfcc_info_t cid) +{ + return MXC_SFCC_RevA_ID((mxc_sfcc_reva_regs_t *)MXC_SFCC, cid); +} + +void MXC_SFCC_Enable(void) +{ + MXC_SFCC_RevA_Enable((mxc_sfcc_reva_regs_t *)MXC_SFCC); +} + +void MXC_SFCC_Disable(void) +{ + MXC_SFCC_RevA_Disable((mxc_sfcc_reva_regs_t *)MXC_SFCC); +} + +void MXC_SFCC_Flush(void) +{ + /* NOTE: MEMPROT authentication bytes are not flushed with the SFCC invalidate bits, + * the GCR SFCC flush is required. + */ + /* Flush all instruction caches */ + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_SFCC_FLUSH; + + /* Wait for flush to complete */ + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_SFCC_FLUSH) {} + + MXC_SFCC_Disable(); + MXC_SFCC_Enable(); +} diff --git a/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.c b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.c new file mode 100644 index 00000000000..1894f78f5b0 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.c @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "sfcc.h" +#include "sfcc_reva.h" +#include "sfcc_reva_regs.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ +static int MXC_SFCC_Ready(mxc_sfcc_reva_regs_t *sfcc) +{ + return (sfcc->ctrl & MXC_F_SFCC_REVA_CTRL_RDY); +} + +int MXC_SFCC_RevA_ID(mxc_sfcc_reva_regs_t *sfcc, mxc_sfcc_info_t cid) +{ + if (sfcc == NULL) { + return E_NULL_PTR; + } + + switch (cid) { + case SFCC_INFO_RELNUM: + return ((sfcc->info & MXC_F_SFCC_REVA_INFO_RELNUM) >> MXC_F_SFCC_REVA_INFO_RELNUM_POS); + + case SFCC_INFO_PARTNUM: + return ((sfcc->info & MXC_F_SFCC_REVA_INFO_PARTNUM) >> MXC_F_SFCC_REVA_INFO_PARTNUM_POS); + + case SFCC_INFO_ID: + return ((sfcc->info & MXC_F_SFCC_REVA_INFO_ID) >> MXC_F_SFCC_REVA_INFO_ID_POS); + + default: + return E_BAD_PARAM; + } +} + +void MXC_SFCC_RevA_Enable(mxc_sfcc_reva_regs_t *sfcc) +{ + // Invalidate cache and wait until ready + sfcc->ctrl &= ~MXC_F_SFCC_REVA_CTRL_EN; + sfcc->invalidate = 1; + + while (!(MXC_SFCC_Ready(sfcc))) {} + + // Enable Cache + sfcc->ctrl |= MXC_F_SFCC_REVA_CTRL_EN; + while (!(MXC_SFCC_Ready(sfcc))) {} +} + +void MXC_SFCC_RevA_Disable(mxc_sfcc_reva_regs_t *sfcc) +{ + // Disable Cache + sfcc->ctrl &= ~MXC_F_SFCC_REVA_CTRL_EN; +} diff --git a/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.h b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.h new file mode 100644 index 00000000000..505a78931a7 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva.h @@ -0,0 +1,41 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "sfcc.h" +#include "sfcc_reva_regs.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +int MXC_SFCC_RevA_ID(mxc_sfcc_reva_regs_t *sfcc, mxc_sfcc_info_t cid); +void MXC_SFCC_RevA_Enable(mxc_sfcc_reva_regs_t *sfcc); +void MXC_SFCC_RevA_Disable(mxc_sfcc_reva_regs_t *sfcc); + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_H_ diff --git a/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva_regs.h b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva_regs.h new file mode 100644 index 00000000000..596296ec485 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SFCC/sfcc_reva_regs.h @@ -0,0 +1,156 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. All Rights Reserved. This software + * is proprietary to Analog Devices, Inc. and its licensors. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + + /** + * @file sfcc_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SFCC_REVA Peripheral Module. + */ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__SFCCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sfcc_reva + * @defgroup sfcc_reva_registers SFCC_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the SFCC_REVA Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup sfcc_reva_registers + * Structure type to access the SFCC_REVA Registers. + */ +typedef struct { + __I uint32_t info; /**< \b 0x0000: SFCC_REVA INFO Register */ + __I uint32_t sz; /**< \b 0x0004: SFCC_REVA SZ Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t ctrl; /**< \b 0x0100: SFCC_REVA CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: SFCC_REVA INVALIDATE Register */ +} mxc_sfcc_reva_regs_t; + +/* Register offsets for module SFCC_REVA */ +/** + * @ingroup sfcc_reva_registers + * @defgroup SFCC_REVA_Register_Offsets Register Offsets + * @brief SFCC_REVA Peripheral Register Offsets from the SFCC_REVA Base Peripheral Address. + * @{ + */ +#define MXC_R_SFCC_REVA_INFO ((uint32_t)0x00000000UL) /**< Offset from SFCC_REVA Base Address: 0x0000 */ +#define MXC_R_SFCC_REVA_SZ ((uint32_t)0x00000004UL) /**< Offset from SFCC_REVA Base Address: 0x0004 */ +#define MXC_R_SFCC_REVA_CTRL ((uint32_t)0x00000100UL) /**< Offset from SFCC_REVA Base Address: 0x0100 */ +#define MXC_R_SFCC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SFCC_REVA Base Address: 0x0700 */ +/**@} end of group sfcc_reva_registers */ + +/** + * @ingroup sfcc_reva_registers + * @defgroup SFCC_REVA_INFO SFCC_REVA_INFO + * @brief Cache ID Register. + * @{ + */ +#define MXC_F_SFCC_REVA_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_SFCC_REVA_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_SFCC_REVA_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ + +#define MXC_F_SFCC_REVA_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_SFCC_REVA_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_SFCC_REVA_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ + +#define MXC_F_SFCC_REVA_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_SFCC_REVA_INFO_ID ((uint32_t)(0x3FUL << MXC_F_SFCC_REVA_INFO_ID_POS)) /**< INFO_ID Mask */ + +/**@} end of group SFCC_REVA_INFO_Register */ + +/** + * @ingroup sfcc_reva_registers + * @defgroup SFCC_REVA_SZ SFCC_REVA_SZ + * @brief Memory Configuration Register. + * @{ + */ +#define MXC_F_SFCC_REVA_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_SFCC_REVA_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_SFCC_REVA_SZ_CCH_POS)) /**< SZ_CCH Mask */ + +#define MXC_F_SFCC_REVA_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_SFCC_REVA_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_SFCC_REVA_SZ_MEM_POS)) /**< SZ_MEM Mask */ + +/**@} end of group SFCC_REVA_SZ_Register */ + +/** + * @ingroup sfcc_reva_registers + * @defgroup SFCC_REVA_CTRL SFCC_REVA_CTRL + * @brief Cache Control and Status Register. + * @{ + */ +#define MXC_F_SFCC_REVA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_SFCC_REVA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_SFCC_REVA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_SFCC_REVA_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_SFCC_REVA_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_SFCC_REVA_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +/**@} end of group SFCC_REVA_CTRL_Register */ + +/** + * @ingroup sfcc_reva_registers + * @defgroup SFCC_REVA_INVALIDATE SFCC_REVA_INVALIDATE + * @brief Invalidate All Registers. + * @{ + */ +#define MXC_F_SFCC_REVA_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_SFCC_REVA_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_SFCC_REVA_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ + +/**@} end of group SFCC_REVA_INVALIDATE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SFCC_SFCC_REVA_REGS_H_ + diff --git a/Libraries/PeriphDrivers/Source/SKBD/skbd_me55.c b/Libraries/PeriphDrivers/Source/SKBD/skbd_me55.c index 41f3a53e989..3a931c21425 100644 --- a/Libraries/PeriphDrivers/Source/SKBD/skbd_me55.c +++ b/Libraries/PeriphDrivers/Source/SKBD/skbd_me55.c @@ -39,9 +39,8 @@ int MXC_SKBD_Init(mxc_skbd_config_t config) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CTB); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SKBD); - // MXC_GPIO_Config(&gpio_cfg_kbd_P0); - // MXC_GPIO_Config(&gpio_cfg_kbd_P1); - MXC_GPIO_Config(&gpio_cfg_kbd_P2); + /* Set the SKBD GPIO configs */ + MXC_GPIO_Config(&gpio_cfg_skbd_P2); return MXC_SKBD_RevA_Init((mxc_skbd_reva_regs_t *)MXC_SKBD, config); } diff --git a/Libraries/PeriphDrivers/Source/SKBD/skbd_reva.c b/Libraries/PeriphDrivers/Source/SKBD/skbd_reva.c index 81db5277bbc..a50cb28cad6 100644 --- a/Libraries/PeriphDrivers/Source/SKBD/skbd_reva.c +++ b/Libraries/PeriphDrivers/Source/SKBD/skbd_reva.c @@ -89,11 +89,12 @@ int MXC_SKBD_RevA_Init(mxc_skbd_reva_regs_t *skbd, mxc_skbd_config_t config) } /* Configure the SKBD */ - temp = - ((config.reg_erase << MXC_F_SKBD_REVA_CTRL1_CLEAR_POS) | MXC_F_SKBD_REVA_CTRL1_AUTOEN); - temp |= (config.debounce << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) & MXC_F_SKBD_REVA_CTRL1_DBTM; - temp |= (outputs << MXC_F_SKBD_REVA_CTRL1_OUTNB_POS) & MXC_F_SKBD_REVA_CTRL1_OUTNB; - skbd->ctrl1 |= temp; + skbd->ctrl1 = (config.reg_erase << MXC_F_SKBD_REVA_CTRL1_CLEAR_POS) | + MXC_F_SKBD_REVA_CTRL1_AUTOEN // ->ctrl1[0] + | MXC_F_SKBD_REVA_CTRL1_CLEAR // ->ctrl1[1] + | MXC_F_SKBD_REVA_CTRL1_OUTNB //ctrl1[11:8] + | ((config.debounce << MXC_F_SKBD_REVA_CTRL1_DBTM_POS) & + MXC_F_SKBD_REVA_CTRL1_DBTM); //ctrl1[15:13] while (!(skbd->sr & MXC_F_SKBD_REVA_SR_BUSY)) {} diff --git a/Libraries/PeriphDrivers/Source/SPIXF/spixf_me55.c b/Libraries/PeriphDrivers/Source/SPIXF/spixf_me55.c index b92113c1ce8..931b3a5ad11 100644 --- a/Libraries/PeriphDrivers/Source/SPIXF/spixf_me55.c +++ b/Libraries/PeriphDrivers/Source/SPIXF/spixf_me55.c @@ -29,14 +29,73 @@ #include "spixf.h" #include "spixf_reva.h" +#if defined(SPIXF_RAM) + +#include "gpio.h" +#include "gpio_regs.h" +#include "gpio_reva_regs.h" +#include "mxc_pins.h" + +/* NOTE: SPIXF functions should not access the flash area when + * executing from RAM. + */ +// Non-const version of 'gpio_cfg_spixf' pin set. +mxc_gpio_cfg_t gpio_cfg_spixf_ram = { MXC_GPIO1, + (MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23 | MXC_GPIO_PIN_24 | + MXC_GPIO_PIN_25 | MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), + MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, + MXC_GPIO_VSSEL_VDDIO, + MXC_GPIO_DRVSTR_0 }; + +#if IAR_PRAGMAS +#pragma section = ".spix_config" +#else +__attribute__((section(".spix_config"))) +#endif +static int MXC_GPIO_Config_SPIXF(mxc_gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = cfg->port; + mxc_gpio_reva_regs_t *port = (mxc_gpio_reva_regs_t *)gpio; + + port->inen |= cfg->mask; + //Switch to I/O mode first + port->en0_set = cfg->mask; + port->en3_clr = cfg->mask; + port->en2_clr = cfg->mask; + port->en1_clr = cfg->mask; + port->en0_clr = cfg->mask; + + // Configure the pad + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + port->vssel &= ~(cfg->mask); + port->ds0 &= ~(cfg->mask); + port->ds1 &= ~(cfg->mask); + + return E_NO_ERROR; +} +#endif + /****** Functions ******/ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Init(uint32_t cmdval, uint32_t frequency) { #ifndef MSDK_NO_GPIO_CLK_INIT - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPIXIP); // SPIX - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPIXFC); // SPIXFC + // Enable clock of SPIXFM + MXC_GCR->pclkdis0 &= ~(0x1 << MXC_SYS_PERIPH_CLOCK_SPIXIP); + // Enable clock of SPIXFC + MXC_GCR->pclkdis0 &= ~(0x1 << MXC_SYS_PERIPH_CLOCK_SPIXFC); +#if defined(SPIXF_RAM) + MXC_GPIO_Config_SPIXF(&gpio_cfg_spixf_ram); +#else MXC_GPIO_Config(&gpio_cfg_spixf); +#endif #endif return MXC_SPIXF_RevA_Init((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -56,6 +115,11 @@ void MXC_SPIXF_IOCtrl(mxc_spixf_ds_t sclk_ds, mxc_spixf_ds_t ss_ds, mxc_spixf_ds MXC_SPIXF_RevA_IOCtrl((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, sclk_ds, ss_ds, sdio_ds, pupdctrl); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Clocks(uint32_t len, uint8_t deass) { return MXC_SPIXF_RevA_Clocks((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -63,6 +127,11 @@ int MXC_SPIXF_Clocks(uint32_t len, uint8_t deass) (mxc_spixfc_fifo_reva_regs_t *)MXC_SPIXFC_FIFO, len, deass); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Transaction(mxc_spixf_req_t *req) { return MXC_SPIXF_RevA_Transaction((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -113,6 +182,11 @@ int MXC_SPIXF_GetFlags(void) //Low level +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetMode(mxc_spixf_mode_t mode) { return MXC_SPIXF_RevA_SetMode((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -130,6 +204,11 @@ int MXC_SPIXF_SetSSPolActiveHigh(void) (mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetSSPolActiveLow(void) { return MXC_SPIXF_RevA_SetSSPolActiveLow((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -141,6 +220,11 @@ int MXC_SPIXF_GetSSPolarity(void) return MXC_SPIXF_RevA_GetSSPolarity((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetSPIFrequency(unsigned int hz) { return MXC_SPIXF_RevA_SetSPIFrequency((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -172,6 +256,11 @@ uint32_t MXC_SPIXF_GetSPIFrequencyWrite(void) return MXC_SPIXF_RevA_GetSPIFrequencyWrite((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetSSActiveTime(mxc_spixf_ssact_t ssact) { return MXC_SPIXF_RevA_SetSSActiveTime((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -183,6 +272,11 @@ mxc_spixf_ssact_t MXC_SPIXF_GetSSActiveTime(void) return MXC_SPIXF_RevA_GetSSActiveTime((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetSSInactiveTime(mxc_spixf_ssiact_t ssiact) { return MXC_SPIXF_RevA_SetSSInactiveTime((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -194,6 +288,11 @@ mxc_spixf_ssiact_t MXC_SPIXF_GetSSInactiveTime(void) return MXC_SPIXF_RevA_GetSSInactiveTime((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetCmdWidth(mxc_spixf_spiwidth_t width) { return MXC_SPIXF_RevA_SetCmdWidth((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, width); @@ -204,6 +303,11 @@ mxc_spixf_spiwidth_t MXC_SPIXF_GetCmdWidth(void) return MXC_SPIXF_RevA_GetCmdWidth((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetAddrWidth(mxc_spixf_spiwidth_t width) { return MXC_SPIXF_RevA_SetAddrWidth((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, width); @@ -214,6 +318,11 @@ mxc_spixf_spiwidth_t MXC_SPIXF_GetAddrWidth(void) return MXC_SPIXF_RevA_GetAddrWidth((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetDataWidth(mxc_spixf_spiwidth_t width) { return MXC_SPIXF_RevA_SetDataWidth((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, width); @@ -229,6 +338,11 @@ int MXC_SPIXF_Set4ByteAddr(void) return MXC_SPIXF_RevA_Set4ByteAddr((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Set3ByteAddr(void) { return MXC_SPIXF_RevA_Set3ByteAddr((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); @@ -239,6 +353,11 @@ unsigned int MXC_SPIXF_GetBytesPerAddr(void) return MXC_SPIXF_RevA_GetBytesPerAddr((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetModeClk(uint8_t mdclk) { return MXC_SPIXF_RevA_SetModeClk((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, mdclk); @@ -249,6 +368,11 @@ uint8_t MXC_SPIXF_GetModeClk(void) return MXC_SPIXF_RevA_GetModeClk((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetCmdValue(uint8_t cmdval) { return MXC_SPIXF_RevA_SetCmdValue((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, cmdval); @@ -294,6 +418,11 @@ uint8_t MXC_SPIXF_GetBBDataInputValue(void) return MXC_SPIXF_RevA_GetBBDataInputValue((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetModeData(uint16_t data) { return MXC_SPIXF_RevA_SetModeData((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -311,6 +440,11 @@ int MXC_SPIXF_SetSCKInverted(void) (mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetSCKNonInverted(void) { return MXC_SPIXF_RevA_SetSCKNonInverted((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -322,6 +456,11 @@ int MXC_SPIXF_GetSCKInverted(void) return MXC_SPIXF_RevA_GetSCKInverted((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SCKFeedbackEnable(void) { return MXC_SPIXF_RevA_SCKFeedbackEnable((mxc_spixfc_reva_regs_t *)MXC_SPIXFC, @@ -484,16 +623,31 @@ int MXC_SPIXF_TXFIFOIsEnabled(void) return MXC_SPIXF_RevA_IsEnabled((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Enable(void) { return MXC_SPIXF_RevA_Enable((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_Disable(void) { return MXC_SPIXF_RevA_Disable((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_IsEnabled(void) { return MXC_SPIXF_RevA_IsEnabled((mxc_spixfc_reva_regs_t *)MXC_SPIXFC); @@ -554,6 +708,11 @@ uint8_t MXC_SPIXF_GetPuPdCtrl(void) return MXC_SPIXF_RevA_GetPuPdCtrl((mxc_spixfm_reva_regs_t *)MXC_SPIXFM); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_SetBusIdle(unsigned int busidle) { return MXC_SPIXF_RevA_SetBusIdle((mxc_spixfm_reva_regs_t *)MXC_SPIXFM, busidle); diff --git a/Libraries/PeriphDrivers/Source/SPIXF/spixf_reva.c b/Libraries/PeriphDrivers/Source/SPIXF/spixf_reva.c index 64e09164088..4802df3b54f 100644 --- a/Libraries/PeriphDrivers/Source/SPIXF/spixf_reva.c +++ b/Libraries/PeriphDrivers/Source/SPIXF/spixf_reva.c @@ -53,6 +53,11 @@ static int SPIXFC_ReadRXFIFO(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfc_fifo_rev static void SPIXFC_TransHandler(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfc_fifo_reva_regs_t *spixfc_fifo, mxc_spixf_req_t *req); +#if defined(SPIXF_RAM) +static int MXC_GetLock_SPIXF(uint32_t *lock, uint32_t value); +static void MXC_FreeLock_SPIXF(uint32_t *lock); +#endif + /******* Globals *******/ typedef struct { mxc_spixf_req_t *req; @@ -61,6 +66,12 @@ typedef struct { static spixf_req_head_t states; /****** Functions ******/ + +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Init(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, uint32_t cmdval, uint32_t frequency) { @@ -71,8 +82,13 @@ int MXC_SPIXF_RevA_Init(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t * MXC_SPIXF_RevA_TXFIFOEnable(spixfc); MXC_SPIXF_RevA_SCKFeedbackEnable(spixfc, spixfm); MXC_SPIXF_RevA_SetSPIFrequency(spixfc, spixfm, frequency); +#if defined(SPIXF_RAM) + MXC_SPIXF_RevA_SetSSActiveTime(spixfc, spixfm, MXC_SPIXF_SYS_CLOCKS_2); + MXC_SPIXF_RevA_SetSSInactiveTime(spixfc, spixfm, MXC_SPIXF_SYS_CLOCKS_9); +#else MXC_SPIXF_RevA_SetSSActiveTime(spixfc, spixfm, MXC_SPIXF_SYS_CLOCKS_0); MXC_SPIXF_RevA_SetSSInactiveTime(spixfc, spixfm, MXC_SPIXF_SYS_CLOCKS_1); +#endif MXC_SPIXF_RevA_SetCmdValue(spixfm, cmdval); MXC_SPIXF_RevA_SetCmdWidth(spixfm, MXC_SPIXF_SINGLE_SDIO); MXC_SPIXF_RevA_SetAddrWidth(spixfm, MXC_SPIXF_SINGLE_SDIO); @@ -133,6 +149,11 @@ void MXC_SPIXF_RevA_IOCtrl(mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_ds_t sclk_d MXC_SPIXF_RevA_SetPuPdCtrl(spixfm, padctrl); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Clocks(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, mxc_spixfc_fifo_reva_regs_t *spixfc_fifo, uint32_t len, uint8_t deass) { @@ -147,10 +168,17 @@ int MXC_SPIXF_RevA_Clocks(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t return E_NO_ERROR; } +#if defined(SPIXF_RAM) + // Lock this SPIXFC + if (MXC_GetLock_SPIXF((uint32_t *)&states.req, 1) != E_NO_ERROR) { + return E_BUSY; + } +#else // Lock this SPIXFC if (MXC_GetLock((uint32_t *)&states.req, 1) != E_NO_ERROR) { return E_BUSY; } +#endif // Wait for any previous data to transmit while (spixfc->fifo_ctrl & MXC_F_SPIXFC_REVA_FIFO_CTRL_TX_FIFO_CNT) {} @@ -191,12 +219,22 @@ int MXC_SPIXF_RevA_Clocks(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t // Enable the feedback clock MXC_SPIXF_RevA_SCKFeedbackEnable(spixfc, spixfm); +#if defined(SPIXF_RAM) + // Unlock this SPIXFC + MXC_FreeLock_SPIXF((uint32_t *)&states.req); +#else // Unlock this SPIXFC MXC_FreeLock((uint32_t *)&states.req); +#endif return num; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Transaction(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfc_fifo_reva_regs_t *spixfc_fifo, mxc_spixf_req_t *req) { @@ -217,10 +255,17 @@ int MXC_SPIXF_RevA_Transaction(mxc_spixfc_reva_regs_t *spixfc, return E_NO_ERROR; } +#if defined(SPIXF_RAM) + // Lock this SPIXFC + if (MXC_GetLock_SPIXF((uint32_t *)&states.req, 1) != E_NO_ERROR) { + return E_BUSY; + } +#else // Lock this SPIXFC if (MXC_GetLock((uint32_t *)&states.req, 1) != E_NO_ERROR) { return E_BUSY; } +#endif // Clear the number of bytes counter req->read_num = 0; @@ -335,8 +380,13 @@ int MXC_SPIXF_RevA_Transaction(mxc_spixfc_reva_regs_t *spixfc, } } // end of while(remain) +#if defined(SPIXF_RAM) + // Unlock this SPIXFC + MXC_FreeLock_SPIXF((uint32_t *)&states.req); +#else // Unlock this SPIXFC MXC_FreeLock((uint32_t *)&states.req); +#endif if (write) { return req->write_num; @@ -422,6 +472,11 @@ void MXC_SPIXF_RevA_Handler(mxc_spixfc_reva_regs_t *spixfc, } } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif __attribute__((noinline)) static int SPIXFC_ReadRXFIFO(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfc_fifo_reva_regs_t *fifo, uint8_t *data, int len) @@ -697,6 +752,11 @@ int MXC_SPIXF_RevA_GetFlags(mxc_spixfc_reva_regs_t *spixfc) //Low level /* ************************************************ */ +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetMode(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_mode_t mode) { @@ -718,6 +778,11 @@ int MXC_SPIXF_RevA_SetSSPolActiveHigh(mxc_spixfc_reva_regs_t *spixfc, return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetSSPolActiveLow(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm) { spixfm->cfg |= MXC_F_SPIXFM_REVA_CFG_SSPOL; @@ -730,6 +795,11 @@ int MXC_SPIXF_RevA_GetSSPolarity(mxc_spixfc_reva_regs_t *spixfc) return !!(spixfc->ss_pol & MXC_F_SPIXFC_REVA_SS_POL_SS_POLARITY); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetSPIFrequency(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, unsigned int hz) { @@ -792,6 +862,11 @@ int MXC_SPIXF_RevA_SetSPIFrequency(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_re } } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif uint32_t MXC_SPIXF_RevA_GetSPIFrequency(mxc_spixfm_reva_regs_t *spixfm) { uint32_t clocks; @@ -805,6 +880,11 @@ uint32_t MXC_SPIXF_RevA_GetSPIFrequency(mxc_spixfm_reva_regs_t *spixfm) return SystemCoreClock / (2 * clocks); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif uint32_t MXC_SPIXF_RevA_GetSPIFrequencyWrite(mxc_spixfc_reva_regs_t *spixfc) { uint32_t clocks; @@ -818,6 +898,11 @@ uint32_t MXC_SPIXF_RevA_GetSPIFrequencyWrite(mxc_spixfc_reva_regs_t *spixfc) return PeripheralClock / (2 * clocks); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetSSActiveTime(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_ssact_t ssact) { @@ -833,6 +918,11 @@ mxc_spixf_ssact_t MXC_SPIXF_RevA_GetSSActiveTime(mxc_spixfc_reva_regs_t *spixfc) return ((spixfc->cfg & MXC_F_SPIXFC_REVA_CFG_SSACT) >> MXC_F_SPIXFC_REVA_CFG_SSACT_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetSSInactiveTime(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_ssiact_t ssiact) { @@ -848,6 +938,11 @@ mxc_spixf_ssiact_t MXC_SPIXF_RevA_GetSSInactiveTime(mxc_spixfc_reva_regs_t *spix return ((spixfc->cfg & MXC_F_SPIXFC_REVA_CFG_SSIACT) >> MXC_F_SPIXFC_REVA_CFG_SSIACT_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetCmdWidth(mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_spiwidth_t width) { MXC_ASSERT(width < MXC_SPIXF_INVALID); @@ -863,6 +958,11 @@ mxc_spixf_spiwidth_t MXC_SPIXF_RevA_GetCmdWidth(mxc_spixfm_reva_regs_t *spixfm) MXC_F_SPIXFM_REVA_FETCH_CTRL_CMD_WIDTH_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetAddrWidth(mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_spiwidth_t width) { MXC_ASSERT(width < MXC_SPIXF_INVALID); @@ -878,6 +978,11 @@ mxc_spixf_spiwidth_t MXC_SPIXF_RevA_GetAddrWidth(mxc_spixfm_reva_regs_t *spixfm) MXC_F_SPIXFM_REVA_FETCH_CTRL_ADDR_WIDTH_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetDataWidth(mxc_spixfm_reva_regs_t *spixfm, mxc_spixf_spiwidth_t width) { MXC_ASSERT(width < MXC_SPIXF_INVALID); @@ -899,6 +1004,11 @@ int MXC_SPIXF_RevA_Set4ByteAddr(mxc_spixfm_reva_regs_t *spixfm) return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Set3ByteAddr(mxc_spixfm_reva_regs_t *spixfm) { spixfm->fetch_ctrl &= (~MXC_F_SPIXFM_REVA_FETCH_CTRL_FOUR_BYTE_ADDR); @@ -914,6 +1024,11 @@ unsigned int MXC_SPIXF_RevA_GetBytesPerAddr(mxc_spixfm_reva_regs_t *spixfm) } } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetModeClk(mxc_spixfm_reva_regs_t *spixfm, uint8_t mdclk) { MXC_SETFIELD(spixfm->mode_ctrl, MXC_F_SPIXFM_REVA_MODE_CTRL_MDCLK, mdclk); @@ -977,6 +1092,11 @@ uint8_t MXC_SPIXF_RevA_GetBBDataInputValue(mxc_spixfc_reva_regs_t *spixfc) MXC_F_SPIXFC_REVA_GEN_CTRL_SDIO_DATA_IN_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetModeData(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm, uint16_t data) { @@ -998,6 +1118,11 @@ int MXC_SPIXF_RevA_SetSCKInverted(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_rev return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetSCKNonInverted(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm) { spixfm->fb_ctrl &= (~MXC_F_SPIXFM_REVA_FB_CTRL_INVERT_EN); @@ -1010,6 +1135,11 @@ int MXC_SPIXF_RevA_GetSCKInverted(mxc_spixfm_reva_regs_t *spixfm) return !!(spixfm->fb_ctrl & MXC_F_SPIXFM_REVA_FB_CTRL_INVERT_EN); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SCKFeedbackEnable(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm) { spixfm->fb_ctrl |= MXC_F_SPIXFM_REVA_FB_CTRL_FB_EN; @@ -1017,6 +1147,11 @@ int MXC_SPIXF_RevA_SCKFeedbackEnable(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_ return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SCKFeedbackDisable(mxc_spixfc_reva_regs_t *spixfc, mxc_spixfm_reva_regs_t *spixfm) { @@ -1025,6 +1160,11 @@ int MXC_SPIXF_RevA_SCKFeedbackDisable(mxc_spixfc_reva_regs_t *spixfc, return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SCKFeedbackIsEnabled(mxc_spixfm_reva_regs_t *spixfm) { return !!(spixfm->fb_ctrl & MXC_F_SPIXFM_REVA_FB_CTRL_FB_EN); @@ -1042,6 +1182,11 @@ uint8_t MXC_SPIXF_RevA_GetSCKSampleDelay(mxc_spixfc_reva_regs_t *spixfc) return ((spixfc->cfg & MXC_F_SPIXFC_REVA_CFG_IOSMPL) >> MXC_F_SPIXFC_REVA_CFG_IOSMPL_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetCmdValue(mxc_spixfm_reva_regs_t *spixfm, uint8_t cmdval) { MXC_SETFIELD(spixfm->fetch_ctrl, MXC_F_SPIXFM_REVA_FETCH_CTRL_CMDVAL, @@ -1055,6 +1200,11 @@ uint8_t MXC_SPIXF_RevA_GetCmdValue(mxc_spixfm_reva_regs_t *spixfm) MXC_F_SPIXFM_REVA_FETCH_CTRL_CMDVAL_POS); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif void MXC_SPIXF_RevA_SetPageSize(mxc_spixfc_reva_regs_t *spixfc, mxc_spixf_page_size_t size) { MXC_SETFIELD(spixfc->cfg, MXC_F_SPIXFC_REVA_CFG_PAGE_SIZE, @@ -1239,6 +1389,11 @@ int MXC_SPIXF_RevA_BitBangModeIsEnabled(mxc_spixfc_reva_regs_t *spixfc) return !!(spixfc->gen_ctrl & MXC_F_SPIXFC_REVA_GEN_CTRL_BBMODE); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_RXFIFOEnable(mxc_spixfc_reva_regs_t *spixfc) { spixfc->gen_ctrl |= MXC_F_SPIXFC_REVA_GEN_CTRL_RX_FIFO_EN; @@ -1256,6 +1411,11 @@ int MXC_SPIXF_RevA_RXFIFOIsEnabled(mxc_spixfc_reva_regs_t *spixfc) return !!(spixfc->gen_ctrl & MXC_F_SPIXFC_REVA_GEN_CTRL_RX_FIFO_EN); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_TXFIFOEnable(mxc_spixfc_reva_regs_t *spixfc) { spixfc->gen_ctrl |= MXC_F_SPIXFC_REVA_GEN_CTRL_TX_FIFO_EN; @@ -1273,23 +1433,43 @@ int MXC_SPIXF_RevA_TXFIFOIsEnabled(mxc_spixfc_reva_regs_t *spixfc) return !!(spixfc->gen_ctrl & MXC_F_SPIXFC_REVA_GEN_CTRL_TX_FIFO_EN); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Enable(mxc_spixfc_reva_regs_t *spixfc) { spixfc->gen_ctrl |= MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE; return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_Disable(mxc_spixfc_reva_regs_t *spixfc) { spixfc->gen_ctrl &= (~MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE); return E_NO_ERROR; } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_IsEnabled(mxc_spixfc_reva_regs_t *spixfc) { return !!(spixfc->gen_ctrl & MXC_F_SPIXFC_REVA_GEN_CTRL_ENABLE); } +#if defined(SPIXF_RAM) && IAR_PRAGMAS +#pragma section = ".spix_config" +#elif defined(SPIXF_RAM) +__attribute__((section(".spix_config"))) +#endif int MXC_SPIXF_RevA_SetBusIdle(mxc_spixfm_reva_regs_t *spixfm, unsigned int busidle) { spixfm->bus_idle = busidle; @@ -1300,3 +1480,49 @@ unsigned int MXC_SPIXF_RevA_GetBusIdle(mxc_spixfm_reva_regs_t *spixfm) { return spixfm->bus_idle; } + +/* ************************************************************************** */ + +// MXC_GetLock +#if defined(SPIXF_RAM) +#if IAR_PRAGMAS +#pragma section = ".spix_config" +#else +__attribute__((section(".spix_config"))) +#endif +int MXC_GetLock_SPIXF(uint32_t *lock, uint32_t value) +{ +#ifndef __riscv + do { + // Return if the lock is taken by a different thread + if (__LDREXW((volatile uint32_t *)lock) != 0) { + return E_BUSY; + } + + // Attempt to take the lock + } while (__STREXW(value, (volatile uint32_t *)lock) != 0); + + // Do not start any other memory access until memory barrier is complete + __DMB(); +#endif // __riscv + + return E_NO_ERROR; +} +#endif + +// MXC_FreeLock +#if defined(SPIXF_RAM) +#if IAR_PRAGMAS +#pragma section = ".spix_config" +#else +__attribute__((section(".spix_config"))) +#endif +void MXC_FreeLock_SPIXF(uint32_t *lock) +{ +#ifndef __riscv + // Ensure memory operations complete before releasing lock + __DMB(); +#endif // __riscv + *lock = 0; +} +#endif diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me55.c b/Libraries/PeriphDrivers/Source/SYS/pins_me55.c index 83e77d3b46a..73e36994bff 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me55.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me55.c @@ -1,6 +1,6 @@ /** - * @file mxc_pins.c - * @brief This file contains constant pin configurations for the peripherals. + * @file mxc_pins.c + * @brief This file contains constant pin configurations for the peripherals. */ /****************************************************************************** @@ -181,3 +181,9 @@ const mxc_gpio_cfg_t gpio_cfg_sc1 = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN const mxc_gpio_cfg_t gpio_cfg_spixf = { MXC_GPIO1, (MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23 | MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25 | MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// SKBD Pin Definitions +const mxc_gpio_cfg_t gpio_cfg_skbd_P2 = { MXC_GPIO1, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16 | + MXC_GPIO_PIN_17 | MXC_GPIO_PIN_18| MXC_GPIO_PIN_19 | MXC_GPIO_PIN_20 | + MXC_GPIO_PIN_21), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index da23e68d20e..5001e8797ea 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -2,7 +2,7 @@ * * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. * (now owned by Analog Devices, Inc.), - * Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + * Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software * is proprietary to Analog Devices, Inc. and its licensors. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/PeriphDrivers/max32572_files.mk b/Libraries/PeriphDrivers/max32572_files.mk index 201e0e4e332..61d8885d02a 100644 --- a/Libraries/PeriphDrivers/max32572_files.mk +++ b/Libraries/PeriphDrivers/max32572_files.mk @@ -2,7 +2,7 @@ # # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved. # (now owned by Analog Devices, Inc.), - # Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software + # Copyright (C) 2023-2024 Analog Devices, Inc. All Rights Reserved. This software # is proprietary to Analog Devices, Inc. and its licensors. # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -94,9 +94,13 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/RTC PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_me55.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_reva.c -# PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SKBD -# PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SKBD/skbd_me55.c -# PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SKBD/skbd_reva.c +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SFCC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SFCC/sfcc_me55.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SFCC/sfcc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SKBD +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SKBD/skbd_me55.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SKBD/skbd_reva.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SMON PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SMON/smon_me55.c diff --git a/Tools/SBT/SBT-rules.mk b/Tools/SBT/SBT-rules.mk index 17e9dcf452f..7b1d285bb80 100644 --- a/Tools/SBT/SBT-rules.mk +++ b/Tools/SBT/SBT-rules.mk @@ -14,7 +14,9 @@ sla: all @echo " " arm-none-eabi-objcopy $(BUILD_DIR)/$(PROJECT).elf --update-section .sig=$(BUILD_DIR)/$(PROJECT).sig @echo " " - $(BUILD_SESSION) -c $(TARGET_SEC) key_file=$(TEST_KEY) ${SCP_PACKETS} $(BUILD_DIR)/$(PROJECT).sbin + @if [ "$(TARGET_SEC)" != "MAX32572" ]; then \ + $(BUILD_SESSION) -c $(TARGET_SEC) key_file=$(TEST_KEY) ${SCP_PACKETS} $(BUILD_DIR)/$(PROJECT).sbin ;\ + fi # The SCPA target. # "make scpa" is a special rule for SCPA applet programs, which are diff --git a/Tools/SBT/devices/MAX32572/keys/maximtestcrk.pub b/Tools/SBT/devices/MAX32572/keys/maximtestcrk.pub index b8b000e1af4..d581296f41e 100644 --- a/Tools/SBT/devices/MAX32572/keys/maximtestcrk.pub +++ b/Tools/SBT/devices/MAX32572/keys/maximtestcrk.pub @@ -1,2 +1,2 @@ a823c8857948dc688f3a3ef3f6f220a514f05c2c6c1cef8c9f2f8df11dcf0142 -3be124619cbbeb51e985328e8e33d321cade19628cc0db43304a7b27f2db8efe +3be124619cbbeb51e985328e8e33d321cade19628cc0db43304a7b27f2db8efe \ No newline at end of file diff --git a/Tools/SBT/devices/MAX32572/scp_packets/writemaximcrk/.gitignore b/Tools/SBT/devices/MAX32572/scp_packets/writemaximcrk/.gitignore deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/Tools/SBT/devices/MAX32572/script/write_sla.txt b/Tools/SBT/devices/MAX32572/script/write_sla.txt index eac4477b0d2..b2f78deece1 100644 --- a/Tools/SBT/devices/MAX32572/script/write_sla.txt +++ b/Tools/SBT/devices/MAX32572/script/write_sla.txt @@ -1 +1 @@ -write-file %PARAM_1% %PARAM_2% +write-file %PARAM_1% 08000000 \ No newline at end of file