riscv: Add support for riscv32

Because upstream strace dose not support riscv32 since v5.3 [1],
this patch is added to support riscv32.

[1] strace/strace@69ff62e

* Makefile.am (EXTRA_DIST): Rename linux/riscv64 to linux/riscv.
* configure.ac: Add riscv32.
* linux/riscv64: Rename to linux/riscv.
* riscv.c: Add RISCV32.

Signed-off-by: Hui Min Mina Chou <[email protected]>

Author: Mina-Chou

configure.ac

@@ -169,9 +169,12 @@ powerpc*)
 		esac
 	fi
 	;;
+riscv32*)
+	arch=riscv
+	AC_DEFINE([RISCV32], 1, [Define for the RISC-V 32-bit architecture])
+	;;
 riscv64*)
-	arch=riscv64
-	karch=riscv
+	arch=riscv
 	AC_DEFINE([RISCV64], 1, [Define for the RISC-V 64-bit architecture])
 	;;
 s390)

src/Makefile.am

@@ -821,19 +821,19 @@ EXTRA_DIST =				\
 	linux/powerpc64le/set_scno.c	\
 	linux/powerpc64le/syscallent.h	\
 	linux/powerpc64le/userent.h	\
-	linux/riscv64/arch_defs_.h		\
-	linux/riscv64/arch_prstatus_regset.c \
-	linux/riscv64/arch_prstatus_regset.h \
-	linux/riscv64/arch_regs.c		\
-	linux/riscv64/get_error.c		\
-	linux/riscv64/get_scno.c		\
-	linux/riscv64/get_syscall_args.c	\
-	linux/riscv64/ioctls_arch0.h	\
-	linux/riscv64/ioctls_inc0.h	\
-	linux/riscv64/raw_syscall.h	\
-	linux/riscv64/set_error.c		\
-	linux/riscv64/set_scno.c		\
-	linux/riscv64/syscallent.h	\
+	linux/riscv/arch_defs_.h		\
+	linux/riscv/arch_prstatus_regset.c \
+	linux/riscv/arch_prstatus_regset.h \
+	linux/riscv/arch_regs.c		\
+	linux/riscv/get_error.c		\
+	linux/riscv/get_scno.c		\
+	linux/riscv/get_syscall_args.c	\
+	linux/riscv/ioctls_arch0.h	\
+	linux/riscv/ioctls_inc0.h	\
+	linux/riscv/raw_syscall.h	\
+	linux/riscv/set_error.c		\
+	linux/riscv/set_scno.c		\
+	linux/riscv/syscallent.h	\
 	linux/s390/arch_defs_.h		\
 	linux/s390/arch_prstatus_regset.c \
 	linux/s390/arch_prstatus_regset.h \

src/linux/riscv/arch_defs_.h

@@ -0,0 +1,8 @@
+#if defined(RISCV32)
+# define ARCH_TIMESIZE 64
+# define HAVE_ARCH_TIME32_SYSCALLS 0
+# define HAVE_ARCH_OLD_TIME64_SYSCALLS 0
+# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV32, 0 }
+#else
+# define PERSONALITY0_AUDIT_ARCH { AUDIT_ARCH_RISCV64, 0 }
+#endif

src/linux/riscv64/arch_prstatus_regset.c src/linux/riscv/arch_prstatus_regset.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020 The strace developers.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef STRACE_RISCV_ASM_STAT_H
+# define STRACE_RISCV_ASM_STAT_H
+
+# include "linux/generic/asm_stat.h"
+
+# if defined(RISCV32)
+#  undef dev_t
+#  undef ino_t
+#  undef off64_t
+#  undef off_t
+#  undef time_t
+
+#  define dev_t		__kernel_loff_t
+#  define ino_t		__kernel_loff_t
+#  define off64_t	__kernel_off64_t
+#  define off_t		__kernel_off64_t
+#  define time_t	__kernel_time64_t
+# endif /* defined(RISCV32) */
+#endif /* !STRACE_RISCV_ASM_STAT_H */

src/linux/riscv64/arch_prstatus_regset.h src/linux/riscv/arch_prstatus_regset.h

@@ -0,0 +1,7 @@
+#if defined(RISCV64)
+# include "../64/ioctls_inc.h"
+#elif defined(RISCV32)
+# include "../32/ioctls_inc.h"
+#else
+# error "Unsupported RISC-V xlen"
+#endif

src/linux/riscv64/arch_regs.c src/linux/riscv/arch_regs.c

@@ -5,7 +5,13 @@
  * SPDX-License-Identifier: LGPL-2.1-or-later
  */
 
-#include "../64/syscallent.h"
+#if defined(RISCV64)
+# include "../64/syscallent.h"
+#elif defined(RISCV32)
+# include "../32/syscallent.h"
+#else
+# error "Unsupported RISC-V xlen"
+#endif
 
 /* #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) */
 [259] = { 3,	TM,		SEN(riscv_flush_icache),	"riscv_flush_icache"	},

src/linux/riscv/asm_stat.h

@@ -9,7 +9,7 @@
 
 #include "defs.h"
 
-#ifdef RISCV64
+#if defined(RISCV64) || defined(RISCV32)
 
 # include "xlat/riscv_flush_icache_flags.h"
 
@@ -30,4 +30,4 @@ SYS_FUNC(riscv_flush_icache)
 	return RVAL_DECODED;
 }
 
-#endif /* RISCV64 */
+#endif /* defined(RISCV64) || defined(RISCV32) */