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‎_unittest/conftest.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@
3838
settings.enable_error_handler = False
3939
settings.enable_desktop_logs = False
4040
settings.desktop_launch_timeout = 180
41-
41+
settings.release_on_exception = False
4242

4343
from pyaedt import Edb
4444
from pyaedt import Hfss

‎_unittest/example_models/T21/SSN_custom.s6p

Lines changed: 5084 additions & 0 deletions
Large diffs are not rendered by default.

‎_unittest/example_models/T21/pcieg5_32gt.ami

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
|******************************************************************************
2+
| Spec. AMI model generated by SPISim's BPro, Generated on 20170831143940
3+
|
4+
| IP of this model belongs to SPISim or its licensed BPro user.
5+
|*****************************************************************************
6+
(ANSYS_PCIeG5_32GT_RX
7+
(Description "Example PCIeG5 Rx 32GT model")
8+
(Reserved_Parameters
9+
(AMI_Version (Usage Info) (Type String) (Value "6.1") (Description "Supported AMI version"))
10+
(Ignore_Bits (Usage Info) (Type Integer) (Default 500) (Description "Ignore four bits to fill up tapped delay line."))
11+
(Max_Init_Aggressors (Usage Info) (Type Integer) (Default 25) (Description "Number of aggressors is actually unlimited."))
12+
(Init_Returns_Impulse (Usage Info) (Type Boolean) (Default True) (Description "Both impulse and parameters_out returned."))
13+
(Supporting_Files (Usage Info) (Type String) (Table ("PCIeG5_32GT.ens")) (Description "CTLE Performance table"))
14+
(GetWave_Exists (Usage Info) (Type Boolean) (Default True) (Description "GetWave is well and truly provided in the module."))
15+
) | End Reserved_Parameters
16+
17+
|****************************************************************************
18+
| Remove or tamper LICENSE_INFO values will cause simulation being aborted!
19+
|****************************************************************************
20+
(Model_Specific
21+
(LICENSE_INFO (Usage In) (Type String) (Default "LICENSED_ANSYS_AEDT_E168EFCC0268A84087F7B23B510CB41F") (Description "Licensing info."))
22+
| ------------------ MAIN Settings ------------------
23+
(MDL_SUB_MODS (Usage In) (Type String) (Default "CTLE,DFE") (Description "Cascaded stages"))
24+
| ------------------ CTLE Settings ------------------
25+
(MDL_IDX_FILE (Usage In) (Type String) (Default "PCIeG5_32GT.ens") (Description "Params index table"))
26+
(MDL_IDX_VALU (Usage In) (Type String) (Default "-1") (Description "Params table rowID"))
27+
(ADC (Usage In) (Type Integer) (Range -5 -15 -5) (Default -5) (Description "DC Gain in dB"))
28+
|(CTLE_OUPT_FILE (Usage In) (Type String) (Default "C:/Temp/WorkSpace/SPISim/CST/PCIe/32GT/PCIeG5_32GT.csv") (Description "Output generated FD array for checking purpose"))
29+
) | End Model_Specific
30+
) | End SPISim_SPEC_AMI

‎_unittest/example_models/T21/pcieg5_32gt.ibs

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
|***************************************************************************
2+
|
3+
[IBIS Ver] 5.1
4+
[File name] pcieg5_32gt.ibs
5+
[File rev] 1.00
6+
[Date] Jan 1, 2017
7+
[Source] BPro (http://www.spisim.com)
8+
[Copyright] Copyright 2017 ~, SPISim LLC. All right reserved.
9+
|
10+
|***************************************************************************
11+
|
12+
[Component] Spec_Model
13+
[Manufacturer] SPISim LLC
14+
[Package]
15+
| typ min max
16+
R_pkg 0.0 0.0 0.0
17+
L_pkg 0.0 0.0 0.0
18+
C_pkg 0.0 0.0 0.0
19+
|
20+
|***************************************************************************
21+
|
22+
[PIN] signal_name model_name R_pin L_pin C_pin
23+
1p TxP Tx NA NA NA
24+
1n TxN Tx NA NA NA
25+
2p RxP Rx NA NA NA
26+
2n RxN Rx NA NA NA
27+
|
28+
|***************************************************************************
29+
|
30+
[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
31+
1p 1n 0.1V NA NA NA
32+
2p 2n 0.1V NA NA NA
33+
|
34+
|****************************************************************
35+
|
36+
[Model] Rx
37+
Model_type Input
38+
|
39+
C_comp 0.00p 0.00p 0.00p
40+
Vinh = 0.55
41+
Vinl = 0.45
42+
|
43+
[Temperature_Range] 25 100 0
44+
[Voltage Range] 1.2 1.14 1.26
45+
|
46+
| The IV table below is equivalent to 50 ohms single-ended load
47+
[GND Clamp]
48+
-6.6 -0.132 -0.132 -0.132
49+
0.0 0.0 0.0 0.0
50+
6.6 0.132 0.132 0.132
51+
52+
[Power Clamp]
53+
-6.6 0.132e-9 0.132e-9 0.132e-9
54+
0.0 0.0 0.0 0.0
55+
6.6 -0.132e-9 -0.132e-9 -0.132e-9
56+
57+
[Algorithmic Model]
58+
Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
59+
Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
60+
Executable Linux_gcc_64 pcieg5_32gt_LX64.so pcieg5_32gt.ami
61+
[End Algorithmic Model]
62+
63+
|
64+
|***************************************************************************
65+
|
66+
[Model] Tx
67+
Model_type Output
68+
Polarity Non-Inverting
69+
Enable Active-High
70+
|
71+
Vmeas = 0.55
72+
| typ min max
73+
C_comp 0 0 0
74+
[Voltage Range] 1.1 1.0 1.2
75+
[Temperature Range] 60 100 0
76+
|
77+
|***************************************************************************
78+
|
79+
[Pulldown]
80+
-2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
81+
0.000 +0.00000E+00 +0.00000E+00 +0.00000E+00
82+
2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
83+
[Pullup]
84+
-2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
85+
0.000 +0.00000E+00 +0.00000E+00 +0.00000E+00
86+
2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
87+
|
88+
[Ramp]
89+
dV/dt_r 0.2796/15p 0.2610/23.5p 0.2976/13p
90+
dV/dt_f 0.2796/15p 0.2610/23.5p 0.2976/13p
91+
|
92+
|
93+
[Algorithmic Model]
94+
Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
95+
Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
96+
Executable Linux_gcc_64 pcieg5_32gt_LX64.so pcieg5_32gt.ami
97+
[End Algorithmic Model]
98+
99+
|***************************************************************************
100+
[End]

‎_unittest/test_01_3dlayout_edb.py

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -307,7 +307,7 @@ def test_15_3dplacement(self):
307307

308308
def test_16_differential_ports(self):
309309
self.aedtapp.set_active_design(self.design_name)
310-
pins = self.aedtapp.modeler.components["R3"].pins
310+
pins = list(self.aedtapp.modeler.components["R3"].pins.keys())
311311
assert self.aedtapp.create_differential_port(pins[0], pins[1], "test_differential", deembed=True)
312312
assert "test_differential" in self.aedtapp.port_list
313313

@@ -376,3 +376,15 @@ def test_22_change_design_settings(self):
376376
assert (
377377
self.aedtapp.get_oo_property_value(self.aedtapp.odesign, "Design Settings", "DCExtrapolation") == "Advanced"
378378
)
379+
380+
def test_23_dissolve_element(self):
381+
comp = self.aedtapp.modeler.components["D1"]
382+
pins = {name: pin for name, pin in comp.pins.items() if name in ["D1-1", "D1-2", "D1-7"]}
383+
self.aedtapp.dissolve_component("D1")
384+
comp = self.aedtapp.modeler.create_components_on_pins(list(pins.keys()))
385+
nets = [
386+
list(pins.values())[0].net_name,
387+
list(pins.values())[1].net_name,
388+
]
389+
assert self.aedtapp.create_ports_on_component_by_nets(comp.name, nets)
390+
assert self.aedtapp.create_pec_on_component_by_nets(comp.name, "GND")

‎_unittest/test_03_Materials.py

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -92,14 +92,18 @@ def test_02_create_material(self):
9292
assert mat1.get_curve_coreloss_type() == "Power Ferrite"
9393
assert isinstance(mat1.material_appearance, list)
9494

95-
mat1.material_appearance = [11, 22, 0]
96-
assert mat1.material_appearance == [11, 22, 0]
97-
mat1.material_appearance = ["11", "22", "10"]
98-
assert mat1.material_appearance == [11, 22, 10]
95+
mat1.material_appearance = [11, 22, 0, 0.5]
96+
assert mat1.material_appearance == [11, 22, 0, 0.5]
97+
mat1.material_appearance = ["11", "22", "10", "0.5"]
98+
assert mat1.material_appearance == [11, 22, 10, 0.5]
9999
with pytest.raises(ValueError):
100-
mat1.material_appearance = [11, 22, 300]
100+
mat1.material_appearance = [11, 22, 300, 0.5]
101101
with pytest.raises(ValueError):
102-
mat1.material_appearance = [11, -22, 0]
102+
mat1.material_appearance = [11, 22, 100, 1.5]
103+
with pytest.raises(ValueError):
104+
mat1.material_appearance = [11, -22, 0, 0.5]
105+
with pytest.raises(ValueError):
106+
mat1.material_appearance = [11, 22, 0, -1]
103107
with pytest.raises(ValueError):
104108
mat1.material_appearance = [11, 22]
105109

‎_unittest/test_04_SBR.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,10 @@ def init(self, aedtapp, local_scratch):
5858
def test_01_open_source(self, source):
5959
assert self.aedtapp.create_sbr_linked_antenna(source, target_cs="feederPosition", fieldtype="farfield")
6060
assert len(self.aedtapp.native_components) == 1
61+
assert self.aedtapp.create_sbr_linked_antenna(
62+
source, target_cs="feederPosition", fieldtype="farfield", source_name="LinkedAntenna"
63+
)
64+
assert len(self.aedtapp.native_components) == 2
6165

6266
def test_02_add_antennas(self):
6367
self.aedtapp.insert_design("add_antennas")

‎_unittest/test_12_1_PostProcessing.py

Lines changed: 26 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -98,25 +98,25 @@ def test_01_Animate_plt(self):
9898
phases = [str(i * 5) + "deg" for i in range(2)]
9999
model_gif = self.aedtapp.post.plot_animated_field(
100100
quantity="Mag_E",
101-
object_list=cutlist,
101+
objects=cutlist,
102102
plot_type="CutPlane",
103103
setup_name=self.aedtapp.nominal_adaptive,
104104
intrinsics={"Freq": "5GHz", "Phase": "0deg"},
105-
export_path=self.local_scratch.path,
106105
variation_variable="Phase",
107-
variation_list=phases,
106+
variations=phases,
108107
show=False,
109108
export_gif=True,
109+
export_path=self.local_scratch.path,
110110
)
111111
assert os.path.exists(model_gif.gif_file)
112112
setup_name = self.aedtapp.existing_analysis_sweeps[0]
113113
intrinsic = {"Freq": "5GHz", "Phase": "180deg"}
114114
pl1 = self.aedtapp.post.create_fieldplot_volume("NewObject_IJD39Q", "Mag_E", setup_name, intrinsic)
115115
model_gif2 = self.aedtapp.post.animate_fields_from_aedtplt(
116-
plotname=pl1.name,
116+
plot_name=pl1.name,
117117
plot_folder=None,
118118
variation_variable="Phase",
119-
variation_list=phases,
119+
variations=phases,
120120
project_path="",
121121
export_gif=False,
122122
show=False,
@@ -136,9 +136,7 @@ def test_02_export_fields(self):
136136
plot2 = self.aedtapp.post.create_fieldplot_volume(vollist, quantity_name2, setup_name, intrinsic)
137137

138138
self.aedtapp.post.export_field_jpg(
139-
os.path.join(self.local_scratch.path, "prova2.jpg"),
140-
plot2.name,
141-
plot2.plotFolder,
139+
os.path.join(self.local_scratch.path, "prova2.jpg"), plot2.name, plot2.plot_folder
142140
)
143141
assert os.path.exists(os.path.join(self.local_scratch.path, "prova2.jpg"))
144142
assert os.path.exists(
@@ -225,7 +223,7 @@ def test_07_export_fields_from_Calculator(self):
225223
os.path.join(self.local_scratch.path, "Efield.fld"),
226224
grid_stop=[5, 5, 5],
227225
grid_step=[0.5, 0.5, 0.5],
228-
isvector=True,
226+
is_vector=True,
229227
intrinsics="5GHz",
230228
)
231229
assert os.path.exists(os.path.join(self.local_scratch.path, "Efield.fld"))
@@ -235,10 +233,10 @@ def test_07_export_fields_from_Calculator(self):
235233
"Setup1 : LastAdaptive",
236234
self.aedtapp.available_variations.nominal_w_values_dict,
237235
os.path.join(self.local_scratch.path, "MagEfieldSph.fld"),
238-
gridtype="Spherical",
236+
grid_type="Spherical",
239237
grid_stop=[5, 300, 300],
240238
grid_step=[5, 50, 50],
241-
isvector=False,
239+
is_vector=False,
242240
intrinsics="5GHz",
243241
)
244242
assert os.path.exists(os.path.join(self.local_scratch.path, "MagEfieldSph.fld"))
@@ -248,10 +246,10 @@ def test_07_export_fields_from_Calculator(self):
248246
"Setup1 : LastAdaptive",
249247
self.aedtapp.available_variations.nominal_w_values_dict,
250248
os.path.join(self.local_scratch.path, "MagEfieldCyl.fld"),
251-
gridtype="Cylindrical",
249+
grid_type="Cylindrical",
252250
grid_stop=[5, 300, 5],
253251
grid_step=[5, 50, 5],
254-
isvector=False,
252+
is_vector=False,
255253
intrinsics="5GHz",
256254
)
257255
assert os.path.exists(os.path.join(self.local_scratch.path, "MagEfieldCyl.fld"))
@@ -271,12 +269,12 @@ def test_09_manipulate_report(self):
271269
assert self.aedtapp.post.create_report("dB(S(1,1))")
272270
assert self.aedtapp.post.create_report(
273271
expressions="MaxMagDeltaS",
274-
variations={"Pass": ["All"]},
275272
setup_sweep_name="Setup1 : AdaptivePass",
273+
variations={"Pass": ["All"]},
276274
primary_sweep_variable="Pass",
277275
report_category="Modal Solution Data",
278276
plot_type="Rectangular Plot",
279-
plotname="Solution Convergence Plot",
277+
plot_name="Solution Convergence Plot",
280278
)
281279
new_report = self.aedtapp.post.reports_by_category.modal_solution("dB(S(1,1))")
282280
assert new_report.create()
@@ -501,13 +499,13 @@ def test_14_Field_Ploton_cutplanedesignname(self):
501499
assert plot1.update_field_plot_settings()
502500
self.aedtapp.logger.info("Generating the image")
503501
plot_obj = self.aedtapp.post.plot_field_from_fieldplot(
504-
plotname=plot1.name,
502+
plot_name=plot1.name,
505503
project_path=self.local_scratch.path,
506-
meshplot=False,
507-
imageformat="jpg",
504+
mesh_plot=False,
505+
image_format="jpg",
508506
view="xy",
509-
show=False,
510507
plot_label=plot1.name + " label",
508+
show=False,
511509
)
512510
assert os.path.exists(plot_obj.image_file)
513511
os.unlink(plot_obj.image_file)
@@ -526,13 +524,13 @@ def test_14_Field_Ploton_cutplanedesignname(self):
526524
assert os.path.exists(plot_obj.image_file)
527525

528526
plot_obj = self.aedtapp.post.plot_field_from_fieldplot(
529-
plotname=plot1.name,
527+
plot_name=plot1.name,
530528
project_path=self.local_scratch.path,
531-
meshplot=False,
532-
imageformat="jpg",
529+
mesh_plot=False,
530+
image_format="jpg",
533531
view="xy",
534-
show=False,
535532
plot_label=plot1.name + " label",
533+
show=False,
536534
file_format="aedtplt",
537535
)
538536
assert os.path.exists(plot_obj.image_file)
@@ -557,11 +555,11 @@ def test_14B_Field_Ploton_Vector(self):
557555
"CutPlane",
558556
setup_name=setup_name,
559557
intrinsics=intrinsic,
560-
export_path=self.local_scratch.path,
561558
mesh_on_fields=False,
562-
imageformat="jpg",
563559
view="isometric",
564560
show=False,
561+
export_path=self.local_scratch.path,
562+
image_format="jpg",
565563
)
566564
assert os.path.exists(plot_obj.image_file)
567565

@@ -580,11 +578,11 @@ def test_15_export_plot(self):
580578
def test_16_create_field_plot(self):
581579
cutlist = ["Global:XY"]
582580
plot = self.aedtapp.post._create_fieldplot(
583-
objlist=cutlist,
584-
quantityName="Mag_E",
581+
objects=cutlist,
582+
quantity="Mag_E",
585583
setup_name=self.aedtapp.nominal_adaptive,
586584
intrinsics={},
587-
listtype="CutPlane",
585+
list_type="CutPlane",
588586
)
589587
assert plot
590588

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