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maxcapodi78PipKat
maxcapodi78
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PipKat
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Create circuit schematics (#4458)
Co-authored-by: maxcapodi78 <Shark78> Co-authored-by: Kathy Pippert <[email protected]>
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‎_unittest/example_models/T21/SSN_custom.s6p

+5,084
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‎_unittest/example_models/T21/pcieg5_32gt.ami

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Original file line numberDiff line numberDiff line change
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|******************************************************************************
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| Spec. AMI model generated by SPISim's BPro, Generated on 20170831143940
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|
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| IP of this model belongs to SPISim or its licensed BPro user.
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|*****************************************************************************
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(ANSYS_PCIeG5_32GT_RX
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(Description "Example PCIeG5 Rx 32GT model")
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(Reserved_Parameters
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(AMI_Version (Usage Info) (Type String) (Value "6.1") (Description "Supported AMI version"))
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(Ignore_Bits (Usage Info) (Type Integer) (Default 500) (Description "Ignore four bits to fill up tapped delay line."))
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(Max_Init_Aggressors (Usage Info) (Type Integer) (Default 25) (Description "Number of aggressors is actually unlimited."))
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(Init_Returns_Impulse (Usage Info) (Type Boolean) (Default True) (Description "Both impulse and parameters_out returned."))
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(Supporting_Files (Usage Info) (Type String) (Table ("PCIeG5_32GT.ens")) (Description "CTLE Performance table"))
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(GetWave_Exists (Usage Info) (Type Boolean) (Default True) (Description "GetWave is well and truly provided in the module."))
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) | End Reserved_Parameters
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|****************************************************************************
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| Remove or tamper LICENSE_INFO values will cause simulation being aborted!
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|****************************************************************************
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(Model_Specific
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(LICENSE_INFO (Usage In) (Type String) (Default "LICENSED_ANSYS_AEDT_E168EFCC0268A84087F7B23B510CB41F") (Description "Licensing info."))
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| ------------------ MAIN Settings ------------------
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(MDL_SUB_MODS (Usage In) (Type String) (Default "CTLE,DFE") (Description "Cascaded stages"))
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| ------------------ CTLE Settings ------------------
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(MDL_IDX_FILE (Usage In) (Type String) (Default "PCIeG5_32GT.ens") (Description "Params index table"))
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(MDL_IDX_VALU (Usage In) (Type String) (Default "-1") (Description "Params table rowID"))
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(ADC (Usage In) (Type Integer) (Range -5 -15 -5) (Default -5) (Description "DC Gain in dB"))
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|(CTLE_OUPT_FILE (Usage In) (Type String) (Default "C:/Temp/WorkSpace/SPISim/CST/PCIe/32GT/PCIeG5_32GT.csv") (Description "Output generated FD array for checking purpose"))
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) | End Model_Specific
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) | End SPISim_SPEC_AMI

‎_unittest/example_models/T21/pcieg5_32gt.ibs

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|***************************************************************************
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|
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[IBIS Ver] 5.1
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[File name] pcieg5_32gt.ibs
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[File rev] 1.00
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[Date] Jan 1, 2017
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[Source] BPro (http://www.spisim.com)
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[Copyright] Copyright 2017 ~, SPISim LLC. All right reserved.
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|
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|***************************************************************************
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|
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[Component] Spec_Model
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[Manufacturer] SPISim LLC
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[Package]
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| typ min max
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R_pkg 0.0 0.0 0.0
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L_pkg 0.0 0.0 0.0
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C_pkg 0.0 0.0 0.0
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|
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|***************************************************************************
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|
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[PIN] signal_name model_name R_pin L_pin C_pin
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1p TxP Tx NA NA NA
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1n TxN Tx NA NA NA
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2p RxP Rx NA NA NA
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2n RxN Rx NA NA NA
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|
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|***************************************************************************
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|
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[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
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1p 1n 0.1V NA NA NA
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2p 2n 0.1V NA NA NA
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|
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|****************************************************************
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|
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[Model] Rx
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Model_type Input
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|
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C_comp 0.00p 0.00p 0.00p
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Vinh = 0.55
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Vinl = 0.45
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|
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[Temperature_Range] 25 100 0
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[Voltage Range] 1.2 1.14 1.26
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|
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| The IV table below is equivalent to 50 ohms single-ended load
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[GND Clamp]
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-6.6 -0.132 -0.132 -0.132
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0.0 0.0 0.0 0.0
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6.6 0.132 0.132 0.132
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[Power Clamp]
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-6.6 0.132e-9 0.132e-9 0.132e-9
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0.0 0.0 0.0 0.0
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6.6 -0.132e-9 -0.132e-9 -0.132e-9
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[Algorithmic Model]
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Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
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Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
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Executable Linux_gcc_64 pcieg5_32gt_LX64.so pcieg5_32gt.ami
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[End Algorithmic Model]
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|
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|***************************************************************************
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|
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[Model] Tx
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Model_type Output
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Polarity Non-Inverting
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Enable Active-High
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|
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Vmeas = 0.55
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| typ min max
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C_comp 0 0 0
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[Voltage Range] 1.1 1.0 1.2
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[Temperature Range] 60 100 0
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|
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|***************************************************************************
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|
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[Pulldown]
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-2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
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0.000 +0.00000E+00 +0.00000E+00 +0.00000E+00
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2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
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[Pullup]
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-2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
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0.000 +0.00000E+00 +0.00000E+00 +0.00000E+00
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2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
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|
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[Ramp]
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dV/dt_r 0.2796/15p 0.2610/23.5p 0.2976/13p
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dV/dt_f 0.2796/15p 0.2610/23.5p 0.2976/13p
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|
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|
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[Algorithmic Model]
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Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
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Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
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Executable Linux_gcc_64 pcieg5_32gt_LX64.so pcieg5_32gt.ami
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[End Algorithmic Model]
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|***************************************************************************
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[End]

‎_unittest/test_21_Circuit.py

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Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
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netlist1 = "netlist_small.cir"
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netlist2 = "Schematic1.qcv"
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touchstone = "SSN_ssn.s6p"
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touchstone_custom = "SSN_custom.s6p"
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touchstone2 = "Galileo_V3P3S0.ts"
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ami_project = "AMI_Example"
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@@ -834,3 +835,56 @@ def test_46_create_vpwl(self):
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# time and voltage different length
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myres = self.aedtapp.modeler.schematic.create_voltage_pwl(compname="V3", time_list=[0], voltage_list=[0, 1])
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assert myres is False
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def test_47_automatic_lna(self):
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touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
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842+
status, diff_pairs, comm_pairs = self.aedtapp.create_lna_schematic_from_snp(
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touchstone=touchstone_file,
844+
start_frequency=0,
845+
stop_frequency=70,
846+
auto_assign_diff_pairs=True,
847+
separation=".",
848+
pattern=["component", "pin", "net"],
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analyze=False,
850+
)
851+
assert status
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853+
def test_48_automatic_tdr(self):
854+
touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
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result, tdr_probe_name = self.aedtapp.create_tdr_schematic_from_snp(
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touchstone=touchstone_file,
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probe_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
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probe_ref_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
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termination_pins=["A-MII-RXD2_32.SQFP28X28_208.P", "A-MII-RXD2_66.SQFP20X20_144.N"],
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differential=True,
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design_name="TDR",
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rise_time=35,
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use_convolution=True,
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analyze=False,
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)
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assert result
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def test_49_automatic_ami(self):
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touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
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ami_file = os.path.join(local_path, "example_models", test_subfolder, "pcieg5_32gt.ibs")
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result, eye_curve_tx, eye_curve_rx = self.aedtapp.create_ami_schematic_from_snp(
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touchstone=touchstone_file,
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ibis_ami=ami_file,
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component_name="Spec_Model",
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tx_buffer_name="1p",
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rx_buffer_name="2p",
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use_ibis_buffer=False,
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differential=True,
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tx_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
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tx_refs=["A-MII-RXD1_65.SQFP20X20_144.N"],
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rx_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
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rx_refs=["A-MII-RXD2_66.SQFP20X20_144.N"],
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bit_pattern="random_bit_count=2.5e3 random_seed=1",
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unit_interval="31.25ps",
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use_convolution=True,
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analyze=False,
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design_name="AMI",
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)
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assert result

‎_unittest_solvers/test_00_analyze.py

+1-1
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@@ -359,7 +359,7 @@ def test_04h_3dl_get_all_return_loss_list(self):
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assert self.hfss3dl_solve.get_all_return_loss_list() == ["S(Port1,Port1)", "S(Port2,Port2)"]
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def test_04i_3dl_get_all_insertion_loss_list(self):
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assert self.hfss3dl_solve.get_all_insertion_loss_list() == ["S(Port1,Port1)", "S(Port2,Port2)"]
362+
assert self.hfss3dl_solve.get_all_insertion_loss_list(tx_prefix="Port1", rx_prefix="Port2") == ['S(Port1,Port2)']
363363

364364
def test_04j_3dl_get_next_xtalk_list(self):
365365
assert self.hfss3dl_solve.get_next_xtalk_list() == ["S(Port1,Port2)"]

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