From cf1d873afa266aae336ced897af7fef880d9de45 Mon Sep 17 00:00:00 2001 From: Samuel Lopez <85613111+Samuelopez-ansys@users.noreply.github.com> Date: Fri, 7 Mar 2025 16:38:25 +0100 Subject: [PATCH] FEAT: Add excitations by type for Circuit interface ports (#5880) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Sébastien Morais <146729917+SMoraisAnsys@users.noreply.github.com> Co-authored-by: pyansys-ci-bot <92810346+pyansys-ci-bot@users.noreply.github.com> --- doc/changelog.d/5880.added.md | 1 + src/ansys/aedt/core/application/analysis.py | 10 ++++++--- .../modeler/circuits/primitives_circuit.py | 4 ++-- .../modeler/circuits/primitives_nexxim.py | 2 +- tests/system/general/test_21_Circuit.py | 1 + .../general/test_22_Circuit_DynamicLink.py | 22 +++++++++---------- 6 files changed, 23 insertions(+), 17 deletions(-) create mode 100644 doc/changelog.d/5880.added.md diff --git a/doc/changelog.d/5880.added.md b/doc/changelog.d/5880.added.md new file mode 100644 index 00000000000..07d4fc640b7 --- /dev/null +++ b/doc/changelog.d/5880.added.md @@ -0,0 +1 @@ +Add excitations by type for Circuit interface ports \ No newline at end of file diff --git a/src/ansys/aedt/core/application/analysis.py b/src/ansys/aedt/core/application/analysis.py index d52c5b7e4ff..454e039ceed 100644 --- a/src/ansys/aedt/core/application/analysis.py +++ b/src/ansys/aedt/core/application/analysis.py @@ -629,10 +629,14 @@ def excitations_by_type(self): """ _dict_out = {} for bound in self.design_excitations.values(): - if bound.type in _dict_out: - _dict_out[bound.type].append(bound) + if self.design_type == "Circuit Design": + bound_type = "InterfacePort" + else: + bound_type = bound.type + if bound_type in _dict_out: + _dict_out[bound_type].append(bound) else: - _dict_out[bound.type] = [bound] + _dict_out[bound_type] = [bound] return _dict_out @property diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py index d34d9edbe99..1957cb0f3cd 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py @@ -1325,12 +1325,12 @@ def refresh_all_ids(self): o = CircuitComponent(self, tabname=self.tab_name) o.name = name[0] if len(name) == 2: - o.schematic_id = name[1] + o.schematic_id = int(name[1]) objID = int(o.schematic_id) else: o.id = int(name[1]) o.schematic_id = name[2] - objID = o.id + objID = int(o.schematic_id) self.components[objID] = o return len(self.components) diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py index 2d24fcadc89..6d21b6cae7e 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py @@ -223,7 +223,7 @@ def create_subcircuit(self, location=None, angle=None, name=None, nested_subcirc o = CircuitComponent(self, tabname=self.tab_name, custom_editor=oed) name = match[0].split(";") o.name = name[0] - o.schematic_id = name[2] + o.schematic_id = int(name[2]) o.id = int(name[1]) return o self.refresh_all_ids() diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py index a2397ee3ca0..0cbe0082d24 100644 --- a/tests/system/general/test_21_Circuit.py +++ b/tests/system/general/test_21_Circuit.py @@ -733,6 +733,7 @@ def test_41_assign_excitations(self, add_app): port.reference_node = "Z" assert c.design_excitations + assert c.excitations_by_type setup = c.create_setup() diff --git a/tests/system/general/test_22_Circuit_DynamicLink.py b/tests/system/general/test_22_Circuit_DynamicLink.py index 99782c33a85..1285e38830c 100644 --- a/tests/system/general/test_22_Circuit_DynamicLink.py +++ b/tests/system/general/test_22_Circuit_DynamicLink.py @@ -130,8 +130,8 @@ def test_06_set_sim_solution_on_hfss_subcircuit(self): @pytest.mark.skipif(config["NonGraphical"] and is_linux, reason="Method not working in Linux and Non graphical") def test_07_create_page_port_and_interface_port(self): - hfss_comp_id = 87 - hfss3Dlayout_comp_id = 86 + hfss_comp_id = 1 + hfss3Dlayout_comp_id = 3 hfssComp_pins = self.aedtapp.modeler.schematic.get_pins(hfss_comp_id) assert type(hfssComp_pins) is list assert len(hfssComp_pins) == 4 @@ -150,51 +150,51 @@ def test_07_create_page_port_and_interface_port(self): # Link 1 Creation portname = self.aedtapp.modeler.schematic.create_page_port( - "Link1", [hfss_pin2location["usb_N_conn"][0], hfss_pin2location["usb_N_conn"][1]], 180 + "Link1", [hfss3Dlayout_pin2location["usb_N_conn"][0], hfss3Dlayout_pin2location["usb_N_conn"][1]], 180 ) assert "Link1" in portname.composed_name portname = self.aedtapp.modeler.schematic.create_page_port( "Link1", - [hfss3Dlayout_pin2location["J3B2.3.USBH2_DP_CH"][0], hfss3Dlayout_pin2location["J3B2.3.USBH2_DP_CH"][1]], + [hfss_pin2location["J3B2.3.USBH2_DP_CH"][0], hfss_pin2location["J3B2.3.USBH2_DP_CH"][1]], 180, ) assert "Link1" in portname.composed_name # Link 2 Creation portname = self.aedtapp.modeler.schematic.create_page_port( - "Link2", [hfss_pin2location["usb_N_pcb"][0], hfss_pin2location["usb_N_pcb"][1]], 180 + "Link2", [hfss3Dlayout_pin2location["usb_N_pcb"][0], hfss3Dlayout_pin2location["usb_N_pcb"][1]], 180 ) assert "Link2" in portname.composed_name portname = self.aedtapp.modeler.schematic.create_page_port( "Link2", - [hfss3Dlayout_pin2location["L3M1.3.USBH2_DN_CH"][0], hfss3Dlayout_pin2location["L3M1.3.USBH2_DN_CH"][1]], + [hfss_pin2location["L3M1.3.USBH2_DN_CH"][0], hfss_pin2location["L3M1.3.USBH2_DN_CH"][1]], 180, ) assert "Link2" in portname.composed_name # Ports Creation portname = self.aedtapp.modeler.schematic.create_interface_port( - "Excitation_1", [hfss_pin2location["USB_VCC_T1"][0], hfss_pin2location["USB_VCC_T1"][1]] + "Excitation_1", [hfss3Dlayout_pin2location["USB_VCC_T1"][0], hfss3Dlayout_pin2location["USB_VCC_T1"][1]] ) assert "Excitation_1" in portname.name portname = self.aedtapp.modeler.schematic.create_interface_port( - "Excitation_2", [hfss_pin2location["usb_P_pcb"][0], hfss_pin2location["usb_P_pcb"][1]] + "Excitation_2", [hfss3Dlayout_pin2location["usb_P_pcb"][0], hfss3Dlayout_pin2location["usb_P_pcb"][1]] ) assert "Excitation_2" in portname.name portname = self.aedtapp.modeler.schematic.create_interface_port( "Port_1", - [hfss3Dlayout_pin2location["L3M1.2.USBH2_DP_CH"][0], hfss3Dlayout_pin2location["L3M1.2.USBH2_DP_CH"][1]], + [hfss_pin2location["L3M1.2.USBH2_DP_CH"][0], hfss_pin2location["L3M1.2.USBH2_DP_CH"][1]], ) assert "Port_1" in portname.name portname = self.aedtapp.modeler.schematic.create_interface_port( "Port_2", - [hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][0], hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][1]], + [hfss_pin2location["J3B2.2.USBH2_DN_CH"][0], hfss_pin2location["J3B2.2.USBH2_DN_CH"][1]], ) assert "Port_2" in portname.name portname = self.aedtapp.modeler.schematic.create_interface_port( "Port_remove", - [hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][0], hfss3Dlayout_pin2location["J3B2.2.USBH2_DN_CH"][1]], + [hfss_pin2location["J3B2.2.USBH2_DN_CH"][0], hfss_pin2location["J3B2.2.USBH2_DN_CH"][1]], ) self.aedtapp.design_excitations[portname.name].delete()