Merge remote-tracking branch 'origin/main' into fix/issue_3422

Author: Devin-Crawford

Diff for: .github/workflows/unit_tests.yml

@@ -69,7 +69,7 @@ jobs:
       - name: 'Unit testing'
         uses: nick-fields/retry@v3
         with:
-          max_attempts: 3
+          max_attempts: 1
           retry_on: error
           timeout_minutes: 40
           command: |
@@ -132,13 +132,13 @@ jobs:
       - name: 'Unit testing'
         uses: nick-fields/retry@v3
         with:
-          max_attempts: 3
+          max_attempts: 2
           retry_on: error
           timeout_minutes: 50
           command: |
             testenv\Scripts\Activate.ps1
             Set-Item -Path env:PYTHONMALLOC -Value "malloc"
-            pytest -n 6 --dist loadfile --durations=50 -v --cov=pyaedt --cov-report=xml --cov-report=html --junitxml=junit/test-results.xml _unittest
+            pytest -n 4 --dist loadfile --durations=50 -v --cov=pyaedt --cov-report=xml --cov-report=html --junitxml=junit/test-results.xml _unittest
 
       - uses: codecov/codecov-action@v4
         env:

Diff for: .pre-commit-config.yaml

@@ -48,7 +48,7 @@ repos:
 
 # validate GitHub workflow files
 - repo: https://github.com/python-jsonschema/check-jsonschema
-  rev: 0.28.0
+  rev: 0.28.1
   hooks:
     - id: check-github-workflows
 

Diff for: _unittest/conftest.py

@@ -38,7 +38,7 @@
 settings.enable_error_handler = False
 settings.enable_desktop_logs = False
 settings.desktop_launch_timeout = 180
-
+settings.release_on_exception = False
 
 from pyaedt import Edb
 from pyaedt import Hfss

Diff for: _unittest/example_models/T21/SSN_custom.s6p

@@ -0,0 +1,30 @@
+|******************************************************************************
+| Spec. AMI model generated by SPISim's BPro, Generated on 20170831143940
+|
+| IP of this model belongs to SPISim or its licensed BPro user.
+|*****************************************************************************
+(ANSYS_PCIeG5_32GT_RX
+   (Description "Example PCIeG5 Rx 32GT model")
+   (Reserved_Parameters
+      (AMI_Version (Usage Info) (Type String) (Value "6.1")         (Description "Supported AMI version"))
+      (Ignore_Bits (Usage Info) (Type Integer) (Default 500)          (Description "Ignore four bits to fill up tapped delay line."))
+      (Max_Init_Aggressors (Usage Info) (Type Integer) (Default 25) (Description "Number of aggressors is actually unlimited."))
+      (Init_Returns_Impulse (Usage Info) (Type Boolean)             (Default True) (Description "Both impulse and parameters_out returned."))
+      (Supporting_Files (Usage Info) (Type String) (Table ("PCIeG5_32GT.ens")) (Description "CTLE Performance table"))
+      (GetWave_Exists  (Usage Info) (Type Boolean) (Default True) (Description "GetWave is well and truly provided in the module."))
+   ) | End Reserved_Parameters
+
+   |****************************************************************************
+   | Remove or tamper LICENSE_INFO values will cause simulation being aborted!
+   |****************************************************************************
+   (Model_Specific
+      (LICENSE_INFO (Usage In) (Type String) (Default "LICENSED_ANSYS_AEDT_E168EFCC0268A84087F7B23B510CB41F") (Description "Licensing info."))
+      | ------------------ MAIN Settings ------------------
+      (MDL_SUB_MODS (Usage In) (Type String) (Default "CTLE,DFE") (Description "Cascaded stages"))
+      | ------------------ CTLE Settings ------------------
+      (MDL_IDX_FILE (Usage In) (Type String) (Default "PCIeG5_32GT.ens") (Description "Params index table"))
+      (MDL_IDX_VALU (Usage In) (Type String) (Default "-1") (Description "Params table rowID"))
+      (ADC (Usage In) (Type Integer) (Range -5 -15 -5) (Default -5) (Description "DC Gain in dB"))
+      |(CTLE_OUPT_FILE (Usage In) (Type String) (Default "C:/Temp/WorkSpace/SPISim/CST/PCIe/32GT/PCIeG5_32GT.csv") (Description "Output generated FD array for checking purpose"))      
+   ) | End Model_Specific
+) | End SPISim_SPEC_AMI

Diff for: _unittest/example_models/T21/pcieg5_32gt.ami

@@ -0,0 +1,100 @@
+|***************************************************************************
+|
+[IBIS Ver]      5.1
+[File name]     pcieg5_32gt.ibs
+[File rev]      1.00
+[Date]          Jan 1, 2017
+[Source]        BPro (http://www.spisim.com)
+[Copyright]     Copyright 2017 ~, SPISim LLC. All right reserved.
+|
+|***************************************************************************
+|
+[Component]     Spec_Model
+[Manufacturer]  SPISim LLC
+[Package]
+|               typ             min             max
+R_pkg           0.0             0.0             0.0
+L_pkg           0.0             0.0             0.0
+C_pkg           0.0             0.0             0.0
+|
+|***************************************************************************
+|
+[PIN]   signal_name     model_name      R_pin   L_pin   C_pin
+1p       TxP             Tx              NA     NA     NA
+1n       TxN             Tx              NA     NA     NA
+2p       RxP             Rx              NA     NA     NA
+2n       RxN             Rx              NA     NA     NA
+|
+|***************************************************************************
+|
+[Diff Pin] inv_pin  vdiff  tdelay_typ  tdelay_min  tdelay_max
+1p         1n       0.1V   NA          NA          NA
+2p         2n       0.1V   NA          NA          NA
+|
+|****************************************************************
+|
+[Model]     Rx
+Model_type  Input
+|
+C_comp 0.00p 0.00p 0.00p
+Vinh = 0.55
+Vinl = 0.45
+|
+[Temperature_Range]  25    100   0
+[Voltage Range]      1.2   1.14  1.26
+|
+| The IV table below is equivalent to 50 ohms single-ended load
+[GND Clamp]
+-6.6              -0.132            -0.132            -0.132
+ 0.0               0.0               0.0               0.0
+ 6.6               0.132             0.132             0.132
+
+[Power Clamp]
+-6.6               0.132e-9          0.132e-9          0.132e-9
+ 0.0               0.0               0.0               0.0
+ 6.6              -0.132e-9          -0.132e-9         -0.132e-9
+
+[Algorithmic Model]
+Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
+Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
+Executable Linux_gcc_64            pcieg5_32gt_LX64.so   pcieg5_32gt.ami
+[End Algorithmic Model]
+
+|
+|***************************************************************************
+|
+[Model]        Tx
+Model_type     Output
+Polarity       Non-Inverting
+Enable         Active-High
+|
+Vmeas =        0.55
+|                            typ                min                max
+C_comp                       0                  0                  0
+[Voltage Range]             1.1                 1.0                1.2
+[Temperature Range]         60                  100                0
+|
+|***************************************************************************
+|
+[Pulldown]
+-2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
+0.000  +0.00000E+00 +0.00000E+00 +0.00000E+00
+2.500  +5.00000E-02 +5.00000E-02 +5.00000E-02
+[Pullup]
+-2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
+0.000  +0.00000E+00 +0.00000E+00 +0.00000E+00
+2.500  -5.00000E-02 -5.00000E-02 -5.00000E-02
+|
+[Ramp]
+dV/dt_r 0.2796/15p    0.2610/23.5p    0.2976/13p
+dV/dt_f 0.2796/15p    0.2610/23.5p    0.2976/13p
+|
+|
+[Algorithmic Model]
+Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
+Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
+Executable Linux_gcc_64            pcieg5_32gt_LX64.so   pcieg5_32gt.ami
+[End Algorithmic Model]
+
+|***************************************************************************
+[End]

Diff for: _unittest/example_models/T21/pcieg5_32gt.ibs

@@ -307,7 +307,7 @@ def test_15_3dplacement(self):
 
     def test_16_differential_ports(self):
         self.aedtapp.set_active_design(self.design_name)
-        pins = self.aedtapp.modeler.components["R3"].pins
+        pins = list(self.aedtapp.modeler.components["R3"].pins.keys())
         assert self.aedtapp.create_differential_port(pins[0], pins[1], "test_differential", deembed=True)
         assert "test_differential" in self.aedtapp.port_list
 
@@ -376,3 +376,15 @@ def test_22_change_design_settings(self):
         assert (
             self.aedtapp.get_oo_property_value(self.aedtapp.odesign, "Design Settings", "DCExtrapolation") == "Advanced"
         )
+
+    def test_23_dissolve_element(self):
+        comp = self.aedtapp.modeler.components["D1"]
+        pins = {name: pin for name, pin in comp.pins.items() if name in ["D1-1", "D1-2", "D1-7"]}
+        self.aedtapp.dissolve_component("D1")
+        comp = self.aedtapp.modeler.create_components_on_pins(list(pins.keys()))
+        nets = [
+            list(pins.values())[0].net_name,
+            list(pins.values())[1].net_name,
+        ]
+        assert self.aedtapp.create_ports_on_component_by_nets(comp.name, nets)
+        assert self.aedtapp.create_pec_on_component_by_nets(comp.name, "GND")

Diff for: _unittest/test_01_3dlayout_edb.py

@@ -92,14 +92,18 @@ def test_02_create_material(self):
         assert mat1.get_curve_coreloss_type() == "Power Ferrite"
         assert isinstance(mat1.material_appearance, list)
 
-        mat1.material_appearance = [11, 22, 0]
-        assert mat1.material_appearance == [11, 22, 0]
-        mat1.material_appearance = ["11", "22", "10"]
-        assert mat1.material_appearance == [11, 22, 10]
+        mat1.material_appearance = [11, 22, 0, 0.5]
+        assert mat1.material_appearance == [11, 22, 0, 0.5]
+        mat1.material_appearance = ["11", "22", "10", "0.5"]
+        assert mat1.material_appearance == [11, 22, 10, 0.5]
         with pytest.raises(ValueError):
-            mat1.material_appearance = [11, 22, 300]
+            mat1.material_appearance = [11, 22, 300, 0.5]
         with pytest.raises(ValueError):
-            mat1.material_appearance = [11, -22, 0]
+            mat1.material_appearance = [11, 22, 100, 1.5]
+        with pytest.raises(ValueError):
+            mat1.material_appearance = [11, -22, 0, 0.5]
+        with pytest.raises(ValueError):
+            mat1.material_appearance = [11, 22, 0, -1]
         with pytest.raises(ValueError):
             mat1.material_appearance = [11, 22]
 

Diff for: _unittest/test_03_Materials.py

@@ -58,6 +58,10 @@ def init(self, aedtapp, local_scratch):
     def test_01_open_source(self, source):
         assert self.aedtapp.create_sbr_linked_antenna(source, target_cs="feederPosition", fieldtype="farfield")
         assert len(self.aedtapp.native_components) == 1
+        assert self.aedtapp.create_sbr_linked_antenna(
+            source, target_cs="feederPosition", fieldtype="farfield", source_name="LinkedAntenna"
+        )
+        assert len(self.aedtapp.native_components) == 2
 
     def test_02_add_antennas(self):
         self.aedtapp.insert_design("add_antennas")

Diff for: _unittest/test_04_SBR.py

@@ -226,6 +226,8 @@ def test_07_object_clone_and_get_properties(self):
         assert len(new_object.faces) == 6
         assert len(new_object.edges) == 12
         assert new_object.display_wireframe == initial_object.display_wireframe
+        new_object.name = "Properties_Box"
+        assert not new_object.name == "Properties_Box"
 
     def test_08_set_model(self):
         o = self.create_copper_box()