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Add HOCOCR2 definition to headers and svd
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Diff for: ‎svd/R7FA4M1AB.svd

+63,843-63,784
Large diffs are not rendered by default.

Diff for: ‎svd/R7FA6M5BH.svd

+47
Original file line numberDiff line numberDiff line change
@@ -9869,6 +9869,53 @@ http://www.renesas.com/disclaimer \n
98699869
</enumeratedValues>
98709870
</field>
98719871
</fields>
9872+
</register>
9873+
<register>
9874+
<name>HOCOCR2</name>
9875+
<description>High-Speed On-Chip Oscillator Control Register 2</description>
9876+
<addressOffset>0x037</addressOffset>
9877+
<size>8</size>
9878+
<access>read-write</access>
9879+
<resetValue>0x00</resetValue>
9880+
<resetMask>0xFC</resetMask>
9881+
<fields>
9882+
<field>
9883+
<name>Reserved</name>
9884+
<description>These bits are read as 000000. The write value should be 000000.</description>
9885+
<lsb>2</lsb>
9886+
<msb>7</msb>
9887+
<access>read-write</access>
9888+
</field>
9889+
<field>
9890+
<name>HCFRQ1</name>
9891+
<description>HOCO Frequency Setting 0</description>
9892+
<lsb>0</lsb>
9893+
<msb>1</msb>
9894+
<access>read-write</access>
9895+
<enumeratedValues>
9896+
<enumeratedValue>
9897+
<name>00</name>
9898+
<description>16 MHz</description>
9899+
<value>#00</value>
9900+
</enumeratedValue>
9901+
<enumeratedValue>
9902+
<name>01</name>
9903+
<description>18 MHz</description>
9904+
<value>#01</value>
9905+
</enumeratedValue>
9906+
<enumeratedValue>
9907+
<name>10</name>
9908+
<description>20 MHz</description>
9909+
<value>#10</value>
9910+
</enumeratedValue>
9911+
<enumeratedValue>
9912+
<name>others</name>
9913+
<description>Setting prohibited</description>
9914+
<isDefault>true</isDefault>
9915+
</enumeratedValue>
9916+
</enumeratedValues>
9917+
</field>
9918+
</fields>
98729919
</register>
98739920
<register>
98749921
<name>MOCOCR</name>

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -8892,7 +8892,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
88928892
uint8_t : 7;
88938893
} HOCOCR_b;
88948894
};
8895-
__IM uint8_t RESERVED8;
8895+
8896+
union
8897+
{
8898+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
8899+
* 2 */
8900+
8901+
struct
8902+
{
8903+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
8904+
uint8_t : 1;
8905+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
8906+
uint8_t : 2;
8907+
} HOCOCR2_b;
8908+
};
88968909

88978910
union
88988911
{
@@ -16145,7 +16158,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure
1614516158
/* ======================================================== HOCOCR ========================================================= */
1614616159
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1614716160
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
16148-
/* ======================================================== MOCOCR ========================================================= */
16161+
/* ======================================================== HOCOCR2 ======================================================== */
16162+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
16163+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
16164+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
16165+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
16166+
/* ======================================================== MOCOCR ========================================================= */
1614916167
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1615016168
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1615116169
/* ======================================================== FLLCR1 ========================================================= */

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -7967,7 +7967,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
79677967
uint8_t : 7;
79687968
} HOCOCR_b;
79697969
};
7970-
__IM uint8_t RESERVED8;
7970+
7971+
union
7972+
{
7973+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
7974+
* 2 */
7975+
7976+
struct
7977+
{
7978+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
7979+
uint8_t : 1;
7980+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
7981+
uint8_t : 2;
7982+
} HOCOCR2_b;
7983+
};
79717984

79727985
union
79737986
{
@@ -13697,7 +13710,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure
1369713710
/* ======================================================== HOCOCR ========================================================= */
1369813711
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1369913712
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
13700-
/* ======================================================== MOCOCR ========================================================= */
13713+
/* ======================================================== HOCOCR2 ======================================================== */
13714+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
13715+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
13716+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
13717+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
13718+
/* ======================================================== MOCOCR ========================================================= */
1370113719
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1370213720
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1370313721
/* ======================================================== FLLCR1 ========================================================= */

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -7785,7 +7785,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
77857785
uint8_t : 7;
77867786
} HOCOCR_b;
77877787
};
7788-
__IM uint8_t RESERVED8;
7788+
7789+
union
7790+
{
7791+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
7792+
* 2 */
7793+
7794+
struct
7795+
{
7796+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
7797+
uint8_t : 1;
7798+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
7799+
uint8_t : 2;
7800+
} HOCOCR2_b;
7801+
};
77897802

77907803
union
77917804
{
@@ -13456,7 +13469,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure
1345613469
/* ======================================================== HOCOCR ========================================================= */
1345713470
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1345813471
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
13459-
/* ======================================================== MOCOCR ========================================================= */
13472+
/* ======================================================== HOCOCR2 ======================================================== */
13473+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
13474+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
13475+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
13476+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
13477+
/* ======================================================== MOCOCR ========================================================= */
1346013478
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1346113479
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1346213480
/* ======================================================== FLLCR1 ========================================================= */

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -8634,7 +8634,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
86348634
uint8_t : 7;
86358635
} HOCOCR_b;
86368636
};
8637-
__IM uint8_t RESERVED8;
8637+
8638+
union
8639+
{
8640+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
8641+
* 2 */
8642+
8643+
struct
8644+
{
8645+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
8646+
uint8_t : 1;
8647+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
8648+
uint8_t : 2;
8649+
} HOCOCR2_b;
8650+
};
86388651

86398652
union
86408653
{
@@ -14833,7 +14846,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure
1483314846
/* ======================================================== HOCOCR ========================================================= */
1483414847
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1483514848
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
14836-
/* ======================================================== MOCOCR ========================================================= */
14849+
/* ======================================================== HOCOCR2 ======================================================== */
14850+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
14851+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
14852+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
14853+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
14854+
/* ======================================================== MOCOCR ========================================================= */
1483714855
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1483814856
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1483914857
/* ======================================================== FLLCR1 ========================================================= */

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -8574,7 +8574,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
85748574
uint8_t : 7;
85758575
} HOCOCR_b;
85768576
};
8577-
__IM uint8_t RESERVED8;
8577+
8578+
union
8579+
{
8580+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
8581+
* 2 */
8582+
8583+
struct
8584+
{
8585+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
8586+
uint8_t : 1;
8587+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
8588+
uint8_t : 2;
8589+
} HOCOCR2_b;
8590+
};
85788591

85798592
union
85808593
{
@@ -16004,7 +16017,12 @@ typedef struct /*!< (@ 0x40008000) R_CPSCU Structure
1600416017
/* ======================================================== HOCOCR ========================================================= */
1600516018
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1600616019
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
16007-
/* ======================================================== MOCOCR ========================================================= */
16020+
/* ======================================================== HOCOCR2 ======================================================== */
16021+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
16022+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
16023+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
16024+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
16025+
/* ======================================================== MOCOCR ========================================================= */
1600816026
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1600916027
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1601016028
/* ======================================================== FLLCR1 ========================================================= */

Diff for: ‎variants/MINIMA/includes/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h

+20-2
Original file line numberDiff line numberDiff line change
@@ -9126,7 +9126,20 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure
91269126
uint8_t : 7;
91279127
} HOCOCR_b;
91289128
};
9129-
__IM uint8_t RESERVED8;
9129+
9130+
union
9131+
{
9132+
__IOM uint8_t HOCOCR2; /*!< (@ 0x00000037) High-Speed On-Chip Oscillator Control Register
9133+
* 2 */
9134+
9135+
struct
9136+
{
9137+
__IOM uint8_t HCFRQ0 : 2; /*!< [1..0] HOCO Frequency Setting 0 */
9138+
uint8_t : 1;
9139+
__IOM uint8_t HCFRQ1 : 3; /*!< [5..3] HOCO Frequency Setting 1 */
9140+
uint8_t : 2;
9141+
} HOCOCR2_b;
9142+
};
91309143

91319144
union
91329145
{
@@ -16514,7 +16527,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure
1651416527
/* ======================================================== HOCOCR ========================================================= */
1651516528
#define R_SYSTEM_HOCOCR_HCSTP_Pos (0UL) /*!< HCSTP (Bit 0) */
1651616529
#define R_SYSTEM_HOCOCR_HCSTP_Msk (0x1UL) /*!< HCSTP (Bitfield-Mask: 0x01) */
16517-
/* ======================================================== MOCOCR ========================================================= */
16530+
/* ======================================================== HOCOCR2 ======================================================== */
16531+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Pos (0UL) /*!< HCFRQ0 (Bit 0) */
16532+
#define R_SYSTEM_HOCOCR2_HCFRQ0_Msk (0x3UL) /*!< HCFRQ0 (Bitfield-Mask: 0x03) */
16533+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Pos (3UL) /*!< HCFRQ1 (Bit 3) */
16534+
#define R_SYSTEM_HOCOCR2_HCFRQ1_Msk (0x38UL) /*!< HCFRQ1 (Bitfield-Mask: 0x07) */
16535+
/* ======================================================== MOCOCR ========================================================= */
1651816536
#define R_SYSTEM_MOCOCR_MCSTP_Pos (0UL) /*!< MCSTP (Bit 0) */
1651916537
#define R_SYSTEM_MOCOCR_MCSTP_Msk (0x1UL) /*!< MCSTP (Bitfield-Mask: 0x01) */
1652016538
/* ======================================================== FLLCR1 ========================================================= */

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