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290 | 290 | / { |
291 | 291 | chosen { |
292 | 292 | zephyr,camera = &dcmi; |
| 293 | + zephyr,display = <dc; |
| 294 | + zephyr,mipi-dsi = &mipi_dsi; |
293 | 295 | zephyr,console = &usart6; |
294 | 296 | zephyr,shell-uart = &usart6; |
295 | 297 | zephyr,cdc-acm-uart0 = &usart6; |
@@ -448,3 +450,80 @@ qspi_flash: &mx25l12833f {}; |
448 | 450 | }; |
449 | 451 |
|
450 | 452 | /delete-node/ &sram2; |
| 453 | + |
| 454 | +&sdram1 { |
| 455 | + /* Frame buffer memory cache will cause screen flickering. */ |
| 456 | + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; |
| 457 | +}; |
| 458 | + |
| 459 | +/* |
| 460 | + *PLL3 calculation for 1024x768@60Hz (57.8 MHz pixel clock) |
| 461 | + * Portenta H7 uses 25 MHz HSE crystal |
| 462 | + * VCO input = HSE / div-m = 25 MHz / 25 = 1 MHz |
| 463 | + * VCO output = VCO input × mul-n = 1 MHz × 289 = 289 MHz |
| 464 | + * Pixel clock = VCO output / div-r = 289 MHz / 5 = 57.8 MHz |
| 465 | + */ |
| 466 | +&pll3 { |
| 467 | + status = "okay"; |
| 468 | + clocks = <&clk_hse>; |
| 469 | + div-m = <25>; /* HSE_VALUE/1MHz: 25MHz/25 = 1 MHz VCO input */ |
| 470 | + mul-n = <289>; /* pixelclock/200kHz: 57800/200 = 289 */ |
| 471 | + div-p = <2>; |
| 472 | + div-q = <7>; |
| 473 | + div-r = <5>; /* 1000/200kHz = 5 -> 289MHz/5 = 57.8 MHz */ |
| 474 | +}; |
| 475 | + |
| 476 | +<dc { |
| 477 | + status = "okay"; |
| 478 | + ext-sdram = <&sdram1>; |
| 479 | + width = <1024>; |
| 480 | + height = <768>; |
| 481 | + def-back-color-red = <0>; |
| 482 | + def-back-color-green = <0>; |
| 483 | + def-back-color-blue = <0>; |
| 484 | + pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>; |
| 485 | + |
| 486 | + display-timings { |
| 487 | + compatible = "zephyr,panel-timing"; |
| 488 | + hsync-active = <0>; |
| 489 | + vsync-active = <0>; |
| 490 | + de-active = <0>; |
| 491 | + pixelclk-active = <0>; |
| 492 | + hsync-len = <68>; |
| 493 | + hfront-porch = <24>; |
| 494 | + hback-porch = <80>; |
| 495 | + vsync-len = <6>; |
| 496 | + vfront-porch = <3>; |
| 497 | + vback-porch = <29>; |
| 498 | + }; |
| 499 | +}; |
| 500 | + |
| 501 | +&mipi_dsi { |
| 502 | + status = "okay"; |
| 503 | + |
| 504 | + pll-ndiv = <40>; |
| 505 | + pll-idf = <2>; |
| 506 | + pll-odf = <0>; |
| 507 | + |
| 508 | + de-active-high; |
| 509 | + bta-ack-disable; /* ANX7625 bridge doesn't respond to BTA requests */ |
| 510 | + largest-packet-size = <16>; |
| 511 | + |
| 512 | + phy-timings = <35 35 35 35 0 10>; |
| 513 | + |
| 514 | + /* |
| 515 | + * This binding allows adding child node with with data-lanes property |
| 516 | + * as required by STM32 MIPI-DSI driver. |
| 517 | + */ |
| 518 | + anx7625: anx7625@0 { |
| 519 | + status = "okay"; |
| 520 | + compatible = "analogix,anx7625"; |
| 521 | + reg = <0>; /* Virtual channel 0 */ |
| 522 | + pixel-format = <0>; /* Not used */ |
| 523 | + data-lanes = <2>; /* 2 data lanes */ |
| 524 | + i2c-bus = <&i2c1>; |
| 525 | + video-on-gpios = <&gpiok 2 GPIO_ACTIVE_HIGH>; |
| 526 | + video-rst-gpios = <&gpioj 3 GPIO_ACTIVE_HIGH>; |
| 527 | + otg-on-gpios = <&gpioj 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; |
| 528 | + }; |
| 529 | +}; |
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