@@ -135,9 +135,6 @@ class RAGreedy : public MachineFunctionPass,
135135 std::unique_ptr<Spiller> SpillerInstance;
136136 PQueue Queue;
137137 unsigned NextCascade;
138-
139- // AVR specific: have we already unallocated REG_Y after a spill was done?
140- bool IsYReserved;
141138
142139 // Live ranges pass through a number of stages as we try to allocate them.
143140 // Some of the stages may also create new live ranges:
@@ -425,7 +422,6 @@ class RAGreedy : public MachineFunctionPass,
425422 void collectHintInfo (unsigned , HintsInfo &);
426423
427424 bool isUnusedCalleeSavedReg (unsigned PhysReg) const ;
428- void UndoRegYAllocation ();
429425};
430426} // end anonymous namespace
431427
@@ -452,7 +448,7 @@ FunctionPass* llvm::createGreedyRegisterAllocator() {
452448 return new RAGreedy ();
453449}
454450
455- RAGreedy::RAGreedy (): MachineFunctionPass(ID), IsYReserved( false ) {
451+ RAGreedy::RAGreedy (): MachineFunctionPass(ID) {
456452 initializeLiveDebugVariablesPass (*PassRegistry::getPassRegistry ());
457453 initializeSlotIndexesPass (*PassRegistry::getPassRegistry ());
458454 initializeLiveIntervalsPass (*PassRegistry::getPassRegistry ());
@@ -1642,34 +1638,6 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
16421638 return 0 ;
16431639}
16441640
1645- // AVR specific code used to handle the reservation of REG_Y if any other
1646- // register has been spilled.
1647- // :NOTE: KEEP THIS CONSTANT UPDATED with the backend!
1648- // This has to be a define because of linkage problems between libraries.
1649- #define REG_Y (51U )
1650- namespace llvm {
1651- bool RA_ReserveREG_Y = false ;
1652- bool RA_InSpillerCode = false ;
1653- } // end of namespace llvm
1654-
1655- void RAGreedy::UndoRegYAllocation () {
1656- // search through all virtual registers where REG_Y has been assigned and
1657- // send them back to the work list for reallocation
1658- for (unsigned i = 0 , e = MRI->getNumVirtRegs (); i != e; ++i) {
1659- unsigned VirtReg = TargetRegisterInfo::index2VirtReg (i);
1660- if (MRI->reg_nodbg_empty (VirtReg))
1661- continue ;
1662-
1663- for (MCRegAliasIterator AI (REG_Y, TRI, true ); AI.isValid (); ++AI)
1664- if (VRM->getPhys (VirtReg) == *AI) {
1665- LiveInterval &LI = LIS->getInterval (VirtReg);
1666- Matrix->unassign (LI);
1667- enqueue (&LI);
1668- }
1669- }
1670- }
1671- #undef REG_Y
1672-
16731641
16741642// ===----------------------------------------------------------------------===//
16751643// Local Splitting
@@ -2610,25 +2578,10 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
26102578 DEBUG (dbgs () << " Do as if this register is in memory\n " );
26112579 NewVRegs.push_back (VirtReg.reg );
26122580 } else {
2613- RA_InSpillerCode = true ;
26142581 NamedRegionTimer T (" Spiller" , TimerGroupName, TimePassesIsEnabled);
26152582 LiveRangeEdit LRE (&VirtReg, NewVRegs, *MF, *LIS, VRM, this , &DeadRemats);
26162583 spiller ().spill (LRE);
26172584 setStage (NewVRegs.begin (), NewVRegs.end (), RS_Done);
2618- RA_InSpillerCode = false ;
2619-
2620- // AVR specific: If we have reached this point and the backend has notified
2621- // it has inserted a spill via ReserveREG_Y, then search for any allocations
2622- // of REG_Y in the live intervals and undo them.
2623- if (!IsYReserved && RA_ReserveREG_Y) {
2624- // do all this work only once
2625- IsYReserved = true ;
2626- // update the reserved register list
2627- MRI->freezeReservedRegs (VRM->getMachineFunction ());
2628- RegClassInfo.runOnMachineFunction (VRM->getMachineFunction ());
2629- // finally perform the real work
2630- UndoRegYAllocation ();
2631- }
26322585
26332586 if (VerifyEnabled)
26342587 MF->verify (this , " After spilling" );
@@ -2688,8 +2641,5 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
26882641 postOptimization ();
26892642
26902643 releaseMemory ();
2691-
2692- IsYReserved = false ;
2693- RA_ReserveREG_Y = false ;
26942644 return true ;
26952645}
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