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[DAG] Remove isVectorClearMaskLegal() check from vector_build dagcombine
This check currently doesn't seem to do anything useful on any in-tree target: On non-x86, it always evaluates to false, so we never hit the code path that creates the shuffle with zero. On x86, it just forwards to isShuffleMaskLegal(), which is a reasonable thing to query in general, but doesn't make sense if only restricted to zero blends. Differential Revision: https://reviews.llvm.org/D24625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282567 91177308-0d34-0410-b5e6-96231b3b80d8
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3 files changed

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lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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@@ -13064,13 +13064,6 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) {
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Mask[i] = Vec2Offset + ExtIndex;
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}
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// Avoid introducing illegal shuffles with zero.
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// TODO: This doesn't actually do anything smart at the moment.
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// We should either delete this, or check legality for all the shuffles
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// we create.
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if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
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return SDValue();
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// The type the input vectors may have changed above.
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InVT1 = VecIn1.getValueType();
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test/CodeGen/AMDGPU/r600-export-fix.ll

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@@ -3,9 +3,9 @@
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;CHECK: EXPORT T{{[0-9]}}.XYZW
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;CHECK: EXPORT T{{[0-9]}}.0000
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;CHECK: EXPORT T{{[0-9]}}.0000
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;CHECK: EXPORT T{{[0-9]}}.0XYZ
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;CHECK: EXPORT T{{[0-9]}}.0YZW
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;CHECK: EXPORT T{{[0-9]}}.XYZW
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;CHECK: EXPORT T{{[0-9]}}.YZ00
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;CHECK: EXPORT T{{[0-9]}}.XY00
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;CHECK: EXPORT T{{[0-9]}}.0000
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;CHECK: EXPORT T{{[0-9]}}.0000
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test/CodeGen/SystemZ/vec-perm-13.ll

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@@ -19,8 +19,8 @@ define <4 x i16> @f1(<4 x i16> %x) {
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; CHECK-VECTOR-NEXT: .space 1
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; CHECK-VECTOR-NEXT: .byte 6
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; CHECK-VECTOR-NEXT: .byte 7
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; CHECK-VECTOR-NEXT: .byte 16
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; CHECK-VECTOR-NEXT: .byte 17
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; CHECK-VECTOR-NEXT: .byte 22
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; CHECK-VECTOR-NEXT: .byte 23
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; CHECK-VECTOR-NEXT: .space 1
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; CHECK-VECTOR-NEXT: .space 1
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; CHECK-VECTOR-NEXT: .space 1

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