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RC 1.4.11 (#464)
Release 1.4.11 * FPGA developer kit now supports Xilinx SDx/Vivado 2019.1 * To upgrade, use Developer AMI v1.7.0 on the AWS Marketplace. The Developer Kit scripts (hdk_setup.sh or sdaccel_setup.sh) will detect the tool version and update the environment based on requirements needed for Xilinx 2019.1 tools. * New functionality: * Added a developer resources section that provides guides on how to setup your own GUI Desktop and compute cluster environment. * Developers can now ask for AFI limit increases via the AWS Support Center Console * Create a case to increase your `EC2 FPGA` service limit from the console. * HLx IPI flow updates * HLx support for AXI Fast Memory mode. * HLx support for 3rd party simulations. * HLx support for changes in shell and AWS IP updates(e.g. sh_ddr). * Bug Fixes: * Documentation fixes in the Shell Interface Specification * Fixes for forum questions * Unable to compile aws_v1_0_vl_rfs.sv in Synopsys VCS * Use fpga_mgmt init in HLx runtime * New XRT versions added to the XRT Installation Instructions to fix segmentation faults when using xclbin instead of awsxclbin files. * Deprecations: * Removed GUI Setup scripts from AMI v1.7.0 onwards.
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.gitmodules

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@@ -10,3 +10,6 @@
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path = SDAccel/examples/xilinx_2018.3
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url = https://github.com/Xilinx/SDAccel_Examples.git
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branch = master
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[submodule "SDAccel/examples/xilinx_2019.1"]
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path = SDAccel/examples/xilinx_2019.1
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url = https://github.com/Xilinx/SDAccel_Examples.git

ERRATA.md

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* DRAM Data retention is not supported for CL designs with less than 4 DDRs enabled
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* Combinatorial loops in CL designs are not supported.
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### 2019.1
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* Vivado `compile_simlib` command fails to generate the following verilog IP libraries for the following simulators.
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| Library(verilog) | Simulator |
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|---|---|
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| `sync_ip` | Cadence IES |
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| `hdmi_gt_controller_v1_0_0` | Synopsys VCS |
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* We are working with Xilinx to provide a fix for these.
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## SDK
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## SDAccel (For additional restrictions see [SDAccel ERRATA](./SDAccel/ERRATA.md))

FAQs.md

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Jenkinsfile

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@@ -122,15 +122,16 @@ task_label = [
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]
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// Put the latest version last
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def xilinx_versions = [ '2017.4', '2018.2', '2018.3' ]
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def xilinx_versions = [ '2017.4', '2018.2', '2018.3', '2019.1' ]
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// We want the default to be the latest.
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def default_xilinx_version = xilinx_versions.last()
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def dsa_map = [
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'2017.4' : [ 'DYNAMIC_5_0' : 'dyn'],
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'2018.2' : [ 'DYNAMIC_5_0' : 'dyn'],
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'2018.3' : [ 'DYNAMIC_5_0' : 'dyn']
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'2018.3' : [ 'DYNAMIC_5_0' : 'dyn'],
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'2019.1' : [ 'DYNAMIC_5_0' : 'dyn']
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]
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def sdaccel_example_default_map = [
@@ -153,6 +154,12 @@ def sdaccel_example_default_map = [
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'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl',
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'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth',
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'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
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],
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'2019.1' : [
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'Hello_World_1ddr': 'SDAccel/examples/xilinx/getting_started/hello_world/helloworld_ocl',
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'Gmem_2Banks_2ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/gmem_2banks_ocl_5.0_shell',
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'Kernel_Global_Bw_4ddr': 'SDAccel/examples/xilinx/getting_started/kernel_to_gmem/kernel_global_bandwidth_5.0_shell',
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'RTL_Vadd_Debug': 'SDAccel/examples/xilinx/getting_started/rtl_kernel/rtl_vadd_hw_debug'
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]
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]
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@@ -174,6 +181,12 @@ def simulator_tool_default_map = [
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'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
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'questa': 'questa/10.6c_1',
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'ies': 'incisive/15.20.063'
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],
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'2019.1' : [
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'vivado': 'xilinx/SDx/2019.1.op2552052',
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'vcs': 'synopsys/vcs-mx/N-2017.12-SP2',
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'questa': 'questa/10.6c_1',
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'ies': 'incisive/15.20.063'
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]
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]
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@@ -270,7 +283,7 @@ def test_run_py_bindings() {
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try {
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sh """
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set -e
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source $WORKSPACE/shared/tests/bin/setup_test_sdk_env_al2.sh "py_bindings"
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source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh "py_bindings"
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python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file}
275288
"""
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} catch (exc) {
@@ -368,7 +381,7 @@ def test_fpga_all_slots() {
368381
}
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catch (exception) {
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echo "Test FPGA Tools All Slots failed"
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input message: "1 slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance."
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input message: "All slot FPGA Tools test failed. Click Proceed or Abort when you are done debugging on the instance."
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throw exception
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}
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finally {
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source $WORKSPACE/shared/tests/bin/setup_test_sdk_env.sh
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newgrp fpgauser
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export SDK_DIR="${WORKSPACE}/sdk"
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source $WORKSPACE/shared/tests/bin/setup_test_env.sh
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python2.7 -m pytest -v $WORKSPACE/${test} --junit-xml $WORKSPACE/${report_file}
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"""
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} catch (exc) {
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//=============================================================================
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// Python Binding Test
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//=============================================================================
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if (test_py_bindings) {
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all_tests['Test Python Bindings'] = {
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stage('Test Python Bindings') {
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node('f1.2xl_runtime_test_al2') {
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test_run_py_bindings()
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}
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}
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}
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}
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// if (test_py_bindings) {
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// all_tests['Test Python Bindings'] = {
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// stage('Test Python Bindings') {
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// node('f1.2xl_runtime_test_al2') {
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// test_run_py_bindings()
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// }
620+
// }
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// }
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// }
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//=============================================================================
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// Precompiled Runtime Tests
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// SDAccel Tests
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//=============================================================================
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876-
if (test_sdaccel_scripts) {
877-
all_tests['Test SDAccel Scripts'] = {
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stage('Test SDAccel Scripts') {
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def nodes = [:]
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for (def xilinx_version in xilinx_versions) {
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882-
String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version)
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String node_name = "Test SDAccel Scripts ${xilinx_version}"
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nodes[node_name] = {
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node(node_label) {
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String report_file = "test_sdaccel_scripts_${xilinx_version}.xml"
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checkout scm
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try {
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sh """
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set -e
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source $WORKSPACE/shared/tests/bin/setup_test_env.sh
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python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file}
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"""
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} finally {
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run_junit(report_file)
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}
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}
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}
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}
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parallel nodes
901-
}
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}
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}
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// if (test_sdaccel_scripts) {
889+
// all_tests['Test SDAccel Scripts'] = {
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// stage('Test SDAccel Scripts') {
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// def nodes = [:]
892+
// for (def xilinx_version in xilinx_versions) {
893+
//
894+
// String node_label = get_task_label(task: 'source_scripts', xilinx_version: xilinx_version)
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// String node_name = "Test SDAccel Scripts ${xilinx_version}"
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// nodes[node_name] = {
897+
// node(node_label) {
898+
// String report_file = "test_sdaccel_scripts_${xilinx_version}.xml"
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// checkout scm
900+
// try {
901+
// sh """
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// set -e
903+
// source $WORKSPACE/shared/tests/bin/setup_test_env.sh
904+
// python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_sdaccel_scripts.py --junit-xml $WORKSPACE/${report_file}
905+
// """
906+
// } finally {
907+
// run_junit(report_file)
908+
// }
909+
// }
910+
// }
911+
// }
912+
// parallel nodes
913+
// }
914+
// }
915+
// }
904916

905917
if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
906918
all_tests['Run SDAccel Tests'] = {
@@ -995,6 +1007,7 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
9951007
}
9961008

9971009
boolean test_sw_emu_supported = true
1010+
boolean test_hw_emu_supported = true
9981011

9991012
if(description_json["targets"]) {
10001013
if(description_json["targets"].contains("sw_emu")) {
@@ -1004,6 +1017,13 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
10041017
test_sw_emu_supported = false
10051018
echo "Description file ${description_file} does not have target sw_emu"
10061019
}
1020+
if(description_json["targets"].contains("hw_emu")) {
1021+
test_hw_emu_supported = true
1022+
echo "Description file ${description_file} has target sw_emu"
1023+
} else {
1024+
test_hw_emu_supported = false
1025+
echo "Description file ${description_file} does not have target sw_emu"
1026+
}
10071027
} else {
10081028
echo "Description json did not have a 'target' key"
10091029
}
@@ -1032,23 +1052,25 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
10321052
}
10331053
}
10341054

1035-
stage(hw_emu_stage_name) {
1036-
node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) {
1037-
checkout scm
1038-
try {
1039-
sh """
1040-
set -e
1041-
source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh
1042-
export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name}
1043-
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version}
1044-
"""
1045-
} catch (error) {
1046-
echo "${hw_emu_stage_name} HW EMU Build generation failed"
1047-
archiveArtifacts artifacts: "${example_path}/**", fingerprint: true
1048-
throw error
1049-
} finally {
1050-
run_junit(hw_emu_report_file)
1051-
git_cleanup()
1055+
if(test_hw_emu_supported) {
1056+
stage(hw_emu_stage_name) {
1057+
node(get_task_label(task: 'sdaccel_builds', xilinx_version: xilinx_version)) {
1058+
checkout scm
1059+
try {
1060+
sh """
1061+
set -e
1062+
source $WORKSPACE/shared/tests/bin/setup_test_build_sdaccel_env.sh
1063+
export AWS_PLATFORM=\$AWS_PLATFORM_${dsa_name}
1064+
python2.7 -m pytest -v $WORKSPACE/SDAccel/tests/test_build_sdaccel_example.py::TestBuildSDAccelExample::test_hw_emu --examplePath ${example_path} --junit-xml $WORKSPACE/${hw_emu_report_file} --timeout=21600 --rteName ${dsa_rte_name} --xilinxVersion ${xilinx_version}
1065+
"""
1066+
} catch (error) {
1067+
echo "${hw_emu_stage_name} HW EMU Build generation failed"
1068+
archiveArtifacts artifacts: "${example_path}/**", fingerprint: true
1069+
throw error
1070+
} finally {
1071+
run_junit(hw_emu_report_file)
1072+
git_cleanup()
1073+
}
10521074
}
10531075
}
10541076
}

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