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Copy file name to clipboardExpand all lines: ERRATA.md
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5. XSIM simulator does not support a cycle-accurate simulation model forthe HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM usedin XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended.
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6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release.
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6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state forall tests. Simulation support for the HBM monitor will be addedin a future release.
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 instances at this time.
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9. Vivado 2025.1 introduces a `set_property DONT_TOUCH` to the HBM model that makes meeting
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timing difficult in the implementation stage. AMD has responded to this issue on their AR, stating that it will be fixed in a future version of Vivado. [See here for more details](https://adaptivesupport.amd.com/s/article/000038502?language=en_US&t=1754923887312). All HDK CL examples have been updated to address this issue. Customers should follow this AR when creating their own designs.
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10. Due to a XSIM bug in Vivado 2025.2, simulation library compilation with VCS and Questa requires a double compilation workaround, already added to `Makefile.common.inc`, until AMD releases a fix. This results in slightly longer compilation time and generation of a `cxl_error.log` file with an expected error caused by the `sc_ultralite_v1_0_rfs.vhd` file (which can be safely ignored).
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## HLx
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1. When executing the `aws::make_ipi`commandin Vivado to set up the HLx IPI environment, the AWS IP instance may default to the name `f1_inst`. This is a known Vivado behavior and can be safely ignored. Users can rename this instance according to their preference.
Copy file name to clipboardExpand all lines: README.md
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# AWS F2
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## F2 FPGA Developer Kit Documentation on ReadTheDocs
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The documentation for the F2 FPGA Developer Kit including our User Guide, tutorials, code snippets, and more can now be found on [our ReadTheDocs website](https://awsdocs-fpga-f2.readthedocs-hosted.com).
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**Please note that the documentation and assets provided on this branch and others prefixed with `f2` are relevant to F2 instances only!**
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## F2 FPGA Development Kit Overview
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The F2 FPGA Development Kit is a hardware-software development kit that enables developers to create accelerators for the high-performance accelerator cards on EC2 F2 instances. Using the development kit, you can architect, simulate, optimize, and test your designs.
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## F2 FPGA Developer Kit Documentation on ReadTheDocs
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The documentation for the F2 FPGA Developer Kit including our User Guide, tutorials, code snippets, and more can now be found on [our ReadTheDocs website](https://awsdocs-fpga-f2.readthedocs-hosted.com).
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# Support
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For any issues with this developer kit documentation or code, please open a [GitHub issue](https://github.com/aws/aws-fpga/issues) with all steps to reproduce.
Copy file name to clipboardExpand all lines: RELEASE_NOTES.md
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# F2 Developer Kit Release Notes
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## v2.3.0
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* Vivado/Vitis 2025.2 Support
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* Both the [FPGA Developer AMI (Ubuntu) - 1.19.0](https://aws.amazon.com/marketplace/pp/prodview-tcl7sjgreh6bq) and [FPGA Developer AMI (Rocky Linux) - 1.19.0](http://aws.amazon.com/marketplace/pp/prodview-7mukkbz7l2uvu) are available with 2025.2 tools installed and ready to use
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*[See what's new in Vivado 2025.2 here](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado/vivado-whats-new.html#tabs-de9b056824-item-d69fba5dd6-tab)
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*[See what's new in Vitis 2025.2 here](https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis/vitis-whats-new.html)
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* AWS EC2 F2 Runtime AMI Builder (RAB) Update
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* Added support for [Vivado Lab Edition 2025.2](https://docs.amd.com/r/en-US/ug908-vivado-programming-debugging/Vivado-Lab-Edition)
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* Virtual Ethernet Driver
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* Updated to use natively-available kernel modules instead of DPDK ones
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* HDK Devkit Updates
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* Cleaned up the legacy code in the [`power_up()` simulation task](./hdk/common/verif/models/sh_bfm/sh_bfm.sv#L1218-L1253) to align with the correct shell clock scheme.
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* Due to a XSIM bug in Vivado 2025.2, a double compilation workaround is added in `Makefile.common.inc` (see [ERRATA](./ERRATA.md#hdk) for more details)
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* AFI and AMI Creation Permission Requirements
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* Added [Setting Up IAM Roles for DevKit Use](./developer_resources/Setting_up_IAM_roles_for_devkit_use.md) doc that shows how to set up an IAM role and the minimum permission configurations needed to create each of these artifacts
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## v2.2.2
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* Introducing the AWS EC2 F2 Runtime AMI Builder (RAB)
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## v2.1.1
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* Added global register offset for the SDE IP. See [CL_SDE software examples](./hdk/cl/examples/cl_sde/software/src/README.md).
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* Added [CL_SDE software exmaple](./hdk/cl/examples/cl_sde/software/src/sde_c2h_user_buffers.c) for a user allocated DMA buffer.
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* Added [CL_SDE software example](./hdk/cl/examples/cl_sde/software/src/sde_c2h_user_buffers.c) for a user allocated DMA buffer.
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*[Documentation](./hdk/docs/List_AFI_on_Marketplace.md) to assist F2 customers with releasing AFIs and AMIs on the AWS Marketplace.
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*[Documentation](./developer_resources/Amazon_DCV_Setup_Guide.md) to assist in creating a virtual desktop based on the FPGA Developer AMI running graphics-intensive applications remotely on Amazon EC2 instances.
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* Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the [cl_mem_perf](./hdk/cl/examples/cl_mem_perf/verif/README.md#test_hbm_perf_randomsv).
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* Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the [cl_mem_perf](./hdk/cl/examples/cl_mem_perf/verif/README.md#system-verilog-tests).
| Hardware accelerator development using Vivado (HDK) | This environment supports the Hardware Development Kit (HDK) design flow, which empowers FPGA developers to create accelerator designs from scratch, using HDL source code and IPs. <br><br>The AMD Vivado tool synthesizes, implements, and generates the Design Check Point (DCP) file used in F2 AFI creation. AWS FPGA developers benefit from the suite of scripts supplied in the HDK that help to automate different design steps. This allows for flexibility in architecting, implementing, and optimizing accelerator designs while using the HDK.| Verilog/SystemVerilog/VHDL | User-implemented DMA engine or Streaming Data Engine (SDE) | Simulation, Virtual JTAG | Hardware developers with advanced FPGA experience |
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| Hardware accelerator development using Vivado (HDK) | This environment supports the Hardware Development Kit (HDK) design flow, which empowers FPGA developers to create accelerator designs from scratch, using HDL source code and IPs. The AMD Vivado tool synthesizes, implements, and generates the Design Check Point (DCP) file used in F2 AFI creation. AWS FPGA developers benefit from the suite of scripts supplied in the HDK that help to automate different design steps. This allows for flexibility in architecting, implementing, and optimizing accelerator designs while using the HDK.| Verilog/System Verilog/VHDL | User-implemented DMA engine or Streaming Data Engine (SDE) | Simulation, Virtual JTAG | Hardware developers with advanced FPGA experience |
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| Hardware accelerator development using Vitis | This environment supports the Vitis design flow, which enables software developers to write C++ code, which may then be compiled into RTL and used in cycle-accurate hardware simulation. After it may then be built into an accelerator design. This step is not necessary, but is encouraged. Vitis may also be used to implement accelerator designs from scratch, using HDL and IPs directly, similar to Vivado. Vitis offers additional analysis tools to aid in the refinement of designs. | Verilog/System Verilog/VHDL | XDMA Engine (coming soon) | Hardware Emulation | Advanced software developers or hardware developers with intermediate to advanced FPGA experience |
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| Hardware accelerator development using Vivado IP Integrator (IPI) and High Level Design (HLx) | This environment supports the Vivado high-level design flow using IP integrator in the GUI. | Block Design in IP Integrator | AWS IP for HLx | Simulation, Virtual JTAG | Hardware developers with intermediate FPGA experience |
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On-premise environment: Customers can set up a [on-premise development (with licensing requirements listed)](./hdk/docs/on_premise_licensing_help.md) environment for [supported AMD tool versions.](#hardware-development-kit-hdk).
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| On-premise environment | Customers can set up a [on-premise development (with licensing requirements listed)](./hdk/docs/on_premise_licensing_help.md) environment for [supported AMD tool versions.](#hardware-development-kit-hdk). |||||
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### Quick Start Links
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-[cl/examples](./hdk/cl/examples): Multiple CL examples to demonstrate connectivity between CL logic, the F2 Shell, and accelerator resources like DDR and HBM.
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- Support for 3rd party simulators
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The HDK currently supports the following tool versions:
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| AMD Vivado Design Suite | Synopsys VCS (Bring your own license) | Siemens Questa (Bring your own license) |
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|:-------|:----------------|
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| Python | 3.10+ |
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### Software-Defined Development Environment
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The software-defined development environment allows customers to compile their C/C++/OpenCL code into AFIs and use C/C++/OpenCL APIs to interface with the accelerator, running on the FPGA. Software developers with little or no FPGA experience will be able to quickly familiarize themselves with the development experience that accelerates cloud applications. The optimized compiler, Vitis, allows easy F2 accelerator development using C/C++/OpenCL and/or Verilog/VHDL.
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| FPGA Developer AMI Version | FPGA Developer AMI ID (us-east-1) | Vivado/Vitis Version Supported | Operating System Version |
Given the large size of the FPGA used for F2, AMD tools work best with at least 4 vCPU’s and 32GiB Memory. We recommend [Compute Optimized and Memory Optimized instance types](https://aws.amazon.com/ec2/instance-types/) to successfully run the synthesis of acceleration code. Developers may start coding and run simulations on low-cost `General Purpose`[instances types](https://aws.amazon.com/ec2/instance-types/).
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