Skip to content

Commit 2ecf9b9

Browse files
AWSaallurikristopk
AWSaalluri
authored and
kristopk
committed
Release candidate for Release V1.4.2 (#426)
* Release candidate for Release V1.4.2 * V1.4.2 release notes & delta updates
1 parent 8847d31 commit 2ecf9b9

File tree

21 files changed

+141
-76
lines changed

21 files changed

+141
-76
lines changed

‎Jenkinsfile

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,9 @@ properties([parameters([
2121
booleanParam(name: 'debug_dcp_gen', defaultValue: false, description: 'Only run FDF on cl_hello_world. Overrides test_*.'),
2222
booleanParam(name: 'debug_fdf_uram', defaultValue: false, description: 'Debug the FDF for cl_uram_example.'),
2323
booleanParam(name: 'fdf_ddr_comb', defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'),
24-
booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.')
24+
booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.'),
25+
booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins')
26+
2527
])])
2628

2729
//=============================================================================
@@ -144,6 +146,13 @@ def is_public_repo() {
144146

145147
def get_task_label(Map args=[ : ]) {
146148
String task_label = args.xilinx_version + '_' + task_label[args.task]
149+
//boolean use_test_ami = params.get('use_test_ami')
150+
151+
if (params.use_test_ami) {
152+
echo "Test AMI Requested"
153+
task_label = task_label + '_test'
154+
}
155+
147156
echo "Label Requested: $task_label"
148157
return task_label
149158
}

‎README.md

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,8 @@ NOTE: For on-premises development, SDx/Vivado must have the correct license and
7777
# Getting Started
7878

7979
### New to AWS?
80-
If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI. These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`).
80+
If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI. These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`). AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US).
81+
8182

8283
### New to AWS FPGAs and setting up a development environment?
8384
The developer kit is supported for Linux operating systems only. You have the choice to develop on AWS EC2 using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or on-premises. Within a linux environment, you should execute `git clone https://github.com/aws/aws-fpga.git` to download the latest release to your EC2 Instance or local server. Using a SSH connection, execute `git clone [email protected]:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/).

‎RELEASE_NOTES.md

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,9 @@
2525
* CL to SH 512-bit AXI4 interface
2626
* 1 DDR controller implemented in the SH (always available)
2727
* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
28+
29+
## Release 1.4.2 (See [ERRATA](./ERRATA.md) for unsupported features)
30+
* Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64
2831

2932
## Release 1.4.1 (See [ERRATA](./ERRATA.md) for unsupported features)
3033
* Simulation performance Improvements

‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -61,8 +61,8 @@ resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X2Y
6161
set_property SNAPPING_MODE ON [get_pblocks pblock_CL_bot]
6262
set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
6363

64-
set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
65-
set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
66-
set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
64+
#set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
65+
#set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
66+
#set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
6767

6868

‎hdk/cl/examples/cl_dram_dma/build/constraints/cl_synth_user.xdc

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
11
# This contains the CL specific constraints for synthesis at the CL level
2-
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
3-
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
4-
5-
2+
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
3+
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]

‎hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
3737
set clock_recipe_c [lindex $argv 10]
3838
set uram_option [lindex $argv 11]
3939
set notify_via_sns [lindex $argv 12]
40-
40+
set VDEFINES [lindex $argv 13]
4141
##################################################
4242
## Flow control variables
4343
##################################################
@@ -104,6 +104,11 @@ puts "All reports and intermediate results will be time stamped with $timestamp"
104104

105105
set_msg_config -id {Chipscope 16-3} -suppress
106106
set_msg_config -string {AXI_QUAD_SPI} -suppress
107+
set_msg_config -string {PIPE_CL_SH_AURORA_STAT} -suppress
108+
set_msg_config -string {PIPE_CL_SH_HMC_STAT} -suppress
109+
set_msg_config -string {PIPE_AURORA_CHANNEL_UP} -suppress
110+
set_msg_config -string {PIPE_HMC_IIC} -suppress
111+
set_msg_config -string {PIPE_SH_CL_AURORA_STAT} -suppress
107112

108113
# Suppress Warnings
109114
# These are to avoid warning messages that may not be real issues. A developer
@@ -123,7 +128,7 @@ set_msg_config -id {Vivado 12-4739} -suppress
123128
set_msg_config -id {Vivado 12-5201} -suppress
124129
set_msg_config -id {DRC CKLD-1} -suppress
125130
set_msg_config -id {IP_Flow 19-2248} -suppress
126-
set_msg_config -id {Opt 31-155} -suppress
131+
#set_msg_config -id {Opt 31-155} -suppress
127132
set_msg_config -id {Synth 8-115} -suppress
128133
set_msg_config -id {Synth 8-3936} -suppress
129134
set_msg_config -id {Vivado 12-1023} -suppress

‎hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#Param needed to avoid clock name collisions
1717
set_param sta.enableAutoGenClkNamePersistence 0
1818
set CL_MODULE $CL_MODULE
19+
set VDEFINES $VDEFINES
1920

2021
create_project -in_memory -part [DEVICE_TYPE] -force
2122

@@ -115,7 +116,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
115116

116117
update_compile_order -fileset sources_1
117118
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
118-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
119+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
119120

120121
set failval [catch {exec grep "FAIL" failfast.csv}]
121122
if { $failval==0 } {

‎hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in
150150
.m_axi_rready (sh_cl_dma_pcis_q.rready)
151151
);
152152

153-
153+
//-----------------------------------------------------
154+
//TIE-OFF unused signals to prevent critical warnings
155+
//-----------------------------------------------------
156+
assign sh_cl_dma_pcis_q.rid[15:6] = 10'b0 ;
157+
assign sh_cl_dma_pcis_q.bid[15:6] = 10'b0 ;
158+
154159
//----------------------------
155160
// axi interconnect for DDR address decodes
156161
//----------------------------

‎hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
3737
set clock_recipe_c [lindex $argv 10]
3838
set uram_option [lindex $argv 11]
3939
set notify_via_sns [lindex $argv 12]
40-
40+
set VDEFINES [lindex $argv 13]
4141
##################################################
4242
## Flow control variables
4343
##################################################
@@ -132,6 +132,7 @@ set_msg_config -id {DRC REQP-1853} -suppress
132132
set_msg_config -id {Synth 8-350} -suppress
133133
set_msg_config -id {Synth 8-3848} -suppress
134134
set_msg_config -id {Synth 8-3917} -suppress
135+
set_msg_config -id {Opt 31-430} -suppress
135136

136137
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
137138

@@ -247,6 +248,7 @@ if {$implement} {
247248
########################
248249
# CL Optimize
249250
########################
251+
set place_preHookTcl ""
250252
if {$opt} {
251253
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
252254
impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl

‎hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#Param needed to avoid clock name collisions
1717
set_param sta.enableAutoGenClkNamePersistence 0
1818
set CL_MODULE $CL_MODULE
19+
set VDEFINES $VDEFINES
1920

2021
create_project -in_memory -part [DEVICE_TYPE] -force
2122

@@ -106,7 +107,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
106107

107108
update_compile_order -fileset sources_1
108109
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
109-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
110+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
110111

111112
set failval [catch {exec grep "FAIL" failfast.csv}]
112113
if { $failval==0 } {

‎hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
3737
set clock_recipe_c [lindex $argv 10]
3838
set uram_option [lindex $argv 11]
3939
set notify_via_sns [lindex $argv 12]
40-
40+
set VDEFINES [lindex $argv 13]
4141
##################################################
4242
## Flow control variables
4343
##################################################

‎hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#Param needed to avoid clock name collisions
1717
set_param sta.enableAutoGenClkNamePersistence 0
1818
set CL_MODULE $CL_MODULE
19+
set VDEFINES $VDEFINES
1920

2021
create_project -in_memory -part [DEVICE_TYPE] -force
2122

@@ -120,7 +121,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
120121

121122
update_compile_order -fileset sources_1
122123
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
123-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
124+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
124125

125126
set failval [catch {exec grep "FAIL" failfast.csv}]
126127
if { $failval==0 } {

‎hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
3737
set clock_recipe_c [lindex $argv 10]
3838
set uram_option [lindex $argv 11]
3939
set notify_via_sns [lindex $argv 12]
40-
40+
set VDEFINES [lindex $argv 13]
4141
##################################################
4242
## Flow control variables
4343
##################################################

‎hdk/cl/examples/cl_uram_example/build/scripts/synth_cl_uram_example.tcl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#Param needed to avoid clock name collisions
1717
set_param sta.enableAutoGenClkNamePersistence 0
1818
set CL_MODULE $CL_MODULE
19+
set VDEFINES $VDEFINES
1920

2021
create_project -in_memory -part [DEVICE_TYPE] -force
2122

@@ -140,7 +141,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
140141

141142
update_compile_order -fileset sources_1
142143
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
143-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
144+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
144145

145146
set failval [catch {exec grep "FAIL" failfast.csv}]
146147
if { $failval==0 } {

‎hdk/common/shell_v04261818/build/constraints/cl_debug_bridge.xdc

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
1-
set bridge [get_debug_cores -filter {NAME=~ WRAPPER_INST/CL/*CL_DEBUG_BRIDGE*}]
1+
set bridge [get_debug_cores -filter {NAME=~WRAPPER_INST/CL/*CL_DEBUG_BRIDGE*}]
22
current_instance $bridge/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst
33

4-
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
5-
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
4+
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance wr_clk]]
5+
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance rd_clk]]
66
set wr_clk_period [get_property PERIOD $wr_clock]
77
set rd_clk_period [get_property PERIOD $rd_clock]
88
set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
99

1010
# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
11-
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
11+
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
1212

1313
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
1414

@@ -22,14 +22,14 @@ current_instance
2222

2323
current_instance $bridge/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst
2424

25-
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
26-
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
25+
set wr_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance wr_clk]]
26+
set rd_clock [get_clocks -of_objects [get_ports -scoped_to_current_instance rd_clk]]
2727
set wr_clk_period [get_property PERIOD $wr_clock]
2828
set rd_clk_period [get_property PERIOD $rd_clock]
2929
set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
3030

3131
# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
32-
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance tck] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
32+
set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
3333

3434
# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
3535

‎hdk/common/shell_v04261818/build/scripts/aws_build_dcp_from_cl.sh

Lines changed: 19 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
# Usage help
1919
function usage
2020
{
21-
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-foreground] [-notify] | [-h] | [-H] | [-help] ]"
21+
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-vdefine macro1,macro2,macro3,.....,macrox] -foreground] [-notify] | [-h] | [-H] | [-help] ]"
2222
echo " "
2323
echo "By default the build is run in the background using nohup so that the"
2424
echo "process will not be terminated if the terminal window is closed."
@@ -44,6 +44,7 @@ notify=0
4444
ignore_memory_requirement=0
4545
expected_memory_usage=30000000
4646
uram_option=2
47+
vdefine=""
4748

4849
function info_msg {
4950
echo -e "INFO: $1"
@@ -90,6 +91,9 @@ while [ "$1" != "" ]; do
9091
-uram_option ) shift
9192
uram_option=$1
9293
;;
94+
-vdefine ) shift
95+
vdefine=$1
96+
;;
9397
-foreground ) foreground=1
9498
;;
9599
-notify ) notify=1
@@ -145,7 +149,20 @@ if [[ $uram_option != @(2|3|4) ]]; then
145149
err_msg "$uram_option isn't a valid URAM option. Valid URAM options are 2 (50%), 3 (75%), and 4 (100%)."
146150
exit 1
147151
fi
152+
# process vdefines
153+
info_msg "VDEFINE is : $vdefine"
154+
shopt -s extglob
155+
IFS=',' read -r -a vdefine_array <<< "$vdefine"
148156

157+
opt_vdefine=""
158+
159+
for index in "${!vdefine_array[@]}"
160+
do
161+
echo "$index ${vdefine_array[index]}"
162+
opt_vdefine+=" -verilog_define "
163+
opt_vdefine+=${vdefine_array[index]}
164+
done
165+
echo "$opt_vdefine"
149166
if [ $expected_memory_usage -gt `get_instance_memory` ]; then
150167

151168
output_message="YOUR INSTANCE has less memory than is necessary for certain builds. This means that your builds will take longer than expected. \nTo change to an instance type with more memory, please check our instance resize guide: http://docs.aws.amazon.com/AWSEC2/latest/UserGuide/ec2-instance-resize.html"
@@ -226,7 +243,7 @@ subsystem_id="0x${id1_version:0:4}";
226243
subsystem_vendor_id="0x${id1_version:4:4}";
227244

228245
# Run vivado
229-
cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $uram_option $notify"
246+
cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $uram_option $notify $opt_vdefine"
230247
if [[ "$foreground" == "0" ]]; then
231248
nohup $cmd > $timestamp.nohup.out 2>&1 &
232249

‎hdk/common/shell_v04261818/build/scripts/check_uram.tcl

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,11 @@
1414
# limitations under the License.
1515

1616
global uramHeight
17+
global CL_MODULE
1718

1819
###Check oreg_b usage for uramHeight==3 and uramHeight==4
1920
set clean 1
21+
if {[string compare $CL_MODULE "cl_uram_example"] == 0} {
2022
if {$uramHeight > 2} {
2123
foreach uram [get_cells -hier -filter {REF_NAME==URAM288 && NAME=~WRAPPER_INST/CL/*} ] {
2224
set oregB [get_property OREG_B $uram]
@@ -83,3 +85,4 @@ if {$uramHeight == 2} {
8385
} else {
8486
error "Error: Variable \'\$uramHeight\' set to unsupported value $uramHeight. Supported values are 2, 3, or 4"
8587
}
88+
}

0 commit comments

Comments
 (0)