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Release candidate for Release V1.4.2 (#426)
* Release candidate for Release V1.4.2 * V1.4.2 release notes & delta updates
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Jenkinsfile

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@@ -21,7 +21,9 @@ properties([parameters([
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booleanParam(name: 'debug_dcp_gen', defaultValue: false, description: 'Only run FDF on cl_hello_world. Overrides test_*.'),
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booleanParam(name: 'debug_fdf_uram', defaultValue: false, description: 'Debug the FDF for cl_uram_example.'),
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booleanParam(name: 'fdf_ddr_comb', defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'),
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booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.')
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booleanParam(name: 'disable_runtime_tests', defaultValue: false, description: 'Option to disable runtime tests.'),
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booleanParam(name: 'use_test_ami', defaultValue: false, description: 'This option asks for the test AMI from Jenkins')
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])])
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//=============================================================================
@@ -144,6 +146,13 @@ def is_public_repo() {
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def get_task_label(Map args=[ : ]) {
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String task_label = args.xilinx_version + '_' + task_label[args.task]
149+
//boolean use_test_ami = params.get('use_test_ami')
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if (params.use_test_ami) {
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echo "Test AMI Requested"
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task_label = task_label + '_test'
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}
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echo "Label Requested: $task_label"
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return task_label
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}

README.md

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@@ -77,7 +77,8 @@ NOTE: For on-premises development, SDx/Vivado must have the correct license and
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# Getting Started
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### New to AWS?
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If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI. These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`).
80+
If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI. These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`). AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US).
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### New to AWS FPGAs and setting up a development environment?
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The developer kit is supported for Linux operating systems only. You have the choice to develop on AWS EC2 using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or on-premises. Within a linux environment, you should execute `git clone https://github.com/aws/aws-fpga.git` to download the latest release to your EC2 Instance or local server. Using a SSH connection, execute `git clone [email protected]:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/).

RELEASE_NOTES.md

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@@ -25,6 +25,9 @@
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* CL to SH 512-bit AXI4 interface
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* 1 DDR controller implemented in the SH (always available)
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* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
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## Release 1.4.2 (See [ERRATA](./ERRATA.md) for unsupported features)
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* Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64
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## Release 1.4.1 (See [ERRATA](./ERRATA.md) for unsupported features)
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* Simulation performance Improvements

hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc

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Original file line numberDiff line numberDiff line change
@@ -61,8 +61,8 @@ resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X2Y
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set_property SNAPPING_MODE ON [get_pblocks pblock_CL_bot]
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set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
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64-
set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
65-
set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
66-
set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
64+
#set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
65+
#set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
66+
#set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
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@@ -1,5 +1,3 @@
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# This contains the CL specific constraints for synthesis at the CL level
2-
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
3-
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
4-
5-
2+
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
3+
set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]

hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

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@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
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set clock_recipe_c [lindex $argv 10]
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set uram_option [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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set VDEFINES [lindex $argv 13]
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##################################################
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## Flow control variables
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##################################################
@@ -104,6 +104,11 @@ puts "All reports and intermediate results will be time stamped with $timestamp"
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set_msg_config -id {Chipscope 16-3} -suppress
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set_msg_config -string {AXI_QUAD_SPI} -suppress
107+
set_msg_config -string {PIPE_CL_SH_AURORA_STAT} -suppress
108+
set_msg_config -string {PIPE_CL_SH_HMC_STAT} -suppress
109+
set_msg_config -string {PIPE_AURORA_CHANNEL_UP} -suppress
110+
set_msg_config -string {PIPE_HMC_IIC} -suppress
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set_msg_config -string {PIPE_SH_CL_AURORA_STAT} -suppress
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# Suppress Warnings
109114
# These are to avoid warning messages that may not be real issues. A developer
@@ -123,7 +128,7 @@ set_msg_config -id {Vivado 12-4739} -suppress
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set_msg_config -id {Vivado 12-5201} -suppress
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set_msg_config -id {DRC CKLD-1} -suppress
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set_msg_config -id {IP_Flow 19-2248} -suppress
126-
set_msg_config -id {Opt 31-155} -suppress
131+
#set_msg_config -id {Opt 31-155} -suppress
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set_msg_config -id {Synth 8-115} -suppress
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set_msg_config -id {Synth 8-3936} -suppress
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set_msg_config -id {Vivado 12-1023} -suppress

hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl

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@@ -16,6 +16,7 @@
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#Param needed to avoid clock name collisions
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set_param sta.enableAutoGenClkNamePersistence 0
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set CL_MODULE $CL_MODULE
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set VDEFINES $VDEFINES
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create_project -in_memory -part [DEVICE_TYPE] -force
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update_compile_order -fileset sources_1
117118
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
118-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
119+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
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120121
set failval [catch {exec grep "FAIL" failfast.csv}]
121122
if { $failval==0 } {

hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv

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@@ -150,7 +150,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in
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.m_axi_rready (sh_cl_dma_pcis_q.rready)
151151
);
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//-----------------------------------------------------
154+
//TIE-OFF unused signals to prevent critical warnings
155+
//-----------------------------------------------------
156+
assign sh_cl_dma_pcis_q.rid[15:6] = 10'b0 ;
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assign sh_cl_dma_pcis_q.bid[15:6] = 10'b0 ;
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//----------------------------
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// axi interconnect for DDR address decodes
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//----------------------------

hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

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Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ set clock_recipe_b [lindex $argv 9]
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set clock_recipe_c [lindex $argv 10]
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set uram_option [lindex $argv 11]
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set notify_via_sns [lindex $argv 12]
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set VDEFINES [lindex $argv 13]
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##################################################
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## Flow control variables
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##################################################
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set_msg_config -id {Synth 8-350} -suppress
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set_msg_config -id {Synth 8-3848} -suppress
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set_msg_config -id {Synth 8-3917} -suppress
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set_msg_config -id {Opt 31-430} -suppress
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
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@@ -247,6 +248,7 @@ if {$implement} {
247248
########################
248249
# CL Optimize
249250
########################
251+
set place_preHookTcl ""
250252
if {$opt} {
251253
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
252254
impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl

hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl

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@@ -16,6 +16,7 @@
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#Param needed to avoid clock name collisions
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set_param sta.enableAutoGenClkNamePersistence 0
1818
set CL_MODULE $CL_MODULE
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set VDEFINES $VDEFINES
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2021
create_project -in_memory -part [DEVICE_TYPE] -force
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@@ -106,7 +107,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
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update_compile_order -fileset sources_1
108109
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
109-
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
110+
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
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111112
set failval [catch {exec grep "FAIL" failfast.csv}]
112113
if { $failval==0 } {

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