Release v1.3.1

Author: kristopk

README.md

@@ -43,13 +43,13 @@ The [HDK directory](./hdk) contains useful information and scripts for developer
 The Vivado HLx allows users to use Vivado in project mode to create designs or import designs using RTL or IP Integrator flows.
 The below documentation covers the setup, tutorials of RTL/IP Integrator flows and FAQ.  Users are recommended to read all documents before starting any design.
 
-[HLx Setup README](./hdk/docs/AWS_IP_Vivado_Setup.md)
+[HLx Setup README](./hdk/docs/IPI_GUI_Vivado_Setup.md)
 
-[HLx Flows](./hdk/docs/AWS_Vivado_Flows.md)
+[HLx Flows](./hdk/docs/IPI_GUI_Flows.md)
 
-[HLx Tutorials/Examples](./hdk/docs/AWS_Tutorials_Examples.md)
+[HLx Tutorials/Examples](./hdk/docs/IPI_GUI_Examples.md)
 
-[HLx FAQ](./hdk/docs/AWS_Vivado_FAQ.md)
+[HLx FAQ](./hdk/docs/IPI_GUI_Vivado_FAQ.md)
 
 <a name="fpgasdk"></a>
 ## FPGA SDK

RELEASE_NOTES.md

@@ -9,7 +9,7 @@
          *    Four DDR4 RDIMM interfaces (with ECC)
          *    AXI4 protocol support on all interfaces
    *    User-defined clock frequency driving all CL to Shell interfaces
-   *	Multiple free running auxilary clocks
+   *	Multiple free running auxiliary clocks
    *    PCIE endpoint presentation to Custom Logic(CL)
          *    Management PF (physical function)
          *    Application PF
@@ -26,17 +26,24 @@
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+## Release 1.3.1 (See [ERRATA](./ERRATA.md) for unsupported features)
+   *    EDMA Driver release 1.0.29 - MSI-X fixes
+   *    Improved IPI documentation
+   *    Documentation updates
+   *    Build flow fixes
+   *    Public LTX files for use with hdk examples AFIs 
+
 ## Release 1.3.0 (See [ERRATA](./ERRATA.md) for unsupported features)
    *    FPGA initiated read/write over PCI (PCI-M)
    *    Redesigned Shell - improved the shell design to allow more complex place and route designs to meet timing
    *    Expanded DMA support
    *    Improved URAM utilization
    *    Improved AXI Interface checking
    *    New customer examples/workflows:  IP Integrator, VHDL and GUI
-   *    SDAccel support - More details will be communicated on AWS forum
+   *    SDAccel preview is accepting developers - See [README](sdk/SDAccel/README.md) registration  
 
 
-**During July, All AFIs created with previous HDK versions will no longer correctly load on an F1 instance**, hence a `fpga-load-local-image` command executed with an AFI created prior to 1.3.0 will return an error and not load.  Watch the forum for additional annnoucements.
+**During July, All AFIs created with previous HDK versions will no longer correctly load on an F1 instance**, hence a `fpga-load-local-image` command executed with an AFI created prior to 1.3.0 will return an error and not load.  Watch the forum for additional announcements.
 
 ## Release 1.3.0 New Features Details
 
@@ -54,18 +61,18 @@ The following major features are included in this HDK release:
 * The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4 
 * DMA usage is covered in the new [CL_DRAM_DMA example](./hdk/cl/examples/cl_dram_dma) RTL verification/simulation and Software 
 * A corresponding AWS Elastic DMA ([EDMA](./sdk/linux_kernel_drivers/edma)) driver is provided.
-* [EDMA Installation Readme](./sdk/linux_kernel_drivers/edma/edma_install.md) provides installation and usage guidlines
+* [EDMA Installation Readme](./sdk/linux_kernel_drivers/edma/edma_install.md) provides installation and usage guidelines
 * See [Kernel_Drivers_README](./sdk/linux_kernel_drivers/README.md) for more information on restrictions for this release
 
 
 ### 3.	PCI-M
 * The PCI-M interface is fully supported for CL generated transactions to the Shell. 
 
 ### 4.	URAM 
-* Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized.  See documnetation on enabling URAM utilization: [URAM_options](./hdk/docs/URAM_Options.md)
+* Restrictions on URAM have been updated to enable 100% of the URAM with a CL to be utilized.  See documentation on enabling URAM utilization: [URAM_options](./hdk/docs/URAM_Options.md)
 
 ### 5.	IPI
-* IPI developer flow is supported
+* IPI developer flow is supported.  See [IPI and GUI flow documentation](./hdk/docs/IPI_GUI_Flows.md)
 
 ### 6.	Build Flow improvments
 * See [Build_Scripts](./hdk/common/shell_v071417d3/build/scripts)

hdk/README.md

@@ -91,10 +91,10 @@ This [checklist](./cl/CHECKLIST_BEFORE_BUILDING_CL.md) should be consulted befor
 The Vivado HLx allows users to use Vivado in project mode to create designs or importing designs using RTL or IP Integrator flows.
 The below documentation covers the setup, tutorials of RTL/IP Integrator flows and FAQ.  Users are recommended to read all documents before starting any design.
 
-[HLx Setup README](./docs/AWS_IP_Vivado_Setup.md)
+[HLx Setup README](./docs/IPI_GUI_Vivado_Setup.md)
 
-[HLx Flows](./docs/AWS_Vivado_Flows.md)
+[HLx Flows](./docs/IPI_GUI_Flows.md)
 
-[HLx Tutorials/Examples](./docs/AWS_Tutorials_Examples.md)
+[HLx Tutorials/Examples](./docs/IPI_GUI_Examples.md)
 
-[HLx FAQ](./docs/AWS_Vivado_FAQ.md)
+[HLx FAQ](./docs/IPI_GUI_Vivado_FAQ.md)

hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings

@@ -1 +1 @@
-152
+0

hdk/cl/examples/cl_dram_dma/build/scripts/.warnings

@@ -1 +1 @@
-220
+0

hdk/cl/examples/cl_dram_dma_hlx/README.md

@@ -9,36 +9,45 @@
 <a name="overview"></a>
 ## Overview
 
-For more information about the cl_dram_dma example, read the following information[CL DRAM DMA CL Example](./../cl_dram_dma/README.md)
+For more information about the cl\_dram\_dma example, read the following information [CL DRAM DMA CL Example](./../cl_dram_dma/README.md)
 
+At this time On-Premise flow is recommended with this environment.
+
+Make sure the [HLx Setup Instructions](../../../docs/AWS_IP_Vivado_Setup.md) are followed and executed.
 
 <a name="hlx"></a>
 ## HLx Flow for CL Example
 
-### Add in the following system variables for clock recipes and IDs for cl_dram_dma example.
+### Add in the following system variables for clock recipes and IDs for cl\_dram\_dma example.
 
-export CLOCK_A_RECIPE=0
+export CLOCK\_A\_RECIPE=0
 
-export CLOCK_B_RECIPE=0
+export CLOCK\_B\_RECIPE=0
 
-export CLOCK_C_RECIPE=0
+export CLOCK\_C\_RECIPE=0
 
-export device_id=0xF001
+export device\_id=0xF001
 
-export vendor_id=0x1D0F
+export vendor\_id=0x1D0F
 
-export subsystem_id=0x1D51
+export subsystem\_id=0x1D51
 
-export subsystem_vendor_id=0xFEDC 
+export subsystem\_vendor\_id=0xFEDC 
 
 
 ### Creating Example Design
 
-Invoke vivado in the cl/examples/cl_dram_dma_hlx directory.
+Change directories to the cl/examples/cl\_dram\_dma\_hlx directory.
+
+Invoke vivado by typing vivado in the console.
+
+In the TCL console type in the following to create the cl\_dram\_dma example.  The example will be generated in cl/examples/cl\_dram\_dma\_hlx/example_projects.  The vivado project is examples\_projects/cl\_dram\_dma.xpr.
 
-In the TCL console type in the following to create the cl_dram_dma example.  The example will be generated in cl/examples/cl_dram_dma_hlx/example_projects.  The vivado project is examples_projects/cl_dram_dma.xpr.
+aws::make\_rtl -examples cl\_dram\_dma
 
-aws::make_rtl -examples cl_dram_dma
+Note when closing and opening the project in the future, the following TCL command must be run when the project first opens or an error could show up in simulation/implementation flow.
+
+aws::make\_rtl
 
 ### Simulation
 Click on Simulation->Run Simulation->Run Behavioral Simulation
@@ -51,20 +60,31 @@ run -all
 
 ### Changing Simulation Sources for Tests
 
-cl_dram_dma has several simulation sources that can be used for simulation (test_ddr, test_dram_dma, test_int, test_peek_poke, test_peek_poke_pcis_axsize).  
+cl\_dram\_dma has several simulation sources that can be used for simulation (test\_ddr, test\_dram\_dma, test\_int, test\_peek\_poke, test\_peek\_poke\_pcis\_axsize).  
 
-By default the test_dram_dma is used in the project.  To switch tests, right click on SIMULATION in the Project Manager and select Simulation Settings…
+By default the test\_dram\_dma is used in the project.  To switch tests, right click on SIMULATION in the Project Manager and select Simulation Settings…
 
 For Verilog options select the … box and change the following name.  Below is an example.
 
-TEST_NAME=test_ddr
+TEST\_NAME=test\_ddr
 
 Click OK, Click Apply, Click OK to back into the Vivado project.
 
 ### Implementing the Design/Tar file
 
-In the Design Runs tab, right click on impl_1 and select Launch Runs… . Click OK in the Launch Runs Dialog Box.  Click OK in the Missing Synthesis Results Dialog Box.
+In the Design Runs tab, right click on impl\_1 and select Launch Runs… . Click OK in the Launch Runs Dialog Box.  Click OK in the Missing Synthesis Results Dialog Box.
 
 This will run both synthesis and implementation.
 
-The completed .tar file is located in <project>.runs/faas_1/build/checkpoints/to_aws/<timestamp>.Developer_CL.tar.  For information on how to create a AFI/GAFI with .tar from the design, following to the How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide documentation.
+The completed .tar file is located in example\_projects/cl\_dram\_dma.runs/faas\_1/build/checkpoints/to\_aws/<timestamp>.Developer\_CL.tar.  For information on how to create a AFI/GAFI with .tar from the design, following to the How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide documentation.
+
+### CL Example Software
+
+The runtime software must be complied for the AFI to run on F1.  Note the EDMA driver must be installed before running on F1.
+
+Use the software in cl/examples/cl\_dram\_dma
+
+    $ cd cl/cl_dram_dma/software/runtime/
+    $ make all
+    $ sudo ./test_dram_dma
+

hdk/cl/examples/cl_hello_world/build/scripts/.warnings

@@ -1 +1 @@
-1
+0

hdk/cl/examples/cl_hello_world_hlx/README.md

@@ -9,35 +9,45 @@
 <a name="overview"></a>
 ## Overview
 
-For more information about the hello_world example, read the following information[Hello World CL Example](./../cl_hello_world/README.md)
+For more information about the hello\_world example, read the following information [Hello World CL Example](./../cl_hello_world/README.md)
 
+At this time On-Premise flow is recommended with this environment.
+
+Make sure the [HLx Setup Instructions](../../../docs/AWS_IP_Vivado_Setup.md) are followed and executed.
 
 <a name="hlx"></a>
 ## HLx Flow for CL Example
 
-### Add in the following system variables for clock recipes and IDs for cl_hello_world example.
+### Add in the following system variables for clock recipes and IDs for cl\_hello\_world example.
 
-export CLOCK_A_RECIPE=0
+export CLOCK\_A\_RECIPE=0
 
-export CLOCK_B_RECIPE=0
+export CLOCK\_B\_RECIPE=0
 
-export CLOCK_C_RECIPE=0
+export CLOCK\_C\_RECIPE=0
 
-export device_id=0xF000
+export device\_id=0xF000
 
-export vendor_id=0x0001
+export vendor\_id=0x1D0F
 
-export subsystem_id=0x1D51
+export subsystem\_id=0x1D51
 
-export subsystem_vendor_id=0xFEDD
+export subsystem\_vendor\_id=0xFEDD
 
 ### Creating Example Design
 
-Invoke vivado in the cl/examples/cl_hello_world_hlx directory.
+Change directories to the cl/examples/cl\_hello\_world\_hlx directory.
+
+Invoke vivado by typing vivado in the console.
+
+In the TCL console type in the following to create the cl\_hello\_world example.  The example will be generated in cl/examples/cl\_hello\_world\_hlx/example\_projects.  The vivado project is examples\_projects/cl\_hello\_world.xpr.
 
-In the TCL console type in the following to create the cl_hello_world example.  The example will be generated in cl/examples/cl_hello_world_hlx/example_projects.  The vivado project is examples_projects/cl_hello_world.xpr.
+aws::make\_rtl -examples cl\_hello\_world
+
+Note when closing and opening the project in the future, the following command must be run or error could show up in simulation/implementation.
+
+aws::make\_rtl
 
-aws::make_rtl -examples cl_hello_world
 
 ### Simulation
 
@@ -51,9 +61,21 @@ run -all
 
 ### Implementing the Design/Tar file
 
-In the Design Runs tab, right click on impl_1 and select Launch Runs… . Click OK in the Launch Runs Dialog Box.  Click OK in the Missing Synthesis Results Dialog Box.
+In the Design Runs tab, right click on impl\_1 and select Launch Runs… . Click OK in the Launch Runs Dialog Box.  Click OK in the Missing Synthesis Results Dialog Box.
 
 This will run both synthesis and implementation.
 
-The completed .tar file is located in <project>.runs/faas_1/build/checkpoints/to_aws/<timestamp>.Developer_CL.tar.  For information on how to create a AFI/GAFI with .tar from the design, following to the How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide documentation.
+The completed .tar file is located in example\_projects/cl\_hello\_world.runs/faas\_1/build/checkpoints/to\_aws/<timestamp>.Developer\_CL.tar.  For information on how to create a AFI/GAFI with .tar from the design, following to the How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide documentation.
+
+### CL Example Software
+
+The runtime software must be complied for the AFI to run on F1.
+
+Use the software in cl/examples/cl\_hello\_world
+
+    $ cd cl/cl_hello_world/software/runtime/
+    $ make all
+    $ sudo ./test_hello_world
+
+
 

hdk/cl/examples/cl_hello_world_ref_hlx/README.md

@@ -0,0 +1,75 @@
+# cl\_hello\_world\_ref HLx
+
+## Table of Contents
+
+1. [Overview](#overview)
+2. [HLx Flow for CL Example](#hlx)
+
+
+<a name="overview"></a>
+## Overview
+
+The cl\_hello\_world\_ref example demonstrates basic Shell-to-CL connectivity, memory-mapped register instantiations and the use of the Virtual LED and DIP switches. The cl\_hello\_world\_ref example implements two registers in the FPGA AppPF BAR0 memory space connected to the OCL AXI-L interface. The two registers are:
+
+1. Hello World Register (offset 0x500)
+
+2. Virtual LED Register (offset 0x504)
+
+The logic for the original cl\_hello\_world example from github is contained in one RTL module (hello\_world.v).  In hello\_world.v, the top level ports are for AXI4Lite interface, clock/reset and ports for VLED and VDIP which allows for IP packaging of the design and reuse with other flows/AXI4Lite Master interfaces.  Note VIO logic is not included with this example from the original cl\_hello\_world example.
+
+At this time On-Premise flow is recommended with this environment.
+
+Make sure the [HLx Setup Instructions](../../../docs/AWS_IP_Vivado_Setup.md) are followed and executed.
+
+
+<a name="hlx"></a>
+## HLx Flow for CL Example
+
+
+### Creating Example Design
+Change directories to the cl/examples/cl\_hello\_world\_ref\_hlx directory.
+
+Invoke vivado by typing vivado in the console.
+
+In the TCL console type in the following to create the cl\_hello\_world\_ref\_hlx example.  The example will be generated in cl/examples/cl\_hello\_world\_ref\_hlx/example\_projects.  The vivado project is examples\_projects/cl\_hello\_world\_ref.xpr.
+
+aws::make\_ipi -examples cl\_hello\_world\_ref
+
+Note when closing and opening the project in the future, the following TCL command must be run when the project first opens or an error could show up in simulation/implementation flow.
+
+aws::make\_ipi
+
+Click Refresh Changed Modules on the top of Block Design.
+
+Once the Block diagram is open, review the different IP blocks especially the settings in the AWS IP.
+
+The hello\_world RTL is added to the BD and the instance name is hello\_world\_0. The hello\_world.v source is moved in the Sources tab after validating the design under the cl\_hello\_world\_0\_0 IP source.
+
+### Simulation
+
+The simulation settings are already configured. However, the following step is necessary.
+
+Add signals needed in the simulation.
+
+Type in the following in the TCL console.  Note if Critical Warnings appear click OK and that the following command needs to ran two times.  This is a known issue and will be addressed in later versions of the design.
+
+run -all
+
+
+### Implementing the Design/Tar file
+
+In the Design Runs tab, right click on impl\_1 and select Launch Runs… . Click OK in the Launch Runs Dialog Box.  Click OK in the Missing Synthesis Results Dialog Box.
+
+This will run both synthesis and implementation.
+
+The completed .tar file is located in example\_project/cl\_hello\_world\_ref.runs/faas\_1/build/checkpoints/to\_aws/<timestamp>.Developer\_CL.tar.  For information on how to create a AFI/GAFI with .tar from the design, following to the How To Create an Amazon FPGA Image (AFI) From One of The CL Examples: Step-by-Step Guide documentation.
+
+### CL Example Software
+
+The runtime software must be complied for the AFI to run on F1.
+
+Use the software in cl/examples/cl\_hello\_world
+
+    $ cd cl/cl_hello_world/software/runtime/
+    $ make all
+    $ sudo ./test_hello_world

hdk/cl/examples/cl_hello_world_vhdl/build/scripts/.critical_warnings

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hdk/cl/examples/cl_hello_world_vhdl/build/scripts/.warnings

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-1
+2