Release 1.2.1

Author: kristopk

.gitignore

@@ -52,3 +52,9 @@ hdk/common/verif/models/.vivado_version
 vivado_pid*.str
 vivado*.jou
 vivado*.log
+
+# Pycharm projects
+.idea/
+
+# Python compiled code
+*.pyc

RELEASE_NOTES.md

@@ -26,6 +26,12 @@
          *     1 DDR controller implemented in the SH (always available)
          *     3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
+# Release 1.2.1
+   *    Updated CL example build scripts with Prohibit URAM sites 
+   *    EDMA Performance improvments 
+   *    Expanded EC2 Instance type support
+   *    CL Examples @250Mhz (Clock recipe A1)
+   *    Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
 
 # Release 1.2.0
 

hdk/cl/examples/README.md

@@ -46,11 +46,18 @@ If you like to start your own CL, check out the [How to create your own CL](../d
 
 Executing the `aws_build_dcp_from_cl.sh` script will perform the entire implementation process converting the CL design into a completed Design Checkpoint that meets timing and placement constrains of the target FPGA.
 The output is a tarball file comprising the DCP file, and other log/manifest files, formatted as `YY_MM_DD-hhmm.Developer_CL.tar`.
-This file would be submitted to AWS to create an AFI.
+This file would be submitted to AWS to create an AFI. By default the build script will use Clock Group A Recipe A0 wich uses a main clock of 125 MHz.
 
     $ cd $CL_DIR/build/scripts
     $ ./aws_build_dcp_from_cl.sh
 
+In order to use a 250 MHz main clock the developer can specify the A1 Clock Group A Recipe as in the following example:
+
+    $ cd $CL_DIR/build/scripts
+    $ ./aws_build_dcp_from_cl.sh -clock_recipe_a A1
+
+Other clock recipes can be specified as well. More details on the [Clock Group Recipes Table](../../docs/clock_recipes.csv) and how to specify different recipes can be found in the following [README](../../common/shell_v04151701/new_cl_template/build/README.md).
+
 **NOTE**: *The DCP generation can take up to several hours to complete, hence the `aws_build_dcp_from_cl.sh` will run the main build process (`vivado`) in within a  `nohup` context: This will allow the build to continue running even if the SSH session is terminated half way through the run*
 
 To be notified via e-mail when the build completes:

hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc

@@ -38,14 +38,17 @@ add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical
 add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_cores.DDR4_2*}]
 add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_inst[2].*}]
 add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/SH_DDR/ddr_stat[2].*}]
-add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}]
+#add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ CL/CL_PCIM_MSTR/CL_TST_PCI}]
 add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells [list CL/CL_DMA_PCIS_SLV/PCI_AXL_REG_SLC CL/CL_PCIM_MSTR/PCI_AXI4_REG_SLC CL/CL_OCL_SLV/AXIL_OCL_REG_SLC CL/CL_SDA_SLV/AXIL_SDA_REG_SLC]]
 add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -hierarchical -filter { NAME =~  "*CL/CL_OCL_SLV/slv_tst_wdata_reg[*][*]*" && PRIMITIVE_TYPE =~ REGISTER.*.* }]
 resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
 set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
 
-set_clock_groups -name cl_main_a0_tck -asynchronous -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] -group [get_clocks tck]
+#set_clock_groups -name cl_main_a0_tck -asynchronous -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]] -group [get_clocks tck]
 
+set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
 
 
 

hdk/cl/examples/cl_dram_dma/build/constraints/cl_synth_user.xdc

@@ -1,3 +1,5 @@
 # This contains the CL specific constraints for synthesis at the CL level
+set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
+set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
 
 

hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings

@@ -0,0 +1 @@
+220

hdk/cl/examples/cl_dram_dma/build/scripts/.warnings

@@ -0,0 +1 @@
+220

hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

@@ -32,8 +32,7 @@ set subsystem_vendor_id [lindex $argv  7]
 set clock_recipe_a      [lindex $argv  8]
 set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
-set run_aws_emulation   [lindex $argv 11]
-set notify_via_sns      [lindex $argv 12]
+set notify_via_sns      [lindex $argv 11]
 
 ##################################################
 ### Implementation step options 
@@ -85,7 +84,6 @@ puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
 puts "Clock Recipe A:         $clock_recipe_a";
 puts "Clock Recipe B:         $clock_recipe_b";
 puts "Clock Recipe C:         $clock_recipe_c";
-puts "Run AWS Emulation:      $run_aws_emulation";
 puts "Notify when done:       $notify_via_sns";
 
 #checking if CL_DIR env variable exists
@@ -438,6 +436,11 @@ foreach uramSite $uramSites {
 ########################
 puts "AWS FPGA: Place design stage";
 
+# Constraints for TCK<->Main Clock
+set_clock_groups -name tck_clk_main_a0 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+set_clock_groups -name tck_drck -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+set_clock_groups -name tck_userclk -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
+
 switch $strategy {
     "BASIC" {
         puts "BASIC strategy."
@@ -580,17 +583,6 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing final DCP to
 write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
 close_project
 
-# ################################################
-# Emulate AWS Bitstream Generation
-# ################################################
-
-# Only run AWS emulation step if explicitly specified.
-
-if {[string compare $run_aws_emulation "1"] == 0} {
-  puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_dcp_verify.tcl to emulate AWS bitstream generation for checking the DCP.";
-  source $HDK_SHELL_DIR/build/scripts/aws_dcp_verify.tcl
-}
-
 # ################################################
 # Create Manifest and Tarball for delivery
 # ################################################

hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh

@@ -27,5 +27,8 @@
 //uncomment below to make SH and CL async
 `define SH_CL_ASYNC
 
+// Uncomment to disable Chipscope
+//`define DISABLE_CHIPSCOPE_DEBUG
+
 `endif
 

hdk/cl/examples/cl_dram_dma/software/runtime/test_dram_dma.c

@@ -63,7 +63,7 @@ int main(int argc, char **argv) {
     fail_on(rc, out, "Interrupt example failed");
 
 out:
-    return 1;
+    return rc;
 }
 
 static int

hdk/cl/examples/cl_hello_world/build/constraints/cl_pnr_user.xdc

@@ -3,3 +3,8 @@
 # False path between vled on CL clock and Shell asynchronous clock
 set_false_path -from [get_cells CL/vled_q_reg*] 
 
+# False paths between main clock and tck
+set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
+

hdk/cl/examples/cl_hello_world/build/scripts/.critical_warnings

@@ -0,0 +1 @@
+0

hdk/cl/examples/cl_hello_world/build/scripts/.warnings

@@ -0,0 +1 @@
+1

hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

@@ -31,8 +31,7 @@ set subsystem_vendor_id [lindex $argv  7]
 set clock_recipe_a      [lindex $argv  8]
 set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
-set run_aws_emulation   [lindex $argv 11]
-set notify_via_sns      [lindex $argv 12]
+set notify_via_sns      [lindex $argv 11]
 
 #################################################
 ## Generate CL_routed.dcp (Done by User)
@@ -50,7 +49,6 @@ puts "PCI Subsystem Vendor ID $subsystem_vendor_id";
 puts "Clock Recipe A:         $clock_recipe_a";
 puts "Clock Recipe B:         $clock_recipe_b";
 puts "Clock Recipe C:         $clock_recipe_c";
-puts "Run AWS Emulation:      $run_aws_emulation";
 puts "Notify when done:       $notify_via_sns";
 
 #checking if CL_DIR env variable exists
@@ -480,17 +478,6 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing final DCP to
 write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
 close_project
 
-# ################################################
-# Emulate AWS Bitstream Generation
-# ################################################
-
-# Only run AWS emulation step if explicitly specified.
-
-if {[string compare $run_aws_emulation "1"] == 0} {
-  puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_dcp_verify.tcl to emulate AWS bitstream generation for checking the DCP.";
-  source $HDK_SHELL_DIR/build/scripts/aws_dcp_verify.tcl
-}
-
 # ################################################
 # Create Manifest and Tarball for delivery
 # ################################################

hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh

@@ -23,4 +23,7 @@
 // FPGA flop init capability).  This will help with routing resources.
 `define FPGA_LESS_RST
 
+// Uncomment to disable Chipscope
+//`define DISABLE_CHIPSCOPE_DEBUG
+
 `endif

hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh

@@ -18,7 +18,7 @@
 # Usage help
 function usage
 {
-    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-run_aws_emulation] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
+    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify] | [-h] | [-H] | [-help] |  ]"
     echo " "
     echo "By default the build is run in the background using nohup so that the"
     echo "process will not be terminated if the terminal window is closed."
@@ -40,7 +40,6 @@ clock_recipe_b=B0
 clock_recipe_c=C0
 vivado_script="create_dcp_from_cl.tcl"
 foreground=0
-run_aws_emulation=0
 notify=0
 ignore_memory_requirement=0
 expected_memory_usage=30000000
@@ -87,8 +86,6 @@ while [ "$1" != "" ]; do
         -clock_recipe_c )       shift
                                 clock_recipe_c=$1
                                 ;;
-        -run_aws_emulation )    run_aws_emulation=1
-                                ;;
         -foreground )           foreground=1
                                 ;;
         -notify )               notify=1
@@ -192,8 +189,9 @@ then
 fi
 
 # Use timestamp for logs and output files
-timestamp=$(date +"%y_%m_%d-%H%M%S")
+timestamp=$(date +"%y_%m_%d-%H%M%S") 
 logname=$timestamp.vivado.log
+ln -s -f $logname last_log
 
 info_msg "Environment variables and directories are present. Checking for Vivado installation."
 
@@ -217,7 +215,7 @@ subsystem_id="0x${id1_version:0:4}";
 subsystem_vendor_id="0x${id1_version:4:4}";
 
 # Run vivado
-cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $run_aws_emulation $notify"
+cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $notify"
 if [[ "$foreground" == "0" ]]; then
   nohup $cmd > $timestamp.nohup.out 2>&1 &
 

hdk/common/shell_v04151701/new_cl_template/build/README.md

@@ -6,7 +6,7 @@
 2. [Build procedure step by step](#stepbystep)
 3. [Build strategies and parallel builds](#strategies)
 4. [About Encrption during build process](#buildencryption)
-5. [Advanced Notes](#buildadvanced notes)
+5. [Advanced Notes](#buildadvanced_notes)
 6. [Build Frequently Asked Questions](#buildfaq)
 
 
@@ -23,7 +23,7 @@ AWS also provides an out-of-the-box generic script called `aws_build_dcp_from_cl
 
 AWS provides multiple options to generate a DCP that meets placement and timing constraints. The `aws_build_dcp_from_cl.sh` provides multiple choices for implementation strategies, invoked by the `-strategy` option. For more details refer to [Build Strategies](#strategies) below or call `aws_build_dcp_from_cl.sh -help` for the list of supported capabilities.
 
-Advanced developers can use different scripts, tools, and techniques (e.g., regioning),  with the  condition that they submit both the `manifest.txt` and "encrypted placed-and-routed design checkpoint (DCP)" in a single tar file that passes final checks. In order to reduce build time the AWS emulation step that performs these checks is disabled during the build process. In order to enable the check, a developer can set the `run_aws_emulation` argument when calling `aws_build_dcp_from_cl.sh`.
+Advanced developers can use different scripts, tools, and techniques (e.g., regioning), with the condition that they submit both the `manifest.txt` and "encrypted placed-and-routed design checkpoint (DCP)" in a single tar file that passes final checks.
 
 <a name="stepbystep"></a>
 ## Build Procedure 
@@ -65,7 +65,7 @@ In order to help developers close timing goals and successfully build their desi
 
 Build script usage:
 
-    $ ./aws_build_dcp_from_cl.sh  [-h | -H | -help] [-script <vivado_script>] [-strategy <BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION>] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-run_aws_emulation] [-foreground] [-notify]
+    $ ./aws_build_dcp_from_cl.sh  [-h | -H | -help] [-script <vivado_script>] [-strategy <BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION>] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify]
 
 Options:
 
@@ -87,9 +87,6 @@ Options:
 * -clock_recipe_c \<C0 ... Cn>
        * Use the Clock Group C clock frequencies defined for the specified Clock Group C recipe. This is an optional argument and the default value will be C0. Refer to the [Clock Group Recipes Table](./../../../../docs/clock_recipes.csv).
 
-* -run_aws_emulation
-       * Run the AWS emulation step to verify your generated DCP. The step emulates what AWS will do to generate a bitstream from the developer DCP.
-
 * -foreground
        * Run the build in the foreground such that all output will go to the terminal and the build may be terminated if the terminal is closed. This option is useful if you want to wait for the build to complete. This option is safe if the terminal is running on the AWS instance, for example on a GUI desktop on the instance.
 
@@ -155,7 +152,7 @@ If you are running on one of the EC2 compute instances with 31GiB DRAM or more,
 
 Developer RTL is encrypted using IEEE 1735 V2 encryption.  This level of encryption protects both the raw source files and the implemented design.  
 
-<a name="buildadvanced notes"></a>
+<a name="buildadvanced_notes"></a>
 ## Advanced Notes 
 
 * The included implementation flow is a baseline flow.  It is possible to add advanced commands/constraints (e.g, rejoining) to the flow.
@@ -168,9 +165,6 @@ Developer RTL is encrypted using IEEE 1735 V2 encryption.  This level of encrypt
 **Q: What are the different files that a developer needs to provide to AWS?**
 The developer should submit a tar file that contains the placed-and-routed DCP along with the required manifest.txt file.
 
-**Q: How do I ensure that the DCP I create will generate a good bistream at AWS?**
-The developer can enable the AWS emulation step by setting the `run_aws_emulation` argument when calling `aws_build_dcp_from_cl.sh`.
-
 **Q: What should I do my design is not meeting timing?**
 The developer should evaluate the timing path to identify a solution that may include design changes or additional constraints. Additionally, the developer can try using one of the different build strategies that may help resolve the timing violations.