Skip to content

Commit dd56025

Browse files
kristopkkristopk
committed
Changes to support release 1.2.2
1 parent 10222be commit dd56025

25 files changed

+205
-57
lines changed

‎FAQs.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ We encourage you to use the [AWS FPGA Developer Forum](https://forums.aws.amazon
204204

205205
The required AWS software is the [FPGA Management Tool set](./sdk/userspace/fpga_mgmt_tools). This software manages loading and clearing AFIs for the instance FPGAs. It also allows developers to retrieve FPGAs status from within the instance. Users will need to load the F1 AMI with the drivers and runtime libraries needed for their FPGA application.
206206

207-
Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope.
207+
Typically, you will not need the HDK nor any Xilinx Vivado tools on an F1 instance that is using prebuilt AFIs; unless, you want to do in-field debug using Vivado's ChipScope (Virtual JTAG).
208208

209209

210210
## Marketplace
@@ -235,7 +235,7 @@ There are two types of interfaces from the instance host CPU to the FPGAs:
235235

236236
The first is the FPGA Image Management Tools. These APIs are detailed in the [SDK portion](./sdk/userspace/fpga_mgmt_tools) of the GitHub repository. FPGA Image Management Tools include APIs to load, clear, and get status of the FPGA.
237237

238-
The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
238+
The second type of interface is direct address access to the Application PCIe Physical Functions (PF) of the FPGA. There is no API for this access. Rather, there is direct access to resources in the Custom Logic (CL) region or Shell that can be accessed by software written on the instance. For example, the ChipScope software (Virtual JTAG) uses address space in a PF to provide FPGA debug support. Developers can create any API to the resources in their CL. See the [Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md) for more details on the address space mapping as seen from the instance.
239239

240240

241241

@@ -379,7 +379,7 @@ Yes. The HDK includes a simulation model for the AWS shell. See the [HDK common
379379

380380
**Q: What resources within the FPGA does the AWS Shell consume?**
381381

382-
The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
382+
The Shell consumes about 20% of the FPGA resources, and that includes the PCIe Gen3 X16, DMA engine, DRAM controller interface, ChipScope (Virtual JTAG) and other health monitoring and image loading logic. No modifications to the Shell or the partition pins between the Shell and the Custom Logic are possible by the FPGA developer.
383383

384384

385385

‎RELEASE_NOTES.md

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,12 +26,17 @@
2626
* 1 DDR controller implemented in the SH (always available)
2727
* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
2828

29+
# Release 1.2.1
30+
* Expanded [clock recipes](./hdk/docs/clock_recipes.csv)
31+
* Virtual JTAG documentation updates
32+
* Included encryption of .sv files for CL examples
33+
2934
# Release 1.2.1
3035
* Updated CL example build scripts with Prohibit URAM sites
3136
* EDMA Performance improvments
3237
* Expanded EC2 Instance type support
3338
* CL Examples @250Mhz (Clock recipe A1)
34-
* Option to exclude chipscope from building CL examples (DISABLE_CHIPSCOPE_DEBUG)
39+
* Option to exclude Chipscope (Virtual JTAG) from building CL examples (DISABLE_VJTAG_DEBUG)
3540

3641
# Release 1.2.0
3742

‎hdk/cl/examples/cl_dram_dma/build/scripts/.critical_warnings

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
152
1+
152

‎hdk/cl/examples/cl_dram_dma/design/cl_dram_dma.sv

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -720,7 +720,7 @@ cl_sda_slv CL_SDA_SLV (
720720
//-----------------------------------------
721721

722722

723-
`ifndef DISABLE_CHIPSCOPE_DEBUG
723+
`ifndef DISABLE_VJTAG_DEBUG
724724

725725
cl_ila CL_ILA (
726726

@@ -751,7 +751,7 @@ cl_vio CL_VIO (
751751
);
752752

753753

754-
`endif // `ifndef DISABLE_CHIPSCOPE_DEBUG
754+
`endif // `ifndef DISABLE_VJTAG_DEBUG
755755

756756
//-----------------------------------------
757757
// Virtual JATG ILA Debug core example

‎hdk/cl/examples/cl_dram_dma/design/cl_dram_dma_defines.vh

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@
2727
//uncomment below to make SH and CL async
2828
`define SH_CL_ASYNC
2929

30-
// Uncomment to disable Chipscope
31-
//`define DISABLE_CHIPSCOPE_DEBUG
30+
// Uncomment to disable Virtual JTAG
31+
//`define DISABLE_VJTAG_DEBUG
3232

3333
`endif
3434

‎hdk/cl/examples/cl_dram_dma/verif/scripts/top.questa.f

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
${SH_LIB_DIR}/bram_2rw.sv
5050
${SH_LIB_DIR}/flop_fifo.sv
5151

52-
+define+DISABLE_CHIPSCOPE_DEBUG
52+
+define+DISABLE_VJTAG_DEBUG
5353
${CL_ROOT}/design/axil_slave.sv
5454
${CL_ROOT}/design/cl_dram_dma_defines.vh
5555
${CL_ROOT}/design/cl_tst_scrb.sv

‎hdk/cl/examples/cl_dram_dma/verif/scripts/top.vcs.f

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@
4545
${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
4646
${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
4747

48-
+define+DISABLE_CHIPSCOPE_DEBUG
48+
+define+DISABLE_VJTAG_DEBUG
4949
${CL_ROOT}/design/axil_slave.sv
5050
${CL_ROOT}/design/cl_dram_dma_defines.vh
5151
${CL_ROOT}/design/cl_tst_scrb.sv

‎hdk/cl/examples/cl_dram_dma/verif/scripts/top.vivado.f

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@
4747
${SH_LIB_DIR}/../ip/axi_register_slice/sim/axi_register_slice.v
4848
${SH_LIB_DIR}/../ip/axi_register_slice_light/sim/axi_register_slice_light.v
4949

50-
--define DISABLE_CHIPSCOPE_DEBUG
50+
--define DISABLE_VJTAG_DEBUG
5151
${CL_ROOT}/design/axil_slave.sv
5252
${CL_ROOT}/design/cl_dram_dma_defines.vh
5353
${CL_ROOT}/design/cl_tst_scrb.sv

‎hdk/cl/examples/cl_hello_world/design/cl_hello_world.sv

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -328,9 +328,9 @@ assign pre_cl_sh_status_vled[15:0] = vled_q[15:0] & sh_cl_status_vdip_q2[15:0];
328328
assign cl_sh_status1[31:0] = `CL_VERSION;
329329

330330
//-----------------------------------------------
331-
// Debug bridge, used if need chipscope
331+
// Debug bridge, used if need Virtual JTAG
332332
//-----------------------------------------------
333-
`ifndef DISABLE_CHIPSCOPE_DEBUG
333+
`ifndef DISABLE_VJTAG_DEBUG
334334

335335
// Flop for timing global clock counter
336336
logic[63:0] sh_cl_glcount0_q;
@@ -381,7 +381,7 @@ always_ff @(posedge clk_main_a0)
381381
);
382382

383383
//-----------------------------------------------
384-
// VIO Example - Needs Chipscope
384+
// VIO Example - Needs Virtual JTAG
385385
//-----------------------------------------------
386386
// Counter running at 125MHz
387387

@@ -465,7 +465,7 @@ always_ff @(posedge clk_main_a0)
465465
.probe10 (vo_cnt_watermark_q)
466466
);
467467

468-
`endif // `ifndef DISABLE_CHIPSCOPE_DEBUG
468+
`endif // `ifndef DISABLE_VJTAG_DEBUG
469469

470470
endmodule
471471

‎hdk/cl/examples/cl_hello_world/design/cl_hello_world_defines.vh

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
// FPGA flop init capability). This will help with routing resources.
2424
`define FPGA_LESS_RST
2525

26-
// Uncomment to disable Chipscope
27-
//`define DISABLE_CHIPSCOPE_DEBUG
26+
// Uncomment to disable Virtual JTAG
27+
//`define DISABLE_VJTAG_DEBUG
2828

2929
`endif

‎hdk/common/shell_v04151701/build/scripts/aws_build_dcp_from_cl.sh

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
# Usage help
1919
function usage
2020
{
21-
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1] [-clock_recipe_c C0 | C1] [-foreground] [-notify] | [-h] | [-H] | [-help] | ]"
21+
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-foreground] [-notify] | [-h] | [-H] | [-help] | ]"
2222
echo " "
2323
echo "By default the build is run in the background using nohup so that the"
2424
echo "process will not be terminated if the terminal window is closed."
@@ -123,15 +123,15 @@ fi
123123

124124
# Check that clock_recipe_b is valid
125125
shopt -s extglob
126-
if [[ $clock_recipe_b != @(B0|B1) ]]; then
127-
err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0 and B1."
126+
if [[ $clock_recipe_b != @(B0|B1|B2|B3|B4|B5) ]]; then
127+
err_msg "$clock_recipe_b isn't a valid Clock Group B recipe. Valid Clock Group B recipes are B0, B1, B2, B3, B4, and B5."
128128
exit 1
129129
fi
130130

131131
# Check that clock_recipe_c is valid
132132
shopt -s extglob
133-
if [[ $clock_recipe_c != @(C0|C1) ]]; then
134-
err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0 and C1."
133+
if [[ $clock_recipe_c != @(C0|C1|C2|C3) ]]; then
134+
err_msg "$clock_recipe_c isn't a valid Clock Group C recipe. Valid Clock Group C recipes are C0, C1, C2, and C3."
135135
exit 1
136136
fi
137137

‎hdk/common/shell_v04151701/build/scripts/aws_clock_properties.tcl

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515

1616
# Set Clock Group properties based on specified recipe
1717
# Clock Group A
18+
set_property CLKFBOUT_MULT_F 6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
19+
set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
1820
if {[string compare $clock_recipe_a "A1"] == 0} {
1921
set_property CLKOUT0_DIVIDE_F 6 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
2022
set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
@@ -34,18 +36,56 @@ if {[string compare $clock_recipe_a "A1"] == 0} {
3436

3537
# Clock Group B
3638
if {[string compare $clock_recipe_b "B1"] == 0} {
39+
set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
40+
set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
3741
set_property CLKOUT0_DIVIDE_F 10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
3842
set_property CLKOUT1_DIVIDE 20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
43+
} elseif {[string compare $clock_recipe_b "B2"] == 0} {
44+
set_property CLKFBOUT_MULT_F 18 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
45+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
46+
set_property CLKOUT0_DIVIDE_F 2 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
47+
set_property CLKOUT1_DIVIDE 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
48+
} elseif {[string compare $clock_recipe_b "B3"] == 0} {
49+
set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
50+
set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
51+
set_property CLKOUT0_DIVIDE_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
52+
set_property CLKOUT1_DIVIDE 20 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
53+
} elseif {[string compare $clock_recipe_b "B4"] == 0} {
54+
set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
55+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
56+
set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
57+
set_property CLKOUT1_DIVIDE 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
58+
} elseif {[string compare $clock_recipe_b "B5"] == 0} {
59+
set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
60+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
61+
set_property CLKOUT0_DIVIDE_F 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
62+
set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
3963
} else { #B0
64+
set_property CLKFBOUT_MULT_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
65+
set_property DIVCLK_DIVIDE 1 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4066
set_property CLKOUT0_DIVIDE_F 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4167
set_property CLKOUT1_DIVIDE 10 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk0/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4268
}
4369

4470
# Clock Group C
4571
if {[string compare $clock_recipe_c "C1"] == 0} {
72+
set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
73+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4674
set_property CLKOUT0_DIVIDE_F 8 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4775
set_property CLKOUT1_DIVIDE 6 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
76+
} elseif {[string compare $clock_recipe_c "C2"] == 0} {
77+
set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
78+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
79+
set_property CLKOUT0_DIVIDE_F 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
80+
set_property CLKOUT1_DIVIDE 12 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
81+
} elseif {[string compare $clock_recipe_c "C3"] == 0} {
82+
set_property CLKFBOUT_MULT_F 16 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
83+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
84+
set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
85+
set_property CLKOUT1_DIVIDE 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4886
} else { #C0
87+
set_property CLKFBOUT_MULT_F 24 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
88+
set_property DIVCLK_DIVIDE 5 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
4989
set_property CLKOUT0_DIVIDE_F 4 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
5090
set_property CLKOUT1_DIVIDE 3 [get_cells SH/kernel_clks_i/clkwiz_kernel_clk1/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst]
5191
}

‎hdk/common/shell_v04151701/build/scripts/aws_gen_clk_constraints.tcl

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,30 @@ switch $clock_recipe_b {
6565
set clk_extra_b1_period 16
6666
set clk_extra_b1_half_period 8
6767
}
68+
"B2" {
69+
set clk_extra_b0_period 2.222
70+
set clk_extra_b0_half_period 1.111
71+
set clk_extra_b1_period 4.444
72+
set clk_extra_b1_half_period 2.222
73+
}
74+
"B3" {
75+
set clk_extra_b0_period 4
76+
set clk_extra_b0_half_period 2
77+
set clk_extra_b1_period 16
78+
set clk_extra_b1_half_period 8
79+
}
80+
"B4" {
81+
set clk_extra_b0_period 3.333
82+
set clk_extra_b0_half_period 1.667
83+
set clk_extra_b1_period 13.333
84+
set clk_extra_b1_half_period 6.667
85+
}
86+
"B5" {
87+
set clk_extra_b0_period 2.5
88+
set clk_extra_b0_half_period 1.25
89+
set clk_extra_b1_period 10
90+
set clk_extra_b1_half_period 5
91+
}
6892
default {
6993
puts "$clock_recipe_b is NOT a valid clock_recipe_b."
7094
}
@@ -84,6 +108,18 @@ switch $clock_recipe_c {
84108
set clk_extra_c1_period 5
85109
set clk_extra_c1_half_period 2.5
86110
}
111+
"C2" {
112+
set clk_extra_c0_period 13.333
113+
set clk_extra_c0_half_period 6.667
114+
set clk_extra_c1_period 10
115+
set clk_extra_c1_half_period 5
116+
}
117+
"C3" {
118+
set clk_extra_c0_period 5
119+
set clk_extra_c0_half_period 2.5
120+
set clk_extra_c1_period 3.75
121+
set clk_extra_c1_half_period 1.875
122+
}
87123
default {
88124
puts "$clock_recipe_c is NOT a valid clock_recipe_c."
89125
}

‎hdk/common/shell_v04151701/new_cl_template/build/README.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
1. [Overview of AFI Build process](#buildoverview)
66
2. [Build procedure step by step](#stepbystep)
77
3. [Build strategies and parallel builds](#strategies)
8-
4. [About Encrption during build process](#buildencryption)
8+
4. [About Encryption during build process](#buildencryption)
99
5. [Advanced Notes](#buildadvanced_notes)
1010
6. [Build Frequently Asked Questions](#buildfaq)
1111

@@ -61,7 +61,7 @@ The build script performs:
6161

6262
<a name="strategies"></a>
6363
#### Build Strategies
64-
In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than anothers. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
64+
In order to help developers close timing goals and successfully build their designs efficiently, the build script provides the means to synthesize with different strategies. The different strategies alter the directives used by the synthesis tool. For example, some directives might specify additional optimizations to close timing, while others may specify less effort to minimize synthesis time for designs that can more easily close timing and area goals. Since every design is different, some strategies may provide better results than another build strategies. If a developer has trouble successfully building their design with one strategy it is encouraged that they try a different strategy, or run a few strategies in parallel using the FPGA Developer AMI. The strategies are described in more detail below.
6565

6666
Build script usage:
6767

@@ -96,7 +96,7 @@ Options:
9696
Strategy descriptions:
9797

9898
* BASIC
99-
* This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance betwwen runtime and Quality of Results (QOR).
99+
* This is the basic flow in Vivado and contains the mandatory steps to be able to build a design. It is designed to provide a good balance between runtime and Quality of Results (QOR).
100100

101101
* EXPLORE
102102
* This is a high-effort flow which is designed to give improved QOR results at the expense of runtime.

0 commit comments

Comments
 (0)