👋 Hey,
In the RISC-V backend the clobber save and restore implementation uses a negative SP offset. We should switch it to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to c.ldsp and c.sdsp which allow us to store and load any register into the stack using a positive SP offset.
Using these instruction in the prologue and epilogue would be nice due to the lower instruction footprint.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.
👋 Hey,
In the RISC-V backend the clobber save and restore implementation uses a negative SP offset. We should switch it to always use a positive SP offset.
When the Compressed instruction extension is enabled we have access to
c.ldspandc.sdspwhich allow us to store and load any register into the stack using a positive SP offset.Using these instruction in the prologue and epilogue would be nice due to the lower instruction footprint.
Implementing this as a positive offset has no downsides when the C extension is disabled. So there isn't very much of a downside to this.