Dataflow System Verilog

[NyloxtheBard]

Reference

• This lab was very well written and documented, I was able to follow what was being taught relatively well. The biggest thing that I think would help with this would be to implement a better tutorial for verilog that goes over the different commands and how to run a simulator, as I had to run it through chatgpt to understand what was happening with the base foundational code in each of the simulator. This should be implemented preferably right after the setup with VS code lab reference

This shows some of the things that I think would be good to go over, as it goes through step by step what the verilog simulator is doing
-I had a really hard time understanding the wavedrom and what it was actually showing me, along with what the simulation was generating. It seemed to be very detailed and working properly, just not documentation or step by step instructions showing what each individual thing is would be helpful, such as what is compiled and a breakdown of that for the first simulator
-All of the answers were originally included as well with each of the simulators, which took away the initial ability to experiment and figure out what was happening with the simulator and finding the answer myself, as I believe it was intended.

• Does not seem to generate all of the given simulation values for the Verilator Testbench, as shown below
  Simulation code Photo:
  
  Verilator TestBench Output
  
  As shown, out of the 8 given values, the benchtest only shows 5 of them, which that number tends to vary throughout the different functions, but still doesn't show all of them.

[jamilkhalaf]

• Clear Project Structure: The lab provides a clear and organized structure, separating the setup, individual functions, and the final integration of all functions. This makes it easy to follow and understand the flow of the project.

• Detailed Function Descriptions: Each function is described in detail, specifying the expected behavior when the corresponding button is pressed or not pressed. The expected outputs are clearly outlined, providing a solid foundation for coding and testing.

• Systematic Testing Approach: The lab includes a systematic testing approach with specific test cases for each function. Expected results are provided, allowing for easy verification of the correctness of the implemented functions.

• Helpful Comments and Hints: The lab includes helpful comments and hints, guiding the user through the implementation process. For example, there are hints on how to use intermediate signals and reminders to uncomment specific lines in the XDC file, enhancing clarity and preventing potential errors.