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@@ -34,6 +55,8 @@ LF analog path (MCP6294 opamp. This has a GBW of 10 MHz), all 'slow' signals.
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## FPGA
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Since the SPARTAN II is a old outdated FPGA, thus is very limited resource there was a need to split LF and HF functionality into two separate FPGA images. Which are stored in ARM flash memory as bitstreams.
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We swap between these images by flashing fpga from ARM on the go. It takes about 1sec. Hence its usually a bad idea to program your device to continuously execute LF alt HF commands.
@@ -50,19 +73,22 @@ In order to save space, these fpga images are LZ4 compressed and included in th
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This means we save some precious space on the ARM but its a bit more complex when flashing to fpga since it has to decompress on the fly.
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### FPGA modes.
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### FPGA modes
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- Major modes
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- Minor modes
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## ARM FPGA communications.
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## ARM FPGA communications
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The ARM talks with FPGA over the Synchronous Serial Port (SSC) rx an tx.
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ARM, send a 16bit configuration with fits the select major mode.
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## ARM GPIO setup
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```
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// First configure the GPIOs, and get ourselves a clock.
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```
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## FPGA Setup
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// Set up DMA to receive samples from the FPGA. We will use the PDC, with
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// a single buffer as a circular buffer (so that we just chain back to
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# HARDWARE OVERVIEW
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## ADC (ANALOG TO DIGITAL CONVERTER)
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The analogue signal that comes from the antenna circuit is fed into an 8-bit Analogue to Digital Converter
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(ADC). This delivers 8 output bits in parallel which represent the current voltage retrieved from the field.
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## FIELD PROGRAMMABLE GATE ARRAY, FPGA
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The 8 output pins from the ADC are connected to 8 pins of the Field Programmable Gate Array (FPGA). An
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FPGA has a great advantage over a normal microcontroller in the sense that it emulates hardware. A
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hardware description can be compiled and flashed into an FPGA.
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## MICROCONTROLLER
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The microcontroller is responsible for the protocol management. It receives the digital encoded signals
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from the FPGA and decodes them. The decoded signals can just be copied to a buffer in the EEPROM
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memory. Additionally, an answer to the received message can be send by encoding a reply and
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##
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## To behave like a READER.
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## To behave like a READER
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By driving all of the buffers LOW, it is possible to make the antenna
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look to the receive path like a parallel LC circuit; this provides a
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high-voltage output signal. This is typically what will be done when we
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are not actively transmitting a carrier (i.e., behaving as a reader).
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## To behave like a TAG
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On the receive side, there are two possibilities, which are selected by
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RLY1. A mechanical relay is used, because the signal from the antenna is
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likely to be more positive or negative than the highest or lowest supply
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is the master). The ARM connects to the outside world over USB.
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## To sniff traffic
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## FPGA purpose
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Digital signal processing.
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In short, apply low pass / hi pass filtering, peak detect, correlate signal meaning IQ pair collecting.
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