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capstone-rs: update to work with 3b2984212fe
Update pre-generated bindings and changelog. Various system register enums have been merged into `Arm64SysOp`. Comments out part of test case due to upstream capstone bug: capstone-engine/capstone#1881
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‎CHANGELOG.md

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
88
## [UNRELEASED] - YYYY-MM-DD
99
### Changed
1010
- Bump minimum Rust version to 1.56.0
11+
- `Arm64OperandType::Sys` contains `Arm64SysOp` instead of `u32`
1112

1213
## [0.11.0] - 2022-05-01
1314

@@ -19,8 +20,6 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
1920

2021
### Fixed
2122
- Soundness issue by remove `Insn` `Clone` impl (see "Removed" note above)
22-
- `capstone-sys`: document that minimum supported Rust version is 1.50.0
23-
- `capstone-sys`: suppress C compiler warning
2423

2524
## [0.10.0] - 2021-08-09
2625

‎capstone-rs/src/arch/arm64.rs

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,7 @@ pub use capstone_sys::arm64_pstate as Arm64Pstate;
2020
pub use capstone_sys::arm64_prefetch_op as ArmPrefetchOp;
2121
pub use capstone_sys::arm64_barrier_op as ArmBarrierOp;
2222
pub use capstone_sys::arm64_sysreg as Arm64Sysreg;
23-
pub use capstone_sys::arm64_ic_op as Arm64IcOp;
24-
pub use capstone_sys::arm64_dc_op as Arm64DcOp;
25-
pub use capstone_sys::arm64_at_op as Arm64AtOp;
26-
pub use capstone_sys::arm64_tlbi_op as Arm64TlbiOp;
23+
pub use capstone_sys::arm64_sys_op as Arm64SysOp;
2724
pub use capstone_sys::arm64_barrier_op as Arm64BarrierOp;
2825

2926
use capstone_sys::cs_arm64_op__bindgen_ty_2;
@@ -122,9 +119,8 @@ pub enum Arm64OperandType {
122119
/// System PState Field (MSR instruction)
123120
Pstate(Arm64Pstate),
124121

125-
// XXX todo(tmfink)
126-
/// IC/DC/AT/TLBI operation (see Arm64IcOp, Arm64DcOp, Arm64AtOp, Arm64TlbiOp)
127-
Sys(u32),
122+
/// System operation (IC/DC/AT/TLBI)
123+
Sys(Arm64SysOp),
128124

129125
/// PRFM operation
130126
Prefetch(ArmPrefetchOp),
@@ -325,8 +321,8 @@ mod test {
325321
RegMsr(arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1),
326322
);
327323
t(
328-
(ARM64_OP_SYS, cs_arm64_op__bindgen_ty_2 { sys: 42 }),
329-
Sys(42),
324+
(ARM64_OP_SYS, cs_arm64_op__bindgen_ty_2 { sys: arm64_sys_op::ARM64_AT_S1E0R }),
325+
Sys(arm64_sys_op::ARM64_AT_S1E0R),
330326
);
331327
t(
332328
(ARM64_OP_PREFETCH, cs_arm64_op__bindgen_ty_2 {

‎capstone-rs/src/test.rs

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1067,7 +1067,7 @@ fn test_arch_arm64_detail() {
10671067
use crate::arch::arm64::Arm64OperandType::*;
10681068
use crate::arch::arm64::Arm64Pstate::*;
10691069
use crate::arch::arm64::Arm64Reg::*;
1070-
use crate::arch::arm64::Arm64Sysreg::*;
1070+
//use crate::arch::arm64::Arm64Sysreg::*;
10711071
use crate::arch::arm64::Arm64Vas::*;
10721072
use crate::arch::arm64::*;
10731073
use capstone_sys::arm64_op_mem;
@@ -1101,6 +1101,8 @@ fn test_arch_arm64_detail() {
11011101
&[],
11021102
&[
11031103
// mrs x9, midr_el1
1104+
// todo(tmfink): https://github.com/capstone-engine/capstone/issues/1881
1105+
/*
11041106
DII::new(
11051107
"mrs",
11061108
b"\x09\x00\x38\xd5",
@@ -1115,6 +1117,7 @@ fn test_arch_arm64_detail() {
11151117
},
11161118
],
11171119
),
1120+
*/
11181121
// msr spsel, #0
11191122
DII::new(
11201123
"msr",

‎capstone-sys/CHANGELOG.md

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,17 @@ All notable changes to this project will be documented in this file.
44
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
55
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
66

7-
## UNRELEASED - YYYY-MM-DD
7+
## [Unreleased] - YYYY-MM-DD
8+
9+
### Changed
10+
- Upgraded bundled capstone to from [f278de39 to 3b298421](https://github.com/aquynh/capstone/compare/f278de39...3b298421)
11+
- Merged enums `arm64_tlbi_op`, `arm64_at_op`, `arm64_dc_op`, `arm64_ic_op` into single enum `arm64_sys_op` (based on upstream [`3e23b60af0`](https://github.com/capstone-engine/capstone/commit/3e23b60af04aa75eb17c14ba33d6ed139a2c405c))
12+
13+
## [0.15.0] - 2022-05-01
814
### Fixed
915
- Document that minimum supported Rust version is actually 1.50.0
1016
- Improperly documented as 1.40.0 in 0.14.0 release
17+
- Suppress C compiler warning
1118

1219
## [0.14.0] - 2021-08-09
1320

@@ -99,6 +106,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
99106
### Removed
100107
- Dependency
101108

109+
[Unreleased]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.15.0...master
110+
[0.15.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.14.0...capstone-sys-v0.15.0
102111
[0.14.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.13.0...capstone-sys-v0.14.0
103112
[0.13.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.12.0...capstone-sys-v0.13.0
104113
[0.12.0]: https://github.com/capstone-rust/capstone-rs/compare/capstone-sys-v0.11.0...capstone-sys-v0.12.0

‎capstone-sys/pre_generated/capstone.rs

Lines changed: 134 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -2404,131 +2404,218 @@ pub enum arm64_op_type {
24042404
ARM64_OP_BARRIER = 70,
24052405
}
24062406
#[repr(u32)]
2407-
#[doc = " TLBI operations"]
2407+
#[doc = " SYS operands (IC/DC/AC/TLBI)"]
24082408
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2409-
pub enum arm64_tlbi_op {
2410-
ARM64_TLBI_INVALID = 0,
2409+
pub enum arm64_sys_op {
2410+
ARM64_SYS_INVALID = 0,
2411+
#[doc = " TLBI operations"]
24112412
ARM64_TLBI_IPAS2E1IS = 1,
2413+
#[doc = " TLBI operations"]
24122414
ARM64_TLBI_IPAS2LE1IS = 2,
2415+
#[doc = " TLBI operations"]
24132416
ARM64_TLBI_VMALLE1IS = 3,
2417+
#[doc = " TLBI operations"]
24142418
ARM64_TLBI_ALLE2IS = 4,
2419+
#[doc = " TLBI operations"]
24152420
ARM64_TLBI_ALLE3IS = 5,
2421+
#[doc = " TLBI operations"]
24162422
ARM64_TLBI_VAE1IS = 6,
2423+
#[doc = " TLBI operations"]
24172424
ARM64_TLBI_VAE2IS = 7,
2425+
#[doc = " TLBI operations"]
24182426
ARM64_TLBI_VAE3IS = 8,
2427+
#[doc = " TLBI operations"]
24192428
ARM64_TLBI_ASIDE1IS = 9,
2429+
#[doc = " TLBI operations"]
24202430
ARM64_TLBI_VAAE1IS = 10,
2431+
#[doc = " TLBI operations"]
24212432
ARM64_TLBI_ALLE1IS = 11,
2433+
#[doc = " TLBI operations"]
24222434
ARM64_TLBI_VALE1IS = 12,
2435+
#[doc = " TLBI operations"]
24232436
ARM64_TLBI_VALE2IS = 13,
2437+
#[doc = " TLBI operations"]
24242438
ARM64_TLBI_VALE3IS = 14,
2439+
#[doc = " TLBI operations"]
24252440
ARM64_TLBI_VMALLS12E1IS = 15,
2441+
#[doc = " TLBI operations"]
24262442
ARM64_TLBI_VAALE1IS = 16,
2443+
#[doc = " TLBI operations"]
24272444
ARM64_TLBI_IPAS2E1 = 17,
2445+
#[doc = " TLBI operations"]
24282446
ARM64_TLBI_IPAS2LE1 = 18,
2447+
#[doc = " TLBI operations"]
24292448
ARM64_TLBI_VMALLE1 = 19,
2449+
#[doc = " TLBI operations"]
24302450
ARM64_TLBI_ALLE2 = 20,
2451+
#[doc = " TLBI operations"]
24312452
ARM64_TLBI_ALLE3 = 21,
2453+
#[doc = " TLBI operations"]
24322454
ARM64_TLBI_VAE1 = 22,
2455+
#[doc = " TLBI operations"]
24332456
ARM64_TLBI_VAE2 = 23,
2457+
#[doc = " TLBI operations"]
24342458
ARM64_TLBI_VAE3 = 24,
2459+
#[doc = " TLBI operations"]
24352460
ARM64_TLBI_ASIDE1 = 25,
2461+
#[doc = " TLBI operations"]
24362462
ARM64_TLBI_VAAE1 = 26,
2463+
#[doc = " TLBI operations"]
24372464
ARM64_TLBI_ALLE1 = 27,
2465+
#[doc = " TLBI operations"]
24382466
ARM64_TLBI_VALE1 = 28,
2467+
#[doc = " TLBI operations"]
24392468
ARM64_TLBI_VALE2 = 29,
2469+
#[doc = " TLBI operations"]
24402470
ARM64_TLBI_VALE3 = 30,
2471+
#[doc = " TLBI operations"]
24412472
ARM64_TLBI_VMALLS12E1 = 31,
2473+
#[doc = " TLBI operations"]
24422474
ARM64_TLBI_VAALE1 = 32,
2475+
#[doc = " TLBI operations"]
24432476
ARM64_TLBI_VMALLE1OS = 33,
2477+
#[doc = " TLBI operations"]
24442478
ARM64_TLBI_VAE1OS = 34,
2479+
#[doc = " TLBI operations"]
24452480
ARM64_TLBI_ASIDE1OS = 35,
2481+
#[doc = " TLBI operations"]
24462482
ARM64_TLBI_VAAE1OS = 36,
2483+
#[doc = " TLBI operations"]
24472484
ARM64_TLBI_VALE1OS = 37,
2485+
#[doc = " TLBI operations"]
24482486
ARM64_TLBI_VAALE1OS = 38,
2487+
#[doc = " TLBI operations"]
24492488
ARM64_TLBI_IPAS2E1OS = 39,
2489+
#[doc = " TLBI operations"]
24502490
ARM64_TLBI_IPAS2LE1OS = 40,
2491+
#[doc = " TLBI operations"]
24512492
ARM64_TLBI_VAE2OS = 41,
2493+
#[doc = " TLBI operations"]
24522494
ARM64_TLBI_VALE2OS = 42,
2495+
#[doc = " TLBI operations"]
24532496
ARM64_TLBI_VMALLS12E1OS = 43,
2497+
#[doc = " TLBI operations"]
24542498
ARM64_TLBI_VAE3OS = 44,
2499+
#[doc = " TLBI operations"]
24552500
ARM64_TLBI_VALE3OS = 45,
2501+
#[doc = " TLBI operations"]
24562502
ARM64_TLBI_ALLE2OS = 46,
2503+
#[doc = " TLBI operations"]
24572504
ARM64_TLBI_ALLE1OS = 47,
2505+
#[doc = " TLBI operations"]
24582506
ARM64_TLBI_ALLE3OS = 48,
2507+
#[doc = " TLBI operations"]
24592508
ARM64_TLBI_RVAE1 = 49,
2509+
#[doc = " TLBI operations"]
24602510
ARM64_TLBI_RVAAE1 = 50,
2511+
#[doc = " TLBI operations"]
24612512
ARM64_TLBI_RVALE1 = 51,
2513+
#[doc = " TLBI operations"]
24622514
ARM64_TLBI_RVAALE1 = 52,
2515+
#[doc = " TLBI operations"]
24632516
ARM64_TLBI_RVAE1IS = 53,
2517+
#[doc = " TLBI operations"]
24642518
ARM64_TLBI_RVAAE1IS = 54,
2519+
#[doc = " TLBI operations"]
24652520
ARM64_TLBI_RVALE1IS = 55,
2521+
#[doc = " TLBI operations"]
24662522
ARM64_TLBI_RVAALE1IS = 56,
2523+
#[doc = " TLBI operations"]
24672524
ARM64_TLBI_RVAE1OS = 57,
2525+
#[doc = " TLBI operations"]
24682526
ARM64_TLBI_RVAAE1OS = 58,
2527+
#[doc = " TLBI operations"]
24692528
ARM64_TLBI_RVALE1OS = 59,
2529+
#[doc = " TLBI operations"]
24702530
ARM64_TLBI_RVAALE1OS = 60,
2531+
#[doc = " TLBI operations"]
24712532
ARM64_TLBI_RIPAS2E1IS = 61,
2533+
#[doc = " TLBI operations"]
24722534
ARM64_TLBI_RIPAS2LE1IS = 62,
2535+
#[doc = " TLBI operations"]
24732536
ARM64_TLBI_RIPAS2E1 = 63,
2537+
#[doc = " TLBI operations"]
24742538
ARM64_TLBI_RIPAS2LE1 = 64,
2539+
#[doc = " TLBI operations"]
24752540
ARM64_TLBI_RIPAS2E1OS = 65,
2541+
#[doc = " TLBI operations"]
24762542
ARM64_TLBI_RIPAS2LE1OS = 66,
2543+
#[doc = " TLBI operations"]
24772544
ARM64_TLBI_RVAE2 = 67,
2545+
#[doc = " TLBI operations"]
24782546
ARM64_TLBI_RVALE2 = 68,
2547+
#[doc = " TLBI operations"]
24792548
ARM64_TLBI_RVAE2IS = 69,
2549+
#[doc = " TLBI operations"]
24802550
ARM64_TLBI_RVALE2IS = 70,
2551+
#[doc = " TLBI operations"]
24812552
ARM64_TLBI_RVAE2OS = 71,
2553+
#[doc = " TLBI operations"]
24822554
ARM64_TLBI_RVALE2OS = 72,
2555+
#[doc = " TLBI operations"]
24832556
ARM64_TLBI_RVAE3 = 73,
2557+
#[doc = " TLBI operations"]
24842558
ARM64_TLBI_RVALE3 = 74,
2559+
#[doc = " TLBI operations"]
24852560
ARM64_TLBI_RVAE3IS = 75,
2561+
#[doc = " TLBI operations"]
24862562
ARM64_TLBI_RVALE3IS = 76,
2563+
#[doc = " TLBI operations"]
24872564
ARM64_TLBI_RVAE3OS = 77,
2565+
#[doc = " TLBI operations"]
24882566
ARM64_TLBI_RVALE3OS = 78,
2489-
}
2490-
#[repr(u32)]
2491-
#[doc = " AT operations"]
2492-
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2493-
pub enum arm64_at_op {
2494-
ARM64_AT_S1E1R = 0,
2495-
ARM64_AT_S1E2R = 1,
2496-
ARM64_AT_S1E3R = 2,
2497-
ARM64_AT_S1E1W = 3,
2498-
ARM64_AT_S1E2W = 4,
2499-
ARM64_AT_S1E3W = 5,
2500-
ARM64_AT_S1E0R = 6,
2501-
ARM64_AT_S1E0W = 7,
2502-
ARM64_AT_S12E1R = 8,
2503-
ARM64_AT_S12E1W = 9,
2504-
ARM64_AT_S12E0R = 10,
2505-
ARM64_AT_S12E0W = 11,
2506-
ARM64_AT_S1E1RP = 12,
2507-
ARM64_AT_S1E1WP = 13,
2508-
}
2509-
#[repr(u32)]
2510-
#[doc = " DC operations"]
2511-
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2512-
pub enum arm64_dc_op {
2513-
ARM64_DC_INVALID = 0,
2514-
ARM64_DC_ZVA = 1,
2515-
ARM64_DC_IVAC = 2,
2516-
ARM64_DC_ISW = 3,
2517-
ARM64_DC_CVAC = 4,
2518-
ARM64_DC_CSW = 5,
2519-
ARM64_DC_CVAU = 6,
2520-
ARM64_DC_CIVAC = 7,
2521-
ARM64_DC_CISW = 8,
2522-
ARM64_DC_CVAP = 9,
2523-
}
2524-
#[repr(u32)]
2525-
#[doc = " IC operations"]
2526-
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
2527-
pub enum arm64_ic_op {
2528-
ARM64_IC_INVALID = 0,
2529-
ARM64_IC_IALLUIS = 1,
2530-
ARM64_IC_IALLU = 2,
2531-
ARM64_IC_IVAU = 3,
2567+
#[doc = " AT operations"]
2568+
ARM64_AT_S1E1R = 79,
2569+
#[doc = " AT operations"]
2570+
ARM64_AT_S1E2R = 80,
2571+
#[doc = " AT operations"]
2572+
ARM64_AT_S1E3R = 81,
2573+
#[doc = " AT operations"]
2574+
ARM64_AT_S1E1W = 82,
2575+
#[doc = " AT operations"]
2576+
ARM64_AT_S1E2W = 83,
2577+
#[doc = " AT operations"]
2578+
ARM64_AT_S1E3W = 84,
2579+
#[doc = " AT operations"]
2580+
ARM64_AT_S1E0R = 85,
2581+
#[doc = " AT operations"]
2582+
ARM64_AT_S1E0W = 86,
2583+
#[doc = " AT operations"]
2584+
ARM64_AT_S12E1R = 87,
2585+
#[doc = " AT operations"]
2586+
ARM64_AT_S12E1W = 88,
2587+
#[doc = " AT operations"]
2588+
ARM64_AT_S12E0R = 89,
2589+
#[doc = " AT operations"]
2590+
ARM64_AT_S12E0W = 90,
2591+
#[doc = " AT operations"]
2592+
ARM64_AT_S1E1RP = 91,
2593+
#[doc = " AT operations"]
2594+
ARM64_AT_S1E1WP = 92,
2595+
#[doc = " DC operations"]
2596+
ARM64_DC_ZVA = 93,
2597+
#[doc = " DC operations"]
2598+
ARM64_DC_IVAC = 94,
2599+
#[doc = " DC operations"]
2600+
ARM64_DC_ISW = 95,
2601+
#[doc = " DC operations"]
2602+
ARM64_DC_CVAC = 96,
2603+
#[doc = " DC operations"]
2604+
ARM64_DC_CSW = 97,
2605+
#[doc = " DC operations"]
2606+
ARM64_DC_CVAU = 98,
2607+
#[doc = " DC operations"]
2608+
ARM64_DC_CIVAC = 99,
2609+
#[doc = " DC operations"]
2610+
ARM64_DC_CISW = 100,
2611+
#[doc = " DC operations"]
2612+
ARM64_DC_CVAP = 101,
2613+
#[doc = " IC operations"]
2614+
ARM64_IC_IALLUIS = 102,
2615+
#[doc = " IC operations"]
2616+
ARM64_IC_IALLU = 103,
2617+
#[doc = " IC operations"]
2618+
ARM64_IC_IVAU = 104,
25322619
}
25332620
#[repr(u32)]
25342621
#[doc = " Prefetch operations (PRFM)"]
@@ -2935,7 +3022,7 @@ pub union cs_arm64_op__bindgen_ty_2 {
29353022
#[doc = "< PState field of MSR instruction."]
29363023
pub pstate: arm64_pstate,
29373024
#[doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)"]
2938-
pub sys: libc::c_uint,
3025+
pub sys: arm64_sys_op,
29393026
#[doc = "< PRFM operation."]
29403027
pub prefetch: arm64_prefetch_op,
29413028
#[doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."]

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