part2.c

#include <stdio.h>
#include <stdlib.h>
#include "types.h"
#include "utils.h"
#include "riscv.h"

void execute_instruction(Instruction instruction, Processor *processor, Byte *memory);

void execute_itype_except_load(Instruction instruction, Processor *processor) {
    switch(instruction.itype.funct3) {
        case 0b000:
            // Corrected to FUNCT3_ADD
            processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] + ((int32_t)instruction.itype.imm << 20 >> 20);
            break;
        case 0b010:
            // Corrected to FUNCT3_SLT
            processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1] < processor->R[instruction.rtype.rs2]) ? 1 : 0;
            break;
        case 0b011:
            // Corrected to FUNCT3_SLTU
            processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1] < processor->R[instruction.rtype.rs2]) ? 1 : 0;
            break;
        case 0b100:
            // Corrected to FUNCT3_XOR
            processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] ^ processor->R[instruction.rtype.rs2];
            break;
        case 0b101:
            // Corrected to FUNCT3_SRL
            processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] >> processor->R[instruction.rtype.rs2];
            break;
        case 0b110:
            // Corrected to FUNCT3_OR
            processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] | processor->R[instruction.rtype.rs2];
            break;
        case 0b111:
            // Corrected to FUNCT3_AND
            processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] & processor->R[instruction.rtype.rs2];
            break;
        default:
            handle_invalid_instruction(instruction);
            exit(-1);
            break;
    }
}

void execute_itype_except_load(Instruction instruction, Processor *processor) {
    switch(instruction.itype.funct3) {
        case 0b000:
            // Corrected to FUNCT3_ADDI
            processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] + sign_extend(instruction.itype.imm, 12);
            break;
        default:
            handle_invalid_instruction(instruction);
            exit(-1);
            break;
    }
}

void execute_ecall(Processor *p, Byte *memory) {
    switch(p->R[10]) { // Cambiado de REG_A7 a 10
        case 1: // Cambiado de ECALL_PRINT_INT a 1
            printf("Print integer: %d\n", p->R[11]); // Cambiado de REG_A0 a 11
            break;
        case 4: // Cambiado de ECALL_PRINT_STRING a 4
            for (int i = p->R[11]; memory[i] != '\0'; ++i) { // Cambiado de REG_A0 a 11
                printf("%c", memory[i]);
            }
            printf("\n");
            break;
        case 10: // Cambiado de ECALL_EXIT a 10
            exit(p->R[11]); // Cambiado de REG_A0 a 11
            break;
        default:
            printf("Illegal ecall number %d\n", -1);
            exit(-1);
            break;
    }
}

void execute_branch(Instruction instruction, Processor *processor) {
    Word offset = sign_extend(((instruction.btype.imm7 << 5) | instruction.btype.imm5) << 1, 12);
    switch(instruction.btype.funct3) {
        case 0b000:
            // Corrected to FUNCT3_BEQ
            if (processor->R[instruction.rtype.rs1] == processor->R[instruction.rtype.rs2]) {
                processor->PC += offset;
            } else {
                processor->PC += 4;
            }
            break;
        default:
            handle_invalid_instruction(instruction);
            exit(-1);
            break;
    }
}

void execute_load(Instruction instruction, Processor *processor, Byte *memory) {
    Word address = processor->R[instruction.itype.rs1] + sign_extend(instruction.itype.imm, 12);
    switch(instruction.itype.funct3) {
        case 0b000:
            // Corrected to FUNCT3_LB
            processor->R[instruction.itype.rd] = sign_extend(memory[address], 8);
            break;
        default:
            handle_invalid_instruction(instruction);
            exit(-1);
            break;
    }
}

void execute_store(Instruction instruction, Processor *processor, Byte *memory) {
    Word address = processor->R[instruction.stype.rs1] + sign_extend(instruction.stype.imm7, 12);
    Word value = processor->R[instruction.stype.rs2];
    switch(instruction.stype.funct3) {
        case 0b000:
            // Corrected to FUNCT3_SB
            memory[address] = value & 0xFF;
            break;
        default:
            handle_invalid_instruction(instruction);
            exit(-1);
            break;
    }
}

void execute_jalr(Instruction instruction, Processor *processor) {
    Word return_address = processor->PC + 4;
    processor->PC = (processor->R[instruction.itype.rs1] + sign_extend(instruction.itype.imm, 12)) & ~1;
    processor->R[instruction.itype.rd] = return_address;
}

void execute_jal(Instruction instruction, Processor *processor) {
    Word return_address = processor->PC + 4;
    processor->PC += sign_extend(instruction.jtype.imm << 1, 21);
    processor->R[instruction.jtype.rd] = return_address;
}

void execute_auipc(Instruction instruction, Processor *processor) {
    processor->R[instruction.utype.rd] = processor->PC + sign_extend(instruction.utype.imm << 12, 32);
}

void execute_lui(Instruction instruction, Processor *processor) {
    processor->R[instruction.utype.rd] = instruction.utype.imm << 12;
}