diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..e7fc1a2b --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +StdCellLib*.tgz diff --git a/Catalog/.gitignore b/Catalog/.gitignore new file mode 100644 index 00000000..f750ad01 --- /dev/null +++ b/Catalog/.gitignore @@ -0,0 +1,9 @@ +*.mag +*.cell +*.svg +*.sp +*.pxi +!INV.cell +__pycache__ +libresilicon.lib +libresilicon.lef diff --git a/Catalog/AND4.cell b/Catalog/AND4.cell index 78ae146d..42124a3c 100644 --- a/Catalog/AND4.cell +++ b/Catalog/AND4.cell @@ -1,13 +1,14 @@ -.DESCRIPTION "a 4-input AND gate" -.SEE_ALSO "NAND3 - a 3-input Not-AND (or NAND) gate" -.ORDER "Gate Drain Source MOSFET" -A Y vdd pmos -B Y vdd pmos -C Y vdd pmos -D Y vdd pmos -Y Z vdd pmos -A Y 2 nmos -B 2 4 nmos -C 4 6 nmos -D 6 gnd nmos -Y Z gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B C D +.outputs Z +.ORDER "MOSFET Gate Drain Source" +pmos A Y vdd +pmos B Y vdd +pmos C Y vdd +pmos D Y vdd +pmos Y Z vdd +nmos A Y 1 +nmos B 1 2 +nmos C 2 3 +nmos D 3 gnd +nmos Y Z gnd diff --git a/Catalog/AOI21.cell b/Catalog/AOI21.cell index 89b5db32..b5fa13ab 100644 --- a/Catalog/AOI21.cell +++ b/Catalog/AOI21.cell @@ -1,9 +1,8 @@ -.DESCRIPTION "a 2-1-input AND-OR-Invert gate" -.SEE_ALSO "AOI21 - a 2-1-input AND-OR-Invert gate" -.ORDER "Gate Drain Source MOSFET" -A Y 1 pmos -B 1 vdd pmos -B1 1 vdd pmos -A Y gnd nmos -B Y 2 nmos -B1 2 gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A A1 +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y vdd +pmos A1 Y vdd +nmos A Y 1 +nmos A1 1 gnd diff --git a/Catalog/AOI31.cell b/Catalog/AOI31.cell index 400940a9..7719e040 100644 --- a/Catalog/AOI31.cell +++ b/Catalog/AOI31.cell @@ -1,11 +1,13 @@ .DESCRIPTION "a 3-1-input AND-OR-Invert gate" .SEE_ALSO "AOI31 - a 3-1-input AND-OR-Invert gate" -.ORDER "Gate Drain Source MOSFET" -A Y 1 pmos -B 1 vdd pmos -B1 1 vdd pmos -B2 1 vdd pmos -A Y gnd nmos -B Y 2 nmos -B1 2 3 nmos -B2 3 gnd nmos +.inputs A B B1 B2 +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y 1 +pmos B 1 vdd +pmos B1 1 vdd +pmos B2 1 vdd +nmos A Y gnd +nmos B Y 2 +nmos B1 2 3 +nmos B2 3 gnd diff --git a/Catalog/ASYNC1.cell b/Catalog/ASYNC1.cell new file mode 100644 index 00000000..67bb09b0 --- /dev/null +++ b/Catalog/ASYNC1.cell @@ -0,0 +1,16 @@ +.AUTOGENERATED by spice2cell script from ASYNC1.spice +.inputs A B +.outputs C CN +.ORDER "MOSFET Gate Drain Source" +nmos B CN net3 +pmos A net4 VDD +pmos B CN net4 +pmos A net1 VDD +pmos B net1 VDD +pmos C CN net1 +pmos CN C VDD +nmos C CN net2 +nmos A net3 GND +nmos B net2 GND +nmos A net2 GND +nmos CN C GND diff --git a/Catalog/ASYNC2.cell b/Catalog/ASYNC2.cell new file mode 100644 index 00000000..b604db8f --- /dev/null +++ b/Catalog/ASYNC2.cell @@ -0,0 +1,12 @@ +.AUTOGENERATED by spice2cell script from ASYNC2.spice +.inputs A B +.outputs C CN +.ORDER "MOSFET Gate Drain Source" +nmos C CN GND +pmos A net1 VDD +pmos B CN net1 +pmos CN C VDD +pmos C CN VDD +nmos B CN net2 +nmos A net2 GND +nmos CN C GND diff --git a/Catalog/ASYNC3.cell b/Catalog/ASYNC3.cell new file mode 100644 index 00000000..c4ec28a6 --- /dev/null +++ b/Catalog/ASYNC3.cell @@ -0,0 +1,16 @@ +.AUTOGENERATED by spice2cell script from ASYNC3.spice +.inputs A B +.outputs C CN +.ORDER "MOSFET Gate Drain Source" +nmos B CN net2 +nmos A net2 GND +nmos A CN net1 +nmos CN C GND +nmos B net1 GND +nmos C net2 net1 +pmos B CN net3 +pmos A net3 VDD +pmos B net4 VDD +pmos A CN net4 +pmos CN C VDD +pmos C net4 net3 diff --git a/Catalog/GNUmakefile b/Catalog/GNUmakefile index 05649795..6c86bf64 100644 --- a/Catalog/GNUmakefile +++ b/Catalog/GNUmakefile @@ -17,7 +17,8 @@ # # //////////////////////////////////////////////////////////////// # -# Copyright (c) 2018 by chipforge +# Copyright (c) 2018, 2019 by +# chipforge - # All rights reserved. # # This Standard Cell Library is licensed under the Libre Silicon @@ -51,11 +52,19 @@ RM ?= rm -f TAR ?= tar -zh DATE := $(shell date +%Y%m%d) -# project tools +# project settings -POPCORN ?= ../Tools/tcl/popcorn -CELLS = INV.cell NAND2.cell NAND3.cell AND4.cell NOR2.cell NOR3.cell OR4.cell -LIMIT = 4 +CELLS = + +# Attention! limit/buffer changes will impact cell catalog + +LIMIT ?= 5 +BUFFER ?= $(LIMIT) # recommended, but free to reduce +LEVEL ?= $(LIMIT) # hack for fencing expand algorithmen +DESCR ?= '?' + +#POPCORN ?= ../Tools/tcl/popcorn +POPCORN ?= ../Tools/popcorn/popcorn -l $(LEVEL) -b $(BUFFER) -D $(DESCR) # ---------------------------------------------------------------- # DEFAULT TARGETS @@ -72,36 +81,162 @@ help: $(ECHO) " help - print this help screen" $(ECHO) " clean - clean up all intermediate files" $(ECHO) "" - $(ECHO) " catalog - compile catalog cells" + $(ECHO) " catalog - compile *all* catalog cells (see list below)" + $(ECHO) " cell CELL= - compile up to dedicated catalog cell" + $(ECHO) "" + $(ECHO) "-------------------------------------------------------------------" + $(ECHO) " available cells [limit=" $(LIMIT) "+ buffer=" $(BUFFER)"]:" + $(ECHO) "-------------------------------------------------------------------" + $(ECHO) "" + $(ECHO) $(CELLS) $(ECHO) "" - .PHONY: clean clean: # $(RM) *.aux *.idx *.log *.toc *.out + $(RM) $(CELLS) + #$(RM) AND4.cell NAND2.cell NAND3.cell NOR2.cell NOR3.cell OR4.cell + $(RM) *.usage *.mag *.svg *.ext *.res.ext *.spice *.nodes *.sp *.sim *.al *.res.lump *.png *.err *.log *.libtemplate *.lib *.truthtable.html *.truthtable.v *.truthtable.txt outputlib/*.gds outputlib/*.lef outputlib/*.mag debuglib/* *.running *.mag.drc *.drc *.predrc *.done *.lef *_debug.oas *_debug.gds *.drc.tcl # ---------------------------------------------------------------- -# DOCUMENTATION TARGETS +# CELL TARGETS # ---------------------------------------------------------------- +# include makefile with highest number of (allowed) stacked transistors + +ifeq ($(LIMIT),2) + include stacked2_cells.mk +else +ifeq ($(LIMIT),3) + include stacked3_cells.mk +else +ifeq ($(LIMIT),4) + include stacked4_cells.mk +else +ifeq ($(LIMIT),5) + include stacked5_cells.mk +endif +endif +endif +endif + .PHONY: catalog -catalog: $(CELLS) +catalog: $(CELLS) + +.PHONY: layout +layout: libresilicon.sp libresilicon.lef libresilicon.lib demoboard.mag doc/StdCellLib.pdf demoboard.svg -AND4.cell: NAND3.cell - $(POPCORN) -l $(LIMIT) -n nand -c $@ -b $(LIMIT) $< -NAND2.cell: INV.cell - $(POPCORN) -l $(LIMIT) -n nand -c $@ $< +libresilicon.sp: *.cell ../Tech/librecell_tech.py ../Tools/perl/cell2spice.pl ../Tools/perl/librecells.pl ../Tech/nmos.sp + ../Tools/perl/cell2spice.pl + ../Tools/perl/librecells.pl + rm -f libresilicon.lib + ../Tools/perl/libgen.pl >libresilicon.libtemplate + libertymerge -b libresilicon.libtemplate -o libresilicon.lib -u *.lib -NAND3.cell: NAND2.cell - $(POPCORN) -l $(LIMIT) -n nand -c $@ $< +demoboard.mag: *.cell libresilicon.sp + perl ../Tools/perl/demoboard.pl >demoboard.mag -NOR2.cell: INV.cell - $(POPCORN) -l $(LIMIT) -n nor -c $@ $< +.PHONY: buildreport +buildreport: + bash ../Tools/reporter.sh -NOR3.cell: NOR2.cell - $(POPCORN) -l $(LIMIT) -n nor -c $@ $< +libresilicon.lef: *.cell libresilicon.sp + ../Tools/perl/lefgen.pl outputlib/*.lef >libresilicon.lef -OR4.cell: NOR3.cell - $(POPCORN) -l $(LIMIT) -n nor -b $(LIMIT) -c $@ $< +libresilicon.lib: *.cell libresilicon.sp + ../Tools/perl/libgen.pl >libresilicon.libtemplate + rm -f libresilicon.lib + libertymerge -b libresilicon.libtemplate -o libresilicon.lib -u *.lib + +.PHONY: qflow +qflow: libresilicon.lef libresilicon.lib + sudo mkdir -p /usr/local/share/qflow/tech/ls050 + sudo cp libresilicon.lef /usr/local/share/qflow/tech/ls050/ls050_stdcells.lef + sudo cp libresilicon.lib /usr/local/share/qflow/tech/ls050/ls05_stdcells.lib + +#AND4.cell: NAND3.cell +# $(POPCORN) -l $(LIMIT) -n nand -c $@ -b $(LIMIT) $< +# +#NAND2.cell: INV.cell +# $(POPCORN) -l $(LIMIT) -n nand -c $@ $< +# +#NAND3.cell: NAND2.cell +# $(POPCORN) -l $(LIMIT) -n nand -c $@ $< +# +#AOI21.cell: INV.cell +# $(POPCORN) -l $(LIMIT) -n aoi -c $@ $< +# +#OAI21.cell: INV.cell +# $(POPCORN) -l $(LIMIT) -n oai -c $@ $< +# +#NOR2.cell: INV.cell +# $(POPCORN) -l $(LIMIT) -n nor -c $@ $< +# +#NOR3.cell: NOR2.cell +# $(POPCORN) -l $(LIMIT) -n nor -c $@ $< +# +#OR4.cell: NOR3.cell +# $(POPCORN) -l $(LIMIT) -n nor -c $@ -b $(LIMIT) $< + +doc/StdCellLib.pdf: *.cell libresilicon.sp +# doc/docu.sh + +.PHONY: importQflow +importQflow: + ../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/gscl45nm/gscl45nm.sp + ../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu018/osu018_stdcells.sp + ../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu035/osu035_stdcells.sp + ../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu050/osu050_stdcells.sp + ../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu018/osu018_stdcells.sp + ../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu035/osu035_stdcells.sp + ../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu050/osu050_stdcells.sp + +mags=$(wildcard *.mag) +svgs=$(mags:.mag=.svg) + +.PHONY: svg +svg: $(svgs) + +test: + echo For debugging run "export PySpiceLogLevel=DEBUG" before make + lctime --debug --liberty libresilicon.lib \ + --include ../Tech/libresilicon.m \ + --spice INV.spice \ + --cell INV \ + --output INV.lib + libertyviz -l INV.lib --cell INV --pin Y --related-pin A --table cell_rise + libertymerge -b libresilicon.lib -o output_liberty.lib -u INV.lib AND2X1.lib + +test2: + /usr/local/bin/lctime --debug --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \ + --include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \ + --spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \ + --cell AND2X1 \ + --output /tmp/and2x1.lib + libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_rise & + libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin B --table rise_transition & + libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin A --table cell_fall & + libertyviz -l /tmp/and2x1.lib --cell AND2X1 --pin Y --related-pin B --table fall_transition & + + +%.svg : %.mag + perl ../Tools/perl/mag2svg.pl $@ + +%.truthtable.v : %.cell + perl ../Tools/perl/truthtable.pl --format=verilog $^ >$@ + +%.truthtable.txt : %.cell + perl ../Tools/perl/truthtable.pl --format=text $^ >$@ + +%.truthtable.html : %.cell + perl ../Tools/perl/truthtable.pl --format=html $^ >$@ + +.PHONY: charter +charter: + perl ../Tools/perl/charter2caravel.pl + + +.PHONY: cell +cell: $(CELL) diff --git a/Catalog/INV.cell b/Catalog/INV.cell index 1226dda9..f862f6f5 100644 --- a/Catalog/INV.cell +++ b/Catalog/INV.cell @@ -1,11 +1,11 @@ -a Not (or Inverter) gate +Not (or Inverter) gate .cell INV .inputs A .outputs Y # ^ Vdd # | # | +-' -# A --o| | pMOS +# A --o| | g # | +-. # | # | @@ -13,10 +13,10 @@ a Not (or Inverter) gate # | # | # | +-' -# A ---| | nMOS +# A ---| | 1 # | +-. # | # _|_ Gnd -pmos A Y vdd vdd 1 1 1 -nmos A Y gnd vdd 1 1 -1 +pmos A Y vdd vdd g 1 1 +1 +nmos A Y gnd gnd 1 1 1 -1 .end diff --git a/Catalog/NAND2.cell b/Catalog/NAND2.cell index ab84e390..068f975c 100644 --- a/Catalog/NAND2.cell +++ b/Catalog/NAND2.cell @@ -1,7 +1,8 @@ -.DESCRIPTION "a 2-input Not-AND (or NAND) gate" -.SEE_ALSO "NAND3 - a 3-input Not-AND (or NAND) gate" -.ORDER "Gate Drain Source MOSFET" -A Y vdd pmos -B Y vdd pmos -A Y 2 nmos -B 2 gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y vdd +pmos B Y vdd +nmos A Y 1 +nmos B 1 gnd diff --git a/Catalog/NAND3.cell b/Catalog/NAND3.cell index 41e99406..c381e0af 100644 --- a/Catalog/NAND3.cell +++ b/Catalog/NAND3.cell @@ -1,11 +1,10 @@ -a 3-input Not-AND (or NAND) gate -.cell NAND3 -.inputs C B A +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B C .outputs Y -pmos C Y vdd vdd 1 1 1 -pmos B Y vdd vdd 1 2 1 -pmos A Y vdd vdd 1 3 1 -nmos A Y 2 gnd 1 1 -1 -nmos B 2 4 gnd 2 1 -2 -nmos C 4 gnd gnd 3 1 -3 -.end +.ORDER "MOSFET Gate Drain Source" +pmos A Y vdd +pmos B Y vdd +pmos C Y vdd +nmos A Y 1 +nmos B 1 2 +nmos C 2 gnd diff --git a/Catalog/NOR2.cell b/Catalog/NOR2.cell index 9eb76135..4867eca3 100644 --- a/Catalog/NOR2.cell +++ b/Catalog/NOR2.cell @@ -1,7 +1,8 @@ -.DESCRIPTION "a 2-input Not-OR (or NOR) gate" -.SEE_ALSO "NOR3 - a 3-input Not-OR (or NOR) gate" -.ORDER "Gate Drain Source MOSFET" -A Y 1 pmos -B 1 vdd pmos -A Y gnd nmos -B Y gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y 1 +pmos B 1 vdd +nmos A Y gnd +nmos B Y gnd diff --git a/Catalog/NOR3.cell b/Catalog/NOR3.cell index a54fa2c1..ec19e63b 100644 --- a/Catalog/NOR3.cell +++ b/Catalog/NOR3.cell @@ -1,9 +1,10 @@ -.DESCRIPTION "a 3-input Not-OR (or NOR) gate" -.SEE_ALSO "NOR2 - a 2-input Not-OR (or NOR) gate" -.ORDER "Gate Drain Source MOSFET" -A Y 1 pmos -B 1 3 pmos -C 3 vdd pmos -A Y gnd nmos -B Y gnd nmos -C Y gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B C +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y 1 +pmos B 1 2 +pmos C 2 vdd +nmos A Y gnd +nmos B Y gnd +nmos C Y gnd diff --git a/Catalog/OAI21.cell b/Catalog/OAI21.cell index 9553df49..f496a779 100644 --- a/Catalog/OAI21.cell +++ b/Catalog/OAI21.cell @@ -1,9 +1,8 @@ -.DESCRIPTION "a 2-1-input OR-AND-Invert gate" -.SEE_ALSO "OAI21 - a 2-1-input OR-AND-Invert gate" -.ORDER "Gate Drain Source MOSFET" -A Y vdd pmos -B Y 1 pmos -B1 1 vdd pmos -A Y 2 nmos -B 2 gnd nmos -B1 2 gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A A1 +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y 1 +pmos A1 1 vdd +nmos A Y gnd +nmos A1 Y gnd diff --git a/Catalog/OAI31.cell b/Catalog/OAI31.cell index 71dc1fcd..5b379fe4 100644 --- a/Catalog/OAI31.cell +++ b/Catalog/OAI31.cell @@ -1,11 +1,13 @@ .DESCRIPTION "a 3-1-input OR-AND-Invert gate" .SEE_ALSO "OAI31 - a 3-1-input OR-AND-Invert gate" -.ORDER "Gate Drain Source MOSFET" -A Y vdd pmos -B Y 1 pmos -B1 1 3 pmos -B2 3 vdd pmos -A Y 2 nmos -B 2 gnd nmos -B1 2 gnd nmos -B2 2 gnd nmos +.inputs A B B1 B2 +.outputs Y +.ORDER "MOSFET Gate Drain Source" +pmos A Y vdd +pmos B Y 1 +pmos B1 1 3 +pmos B2 3 vdd +nmos A Y 2 +nmos B 2 gnd +nmos B1 2 gnd +nmos B2 2 gnd diff --git a/Catalog/OR4.cell b/Catalog/OR4.cell index 178753fb..f0824cd2 100644 --- a/Catalog/OR4.cell +++ b/Catalog/OR4.cell @@ -1,13 +1,14 @@ -.DESCRIPTION "a 4-input OR gate" -.SEE_ALSO "NOR3 - a 3-input Not-OR (or NOR) gate" -.ORDER "Gate Drain Source MOSFET" -A Y 1 pmos -B 1 3 pmos -C 3 5 pmos -D 5 vdd pmos -Y Z vdd pmos -A Y gnd nmos -B Y gnd nmos -C Y gnd nmos -D Y gnd nmos -Y Z gnd nmos +.AUTOGENERATED by Popcorn Tcl Script +.inputs A B C D +.outputs Z +.ORDER "MOSFET Gate Drain Source" +pmos A Y 1 +pmos B 1 2 +pmos C 2 3 +pmos D 3 vdd +pmos Y Z vdd +nmos A Y gnd +nmos B Y gnd +nmos C Y gnd +nmos D Y gnd +nmos Y Z gnd diff --git a/Catalog/doc/GNUmakefile b/Catalog/doc/GNUmakefile new file mode 100644 index 00000000..5a599a49 --- /dev/null +++ b/Catalog/doc/GNUmakefile @@ -0,0 +1,8 @@ +all: + ./docu.sh + +clean: + rm -f *_schematic.tex cells.tex + rm -f *.aux *.idx *.log *.toc *.pdf *.png *.svg *_svg.tex + killall -q pdflatex || true + diff --git a/Catalog/doc/StdCellLib.tex b/Catalog/doc/StdCellLib.tex new file mode 100644 index 00000000..3a723fdc --- /dev/null +++ b/Catalog/doc/StdCellLib.tex @@ -0,0 +1,100 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/stdcelllib.tex +%% +%% Purpose: Top Level File for Standard Cell Library Documentation +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2018 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\documentclass[10pt,a4paper,twoside]{article} +\usepackage[utf8]{inputenc} +\usepackage[english]{babel} +%\usepackage{amsmath} +%\usepackage{amsfonts} +\usepackage{amssymb} +%\usepackage{gensymb} +%\usepackage{graphicx} +\usepackage[digital,srcmeas,semicon]{circdia} +% \usepackage[dvipsnames]{xcolor} +\usepackage[left=2cm,right=2cm,top=2cm,bottom=2cm]{geometry} + +\title{LibreSilicon Standard Cell Library} +\author{Hagen Sankowski} +\date{\today} + +\makeindex % usefull for ToC +\setlength{\parindent}{0pt} % get rid of annoying indents + +\begin{document} +\maketitle +\begin{abstract} +\begin{quote} +Copyright \textcopyright 2018 CHIPFORGE.ORG. All rights reserved. + +This process is licensed under the Libre Silicon public license; you can redistribute it and/or modify it under the terms of the Libre Silicon public license as published by the Libre Silicon alliance either version 2 of the License, or (at your option) any later version. + +This design is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the Libre Silicon Public License for more details. + +For further clarification consult the complete documentation of the process. +\end{quote} +\end{abstract} + +\clearpage +\tableofcontents +\clearpage + +\pagestyle{headings} + +\section{Considerations} +\newcommand{\stacktfour}{YES} +%\newcommand{\stacktfour}{NO} +\clearpage + +\section{Logical Cells} +\twocolumn + +\input{cells.tex} +\clearpage + + +%\onecolumn +%\section{Physical Cells} + +%\twocolumn +%\input{TIE0_manpage.tex} +%\input{TIE1_manpage.tex} +%\input{FILL_manpage.tex} + +VDDIO \\ +GND \\ +ANA + +\onecolumn +\ +\end{document} diff --git a/Catalog/doc/docu.sh b/Catalog/doc/docu.sh new file mode 100755 index 00000000..573b1665 --- /dev/null +++ b/Catalog/doc/docu.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +#cd .. +for a in *.cell +do + ../Tools/tcl/_schematic -i . -o doc $a +done +cd doc +echo "" >cells.tex +for a in *_schematic.tex +do + echo \\clearpage >>cells.tex + echo \\section{Cell ${a//_schematic\.tex/}} >>cells.tex + echo \\input{$a} >>cells.tex + #echo "Text below the schematic" >>cells.tex + + echo \\documentclass{article} >${a//_schematic/_svg} + echo \\usepackage[digital,srcmeas,semicon]{circdia} >>${a//_schematic/_svg} + echo \\begin{document} >>${a//_schematic/_svg} + echo \\thispagestyle{empty} >>${a//_schematic/_svg} + echo \\input {$a} >>${a//_schematic/_svg} + echo \\end{document} >>${a//_schematic/_svg} + pdflatex ${a//_schematic/_svg} + pdfcrop ${a//_schematic.tex/_svg.pdf} + pdf2svg ${a//_schematic.tex/_svg.pdf} ${a//_schematic.tex/_svg.svg} + convert -trim ${a//_schematic.tex/_svg.svg} ${a//_schematic.tex/_svg.png} +done +pdflatex StdCellLib.tex +pdflatex StdCellLib.tex +cp StdCellLib.pdf ../../Documents/StdCellLib.pdf +echo "You can view the generated documentation by calling:" +echo "evince doc/StdCellLib.pdf" diff --git a/Catalog/popcorn/INV.cell b/Catalog/popcorn/INV.cell new file mode 100644 index 00000000..f862f6f5 --- /dev/null +++ b/Catalog/popcorn/INV.cell @@ -0,0 +1,22 @@ +Not (or Inverter) gate +.cell INV +.inputs A +.outputs Y +# ^ Vdd +# | +# | +-' +# A --o| | g +# | +-. +# | +# | +# *---- Y +# | +# | +# | +-' +# A ---| | 1 +# | +-. +# | +# _|_ Gnd +pmos A Y vdd vdd g 1 1 +1 +nmos A Y gnd gnd 1 1 1 -1 +.end diff --git a/Catalog/stacked2_cells.mk b/Catalog/stacked2_cells.mk new file mode 100644 index 00000000..6524ccb9 --- /dev/null +++ b/Catalog/stacked2_cells.mk @@ -0,0 +1,124 @@ +# ************ LibreSilicon's StdCellLibrary ******************* +# +# Organisation: Chipforge +# Germany / European Union +# +# Profile: Chipforge focus on fine System-on-Chip Cores in +# Verilog HDL Code which are easy understandable and +# adjustable. For further information see +# www.chipforge.org +# there are projects from small cores up to PCBs, too. +# +# File: StdCellLib/Catalog/stacked2_cells.mk +# +# Purpose: Makefile for Cell Generation with popcorn +# +# ************ GNU Make 3.80 Source Code **************** +# +# //////////////////////////////////////////////////////////////// +# +# Copyright (c) 2018, 2019 by +# chipforge - +# All rights reserved. +# +# This Standard Cell Library is licensed under the Libre Silicon +# public license; you can redistribute it and/or modify it under +# the terms of the Libre Silicon public license as published by +# the Libre Silicon alliance, either version 1 of the License, or +# (at your option) any later version. +# +# This design is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the Libre Silicon Public License for more details. +# +# //////////////////////////////////////////////////////////////////// + +# ---------------------------------------------------------------- +# DESCRIPTION +# ---------------------------------------------------------------- + +# list all dependencies for cells with up to 2 stacked transistors + +# ---------------------------------------------------------------- +# CELL TARGETS +# ---------------------------------------------------------------- + +ifeq ($(BUFFER),2) + +# -------- now buffered ------------------------------------ + +CELLS += AAO22 \ + AND2 \ + AO21 \ + OA21 \ + OOA22 \ + OR2 + +AAO22: DESCR = "2-2-input AND-AND-OR gate" +AAO22: LEVEL = 2 +AAO22: AO21 + $(POPCORN) -m nand -c $@ $< > $@ + +AND2: DESCR = "2-input AND gate" +AND2: INV + $(POPCORN) -m nand -c $@ $< > $@ + +AO21: DESCR = "2-1-input AND-OR gate" +AO21: OR2 + $(POPCORN) -m aoi -c $@ $< > $@ + +OA21: DESCR = "2-1-input OR-AND gate" +OA21: AND2 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA22: DESCR = "2-2-input OR-OR-AND gate" +OOA22: LEVEL = 2 +OOA22: OA21 + $(POPCORN) -m nor -c $@ $< > $@ + +OR2: DESCR = "2-input OR gate" +OR2: INV + $(POPCORN) -m nor -c $@ $< > $@ + +BUFFERED = true + +else + +# -------- not buffered ------------------------------------ + +CELLS += AAOI22 \ + AOI21 \ + NAND2 \ + NOR2 \ + OAI21 \ + OOAI22 + +AAOI22: DESCR = "2-2-input AND-AND-OR-Invert gate" +AAOI22: LEVEL = 2 +AAOI22: AOI21 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOI21: DESCR = "2-1-input AND-OR-Invert gate" +AOI21: NOR2 + $(POPCORN) -m aoi -c $@ $< > $@ + +NAND2: DESCR = "2-input Not-AND (or NAND) gate" +NAND2: INV + $(POPCORN) -m nand -c $@ $< > $@ + +NOR2: DESCR = "2-input Not-OR (or NOR) gate" +NOR2: LEVEL = 2 +NOR2: INV + $(POPCORN) -m nor -c $@ $< > $@ + +OAI21: DESCR = "2-1-input OR-AND-Invert gate" +OAI21: NAND2 + $(POPCORN) -m oai -c $@ $< > $@ + +OOAI22: DESCR = "2-2-input OR-OR-AND-Invert gate" +OOAI22: LEVEL = 2 +OOAI22: OAI21 + $(POPCORN) -m nor -c $@ $< > $@ + +endif diff --git a/Catalog/stacked3_cells.mk b/Catalog/stacked3_cells.mk new file mode 100644 index 00000000..4b3f71af --- /dev/null +++ b/Catalog/stacked3_cells.mk @@ -0,0 +1,500 @@ +# ************ LibreSilicon's StdCellLibrary ******************* +# +# Organisation: Chipforge +# Germany / European Union +# +# Profile: Chipforge focus on fine System-on-Chip Cores in +# Verilog HDL Code which are easy understandable and +# adjustable. For further information see +# www.chipforge.org +# there are projects from small cores up to PCBs, too. +# +# File: StdCellLib/Catalog/stacked3_cells.mk +# +# Purpose: Makefile for Cell Generation with popcorn +# +# ************ GNU Make 3.80 Source Code **************** +# +# //////////////////////////////////////////////////////////////// +# +# Copyright (c) 2018, 2019 by +# chipforge - +# All rights reserved. +# +# This Standard Cell Library is licensed under the Libre Silicon +# public license; you can redistribute it and/or modify it under +# the terms of the Libre Silicon public license as published by +# the Libre Silicon alliance, either version 1 of the License, or +# (at your option) any later version. +# +# This design is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the Libre Silicon Public License for more details. +# +# //////////////////////////////////////////////////////////////////// + +# ---------------------------------------------------------------- +# DESCRIPTION +# ---------------------------------------------------------------- + +# list all dependencies for cells with 3 stacked transistors +# +include stacked2_cells.mk + +# ---------------------------------------------------------------- +# CELL TARGETS +# ---------------------------------------------------------------- + +ifdef BUFFERED + +# -------- already buffered -------------------------------- + +CELLS += AAAO332 \ + AAAO333 \ + AAO331 \ + AND3 \ + AO22 \ + AO31 \ + AO311 \ + AAO32 \ + AAO33 \ + AO331 \ + AO332 \ + AOA211 \ + AOA221 \ + AOAO2111 \ + AOOA212 \ + OA22 \ + OA31 \ + OA32 \ + OAO211 \ + OAO212 \ + OAO221 \ + OAOA2111 \ + OR3 \ + OOA32 \ + OOA321 \ + OOA33 \ + OOA331 \ + OOOA332 \ + OOOA333 + +AAAO332: DESCR = "3-3-2-input AND-AND-AND-OR gate" +AAAO332: LEVEL = 3 +AAAO332: AAAO331 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAAO333: DESCR = "3-3-3-input AND-AND-AND-OR gate" +AAAO333: LEVEL = 3 +AAAO333: AAAO332 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO331: DESCR = "3-3-1-input AND-AND-OR gate" +AAO331: LEVEL = 3 +AAO331: AAO321 + $(POPCORN) -m aoi -c $@ $< > $@ + +AND3: DESCR = "3-input AND gate" +AND3: AND2 + $(POPCORN) -m nand -c $(*F) -c $@ $< > $@ + +AO22: DESCR = "2-2-input AND-OR gate" +AO22: OR3 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO31: DESCR = "3-1-input AND-OR gate" +AO31: AO21 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO32: DESCR = "3-2-input AND-AND-OR gate" +AAO32: AAO22 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO321: DESCR = "3-2-1-input AND-OR gate" +AO321: AO221 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO33: DESCR = "3-3-input AND-AND-OR gate" +AAO33: LEVEL = 3 +AAO33: AAO32 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOA211: DESCR = "2-1-1-input AND-OR-AND gate" +AOA211: OA21 + $(POPCORN) -m nand -c $@ $< > $@ + +AOA221: DESCR = "2-2-1-input AND-OR-AND gate" +AOA221: OA31 + $(POPCORN) -m nand -c $@ $< > $@ + +AOAO2111: DESCR = "2-1-1-1-input AND-OR-AND-OR gate" +AOAO2111: OAO211 + $(POPCORN) -m nand -c $@ $< > $@ + +AOOA212: DESCR = "2-1-2-input AND-OR-OR-AND gate" +AOOA212: OOA22 + $(POPCORN) -m nand -c $@ $< > $@ + +OA22: DESCR = "2-2-input OR-AND gate" +OA22: AND3 + $(POPCORN) -m oai -c $@ $< > $@ + +OA31: DESCR = "3-1-input OR-AND gate" +OA31: OA21 + $(POPCORN) -m oai -c $@ $< > $@ + +OA32: DESCR = "3-2-input OR-AND gate" +OA32: OA22 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA32: DESCR = "3-2-input OR-OR-AND gate" +OOA32: OOA22 + $(POPCORN) -m oai -c $@ $< > $@ + +OAO211: DESCR = "2-1-1-input OR-AND-OR gate" +OAO211: AO21 + $(POPCORN) -m nor -c $@ $< > $@ + +OAO212: DESCR = "2-1-2-input OR-AND-OR gate" +OAO212: AO22 + $(POPCORN) -m nor -c $@ $< > $@ + +OAO221: DESCR = "2-2-1-input OR-AND-OR gate" +OAO221: AO31 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOA2111: DESCR = "2-1-1-1-input OR-AND-OR-AND gate" +OAOA2111: AOA211 + $(POPCORN) -m nor -c $@ $< > $@ + +OR3: DESCR = "3-input OR gate" +OR3: OR2 + $(POPCORN) -m nor -c $@ $< > $@ + +OOA321: DESCR = "3-2-1-input OR-OR-AND gate" +OOA321: OOA221 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA33: DESCR = "3-3-input OR-OR-AND gate" +OOA33: LEVEL = 3 +OOA33: OOA32 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA331: DESCR = "3-3-1-input OR-OR-AND gate" +OOA331: LEVEL = 3 +OOA331: OOA321 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOA332: DESCR = "3-3-2-input OR-OR-OR-AND gate" +OOOA332: LEVEL = 3 +OOOA332: OOA331 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOA333: DESCR = "3-3-3-input OR-OR-OR-AND gate" +OOOA333: LEVEL = 3 +OOOA333: OOOA332 + $(POPCORN) -m oai -c $@ $< > $@ + +else +ifeq ($(BUFFER),3) + +# -------- now buffered ------------------------------------ + +CELLS += AAAO332 \ + AAAO333 \ + AAO331 \ + AND3 \ + AO31 \ + AO311 \ + AAO32 \ + AO33 \ + AO331 \ + AO332 \ + AOA211 \ + AOA221 \ + AOAO2111 \ + AOOA212 \ + OA22 \ + OA31 \ + OA32 \ + OAO211 \ + OAO212 \ + OAO221 \ + OAOA2111 \ + OR3 \ + OOA32 \ + OOA321 \ + OOA33 \ + OOA331 \ + OOOA332 \ + OOOA333 + +AAAO332: DESCR = "3-3-2-input AND-AND-AND-OR gate" +AAAO332: LEVEL = 3 +AAAO332: AAAO331 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAAO333: DESCR = "3-3-3-input AND-AND-AND-OR gate" +AAAO333: LEVEL = 3 +AAAO333: AAAO332 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO331: DESCR = "3-3-1-input AND-AND-OR gate" +AAO331: LEVEL = 3 +AAO331: AAO321 + $(POPCORN) -m aoi -c $@ $< > $@ + +AND3: DESCR = "3-input AND gate" +AND3: NAND2 + $(POPCORN) -m nand -c $@ $< > $@ + +AO22: DESCR = "2-2-input AND-OR gate" +AO22: OR3 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO31: DESCR = "3-1-input AND-OR gate" +AO31: AOI21 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO32: DESCR = "3-2-input AND-AND-OR gate" +AAO32: AAOI22 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO321: DESCR = "3-2-1-input AND-OR gate" +AO321: AO221 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAO33: DESCR = "3-3-input AND-AND-OR gate" +AAO33: LEVEL = 3 +AAO33: AAO32 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOA211: DESCR = "2-1-1-input AND-OR-AND gate" +AOA211: OAI21 + $(POPCORN) -m nand -c $@ $< > $@ + +AOA221: DESCR = "2-2-1-input AND-OR-AND gate" +AOA221: OA31 + $(POPCORN) -m nand -c $@ $< > $@ + +AOAO2111: DESCR = "2-1-1-1-input AND-OR-AND-OR gate" +AOAO2111: OAO211 + $(POPCORN) -m nand -c $@ $< > $@ + +AOOA212: DESCR = "2-1-2-input AND-OR-OR-AND gate" +AOOA212: OOAI22 + $(POPCORN) -m nand -c $@ $< > $@ + +OA22: DESCR = "2-2-input OR-AND gate" +OA22: AND3 + $(POPCORN) -m oai -c $@ $< > $@ + +OA31: DESCR = "3-1-input OR-AND gate" +OA31: OAI21 + $(POPCORN) -m oai -c $@ $< > $@ + +OA32: DESCR = "3-2-input OR-AND gate" +OA32: OA22 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA32: DESCR = "3-2-input OR-OR-AND gate" +OOA32: OOAI22 + $(POPCORN) -m oai -c $@ $< > $@ + +OAO211: DESCR = "2-1-1-input OR-AND-OR gate" +OAO211: AOI21 + $(POPCORN) -m nor -c $@ $< > $@ + +OAO212: DESCR = "2-1-2-input OR-AND-OR gate" +OAO212: AOI22 + $(POPCORN) -m nor -c $@ $< > $@ + +OAO221: DESCR = "2-2-1-input OR-AND-OR gate" +OAO221: AO31 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOA2111: DESCR = "2-1-1-1-input OR-AND-OR-AND gate" +OAOA2111: AOA211 + $(POPCORN) -m nor -c $@ $< > $@ + +OR3: DESCR = "3-input OR gate" +OR3: NOR2 + $(POPCORN) -m nor -c $@ $< > $@ + +OOA321: DESCR = "3-2-1-input OR-OR-AND gate" +OOA321: OOA221 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA33: DESCR = "3-3-input OR-OR-AND gate" +OOA33: LEVEL = 3 +OOA33: OOA32 + $(POPCORN) -m oai -c $@ $< > $@ + +OOA331: DESCR = "3-3-1-input OR-OR-AND gate" +OOA331: LEVEL = 3 +OOA331: OOA321 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOA332: DESCR = "3-3-2-input OR-OR-OR-AND gate" +OOOA332: LEVEL = 3 +OOOA332: OOA331 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOA333: DESCR = "3-3-3-input OR-OR-OR-AND gate" +OOOA333: LEVEL = 3 +OOOA333: OOOA332 + $(POPCORN) -m oai -c $@ $< > $@ + +BUFFERED = true + +else + +# -------- not buffered ------------------------------------ + +CELLS += AAAOI332 \ + AAAOI333 \ + AAOI321 \ + AAOI331 \ + AOAI211 \ + AOAI221 \ + AOAOI2111 \ + AOI211 \ + AOI31 \ + AAOI32 \ + AAOI33 \ + AOOAI212 \ + NAND3 \ + NOR3 \ + OAI22 \ + OAI31 \ + OAI32 \ + OAOAI2111 \ + OAOI211 \ + OAOI212 \ + OAOI221 \ + OOAI32 \ + OOAI321 \ + OOAI33 \ + OOAI331 \ + OOOAI332 \ + OOOOAI333 + +AAAOI332: DESCR = "3-3-2-input AND-AND-AND-OR-Invert gate" +AAAOI332: LEVEL = 3 +AAAOI332: AAOI331 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAAOI333: DESCR = "3-3-3-input AND-AND-AND-OR-Invert gate" +AAAOI333: LEVEL = 3 +AAAOI333: AAAOI332 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAOI331: DESCR = "3-3-1-input AND-AND-OR-Invert gate" +AAOI331: LEVEL = 3 +AAOI331: AAOI321 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOAI211: DESCR = "2-1-1-input AND-OR-AND-Invert gate" +AOAI211: OAI21 + $(POPCORN) -m nand -c $@ $< > $@ + +AOAI221: DESCR = "2-2-1-input AND-OR-AND-Invert gate" +AOAI221: OAI31 + $(POPCORN) -m nand -c $@ $< > $@ + +AOAOI2111: DESCR = "2-1-1-1-input AND-OR-AND-OR-Invert gate" +AOAOI2111: OAOI211 + $(POPCORN) -m nand -c $@ $< > $@ + +AOI22: DESCR = "2-2-input AND-OR-Invert gate" +AOI22: NOR3 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOI31: DESCR = "3-1-input AND-OR-Invert gate" +AOI31: AOI21 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAOI32: DESCR = "3-2-input AND-AND-OR-Invert gate" +AAOI32: AAOI22 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAOI321: DESCR = "3-2-1-input AND-AND-OR-Invert gate" +AAOI321: AAOI221 + $(POPCORN) -m aoi -c $@ $< > $@ + +AAOI33: DESCR = "3-3-input AND-AND-OR-Invert gate" +AAOI33: LEVEL = 3 +AAOI33: AAOI32 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOOAI212: DESCR = "2-1-2-input AND-OR-OR-AND-Invert gate" +AOOAI212: OOAI22 + $(POPCORN) -m nand -c $@ $< > $@ + +NAND3: DESCR = "3-input Not-AND (or NAND) gate" +NAND3: NAND2 + $(POPCORN) -m nand -c $@ $< > $@ + +NOR3: DESCR = "3-input Not-OR (or NOR) gate" +NOR3: NOR2 + $(POPCORN) -m nor -c $@ $< > $@ + +OAI22: DESCR = "2-2-input OR-AND-Invert gate" +OAI22: NAND3 + $(POPCORN) -m oai -c $@ $< > $@ + +OAI31: DESCR = "3-1-input OR-AND-Invert gate" +OAI31: OAI21 + $(POPCORN) -m oai -c $@ $< > $@ + +OAI32: DESCR = "3-2-input OR-AND-Invert gate" +OAI32: OAI22 + $(POPCORN) -m oai -c $@ $< > $@ + +OOAI32: DESCR = "3-2-input OR-OR-AND-Invert gate" +OOAI32: OOAI22 + $(POPCORN) -m oai -c $@ $< > $@ + +OAOAI2111: DESCR = "2-1-1-1-input OR-AND-OR-AND-Invert gate" +OAOAI2111: AOAI211 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOI211: DESCR = "2-1-1-input OR-AND-OR-Invert gate" +OAOI211: AOI21 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOI212: DESCR = "2-1-2-input OR-AND-OR-Invert gate" +OAOI212: AOI22 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOI221: DESCR = "2-2-1-input OR-AND-OR-Invert gate" +OAOI221: AOI31 + $(POPCORN) -m nor -c $@ $< > $@ + +OOAI321: DESCR = "3-2-1-input OR-OR-AND-Invert gate" +OOAI321: OOAI221 + $(POPCORN) -m oai -c $@ $< > $@ + +OOAI33: DESCR = "3-3-input OR-OR-AND-Invert gate" +OOAI33: LEVEL = 3 +OOAI33: OOAI32 + $(POPCORN) -m oai -c $@ $< > $@ + +OOAI331: DESCR = "3-3-1-input OR-OR-AND-Invert gate" +OOAI331: LEVEL = 3 +OOAI331: OOAI321 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOAI332: DESCR = "3-3-2-input OR-OR-OR-AND-Invert gate" +OOOAI332: LEVEL = 3 +OOOAI332: OOAI331 + $(POPCORN) -m oai -c $@ $< > $@ + +OOOAI333: DESCR = "3-3-3-input OR-OR-OR-AND-Invert gate" +OOOAI333: LEVEL = 3 +OOOAI333: OOOAI332 + $(POPCORN) -m oai -c $@ $< > $@ + +endif +endif diff --git a/Catalog/stacked4_cells.mk b/Catalog/stacked4_cells.mk new file mode 100644 index 00000000..4cf6b22e --- /dev/null +++ b/Catalog/stacked4_cells.mk @@ -0,0 +1,275 @@ +# ************ LibreSilicon's StdCellLibrary ******************* +# +# Organisation: Chipforge +# Germany / European Union +# +# Profile: Chipforge focus on fine System-on-Chip Cores in +# Verilog HDL Code which are easy understandable and +# adjustable. For further information see +# www.chipforge.org +# there are projects from small cores up to PCBs, too. +# +# File: StdCellLib/Catalog/stacked4_cells.mk +# +# Purpose: Makefile for Cell Generation with popcorn +# +# ************ GNU Make 3.80 Source Code **************** +# +# //////////////////////////////////////////////////////////////// +# +# Copyright (c) 2018, 2019 by +# chipforge - +# All rights reserved. +# +# This Standard Cell Library is licensed under the Libre Silicon +# public license; you can redistribute it and/or modify it under +# the terms of the Libre Silicon public license as published by +# the Libre Silicon alliance, either version 1 of the License, or +# (at your option) any later version. +# +# This design is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the Libre Silicon Public License for more details. +# +# //////////////////////////////////////////////////////////////////// + +# ---------------------------------------------------------------- +# DESCRIPTION +# ---------------------------------------------------------------- + +# list all dependencies for cells with 4 stacked transistors +# +include stacked3_cells.mk + +# ---------------------------------------------------------------- +# CELL TARGETS +# ---------------------------------------------------------------- + +# -------- already buffered -------------------------------- + +ifdef BUFFERED + +CELLS += AND4 \ + AO23 \ + AO41 \ + AOA212 \ + AOA311 \ + OA22 \ + OA23 \ + OA3111 \ + OA41 \ + OA4111 \ + OAO2111 \ + OAO311 \ + OAOA2211 \ + OAOA3211 \ + OR4 + +AND4: DESCR = "4-input AND gate" +AND4: AND3 + $(POPCORN) -m nand -c $@ $< > $@ + +AO23: DESCR = "2-3-input AND-OR gate" +AO23: OR4 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO41: DESCR = "4-1-input AND-OR gate" +AO41: AO31 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOA212: DESCR = "2-1-2-input AND-OR-AND gate" +AOA212: OA22 + $(POPCORN) -m nand -c $@ $< > $@ + +AOA311: DESCR = "3-1-1-input AND-OR-AND gate" +AOA311: AOA211 + $(POPCORN) -m aoi -c $@ $< > $@ + +OA22: DESCR = "2-2-input OR-AND gate" +OA22: AND3 + $(POPCORN) -m oai -c $@ $< > $@ + +OA23: DESCR = "2-3-input OR-AND gate" +OA23: AND4 + $(POPCORN) -m oai -c $@ $< > $@ + +OA33: DESCR = "3-3-input OR-AND gate" +OA33: OA23 + $(POPCORN) -m oai -c $@ $< > $@ + +OA41: DESCR = "4-1-input OR-AND gate" +OA41: OA31 + $(POPCORN) -m oai -c $@ $< > $@ + +OA43: DESCR = "4-3-input OR-AND gate" +OA43: OA33 + $(POPCORN) -m oai -c $@ $< > $@ + +OAO311: DESCR = "3-1-1-input OR-AND-OR gate" +OAO311: OAO211 + $(POPCORN) -m oai -c $@ $< > $@ + +OAOA2211: DESCR = "2-2-1-1-input OR-AND-OR-AND gate" +OAOA2211: AOA311 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOA3211: DESCR = "3-2-1-1-input OR-AND-OR-AND gate" +OAOA3211: OAOA2211 + $(POPCORN) -m oai -c $@ $< > $@ + +OR4: DESCR = "4-input OR gate" +OR4: OR3 + $(POPCORN) -m nor -c $@ $< > $@ + +# -------- now buffered ------------------------------------ + +else +ifeq ($(BUFFER),4) + +CELLS += AND4 \ + AO23 \ + AO41 \ + AOA212 \ + AOA311 \ + OA22 \ + OA23 \ + OA3111 \ + OA41 \ + OA4111 \ + OAO2111 \ + OAO311 \ + OAOA2211 \ + OAOA3211 \ + OR4 + +AND4: DESCR = "4-input AND gate" +AND4: NAND3 + $(POPCORN) -m nand -c $@ $< > $@ + +AO23: DESCR = "2-3-input AND-OR gate" +AO23: OR4 + $(POPCORN) -m aoi -c $@ $< > $@ + +AO41: DESCR = "4-1-input AND-OR gate" +AO41: AOI31 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOA212: DESCR = "2-1-2-input AND-OR-AND gate" +AOA212: OAI22 + $(POPCORN) -m nand -c $@ $< > $@ + +AOA311: DESCR = "3-1-1-input AND-OR-AND gate" +AOA311: AOAI211 + $(POPCORN) -m aoi -c $@ $< > $@ + +OA22: DESCR = "2-2-input OR-AND gate" +OA22: AND3 + $(POPCORN) -m oai -c $@ $< > $@ + +OA23: DESCR = "2-3-input OR-AND gate" +OA23: AND4 + $(POPCORN) -m oai -c $@ $< > $@ + +OA33: DESCR = "3-3-input OR-AND gate" +OA33: OA23 + $(POPCORN) -m oai -c $@ $< > $@ + +OA41: DESCR = "4-1-input OR-AND gate" +OA41: OAI31 + $(POPCORN) -m oai -c $@ $< > $@ + +OA43: DESCR = "4-3-input OR-AND gate" +OA43: OA33 + $(POPCORN) -m oai -c $@ $< > $@ + +OAO311: DESCR = "3-1-1-input OR-AND-OR gate" +OAO311: OAOI211 + $(POPCORN) -m oai -c $@ $< > $@ + +OAOA2211: DESCR = "2-2-1-1-input OR-AND-OR-AND gate" +OAOA2211: AOA311 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOA3211: DESCR = "3-2-1-1-input OR-AND-OR-AND gate" +OAOA3211: OAOA2211 + $(POPCORN) -m oai -c $@ $< > $@ + +OR4: DESCR = "4-input OR gate" +OR4: NOR3 + $(POPCORN) -m nor -c $@ $< > $@ + +BUFFERED = true + +# -------- not buffered ------------------------------------ + +else + +CELLS += AOAI212 \ + AOAI311 \ + AOI23 \ + AOI41 \ + NAND4 \ + NOR4 \ + OAI23 \ + OAI3111 \ + OAI41 \ + OAI4111 \ + OAOAI2211 \ + OAOAI3211 \ + OAOI311 + +AOAI212: DESCR = "2-1-2-input AND-OR-AND-Invert gate" +AOAI212: OAI22 + $(POPCORN) -m nand -c $@ $< > $@ + +AOAI311: DESCR = "3-1-1-input AND-OR-AND-Invert gate" +AOAI311: AOAI211 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOI23: DESCR = "2-3-input AND-OR-Invert gate" +AOI23: NOR4 + $(POPCORN) -m aoi -c $@ $< > $@ + +AOI41: DESCR = "4-1-input AND-OR-Invert gate" +AOI41: AOI31 + $(POPCORN) -m aoi -c $@ $< > $@ + +NAND4: DESCR = "4-input Not-AND (or NAND) gate" +NAND4: NAND3 + $(POPCORN) -m nand -c $@ $< > $@ + +NOR4: DESCR = "4-input Not-OR (or NOR) gate" +NOR4: NOR3 + $(POPCORN) -m nor -c $@ $< > $@ + +OAI23: DESCR = "2-3-input OR-AND-Invert gate" +OAI23: NAND4 + $(POPCORN) -m oai -c $@ $< > $@ + +OAI41: DESCR = "4-1-input OR-AND-Invert gate" +OAI41: OAI31 + $(POPCORN) -m oai -c $@ $< > $@ + +OAI33: DESCR = "3-1-input OR-AND-Invert gate" +OAI33: OAI23 + $(POPCORN) -m oai -c $@ $< > $@ + +OAI43: DESCR = "4-3-input OR-AND-Invert gate" +OAI43: OAI33 + $(POPCORN) -m oai -c $@ $< > $@ + +OAOAI2211: DESCR = "2-2-1-1-input OR-AND-OR-AND-Invert gate" +OAOAI2211: AOAI311 + $(POPCORN) -m nor -c $@ $< > $@ + +OAOAI3211: DESCR = "3-2-1-1-input OR-AND-OR-AND-Invert gate" +OAOAI3211: OAOAI2211 + $(POPCORN) -m oai -c $@ $< > $@ + +OAOI311: DESCR = "3-1-1-input OR-AND-OR-Invert gate" +OAOI311: OAOI211 + $(POPCORN) -m oai -c $@ $< > $@ + +endif +endif diff --git a/Catalog/stacked5_cells.mk b/Catalog/stacked5_cells.mk new file mode 100644 index 00000000..589056b9 --- /dev/null +++ b/Catalog/stacked5_cells.mk @@ -0,0 +1,92 @@ +# ************ LibreSilicon's StdCellLibrary ******************* +# +# Organisation: Chipforge +# Germany / European Union +# +# Profile: Chipforge focus on fine System-on-Chip Cores in +# Verilog HDL Code which are easy understandable and +# adjustable. For further information see +# www.chipforge.org +# there are projects from small cores up to PCBs, too. +# +# File: StdCellLib/Catalog/stacked5_cells.mk +# +# Purpose: Makefile for Cell Generation with popcorn +# +# ************ GNU Make 3.80 Source Code **************** +# +# //////////////////////////////////////////////////////////////// +# +# Copyright (c) 2018, 2019 by +# chipforge - +# All rights reserved. +# +# This Standard Cell Library is licensed under the Libre Silicon +# public license; you can redistribute it and/or modify it under +# the terms of the Libre Silicon public license as published by +# the Libre Silicon alliance, either version 1 of the License, or +# (at your option) any later version. +# +# This design is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +# See the Libre Silicon Public License for more details. +# +# //////////////////////////////////////////////////////////////////// + +# ---------------------------------------------------------------- +# DESCRIPTION +# ---------------------------------------------------------------- + +# list all dependencies for cells with 5 stacked transistors +# +include stacked4_cells.mk + +# ---------------------------------------------------------------- +# CELL TARGETS +# ---------------------------------------------------------------- + +# -------- already buffered -------------------------------- + +ifdef BUFFERED + +CELLS += AND5 \ + OR5 + +AND5: AND4 + $(POPCORN) -m nand -c $@ $< > $@ + +OR5: OR4 + $(POPCORN) -m nor -c $@ $< > $@ + +# -------- now buffered ------------------------------------ + +else +ifeq ($(BUFFER),5) + +CELLS += AND5 \ + OR5 + +AND5: NAND4 + $(POPCORN) -m nand -c $@ $< > $@ + +OR5: NOR4 + $(POPCORN) -m nor -c $@ $< > $@ + +BUFFERED = true + +# -------- not buffered ------------------------------------ + +else + +CELLS += NAND5 \ + NOR5 + +NAND5: NAND4 + $(POPCORN) -m nand -c $@ $< > $@ + +NOR5: NOR4 + $(POPCORN) -m nor -c $@ $< > $@ + +endif +endif diff --git a/Docker/Dockerfile b/Docker/Dockerfile new file mode 100644 index 00000000..28ef09be --- /dev/null +++ b/Docker/Dockerfile @@ -0,0 +1,63 @@ +#docker pull ubuntu:20.10 + +FROM ubuntu:20.10 as build + +ENV TZ=Europe/Vienna +ENV LANG=C.UTF-8 + +RUN apt update --fix-missing +RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone +#RUN apt-get update && apt-get -y install npm blender texlive-full inkscape kicad iverilog gtkwave lsb + +RUN apt-get update && apt-get -y install qflow imagemagick libcairo2-dev tcllib tklib make g++ libreadline-dev python3-cairosvg python3 python3-numpy libblas-dev ngspice z3 tcl8.6-dev tk8.6-dev python3-scipy python3-matplotlib texlive-latex-recommended unzip glpk-utils libglpk-dev python3-pulp git wget gauche python3-toml python3-pytoml python3-pip mmv libglu1-mesa-dev libcurl4-gnutls-dev pdf2svg python3-yaml python3-cffi python3-pyparsing python3-certifi tcl magic libsqlite3-dev python3-setuptools python3-networkx python3-sympy +RUN apt-get -y install libngspice0 libngspice0-dev python3-gdspy python3-kiwisolver +#RUN apt-get -y install klayout libopengl-dev opensta opensta-dev +#RUN apt-get -y install python-z3 +RUN apt-get -y install python3-z3 + +#RUN apt --fix-broken install +#RUN apt --fix-missing + +RUN pip3 install PySpice + +RUN git clone https://github.com/KLayout/klayout +WORKDIR klayout +RUN python3 setup.py build --parallel 1 +RUN python3 setup.py install +WORKDIR .. + +RUN wget -c http://www.taylorgruppe.de/circdia/circdia.zip +RUN mkdir -p /usr/share/texlive/texmf-dist/tex/circdia +RUN unzip -u -o -d /usr/share/texlive/texmf-dist/tex/circdia circdia.zip +RUN mktexlsr + +RUN git clone https://codeberg.org/tok/librecell +WORKDIR librecell/librecell-common +RUN python3 setup.py install +WORKDIR ../.. +WORKDIR librecell/librecell-meta +RUN python3 setup.py install +WORKDIR ../.. +WORKDIR librecell/librecell-lib +RUN python3 setup.py install +WORKDIR ../.. +WORKDIR librecell/librecell-layout +RUN python3 setup.py install +WORKDIR ../.. + +RUN wget -c http://www.taylorgruppe.de/circdia/circdia.zip +RUN mkdir -p /usr/share/texlive/texmf-dist/tex/circdia +RUN unzip -u -o -d /usr/share/texlive/texmf-dist/tex/circdia circdia.zip +RUN mktexlsr + +RUN git clone https://github.com/thesourcerer8/StdCellLib +WORKDIR StdCellLib/Catalog +#RUN make catalog +RUN make importQflow + +RUN rm /usr/local/lib/python3.8/dist-packages/PySMT-0.9.1.dev86-py3.8.egg/six.py + +#echo "Installation of the StdCellLib is finished." +#echo "To build a whole standard cell library you can now run:" +#echo "make layout ; make doc ; perl ../Tools/perl/buildreport.pl ; cd .. ; make dist" +#sudo make qflow diff --git a/Docker/bash.sh b/Docker/bash.sh new file mode 100644 index 00000000..181893a3 --- /dev/null +++ b/Docker/bash.sh @@ -0,0 +1 @@ +docker run -it thesourcerer8/stdcelllib /bin/bash diff --git a/Docker/build.sh b/Docker/build.sh new file mode 100644 index 00000000..74b0ca9a --- /dev/null +++ b/Docker/build.sh @@ -0,0 +1 @@ +docker build --tag thesourcerer8/stdcelllib . diff --git a/Documents/LaTeX/AAAO222_circuit.tex b/Documents/LaTeX/AAAO222_circuit.tex new file mode 100644 index 00000000..5a6b86fb --- /dev/null +++ b/Documents/LaTeX/AAAO222_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO222_circuit.tex +%% +%% Purpose: Circuit File for AAAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/BUF_manpage.tex b/Documents/LaTeX/AAAO222_manpage.tex similarity index 83% rename from Documents/LaTeX/BUF_manpage.tex rename to Documents/LaTeX/AAAO222_manpage.tex index b1f0df5d..ffc5c194 100644 --- a/Documents/LaTeX/BUF_manpage.tex +++ b/Documents/LaTeX/AAAO222_manpage.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_BUF.tex +%% File: StdCellLib/Documents/LaTeX/AAAO222_manpage.tex %% -%% Purpose: Manual Page File for BUF +%% Purpose: Manual Page File for AAAO222 %% %% ************ LaTeX with circdia.sty package *************** %% @@ -32,23 +32,23 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{BUF} +\label{AAAO222} \paragraph{Cell} \begin{quote} - \textbf{BUF} - a Buffer gate + \textbf{AAAO222} - a 2-2-2-input AND-AND-AND-OR gate \end{quote} \paragraph{Synopsys} \begin{quote} - BUF(Z, A) + AAAO222(Z, C1, C, B1, B, A1, A) \end{quote} \paragraph{Description} -\input{BUF_circuit.tex} -\input{BUF_schematic.tex} +\input{AAAO222_circuit.tex} +%\input{AAAO222_schematic.tex} \paragraph{Truth Table} -\input{BUF_truthtable.tex} +%\input{AAAO222_truthtable.tex} \paragraph{Usage} @@ -57,8 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - INV - a Not (or Inverter) gate -\end{quote} diff --git a/Documents/LaTeX/AOI222_circuit.tex b/Documents/LaTeX/AAAO322_circuit.tex similarity index 67% rename from Documents/LaTeX/AOI222_circuit.tex rename to Documents/LaTeX/AAAO322_circuit.tex index a21fadc3..a317a54e 100644 --- a/Documents/LaTeX/AOI222_circuit.tex +++ b/Documents/LaTeX/AAAO322_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI222.tex +%% File: StdCellLib/Documents/LaTeX/AAAO322_circuit.tex %% -%% Purpose: Circuit File for AOI222 +%% Purpose: Circuit File for AAAO322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,25 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{11}{L}{B1} % pin B1 - \pin{1}{13}{L}{C0} % pin C0 - \pin{1}{17}{L}{C1} % pin C1 - \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{15}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR gate -> right + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 \wire{9}{3}{9}{7} % wire between AND and NOR \wire{9}{11}{9}{15} % wire between AND and NOR - \pin{17}{9}{R}{Z} % pin Z + \pin{23}{9}{R}{Z} % pin Z \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAAO322_manpage.tex b/Documents/LaTeX/AAAO322_manpage.tex new file mode 100644 index 00000000..7d6b4ce3 --- /dev/null +++ b/Documents/LaTeX/AAAO322_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO322_manpage.tex +%% +%% Purpose: Manual Page File for AAAO322 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAO322} +\paragraph{Cell} +\begin{quote} + \textbf{AAAO322} - a 3-2-2-input AND-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAO322(Z, C2, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAO322_circuit.tex} +%\input{AAAO322_schematic.tex} + +\paragraph{Truth Table} +%\input{AAAO322_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAAO332_circuit.tex b/Documents/LaTeX/AAAO332_circuit.tex new file mode 100644 index 00000000..f0d1ca25 --- /dev/null +++ b/Documents/LaTeX/AAAO332_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO332_circuit.tex +%% +%% Purpose: Circuit File for AAAO332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAAO332_manpage.tex b/Documents/LaTeX/AAAO332_manpage.tex new file mode 100644 index 00000000..1d101556 --- /dev/null +++ b/Documents/LaTeX/AAAO332_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO332_manpage.tex +%% +%% Purpose: Manual Page File for AAAO332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAO332} +\paragraph{Cell} +\begin{quote} + \textbf{AAAO332} - a 3-3-2-input AND-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAO332(Z, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAO332_circuit.tex} +%\input{AAAO332_schematic.tex} + +\paragraph{Truth Table} +%\input{AAAO332_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAAO333_circuit.tex b/Documents/LaTeX/AAAO333_circuit.tex new file mode 100644 index 00000000..1d08247b --- /dev/null +++ b/Documents/LaTeX/AAAO333_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO333_circuit.tex +%% +%% Purpose: Circuit File for AAAO333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAAO333_manpage.tex b/Documents/LaTeX/AAAO333_manpage.tex new file mode 100644 index 00000000..5dc30992 --- /dev/null +++ b/Documents/LaTeX/AAAO333_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO333_manpage.tex +%% +%% Purpose: Manual Page File for AAAO333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAO333} +\paragraph{Cell} +\begin{quote} + \textbf{AAAO333} - a 3-3-3-input AND-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAO333(Z, C2, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAO333_circuit.tex} +%\input{AAAO333_schematic.tex} + +\paragraph{Truth Table} +%\input{AAAO333_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAAO432_circuit.tex b/Documents/LaTeX/AAAO432_circuit.tex new file mode 100644 index 00000000..d3af138e --- /dev/null +++ b/Documents/LaTeX/AAAO432_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO432_circuit.tex +%% +%% Purpose: Circuit File for AAAO432 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{16}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \pin{1}{19}{L}{C3} % pin C3 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{16} % wire between AND and NOR + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAAO432_manpage.tex b/Documents/LaTeX/AAAO432_manpage.tex new file mode 100644 index 00000000..c6951b42 --- /dev/null +++ b/Documents/LaTeX/AAAO432_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAO432_manpage.tex +%% +%% Purpose: Manual Page File for AAAO432 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAO432} +\paragraph{Cell} +\begin{quote} + \textbf{AAAO432} - a 4-3-2-input AND-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAO432(Z, C3, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAO432_circuit.tex} +%\input{AAAO432_schematic.tex} + +\paragraph{Truth Table} +%\input{AAAO432_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAAOI222_circuit.tex b/Documents/LaTeX/AAAOI222_circuit.tex new file mode 100644 index 00000000..dd286353 --- /dev/null +++ b/Documents/LaTeX/AAAOI222_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI222_circuit.tex +%% +%% Purpose: Circuit File for AAAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{18} + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{17}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA2111_manpage.tex b/Documents/LaTeX/AAAOI222_manpage.tex similarity index 80% rename from Documents/LaTeX/OA2111_manpage.tex rename to Documents/LaTeX/AAAOI222_manpage.tex index 2b86141d..dcda7b25 100644 --- a/Documents/LaTeX/OA2111_manpage.tex +++ b/Documents/LaTeX/AAAOI222_manpage.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OA2111.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI222_manpage.tex %% -%% Purpose: Manual Page File for OA2111 +%% Purpose: Manual Page File for AAAOI222 %% %% ************ LaTeX with circdia.sty package *************** %% @@ -32,23 +32,23 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{OA2111} +\label{AAAOI222} \paragraph{Cell} \begin{quote} - \textbf{OA2111} - a 2-1-1-1-input OR-AND gate + \textbf{AAAOI222} - a 2-2-2-input AND-AND-AND-OR-Invert gate \end{quote} \paragraph{Synopsys} \begin{quote} - OA2111(Z, D1, D0, C, B, A) + AAAOI222(Z, C1, C, B1, B, A1, A) \end{quote} \paragraph{Description} -\input{OA2111_circuit.tex} -%\input{OA2111_schematic.tex} +\input{AAAOI222_circuit.tex} +\input{AAAOI222_schematic.tex} \paragraph{Truth Table} -\input{OA2111_truthtable.tex} +\input{AAAOI222_truthtable.tex} \paragraph{Usage} @@ -57,8 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - OA3111 - a 3-1-1-1-input AND-OR gate -\end{quote} diff --git a/Documents/LaTeX/AOI222_schematic.tex b/Documents/LaTeX/AAAOI222_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI222_schematic.tex rename to Documents/LaTeX/AAAOI222_schematic.tex index 894d2c9a..c7c3659f 100644 --- a/Documents/LaTeX/AOI222_schematic.tex +++ b/Documents/LaTeX/AAAOI222_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI222.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI222_schematic.tex %% -%% Purpose: Schematic File for AOI222 +%% Purpose: Schematic File for AAAOI222 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI222_truthtable.tex b/Documents/LaTeX/AAAOI222_truthtable.tex similarity index 92% rename from Documents/LaTeX/AOI222_truthtable.tex rename to Documents/LaTeX/AAAOI222_truthtable.tex index 987547ee..02c01f66 100644 --- a/Documents/LaTeX/AOI222_truthtable.tex +++ b/Documents/LaTeX/AAAOI222_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI222.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI222_truthtable.tex %% -%% Purpose: Truth Table File for AOI222 +%% Purpose: Truth Table File for AAAOI222 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI322_circuit.tex b/Documents/LaTeX/AAAOI322_circuit.tex similarity index 72% rename from Documents/LaTeX/AOI322_circuit.tex rename to Documents/LaTeX/AAAOI322_circuit.tex index 6da4cee1..e162aa45 100644 --- a/Documents/LaTeX/AOI322_circuit.tex +++ b/Documents/LaTeX/AAAOI322_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI322.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI322_circuit.tex %% -%% Purpose: Circuit File for AOI322 +%% Purpose: Circuit File for AAAOI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,23 +34,24 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{11}{L}{B1} % pin B1 - \pin{1}{13}{L}{C0} % pin C0 + \pin{1}{13}{L}{C} % pin C \pin{1}{15}{L}{C1} % pin C1 \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR gate -> right \wire{9}{3}{9}{7} % wire between AND and NOR \wire{9}{11}{9}{15} % wire between AND and NOR - \pin{17}{9}{R}{Z} % pin Z + \pin{17}{9}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAAOI322_manpage.tex b/Documents/LaTeX/AAAOI322_manpage.tex new file mode 100644 index 00000000..fecb2e58 --- /dev/null +++ b/Documents/LaTeX/AAAOI322_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI322_manpage.tex +%% +%% Purpose: Manual Page File for AAAOI322 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAOI322} +\paragraph{Cell} +\begin{quote} + \textbf{AAAOI322} - a 3-2-2-input AND-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAOI322(Z, C2, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAOI322_circuit.tex} +\input{AAAOI322_schematic.tex} + +\paragraph{Truth Table} +\input{AAAOI322_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI322_schematic.tex b/Documents/LaTeX/AAAOI322_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI322_schematic.tex rename to Documents/LaTeX/AAAOI322_schematic.tex index 278bb29f..700dc3f1 100644 --- a/Documents/LaTeX/AOI322_schematic.tex +++ b/Documents/LaTeX/AAAOI322_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI322.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI322_schematic.tex %% -%% Purpose: Schematic File for AOI322 +%% Purpose: Schematic File for AAAOI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI322_truthtable.tex b/Documents/LaTeX/AAAOI322_truthtable.tex similarity index 93% rename from Documents/LaTeX/AOI322_truthtable.tex rename to Documents/LaTeX/AAAOI322_truthtable.tex index de2b60d1..45aa6a9d 100644 --- a/Documents/LaTeX/AOI322_truthtable.tex +++ b/Documents/LaTeX/AAAOI322_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI322.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI322_truthtable.tex %% -%% Purpose: Truth Table File for AOI322 +%% Purpose: Truth Table File for AAAOI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI332_circuit.tex b/Documents/LaTeX/AAAOI332_circuit.tex similarity index 68% rename from Documents/LaTeX/AOI332_circuit.tex rename to Documents/LaTeX/AAAOI332_circuit.tex index 1d95d9ab..dd319dd6 100644 --- a/Documents/LaTeX/AOI332_circuit.tex +++ b/Documents/LaTeX/AAAOI332_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI332.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI332_circuit.tex %% -%% Purpose: Circuit File for AOI332 +%% Purpose: Circuit File for AAAOI332 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,24 +34,25 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{9}{L}{B1} % pin B1 \pin{1}{11}{L}{B2} % pin B2 - \pin{1}{13}{L}{C0} % pin C0 + \pin{1}{13}{L}{C} % pin C \pin{1}{15}{L}{C1} % pin C1 \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR gate -> right - \wire{9}{3}{9}{7} % wire between AND and NOR - \wire{9}{11}{9}{15} % wire between AND and NOR - \pin{17}{9}{R}{Z} % pin Z + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{17}{9}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAAOI332_manpage.tex b/Documents/LaTeX/AAAOI332_manpage.tex new file mode 100644 index 00000000..6269d1f6 --- /dev/null +++ b/Documents/LaTeX/AAAOI332_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI332_manpage.tex +%% +%% Purpose: Manual Page File for AAAOI332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAOI332} +\paragraph{Cell} +\begin{quote} + \textbf{AAAOI332} - a 3-3-2-input AND-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAOI332(Z, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAOI332_circuit.tex} +\input{AAAOI332_schematic.tex} + +\paragraph{Truth Table} +\input{AAAOI332_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI332_schematic.tex b/Documents/LaTeX/AAAOI332_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI332_schematic.tex rename to Documents/LaTeX/AAAOI332_schematic.tex index d210f161..8d211d82 100644 --- a/Documents/LaTeX/AOI332_schematic.tex +++ b/Documents/LaTeX/AAAOI332_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI332.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI332_schematic.tex %% -%% Purpose: Schematic File for AOI332 +%% Purpose: Schematic File for AAAOI332 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI332_truthtable.tex b/Documents/LaTeX/AAAOI332_truthtable.tex similarity index 94% rename from Documents/LaTeX/AOI332_truthtable.tex rename to Documents/LaTeX/AAAOI332_truthtable.tex index e1a4e0cd..7b9d39e5 100644 --- a/Documents/LaTeX/AOI332_truthtable.tex +++ b/Documents/LaTeX/AAAOI332_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI332.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI332_truthtable.tex %% -%% Purpose: Truth Table File for AOI332 +%% Purpose: Truth Table File for AAAOI332 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AAAOI333_circuit.tex b/Documents/LaTeX/AAAOI333_circuit.tex new file mode 100644 index 00000000..ce445e37 --- /dev/null +++ b/Documents/LaTeX/AAAOI333_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI333_circuit.tex +%% +%% Purpose: Circuit File for AAAOI333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{18} + \usgate + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{15} % wire between AND and NOR + \pin{17}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAAOI333_manpage.tex b/Documents/LaTeX/AAAOI333_manpage.tex new file mode 100644 index 00000000..6a1e966e --- /dev/null +++ b/Documents/LaTeX/AAAOI333_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI333_manpage.tex +%% +%% Purpose: Manual Page File for AAAOI333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAOI333} +\paragraph{Cell} +\begin{quote} + \textbf{AAAOI333} - a 3-3-3-input AND-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAOI333(Y, C2, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAOI333_circuit.tex} +\input{AAAOI333_schematic.tex} + +\paragraph{Truth Table} +\input{AAAOI333_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI333_schematic.tex b/Documents/LaTeX/AAAOI333_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI333_schematic.tex rename to Documents/LaTeX/AAAOI333_schematic.tex index 6ec81fc9..7b9519b0 100644 --- a/Documents/LaTeX/AOI333_schematic.tex +++ b/Documents/LaTeX/AAAOI333_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI333.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI333_schematic.tex %% -%% Purpose: Schematic File for AOI333 +%% Purpose: Schematic File for AAAOI333 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI333_truthtable.tex b/Documents/LaTeX/AAAOI333_truthtable.tex similarity index 95% rename from Documents/LaTeX/AOI333_truthtable.tex rename to Documents/LaTeX/AAAOI333_truthtable.tex index 1f9767ed..931f0d9e 100644 --- a/Documents/LaTeX/AOI333_truthtable.tex +++ b/Documents/LaTeX/AAAOI333_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI333.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI333_truthtable.tex %% -%% Purpose: Truth Table File for AOI333 +%% Purpose: Truth Table File for AAAOI333 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI333_circuit.tex b/Documents/LaTeX/AAAOI432_circuit.tex similarity index 65% rename from Documents/LaTeX/OAI333_circuit.tex rename to Documents/LaTeX/AAAOI432_circuit.tex index a20cc6bd..746b7f8c 100644 --- a/Documents/LaTeX/OAI333_circuit.tex +++ b/Documents/LaTeX/AAAOI432_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI333.tex +%% File: StdCellLib/Documents/LaTeX/AAAOI432_circuit.tex %% -%% Purpose: Circuit File for OAI333 +%% Purpose: Circuit File for AAAOI432 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,25 +34,26 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{3}{L}{A1} % pin A1 - \pin{1}{5}{L}{A2} % pin A2 - \pin{1}{7}{L}{B0} % pin B0 + \usgate + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{16}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B \pin{1}{9}{L}{B1} % pin B1 \pin{1}{11}{L}{B2} % pin B2 - \pin{1}{13}{L}{C0} % pin C0 + \pin{1}{13}{L}{C} % pin C \pin{1}{15}{L}{C1} % pin C1 \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{7} % wire between OR and NAND - \wire{9}{11}{9}{15} % wire between OR and NAND - \pin{17}{9}{R}{Z} % pin Z + \pin{1}{19}{L}{C3} % pin C3 + \wire{9}{3}{9}{7} % wire between AND and NOR + \wire{9}{11}{9}{16} % wire between AND and NOR + \pin{17}{9}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAAOI432_manpage.tex b/Documents/LaTeX/AAAOI432_manpage.tex new file mode 100644 index 00000000..8923b7f3 --- /dev/null +++ b/Documents/LaTeX/AAAOI432_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAAOI432_manpage.tex +%% +%% Purpose: Manual Page File for AAAOI432 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAAOI432} +\paragraph{Cell} +\begin{quote} + \textbf{AAAOI432} - a 4-3-2-input AND-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAAOI432(Y, C3, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAAOI432_circuit.tex} +%\input{AAAOI432_schematic.tex} + +\paragraph{Truth Table} +%\input{AAAOI432_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO221_circuit.tex b/Documents/LaTeX/AAO221_circuit.tex new file mode 100644 index 00000000..00ae3b20 --- /dev/null +++ b/Documents/LaTeX/AAO221_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO221_circuit.tex +%% +%% Purpose: Circuit File for AAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO221_manpage.tex b/Documents/LaTeX/AAO221_manpage.tex new file mode 100644 index 00000000..a02c2cff --- /dev/null +++ b/Documents/LaTeX/AAO221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO221_manpage.tex +%% +%% Purpose: Manual Page File for AAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO221} +\paragraph{Cell} +\begin{quote} + \textbf{AAO221} - a 2-2-1-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAO221_circuit.tex} +%\input{AAO221_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO22_circuit.tex b/Documents/LaTeX/AAO22_circuit.tex new file mode 100644 index 00000000..ac6531c1 --- /dev/null +++ b/Documents/LaTeX/AAO22_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO22_circuit.tex +%% +%% Purpose: Circuit File for AAO22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO22_manpage.tex b/Documents/LaTeX/AAO22_manpage.tex new file mode 100644 index 00000000..f157c6f5 --- /dev/null +++ b/Documents/LaTeX/AAO22_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO22_manpage.tex +%% +%% Purpose: Manual Page File for AAO22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO22} +\paragraph{Cell} +\begin{quote} + \textbf{AAO22} - a 2-2-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO22(Z, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO22_circuit.tex} +%\input{AAO22_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAO321_circuit.tex b/Documents/LaTeX/AAO321_circuit.tex new file mode 100644 index 00000000..eac34ba1 --- /dev/null +++ b/Documents/LaTeX/AAO321_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO321_circuit.tex +%% +%% Purpose: Circuit File for AAO321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO321_manpage.tex b/Documents/LaTeX/AAO321_manpage.tex new file mode 100644 index 00000000..879c9f1e --- /dev/null +++ b/Documents/LaTeX/AAO321_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO321_manpage.tex +%% +%% Purpose: Manual Page File for AAO321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO321} +\paragraph{Cell} +\begin{quote} + \textbf{AAO321} - a 3-2-1-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAO321_circuit.tex} +%\input{AAO321_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO32_circuit.tex b/Documents/LaTeX/AAO32_circuit.tex new file mode 100644 index 00000000..275e45db --- /dev/null +++ b/Documents/LaTeX/AAO32_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO32_circuit.tex +%% +%% Purpose: Circuit File for AAO32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO32_manpage.tex b/Documents/LaTeX/AAO32_manpage.tex new file mode 100644 index 00000000..6af9a1b3 --- /dev/null +++ b/Documents/LaTeX/AAO32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO32_manpage.tex +%% +%% Purpose: Manual Page File for AAO32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO32} +\paragraph{Cell} +\begin{quote} + \textbf{AAO32} - a 3-2-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO32_circuit.tex} +%\input{AAO32_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO331_circuit.tex b/Documents/LaTeX/AAO331_circuit.tex new file mode 100644 index 00000000..e77f7a3a --- /dev/null +++ b/Documents/LaTeX/AAO331_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO331_circuit.tex +%% +%% Purpose: Circuit File for AAO331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO331_manpage.tex b/Documents/LaTeX/AAO331_manpage.tex new file mode 100644 index 00000000..7cdfa26d --- /dev/null +++ b/Documents/LaTeX/AAO331_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO331_manpage.tex +%% +%% Purpose: Manual Page File for AAO331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO331} +\paragraph{Cell} +\begin{quote} + \textbf{AAO331} - a 3-3-1-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAO331_circuit.tex} +%\input{AAO331_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO33_circuit.tex b/Documents/LaTeX/AAO33_circuit.tex new file mode 100644 index 00000000..0c9a89f1 --- /dev/null +++ b/Documents/LaTeX/AAO33_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO33_circuit.tex +%% +%% Purpose: Circuit File for AAO33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO33_manpage.tex b/Documents/LaTeX/AAO33_manpage.tex new file mode 100644 index 00000000..e53dab49 --- /dev/null +++ b/Documents/LaTeX/AAO33_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO33_manpage.tex +%% +%% Purpose: Manual Page File for AAO33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO33} +\paragraph{Cell} +\begin{quote} + \textbf{AAO33} - a 3-3-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO33(Z, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO33_circuit.tex} +%\input{AAO33_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO421_circuit.tex b/Documents/LaTeX/AAO421_circuit.tex new file mode 100644 index 00000000..441d80c0 --- /dev/null +++ b/Documents/LaTeX/AAO421_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO421_circuit.tex +%% +%% Purpose: Circuit File for AAO421 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{16} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \pin{1}{15}{L}{C3} % pin C3 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{12}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO421_manpage.tex b/Documents/LaTeX/AAO421_manpage.tex new file mode 100644 index 00000000..0086d988 --- /dev/null +++ b/Documents/LaTeX/AAO421_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO421_manpage.tex +%% +%% Purpose: Manual Page File for AAO421 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO421} +\paragraph{Cell} +\begin{quote} + \textbf{AAO421} - a 4-2-1-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO421(Z, C3, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAO421_circuit.tex} +%\input{AAO421_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO421_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO42_circuit.tex b/Documents/LaTeX/AAO42_circuit.tex new file mode 100644 index 00000000..63e140e3 --- /dev/null +++ b/Documents/LaTeX/AAO42_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO42_circuit.tex +%% +%% Purpose: Circuit File for AAO42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{10}{9}{8} % wire between AND and NOR + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO42_manpage.tex b/Documents/LaTeX/AAO42_manpage.tex new file mode 100644 index 00000000..db4637cf --- /dev/null +++ b/Documents/LaTeX/AAO42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO42_manpage.tex +%% +%% Purpose: Manual Page File for AAO42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO42} +\paragraph{Cell} +\begin{quote} + \textbf{AAO42} - a 4-2-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO42(Z, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO42_circuit.tex} +%\input{AAO42_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO431_circuit.tex b/Documents/LaTeX/AAO431_circuit.tex new file mode 100644 index 00000000..ac01d7cf --- /dev/null +++ b/Documents/LaTeX/AAO431_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO431_circuit.tex +%% +%% Purpose: Circuit File for AAO431 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{16} + \usgate + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \pin{1}{15}{L}{C3} % pin C3 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{12}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO431_manpage.tex b/Documents/LaTeX/AAO431_manpage.tex new file mode 100644 index 00000000..73a29fe5 --- /dev/null +++ b/Documents/LaTeX/AAO431_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO431_manpage.tex +%% +%% Purpose: Manual Page File for AAO431 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO431} +\paragraph{Cell} +\begin{quote} + \textbf{AAO431} - a 4-3-1-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO431(Z, C3, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAO431_circuit.tex} +%\input{AAO431_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO431_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO43_circuit.tex b/Documents/LaTeX/AAO43_circuit.tex new file mode 100644 index 00000000..15ce7eff --- /dev/null +++ b/Documents/LaTeX/AAO43_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO43_circuit.tex +%% +%% Purpose: Circuit File for AAO43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{10}{9}{8} % wire between AND and NOR + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO43_manpage.tex b/Documents/LaTeX/AAO43_manpage.tex new file mode 100644 index 00000000..a786dc8f --- /dev/null +++ b/Documents/LaTeX/AAO43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO43_manpage.tex +%% +%% Purpose: Manual Page File for AAO43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO43} +\paragraph{Cell} +\begin{quote} + \textbf{AAO43} - a 4-3-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO43(Z, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO43_circuit.tex} +%\input{AAO43_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAO44_circuit.tex b/Documents/LaTeX/AAO44_circuit.tex new file mode 100644 index 00000000..ae50ecb7 --- /dev/null +++ b/Documents/LaTeX/AAO44_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO44_circuit.tex +%% +%% Purpose: Circuit File for AAO44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{16} + \usgate + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{4}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{8}{R}{}{} % NOR + \gate{not}{19}{8}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{1}{9}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \pin{1}{15}{L}{B3} % pin B3 + \wire{9}{4}{9}{6} % wire between AND and NOR + \wire{9}{12}{9}{10} % wire between AND and NOR + \pin{23}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAO44_manpage.tex b/Documents/LaTeX/AAO44_manpage.tex new file mode 100644 index 00000000..e48f885c --- /dev/null +++ b/Documents/LaTeX/AAO44_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAO44_manpage.tex +%% +%% Purpose: Manual Page File for AAO44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAO44} +\paragraph{Cell} +\begin{quote} + \textbf{AAO44} - a 4-4-input AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAO44(Z, B3, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAO44_circuit.tex} +%\input{AAO44_schematic.tex} + +\paragraph{Truth Table} +%\input{AAO44_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOA221_circuit.tex b/Documents/LaTeX/AAOA221_circuit.tex new file mode 100644 index 00000000..80528ad3 --- /dev/null +++ b/Documents/LaTeX/AAOA221_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA221_circuit.tex +%% +%% Purpose: Circuit File for AAOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOA221_manpage.tex b/Documents/LaTeX/AAOA221_manpage.tex new file mode 100644 index 00000000..847fe9d2 --- /dev/null +++ b/Documents/LaTeX/AAOA221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA221_manpage.tex +%% +%% Purpose: Manual Page File for AAOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOA221} +\paragraph{Cell} +\begin{quote} + \textbf{AAOA221} - a 2-2-1-input AND-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOA221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOA221_circuit.tex} +%\input{AAOA221_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOA221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOA321_circuit.tex b/Documents/LaTeX/AAOA321_circuit.tex new file mode 100644 index 00000000..4590243e --- /dev/null +++ b/Documents/LaTeX/AAOA321_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA321_circuit.tex +%% +%% Purpose: Circuit File for AAOA321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOA321_manpage.tex b/Documents/LaTeX/AAOA321_manpage.tex new file mode 100644 index 00000000..02857027 --- /dev/null +++ b/Documents/LaTeX/AAOA321_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA321_manpage.tex +%% +%% Purpose: Manual Page File for AAOA321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOA321} +\paragraph{Cell} +\begin{quote} + \textbf{AAOA321} - a 3-2-1-input AND-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOA321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOA321_circuit.tex} +%\input{AAOA321_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOA321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOA331_circuit.tex b/Documents/LaTeX/AAOA331_circuit.tex new file mode 100644 index 00000000..d22987a9 --- /dev/null +++ b/Documents/LaTeX/AAOA331_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA331_circuit.tex +%% +%% Purpose: Circuit File for AAOA331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOA331_manpage.tex b/Documents/LaTeX/AAOA331_manpage.tex new file mode 100644 index 00000000..99aee843 --- /dev/null +++ b/Documents/LaTeX/AAOA331_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOA331_manpage.tex +%% +%% Purpose: Manual Page File for AAOA331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOA331} +\paragraph{Cell} +\begin{quote} + \textbf{AAOA331} - a 3-3-1-input AND-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOA331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOA331_circuit.tex} +%\input{AAOA331_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOA331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOAI221_circuit.tex b/Documents/LaTeX/AAOAI221_circuit.tex new file mode 100644 index 00000000..296b1798 --- /dev/null +++ b/Documents/LaTeX/AAOAI221_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI221_circuit.tex +%% +%% Purpose: Circuit File for AAOAI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOAI221_manpage.tex b/Documents/LaTeX/AAOAI221_manpage.tex new file mode 100644 index 00000000..b145338d --- /dev/null +++ b/Documents/LaTeX/AAOAI221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI221_manpage.tex +%% +%% Purpose: Manual Page File for AAOAI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOAI221} +\paragraph{Cell} +\begin{quote} + \textbf{AAOAI221} - a 2-2-1-input AND-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOAI221(Y, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOAI221_circuit.tex} +%\input{AAOAI221_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOAI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOAI321_circuit.tex b/Documents/LaTeX/AAOAI321_circuit.tex new file mode 100644 index 00000000..1349bc94 --- /dev/null +++ b/Documents/LaTeX/AAOAI321_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI321_circuit.tex +%% +%% Purpose: Circuit File for AAOAI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOAI321_manpage.tex b/Documents/LaTeX/AAOAI321_manpage.tex new file mode 100644 index 00000000..906a2230 --- /dev/null +++ b/Documents/LaTeX/AAOAI321_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI321_manpage.tex +%% +%% Purpose: Manual Page File for AAOAI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOAI321} +\paragraph{Cell} +\begin{quote} + \textbf{AAOAI321} - a 3-2-1-input AND-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOAI321(Y, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOAI321_circuit.tex} +%\input{AAOAI321_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOAI321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOAI331_circuit.tex b/Documents/LaTeX/AAOAI331_circuit.tex new file mode 100644 index 00000000..f103484e --- /dev/null +++ b/Documents/LaTeX/AAOAI331_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI331_circuit.tex +%% +%% Purpose: Circuit File for AAOAI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{8}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between AND and OR + \wire{9}{10}{9}{11} % wire between AND and OR + \wire{16}{1}{16}{2} % wire between OR and NAND + \wire{16}{6}{16}{8} % wire between OR and NAND + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOAI331_manpage.tex b/Documents/LaTeX/AAOAI331_manpage.tex new file mode 100644 index 00000000..82ef7269 --- /dev/null +++ b/Documents/LaTeX/AAOAI331_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOAI331_manpage.tex +%% +%% Purpose: Manual Page File for AAOAI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOAI331} +\paragraph{Cell} +\begin{quote} + \textbf{AAOAI331} - a 3-3-1-input AND-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOAI331(Y, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOAI331_circuit.tex} +%\input{AAOAI331_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOAI331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOI221_circuit.tex b/Documents/LaTeX/AAOI221_circuit.tex similarity index 69% rename from Documents/LaTeX/AOI221_circuit.tex rename to Documents/LaTeX/AAOI221_circuit.tex index a1edafe5..3ae64a26 100644 --- a/Documents/LaTeX/AOI221_circuit.tex +++ b/Documents/LaTeX/AAOI221_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI221.tex +%% File: StdCellLib/Documents/LaTeX/AAOI221_circuit.tex %% -%% Purpose: Circuit File for AOI221 +%% Purpose: Circuit File for AAOI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,21 +34,22 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \pin{1}{9}{L}{C0} % pin C0 - \pin{1}{13}{L}{C1} % pin C1 - \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR gate -> right - \wire{9}{1}{9}{3} % wire between AND and NOR - \wire{9}{11}{9}{7} % wire between AND and NOR + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR \wire{2}{1}{9}{1} % wire before NOR - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAOI221_manpage.tex b/Documents/LaTeX/AAOI221_manpage.tex new file mode 100644 index 00000000..012bef42 --- /dev/null +++ b/Documents/LaTeX/AAOI221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI221_manpage.tex +%% +%% Purpose: Manual Page File for AAOI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI221} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI221} - a 2-2-1-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOI221_circuit.tex} +\input{AAOI221_schematic.tex} + +\paragraph{Truth Table} +\input{AAOI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI221_schematic.tex b/Documents/LaTeX/AAOI221_schematic.tex similarity index 94% rename from Documents/LaTeX/AOI221_schematic.tex rename to Documents/LaTeX/AAOI221_schematic.tex index c1a6f2ee..050d8014 100644 --- a/Documents/LaTeX/AOI221_schematic.tex +++ b/Documents/LaTeX/AAOI221_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI221.tex +%% File: StdCellLib/Documents/LaTeX/AAOI221_schematic.tex %% -%% Purpose: Schematic File for AOI221 +%% Purpose: Schematic File for AAOI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI221_truthtable.tex b/Documents/LaTeX/AAOI221_truthtable.tex similarity index 91% rename from Documents/LaTeX/AOI221_truthtable.tex rename to Documents/LaTeX/AAOI221_truthtable.tex index 2823d9f2..a2a03a18 100644 --- a/Documents/LaTeX/AOI221_truthtable.tex +++ b/Documents/LaTeX/AAOI221_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI221.tex +%% File: StdCellLib/Documents/LaTeX/AAOI221_truthtable.tex %% -%% Purpose: Truth Table File for AOI221 +%% Purpose: Truth Table File for AAOI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AAOI22_circuit.tex b/Documents/LaTeX/AAOI22_circuit.tex new file mode 100644 index 00000000..c3a99faa --- /dev/null +++ b/Documents/LaTeX/AAOI22_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI22_circuit.tex +%% +%% Purpose: Circuit File for AAOI22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI22_manpage.tex b/Documents/LaTeX/AAOI22_manpage.tex new file mode 100644 index 00000000..f0fc80bf --- /dev/null +++ b/Documents/LaTeX/AAOI22_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI22_manpage.tex +%% +%% Purpose: Manual Page File for AAOI22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI22} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI22} - a 2-2-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI22(Z, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI22_circuit.tex} +%\input{AAOI22_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI22_schematic.tex b/Documents/LaTeX/AAOI22_schematic.tex similarity index 94% rename from Documents/LaTeX/AOI22_schematic.tex rename to Documents/LaTeX/AAOI22_schematic.tex index 8c64131e..f0a0684a 100644 --- a/Documents/LaTeX/AOI22_schematic.tex +++ b/Documents/LaTeX/AAOI22_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI22.tex +%% File: StdCellLib/Documents/LaTeX/AAOI22_schematic.tex %% -%% Purpose: Schematic File for AOI22 +%% Purpose: Schematic File for AAOI22 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI22_truthtable.tex b/Documents/LaTeX/AAOI22_truthtable.tex similarity index 91% rename from Documents/LaTeX/AOI22_truthtable.tex rename to Documents/LaTeX/AAOI22_truthtable.tex index e449cd89..4fed6855 100644 --- a/Documents/LaTeX/AOI22_truthtable.tex +++ b/Documents/LaTeX/AAOI22_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI22.tex +%% File: StdCellLib/Documents/LaTeX/AAOI22_truthtable.tex %% -%% Purpose: Truth Table File for AOI22 +%% Purpose: Truth Table File for AAOI22 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI321_circuit.tex b/Documents/LaTeX/AAOI321_circuit.tex similarity index 68% rename from Documents/LaTeX/AOI321_circuit.tex rename to Documents/LaTeX/AAOI321_circuit.tex index bafb10ed..36cb6bb6 100644 --- a/Documents/LaTeX/AOI321_circuit.tex +++ b/Documents/LaTeX/AAOI321_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI321.tex +%% File: StdCellLib/Documents/LaTeX/AAOI321_circuit.tex %% -%% Purpose: Circuit File for AOI321 +%% Purpose: Circuit File for AAOI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \pin{1}{9}{L}{C0} % pin C0 - \pin{1}{11}{L}{C1} % pin C1 - \pin{1}{13}{L}{C2} % pin C2 - \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR gate -> right - \wire{9}{1}{9}{3} % wire between AND and NOR - \wire{9}{11}{9}{7} % wire between AND and NOR + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR \wire{2}{1}{9}{1} % wire before NOR - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAOI321_manpage.tex b/Documents/LaTeX/AAOI321_manpage.tex new file mode 100644 index 00000000..df7183f6 --- /dev/null +++ b/Documents/LaTeX/AAOI321_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI321_manpage.tex +%% +%% Purpose: Manual Page File for AAOI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI321} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI321} - a 3-2-1-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOI321_circuit.tex} +\input{AAOI321_schematic.tex} + +\paragraph{Truth Table} +\input{AAOI321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI321_schematic.tex b/Documents/LaTeX/AAOI321_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI321_schematic.tex rename to Documents/LaTeX/AAOI321_schematic.tex index 4057bb21..41ce188c 100644 --- a/Documents/LaTeX/AOI321_schematic.tex +++ b/Documents/LaTeX/AAOI321_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI321.tex +%% File: StdCellLib/Documents/LaTeX/AAOI321_schematic.tex %% -%% Purpose: Schematic File for AOI321 +%% Purpose: Schematic File for AAOI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI321_truthtable.tex b/Documents/LaTeX/AAOI321_truthtable.tex similarity index 92% rename from Documents/LaTeX/AOI321_truthtable.tex rename to Documents/LaTeX/AAOI321_truthtable.tex index 9c38038b..bcc71fc8 100644 --- a/Documents/LaTeX/AOI321_truthtable.tex +++ b/Documents/LaTeX/AAOI321_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI321.tex +%% File: StdCellLib/Documents/LaTeX/AAOI321_truthtable.tex %% -%% Purpose: Truth Table File for AOI321 +%% Purpose: Truth Table File for AAOI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AAOI32_circuit.tex b/Documents/LaTeX/AAOI32_circuit.tex new file mode 100644 index 00000000..7a8e8717 --- /dev/null +++ b/Documents/LaTeX/AAOI32_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI32_circuit.tex +%% +%% Purpose: Circuit File for AAOI32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI32_manpage.tex b/Documents/LaTeX/AAOI32_manpage.tex new file mode 100644 index 00000000..dc37db16 --- /dev/null +++ b/Documents/LaTeX/AAOI32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI32_manpage.tex +%% +%% Purpose: Manual Page File for AAOI32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI32} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI32} - a 3-2-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI32_circuit.tex} +%\input{AAOI32_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOI32_schematic.tex b/Documents/LaTeX/AAOI32_schematic.tex new file mode 100644 index 00000000..ae6d0321 --- /dev/null +++ b/Documents/LaTeX/AAOI32_schematic.tex @@ -0,0 +1,76 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI32_schematic.tex +%% +%% Purpose: Schematic File for AAOI32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Schematic (one stage, 2$T_{p}$/3$T_{n}$ stacked, 10T total) + \begin{figure}[h] %\caption{Schematic} + \begin{center} + \begin{circuitdiagram}{36}{33} + \pin{2}{14.5}{L}{A0} % pin A0, n-channel + \pin{2}{8.5}{L}{A1} % pin A1, n-channel + \pin{14}{14.5}{L}{B0} % pin B0, p-channel + \pin{14}{8.5}{L}{B1} % pin B1, p-channel + \pin{14}{2.5}{L}{B2} % pin B2, n-channel + \pin{2}{23.5}{L}{A0} % pin A0, p-channel + \pin{14}{23.5}{L}{A1} % pin A1, p-channel + \pin{2}{29.5}{L}{B0} % pin B0, p-channel + \pin{14}{29.5}{L}{B1} % pin B1, p-channel + \pin{26}{29.5}{L}{B2} % pin B2, p-channel + \trans[\wireU{0.5}]{nenh*}{6}{10}{R}{$M_{NA1}$}{} + \trans[\wireUD{0.5}]{nenh*}{6}{16}{R}{$M_{NA0}$}{} + \trans[\wireUD{0.5}]{nenh*}{18}{16}{R}{$M_{NB0}$}{} + \trans[\wireUD{0.5}]{nenh*}{18}{10}{R}{$M_{NB1}$}{} + \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NB2}$}{} + \trans[\wireUD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA0}$} + \trans[\wireUD{0.5}]{penh*}{6}{28}{R}{}{$M_{PB0}$} + \trans[\wireD{0.5}]{penh*}{18}{28}{R}{}{$M_{PB1}$} + \trans[\wireUD{0.5}]{penh*}{18}{22}{R}{}{$M_{PA1}$} + \trans[\wireD{0.5}]{penh*}{30}{28}{R}{}{$M_{PB2}$} + \ground{8}{0.5}{D} % ground below nmos + \ground{20}{0.5}{D} % ground below nmos + \power{8}{31.5}{U}{} % power above left pmos + \power{20}{31.5}{U}{} % power above left pmos + \power{32}{31.5}{U}{} % power above left pmos + \wire{8}{1}{8}{7} + \wire{8}{25}{32}{25} % wire short between pmos + \wire{8}{19}{34}{19} % wire before pin Z + \junct{8}{19} + \junct{8}{25} + \junct{20}{25} + \junct{20}{19} + \pin{35}{19}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOI311_truthtable.tex b/Documents/LaTeX/AAOI32_truthtable.tex similarity index 65% rename from Documents/LaTeX/AOI311_truthtable.tex rename to Documents/LaTeX/AAOI32_truthtable.tex index a0e2445d..9eec7581 100644 --- a/Documents/LaTeX/AOI311_truthtable.tex +++ b/Documents/LaTeX/AAOI32_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI211.tex +%% File: StdCellLib/Documents/LaTeX/AAOI32_truthtable.tex %% -%% Purpose: Truth Table File for AOI211 +%% Purpose: Truth Table File for AAOI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,17 +34,19 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} - {\(Z = \lnot ((C2 \land C1 \land C0) \lor B \lor A) \)} - \begin{table}[h] %\caption{\(Z = \lnot ((C2 \land C1 \land C0) \lor B \lor A) \)} + {\(Z = \lnot ((B2 \land B1 \land B0) \lor (A1 \land A0)) \)} + \begin{table}[h] %\caption{\(Z = \lnot ((B2 \land B1 \land B0) \lor (A1 \land A0)) \)} \begin{center} \begin{tabular}{|c|c|c|c|c||c|} \hline - C2 & C1 & C0 & B & A & Z \\ \hline\hline - 0 & X & X & 0 & 0 & 1 \\ \hline - 1 & 1 & 1 & X & X & 0 \\ \hline - X & 0 & X & 0 & 0 & 1 \\ \hline - X & X & 0 & 0 & 0 & 1 \\ \hline - X & X & X & 1 & X & 0 \\ \hline - X & X & X & X & 1 & 0 \\ \hline + B2 & B1 & B0 & A1 & A0 & Z \\ \hline\hline + 0 & X & X & 0 & X & 1\\ \hline + 0 & X & X & X & 0 & 1\\ \hline + 1 & 1 & 1 & X & X & 0\\ \hline + X & 0 & X & 0 & X & 1\\ \hline + X & 0 & X & X & 0 & 1\\ \hline + X & X & 0 & 0 & X & 1\\ \hline + X & X & 0 & X & 0 & 1\\ \hline + X & X & X & 1 & 1 & 0\\ \hline \end{tabular} \end{center} \end{table} diff --git a/Documents/LaTeX/AOI331_circuit.tex b/Documents/LaTeX/AAOI331_circuit.tex similarity index 72% rename from Documents/LaTeX/AOI331_circuit.tex rename to Documents/LaTeX/AAOI331_circuit.tex index 4f7d1832..def323dd 100644 --- a/Documents/LaTeX/AOI331_circuit.tex +++ b/Documents/LaTeX/AAOI331_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI331.tex +%% File: StdCellLib/Documents/LaTeX/AAOI331_circuit.tex %% -%% Purpose: Circuit File for AOI331 +%% Purpose: Circuit File for AAOI331 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,23 +34,24 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{5}{L}{B1} % pin B1 \pin{1}{7}{L}{B2} % pin B2 - \pin{1}{9}{L}{C0} % pin C0 + \pin{1}{9}{L}{C} % pin C \pin{1}{11}{L}{C1} % pin C1 \pin{1}{13}{L}{C2} % pin C2 - \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR gate -> right - \wire{9}{1}{9}{3} % wire between AND and NOR - \wire{9}{11}{9}{7} % wire between AND and NOR + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{11}{9}{7} % wire between AND and NOR \wire{2}{1}{9}{1} % wire before NOR - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAOI331_manpage.tex b/Documents/LaTeX/AAOI331_manpage.tex new file mode 100644 index 00000000..67d005ee --- /dev/null +++ b/Documents/LaTeX/AAOI331_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI331_manpage.tex +%% +%% Purpose: Manual Page File for AAOI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI331} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI331} - a 3-3-1-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOI331_circuit.tex} +\input{AAOI331_schematic.tex} + +\paragraph{Truth Table} +\input{AAOI331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI331_schematic.tex b/Documents/LaTeX/AAOI331_schematic.tex similarity index 97% rename from Documents/LaTeX/AOI331_schematic.tex rename to Documents/LaTeX/AAOI331_schematic.tex index 81c928e0..e90abdda 100644 --- a/Documents/LaTeX/AOI331_schematic.tex +++ b/Documents/LaTeX/AAOI331_schematic.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI331.tex +%% File: StdCellLib/Documents/LaTeX/AAOI331_schematic.tex %% -%% Purpose: Schematic File for AOI331 +%% Purpose: Schematic File for AAOI331 %% %% ************ LaTeX with circdia.sty package *************** %% diff --git a/Documents/LaTeX/AOI331_truthtable.tex b/Documents/LaTeX/AAOI331_truthtable.tex similarity index 92% rename from Documents/LaTeX/AOI331_truthtable.tex rename to Documents/LaTeX/AAOI331_truthtable.tex index 60f30310..17e0a9c5 100644 --- a/Documents/LaTeX/AOI331_truthtable.tex +++ b/Documents/LaTeX/AAOI331_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI331.tex +%% File: StdCellLib/Documents/LaTeX/AAOI331_truthtable.tex %% -%% Purpose: Truth Table File for AOI331 +%% Purpose: Truth Table File for AAOI331 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI333_circuit.tex b/Documents/LaTeX/AAOI33_circuit.tex similarity index 64% rename from Documents/LaTeX/AOI333_circuit.tex rename to Documents/LaTeX/AAOI33_circuit.tex index e31b9ed7..1d9ec050 100644 --- a/Documents/LaTeX/AOI333_circuit.tex +++ b/Documents/LaTeX/AAOI33_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI333.tex +%% File: StdCellLib/Documents/LaTeX/AAOI33_circuit.tex %% -%% Purpose: Circuit File for AOI333 +%% Purpose: Circuit File for AAOI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,25 +34,22 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{A1} % pin A1 \pin{1}{5}{L}{A2} % pin A2 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{9}{L}{B1} % pin B1 \pin{1}{11}{L}{B2} % pin B2 - \pin{1}{13}{L}{C0} % pin C0 - \pin{1}{15}{L}{C1} % pin C1 - \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{15}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{9}{R}{}{} % NOR gate -> right - \wire{9}{3}{9}{7} % wire between AND and NOR - \wire{9}{11}{9}{15} % wire between AND and NOR - \pin{17}{9}{R}{Z} % pin Z + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{9}{9}{8} % wire between AND and NOR + \pin{17}{6}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AAOI33_manpage.tex b/Documents/LaTeX/AAOI33_manpage.tex new file mode 100644 index 00000000..b2c27451 --- /dev/null +++ b/Documents/LaTeX/AAOI33_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI33_manpage.tex +%% +%% Purpose: Manual Page File for AAOI33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI33} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI33} - a 3-3-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI33(Z, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI33_circuit.tex} +\input{AAOI33_schematic.tex} + +\paragraph{Truth Table} +\input{AAOI33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI33_schematic.tex b/Documents/LaTeX/AAOI33_schematic.tex similarity index 95% rename from Documents/LaTeX/AOI33_schematic.tex rename to Documents/LaTeX/AAOI33_schematic.tex index f2ef4b99..143ef17d 100644 --- a/Documents/LaTeX/AOI33_schematic.tex +++ b/Documents/LaTeX/AAOI33_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI33.tex +%% File: StdCellLib/Documents/LaTeX/AAOI33_schematic.tex %% -%% Purpose: Schematic File for AOI33 +%% Purpose: Schematic File for AAOI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AOI33_truthtable.tex b/Documents/LaTeX/AAOI33_truthtable.tex similarity index 92% rename from Documents/LaTeX/AOI33_truthtable.tex rename to Documents/LaTeX/AAOI33_truthtable.tex index 9fe275fd..fe477753 100644 --- a/Documents/LaTeX/AOI33_truthtable.tex +++ b/Documents/LaTeX/AAOI33_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI33.tex +%% File: StdCellLib/Documents/LaTeX/AAOI33_truthtable.tex %% -%% Purpose: Truth Table File for AOI33 +%% Purpose: Truth Table File for AAOI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/AAOI421_circuit.tex b/Documents/LaTeX/AAOI421_circuit.tex new file mode 100644 index 00000000..e760a007 --- /dev/null +++ b/Documents/LaTeX/AAOI421_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI421_circuit.tex +%% +%% Purpose: Circuit File for AAOI421 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{16} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \pin{1}{15}{L}{C3} % pin C3 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{12}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{17}{5}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI421_manpage.tex b/Documents/LaTeX/AAOI421_manpage.tex new file mode 100644 index 00000000..f8d78805 --- /dev/null +++ b/Documents/LaTeX/AAOI421_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI421_manpage.tex +%% +%% Purpose: Manual Page File for AAOI421 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI421} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI421} - a 4-2-1-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI421(Y, C3, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOI421_circuit.tex} +%\input{AAOI421_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI421_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOI42_circuit.tex b/Documents/LaTeX/AAOI42_circuit.tex new file mode 100644 index 00000000..a2ed2d3a --- /dev/null +++ b/Documents/LaTeX/AAOI42_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI42_circuit.tex +%% +%% Purpose: Circuit File for AAOI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{10}{9}{8} % wire between AND and NOR + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI42_manpage.tex b/Documents/LaTeX/AAOI42_manpage.tex new file mode 100644 index 00000000..c1e3de38 --- /dev/null +++ b/Documents/LaTeX/AAOI42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI42_manpage.tex +%% +%% Purpose: Manual Page File for AAOI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI42} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI42} - a 4-2-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI42(Y, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI42_circuit.tex} +%\input{AAOI42_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOI431_circuit.tex b/Documents/LaTeX/AAOI431_circuit.tex new file mode 100644 index 00000000..f0837cc4 --- /dev/null +++ b/Documents/LaTeX/AAOI431_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI431_circuit.tex +%% +%% Purpose: Circuit File for AAOI431 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{16} + \usgate + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{5}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \pin{1}{15}{L}{C3} % pin C3 + \wire{9}{1}{9}{3} % wire between AND and NOR + \wire{9}{12}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire before NOR + \pin{17}{5}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI431_manpage.tex b/Documents/LaTeX/AAOI431_manpage.tex new file mode 100644 index 00000000..8c3119e4 --- /dev/null +++ b/Documents/LaTeX/AAOI431_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI431_manpage.tex +%% +%% Purpose: Manual Page File for AAOI431 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI431} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI431} - a 4-3-1-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI431(Y, C3, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AAOI431_circuit.tex} +%\input{AAOI431_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI431_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOI43_circuit.tex b/Documents/LaTeX/AAOI43_circuit.tex new file mode 100644 index 00000000..f37f31e9 --- /dev/null +++ b/Documents/LaTeX/AAOI43_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI43_circuit.tex +%% +%% Purpose: Circuit File for AAOI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between AND and NOR + \wire{9}{10}{9}{8} % wire between AND and NOR + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI43_manpage.tex b/Documents/LaTeX/AAOI43_manpage.tex new file mode 100644 index 00000000..d5f76202 --- /dev/null +++ b/Documents/LaTeX/AAOI43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI43_manpage.tex +%% +%% Purpose: Manual Page File for AAOI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI43} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI43} - a 4-3-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI43(Y, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI43_circuit.tex} +%\input{AAOI43_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOI44_circuit.tex b/Documents/LaTeX/AAOI44_circuit.tex new file mode 100644 index 00000000..619cdb9c --- /dev/null +++ b/Documents/LaTeX/AAOI44_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI44_circuit.tex +%% +%% Purpose: Circuit File for AAOI44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{16} + \usgate + \gate[\inputs{4}]{and}{5}{12}{R}{}{} % AND + \gate[\inputs{4}]{and}{5}{4}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{8}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{1}{9}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \pin{1}{15}{L}{B3} % pin B3 + \wire{9}{4}{9}{6} % wire between AND and NOR + \wire{9}{12}{9}{10} % wire between AND and NOR + \pin{17}{8}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOI44_manpage.tex b/Documents/LaTeX/AAOI44_manpage.tex new file mode 100644 index 00000000..110a72b4 --- /dev/null +++ b/Documents/LaTeX/AAOI44_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOI44_manpage.tex +%% +%% Purpose: Manual Page File for AAOI44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOI44} +\paragraph{Cell} +\begin{quote} + \textbf{AAOI44} - a 4-4-input AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOI44(Y, B3, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOI44_circuit.tex} +%\input{AAOI44_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOI44_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AAOOA222_circuit.tex b/Documents/LaTeX/AAOOA222_circuit.tex new file mode 100644 index 00000000..ee489f84 --- /dev/null +++ b/Documents/LaTeX/AAOOA222_circuit.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOOA222_circuit.tex +%% +%% Purpose: Circuit File for AAOOA222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{18} + \usgate + \gate[\inputs{2}]{and}{5}{15}{R}{}{} % OR + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{12}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nand}{19}{8}{R}{}{} % NOR + \gate{not}{26}{8}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{9}{14}{9}{15} % wire between AND and OR + \wire{9}{9}{9}{10} % wire between AND and OR + \wire{16}{3}{16}{6} % wire between OR and NAND + \wire{16}{10}{16}{12} % wire between OR and NAND + \pin{30}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOOA222_manpage.tex b/Documents/LaTeX/AAOOA222_manpage.tex new file mode 100644 index 00000000..06c14cd3 --- /dev/null +++ b/Documents/LaTeX/AAOOA222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOOA222_manpage.tex +%% +%% Purpose: Manual Page File for AAOOA222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOOA222} +\paragraph{Cell} +\begin{quote} + \textbf{AAOOA222} - a 2-2-2-input AND-AND-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOOA222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOOA222_circuit.tex} +%\input{AAOOA222_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOOA222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AAOOAI222_circuit.tex b/Documents/LaTeX/AAOOAI222_circuit.tex new file mode 100644 index 00000000..d73e2e99 --- /dev/null +++ b/Documents/LaTeX/AAOOAI222_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOOAI222_circuit.tex +%% +%% Purpose: Circuit File for AAOOAI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{and}{5}{15}{R}{}{} % OR + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{12}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nand}{19}{8}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{9}{14}{9}{15} % wire between AND and OR + \wire{9}{9}{9}{10} % wire between AND and OR + \wire{16}{3}{16}{6} % wire between OR and NAND + \wire{16}{10}{16}{12} % wire between OR and NAND + \pin{24}{8}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AAOOAI222_manpage.tex b/Documents/LaTeX/AAOOAI222_manpage.tex new file mode 100644 index 00000000..031fcebb --- /dev/null +++ b/Documents/LaTeX/AAOOAI222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AAOOAI222_manpage.tex +%% +%% Purpose: Manual Page File for AAOOAI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AAOOAI222} +\paragraph{Cell} +\begin{quote} + \textbf{AAOOAI222} - a 2-2-2-input AND-AND-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AAOOAI222(Y, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AAOOAI222_circuit.tex} +%\input{AAOOAI222_schematic.tex} + +\paragraph{Truth Table} +%\input{AAOOAI222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AND2_circuit.tex b/Documents/LaTeX/AND2_circuit.tex new file mode 100644 index 00000000..d2f24df4 --- /dev/null +++ b/Documents/LaTeX/AND2_circuit.tex @@ -0,0 +1,49 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AND2_circuit.tex +%% +%% Purpose: Circuit File for AND2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{17}{6} + \usgate + \gate[\inputs{2}]{nand}{5}{3}{R}{}{} % NAND + \gate{not}{12}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{16}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AND2_manpage.tex b/Documents/LaTeX/AND2_manpage.tex new file mode 100644 index 00000000..c61c1954 --- /dev/null +++ b/Documents/LaTeX/AND2_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AND2_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AND2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AND2 - a 2-input AND gate} \label{logical:AND2} + +\paragraph{Synopsys} +\begin{quote} + AND2 (Z A1 A) +\end{quote} + +\paragraph{Description} +\input{AND2_circuit.tex} +%\input{AND2_schematic.tex} + +\paragraph{Truth Table} +%\input{AND2_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AND3_circuit.tex b/Documents/LaTeX/AND3_circuit.tex new file mode 100644 index 00000000..f7fc65a2 --- /dev/null +++ b/Documents/LaTeX/AND3_circuit.tex @@ -0,0 +1,50 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AND3_circuit.tex +%% +%% Purpose: Circuit File for AND3 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{17}{6} + \usgate + \gate[\inputs{3}]{nand}{5}{3}{R}{}{} % NAND + \gate{not}{12}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{16}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AND3_manpage.tex b/Documents/LaTeX/AND3_manpage.tex new file mode 100644 index 00000000..a648c04e --- /dev/null +++ b/Documents/LaTeX/AND3_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AND3_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AND3 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AND3 - a 3-input AND gate} \label{logical:AND3} + +\paragraph{Synopsys} +\begin{quote} + AND3 (Z A2 A1 A) +\end{quote} + +\paragraph{Description} +\input{AND3_circuit.tex} +%\input{AND3_schematic.tex} + +\paragraph{Truth Table} +%\input{AND3_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AND4_circuit.tex b/Documents/LaTeX/AND4_circuit.tex index 675ee5e6..f3375778 100644 --- a/Documents/LaTeX/AND4_circuit.tex +++ b/Documents/LaTeX/AND4_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AND4.tex +%% File: StdCellLib/Documents/LaTeX/AND4_circuit.tex %% %% Purpose: Circuit File for AND4 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,15 +34,16 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{17}{8} + \usgate + \gate[\inputs{4}]{nand}{5}{4}{R}{}{} % NAND + \gate{not}{12}{4}{R}{}{} % NOT \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D} % pin D - \gate[\inputs{4}]{nand}{5}{4}{R}{}{} % AND gate -> right - \gate{not}{12}{4}{R}{}{} % NOT gate -> right + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 \pin{16}{4}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/AND4_manpage.tex b/Documents/LaTeX/AND4_manpage.tex index c0ef9702..5d2359f0 100644 --- a/Documents/LaTeX/AND4_manpage.tex +++ b/Documents/LaTeX/AND4_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,7 +40,7 @@ \paragraph{Synopsys} \begin{quote} - AND4(Z, D, C, B, A) + AND4(Z, A3, A2, A1, A) \end{quote} \paragraph{Description} @@ -58,7 +58,4 @@ \paragraph{Files} -\paragraph{See also} -\begin{quote} - OR4 - a 4-input OR gate -\end{quote} +\clearpage diff --git a/Documents/LaTeX/AO2111_manpage.tex b/Documents/LaTeX/AO2111_manpage.tex deleted file mode 100644 index cd2ff38c..00000000 --- a/Documents/LaTeX/AO2111_manpage.tex +++ /dev/null @@ -1,64 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AO2111.tex -%% -%% Purpose: Manual Page File for AO2111 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AO2111} -\paragraph{Cell} -\begin{quote} - \textbf{AO2111} - a 2-1-1-1-input AND-OR gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AO2111(Z, D1, D0, C, B, A) -\end{quote} - -\paragraph{Description} -\input{AO2111_circuit.tex} -%\input{AO2111_schematic_AO2111.tex} - -\paragraph{Truth Table} -\input{AO2111_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AO3111 - a 3-1-1-1-input AND-OR gate -\end{quote} diff --git a/Documents/LaTeX/AO2111_truthtable.tex b/Documents/LaTeX/AO2111_truthtable.tex deleted file mode 100644 index fa4eb6dd..00000000 --- a/Documents/LaTeX/AO2111_truthtable.tex +++ /dev/null @@ -1,54 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/truthtable_AO2111.tex -%% -%% Purpose: Truth Table File for AO2111 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// - -\begin{center} - {\(Z = (D1 \land D0) \lor C \lor B \lor A \)} - \begin{table}[h] %\caption{\(Z = (D1 \land D0) \lor C \lor B \lor A \)} - \begin{center} - \begin{tabular}{|c|c|c|c|c||c|} \hline - D1 & D0 & C & B & A & Z \\ \hline\hline - 0 & X & 0 & 0 & 0 & 0 \\ \hline - 0 & X & 1 & X & X & 1 \\ \hline - 0 & X & X & 1 & X & 1 \\ \hline - 0 & X & X & X & 1 & 1 \\ \hline - X & 0 & 0 & 0 & 0 & 0 \\ \hline - X & 0 & 1 & X & X & 1 \\ \hline - X & 0 & X & 1 & X & 1 \\ \hline - X & 0 & X & X & 1 & 1 \\ \hline - 1 & 1 & X & X & X & 1 \\ \hline - \end{tabular} - \end{center} - \end{table} -\end{center} diff --git a/Documents/LaTeX/AO21_circuit.tex b/Documents/LaTeX/AO21_circuit.tex new file mode 100644 index 00000000..b53ea947 --- /dev/null +++ b/Documents/LaTeX/AO21_circuit.tex @@ -0,0 +1,52 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO21_circuit.tex +%% +%% Purpose: Circuit File for AO21 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{8} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA3111_manpage.tex b/Documents/LaTeX/AO21_manpage.tex similarity index 78% rename from Documents/LaTeX/OA3111_manpage.tex rename to Documents/LaTeX/AO21_manpage.tex index 33b495df..5a470aa5 100644 --- a/Documents/LaTeX/OA3111_manpage.tex +++ b/Documents/LaTeX/AO21_manpage.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OA3111.tex +%% File: StdCellLib/Documents/LaTeX/AO21_manpage.tex %% -%% Purpose: Manual Page File for OA3111 +%% Purpose: Auto-generated Manual Page for AO21 %% %% ************ LaTeX with circdia.sty package *************** %% @@ -32,23 +32,19 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{OA3111} -\paragraph{Cell} -\begin{quote} - \textbf{OA3111} - a 3-1-1-1-input OR-AND gate -\end{quote} +\subsection{AO21 - a 2-1-input AND-OR gate} \label{logical:AO21} \paragraph{Synopsys} \begin{quote} - OA3111(Z, D2, D1, D0, C, B, A) + AO21 (Z B1 B A) \end{quote} \paragraph{Description} -\input{OA3111_circuit.tex} -%\input{OA3111_schematic.tex} +\input{AO21_circuit.tex} +%\input{AO21_schematic.tex} \paragraph{Truth Table} -\input{OA3111_truthtable.tex} +%\input{AO21_truthtable.tex} \paragraph{Usage} @@ -58,7 +54,4 @@ \paragraph{Files} -\paragraph{See also} -\begin{quote} - OA2111 - a 2-1-1-1-input AND-OR gate -\end{quote} +\clearpage diff --git a/Documents/LaTeX/AO22_circuit.tex b/Documents/LaTeX/AO22_circuit.tex new file mode 100644 index 00000000..37fa6382 --- /dev/null +++ b/Documents/LaTeX/AO22_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO22_circuit.tex +%% +%% Purpose: Circuit File for AO22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{2}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A! + \pin{1}{5}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{9}{5}{9}{7} % wire between AND and NOR + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO22_manpage.tex b/Documents/LaTeX/AO22_manpage.tex new file mode 100644 index 00000000..f6a13e15 --- /dev/null +++ b/Documents/LaTeX/AO22_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO22_manpage.tex +%% +%% Purpose: Manual Page File for AO22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AO22} +\paragraph{Cell} +\begin{quote} + \textbf{AO22} - a 2-2-input AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AO22(Z, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AO22_circuit.tex} +%\input{AO22_schematic.tex} + +\paragraph{Truth Table} +%\input{AO22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AO3111_circuit.tex b/Documents/LaTeX/AO23_circuit.tex similarity index 65% rename from Documents/LaTeX/AO3111_circuit.tex rename to Documents/LaTeX/AO23_circuit.tex index 77fd0fc9..2a13a733 100644 --- a/Documents/LaTeX/AO3111_circuit.tex +++ b/Documents/LaTeX/AO23_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AO3111.tex +%% File: StdCellLib/Documents/LaTeX/AO23_circuit.tex %% -%% Purpose: Circuit File for AO3111 +%% Purpose: Circuit File for AO23 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,22 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \gate{not}{19}{4}{R}{}{} % NOT \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D0} % pin D0 - \pin{1}{9}{L}{D1} % pin D1 - \pin{1}{11}{L}{D2} % pin D2 - \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR gate -> right - \gate{not}{19}{4}{R}{}{} % NOT gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{2}{5}{9}{5} % wire from pin C - \wire{9}{9}{9}{7} % wire between AND and NOR + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{9}{7}{9}{9} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 \pin{23}{4}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/AO23_manpage.tex b/Documents/LaTeX/AO23_manpage.tex new file mode 100644 index 00000000..aee79bac --- /dev/null +++ b/Documents/LaTeX/AO23_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO23_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AO23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AO23 - a 2-3-input AND-OR gate} \label{logical:AO23} + +\paragraph{Synopsys} +\begin{quote} + AO23 (Z B1 B A2 A1 A) +\end{quote} + +\paragraph{Description} +\input{AO23_circuit.tex} +%\input{AO23_schematic.tex} + +\paragraph{Truth Table} +%\input{AO23_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AO31_circuit.tex b/Documents/LaTeX/AO31_circuit.tex new file mode 100644 index 00000000..0706a6c0 --- /dev/null +++ b/Documents/LaTeX/AO31_circuit.tex @@ -0,0 +1,53 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO31_circuit.tex +%% +%% Purpose: Circuit File for AO31 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{8} + \usgate + \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO31_manpage.tex b/Documents/LaTeX/AO31_manpage.tex new file mode 100644 index 00000000..cd062781 --- /dev/null +++ b/Documents/LaTeX/AO31_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO31_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AO31 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AO31 - a 3-1-input AND-OR gate} \label{logical:AO31} + +\paragraph{Synopsys} +\begin{quote} + AO31 (Z B2 B1 B A) +\end{quote} + +\paragraph{Description} +\input{AO31_circuit.tex} +%\input{AO31_schematic.tex} + +\paragraph{Truth Table} +%\input{AO31_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AO32_circuit.tex b/Documents/LaTeX/AO32_circuit.tex new file mode 100644 index 00000000..bd474b55 --- /dev/null +++ b/Documents/LaTeX/AO32_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO32_circuit.tex +%% +%% Purpose: Circuit File for AOI32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{3}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{9}{7}{9}{5} % wire between AND and NOR + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO32_manpage.tex b/Documents/LaTeX/AO32_manpage.tex new file mode 100644 index 00000000..009d9281 --- /dev/null +++ b/Documents/LaTeX/AO32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO32_manpage.tex +%% +%% Purpose: Manual Page File for AO32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AO32} +\paragraph{Cell} +\begin{quote} + \textbf{AO32} - a 3-2-input AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AO32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AO32_circuit.tex} +%\input{AO32_schematic.tex} + +\paragraph{Truth Table} +%\input{AO32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AO33_circuit.tex b/Documents/LaTeX/AO33_circuit.tex new file mode 100644 index 00000000..2b3fa381 --- /dev/null +++ b/Documents/LaTeX/AO33_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO33_circuit.tex +%% +%% Purpose: Circuit File for AO33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \gate{not}{19}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{7}{9}{9} % wire between OR and NAND + \pin{23}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO33_manpage.tex b/Documents/LaTeX/AO33_manpage.tex new file mode 100644 index 00000000..badb8da4 --- /dev/null +++ b/Documents/LaTeX/AO33_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO33_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AO33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AO33 - a 3-3-input AND-OR-Invert gate} \label{logical:AO33} + +\paragraph{Synopsys} +\begin{quote} + AO33 (Z B2 B1 B A2 A1 A) +\end{quote} + +\paragraph{Description} +\input{AO33_circuit.tex} +%\input{AO33_schematic.tex} + +\paragraph{Truth Table} +%\input{AO33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AO3111_truthtable.tex b/Documents/LaTeX/AO33_truthtable.tex similarity index 95% rename from Documents/LaTeX/AO3111_truthtable.tex rename to Documents/LaTeX/AO33_truthtable.tex index 63966b57..51b543ab 100644 --- a/Documents/LaTeX/AO3111_truthtable.tex +++ b/Documents/LaTeX/AO33_truthtable.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AO3111.tex +%% File: StdCellLib/Documents/LaTeX/AO33_truthtable.tex %% -%% Purpose: Truth Table File for AO3111 +%% Purpose: Truth Table File for AO33 %% %% ************ LaTeX with circdia.sty package *************** %% diff --git a/Documents/LaTeX/AO41_circuit.tex b/Documents/LaTeX/AO41_circuit.tex new file mode 100644 index 00000000..2e11c723 --- /dev/null +++ b/Documents/LaTeX/AO41_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO41_circuit.tex +%% +%% Purpose: Circuit File for AO41 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{4}]{and}{5}{6}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{B3} % pin B3 + \wire{9}{5}{9}{6} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO41_manpage.tex b/Documents/LaTeX/AO41_manpage.tex new file mode 100644 index 00000000..3703ce6b --- /dev/null +++ b/Documents/LaTeX/AO41_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO41_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AO41 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AO41 - a 4-1-input AND-OR gate} \label{logical:AO41} + +\paragraph{Synopsys} +\begin{quote} + AO41 (Z B3 B2 B1 B A) +\end{quote} + +\paragraph{Description} +\input{AO41_circuit.tex} +%\input{AO41_schematic.tex} + +\paragraph{Truth Table} +%\input{AO41_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AO42_circuit.tex b/Documents/LaTeX/AO42_circuit.tex new file mode 100644 index 00000000..e537a768 --- /dev/null +++ b/Documents/LaTeX/AO42_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO42_circuit.tex +%% +%% Purpose: Circuit File for AO42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{4}]{and}{5}{8}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \pin{1}{11}{L}{B3} % pin B3 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{9}{8}{9}{5} % wire between AND and NOR + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO42_manpage.tex b/Documents/LaTeX/AO42_manpage.tex new file mode 100644 index 00000000..92200f42 --- /dev/null +++ b/Documents/LaTeX/AO42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO42_manpage.tex +%% +%% Purpose: Manual Page File for AO42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AO42} +\paragraph{Cell} +\begin{quote} + \textbf{AO42} - a 4-2-input AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AO42(Z, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AO42_circuit.tex} +%\input{AO42_schematic.tex} + +\paragraph{Truth Table} +%\input{AO42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AO43_circuit.tex b/Documents/LaTeX/AO43_circuit.tex new file mode 100644 index 00000000..50373b32 --- /dev/null +++ b/Documents/LaTeX/AO43_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO43_circuit.tex +%% +%% Purpose: Circuit File for AO43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \gate{not}{19}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin 42 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{7}{9}{10} % wire between OR and NAND + \pin{23}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AO43_manpage.tex b/Documents/LaTeX/AO43_manpage.tex new file mode 100644 index 00000000..bc4a16b6 --- /dev/null +++ b/Documents/LaTeX/AO43_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AO43_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AO43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AO43 - a 4-3-input AND-OR-Invert gate} \label{logical:AO43} + +\paragraph{Synopsys} +\begin{quote} + AO43 (Z, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AO43_circuit.tex} +%\input{AO43_schematic.tex} + +\paragraph{Truth Table} +%\input{AO43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOA211_circuit.tex b/Documents/LaTeX/AOA211_circuit.tex new file mode 100644 index 00000000..e6ed0b63 --- /dev/null +++ b/Documents/LaTeX/AOA211_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA211_circuit.tex +%% +%% Purpose: Circuit File for AOA211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{10} + \usgate + \gate[\inputs{2}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{9}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOA211_manpage.tex b/Documents/LaTeX/AOA211_manpage.tex new file mode 100644 index 00000000..353ea3e2 --- /dev/null +++ b/Documents/LaTeX/AOA211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA211_manpage.tex +%% +%% Purpose: Manual Page File for AOA211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOA211} +\paragraph{Cell} +\begin{quote} + \textbf{AOA211} - a 2-1-1-input AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOA211(Z, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOA211_circuit.tex} +%\input{AOA211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOA211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOA212_circuit.tex b/Documents/LaTeX/AOA212_circuit.tex new file mode 100644 index 00000000..1e21745d --- /dev/null +++ b/Documents/LaTeX/AOA212_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA212_circuit.tex +%% +%% Purpose: Circuit File for AOA212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{19}{3}{R}{}{} % NAND + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{16}{5}{16}{7} % wire between AND and OR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOA212_manpage.tex b/Documents/LaTeX/AOA212_manpage.tex new file mode 100644 index 00000000..abc6220b --- /dev/null +++ b/Documents/LaTeX/AOA212_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA212_manpage.tex +%% +%% Purpose: Manual Page File for AOA212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOA212} +\paragraph{Cell} +\begin{quote} + \textbf{AOA212} - a 2-1-2-input AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOA212(Z, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOA212_circuit.tex} +%\input{AOA212_schematic.tex} + +\paragraph{Truth Table} +%\input{AOA212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOA221_circuit.tex b/Documents/LaTeX/AOA221_circuit.tex new file mode 100644 index 00000000..8ef72509 --- /dev/null +++ b/Documents/LaTeX/AOA221_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA221_circuit.tex +%% +%% Purpose: Circuit File for AOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{9}{7}{9}{9} % wire between AND and OR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOA221_manpage.tex b/Documents/LaTeX/AOA221_manpage.tex new file mode 100644 index 00000000..ac63e912 --- /dev/null +++ b/Documents/LaTeX/AOA221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA221_manpage.tex +%% +%% Purpose: Manual Page File for AOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOA221} +\paragraph{Cell} +\begin{quote} + \textbf{AOA221} - a 2-2-1-input AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOA221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AOA221_circuit.tex} +%\input{AOA221_schematic.tex} + +\paragraph{Truth Table} +%\input{AOA221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI311_circuit.tex b/Documents/LaTeX/AOA311_circuit.tex similarity index 69% rename from Documents/LaTeX/OAI311_circuit.tex rename to Documents/LaTeX/AOA311_circuit.tex index 4f1911e8..a09383d8 100644 --- a/Documents/LaTeX/OAI311_circuit.tex +++ b/Documents/LaTeX/AOA311_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI311.tex +%% File: StdCellLib/Documents/LaTeX/AOA311_circuit.tex %% -%% Purpose: Circuit File for OAI311 +%% Purpose: Circuit File for AOA311 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,20 +34,22 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{10} + \begin{circuitdiagram}{31}{10} + \usgate + \gate[\inputs{3}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND + \gate{not}{26}{3}{R}{}{} % NOT \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C0} % pin C0 - \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 \pin{1}{9}{L}{C2} % pin C2 - \gate[\inputs{3}]{or}{5}{7}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND gate -> right - \wire{9}{5}{9}{7} % wire between OR and NAND - \wire{2}{1}{9}{1} % wire between pin and NAND - \wire{2}{3}{9}{3} % wire between pin and NAND - \pin{17}{3}{R}{Z} % pin Z + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin C + \pin{30}{3}{R}{Z} % pin Z \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOA311_manpage.tex b/Documents/LaTeX/AOA311_manpage.tex new file mode 100644 index 00000000..4b0e1a64 --- /dev/null +++ b/Documents/LaTeX/AOA311_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOA311_manpage.tex +%% +%% Purpose: Manual Page File for AOA311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOA311} +\paragraph{Cell} +\begin{quote} + \textbf{AOA311} - a 3-1-1-input AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOA311(Z, C2, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOA311_circuit.tex} +%\input{AOA311_schematic.tex} + +\paragraph{Truth Table} +%\input{AOA311_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAI211_circuit.tex b/Documents/LaTeX/AOAI211_circuit.tex new file mode 100644 index 00000000..2cb440d0 --- /dev/null +++ b/Documents/LaTeX/AOAI211_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI211_circuit.tex +%% +%% Purpose: Circuit File for AOAI211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{10} + \usgate + \gate[\inputs{2}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{9}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin C + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAI211_manpage.tex b/Documents/LaTeX/AOAI211_manpage.tex new file mode 100644 index 00000000..8537a5f9 --- /dev/null +++ b/Documents/LaTeX/AOAI211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI211_manpage.tex +%% +%% Purpose: Manual Page File for AOAI211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAI211} +\paragraph{Cell} +\begin{quote} + \textbf{AOAI211} - a 2-1-1-input AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAI211(Z, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAI211_circuit.tex} +%\input{AOAI211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAI211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAI212_circuit.tex b/Documents/LaTeX/AOAI212_circuit.tex new file mode 100644 index 00000000..baf5a044 --- /dev/null +++ b/Documents/LaTeX/AOAI212_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI212_circuit.tex +%% +%% Purpose: Circuit File for AOAI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{19}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{16}{5}{16}{7} % wire between AND and OR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin B + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAI212_manpage.tex b/Documents/LaTeX/AOAI212_manpage.tex new file mode 100644 index 00000000..8aa80bbd --- /dev/null +++ b/Documents/LaTeX/AOAI212_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI212_manpage.tex +%% +%% Purpose: Manual Page File for AOAI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAI212} +\paragraph{Cell} +\begin{quote} + \textbf{AOAI212} - a 2-1-2-input AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAI212(Y, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAI212_circuit.tex} +%\input{AOAI212_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAI212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAI221_circuit.tex b/Documents/LaTeX/AOAI221_circuit.tex new file mode 100644 index 00000000..ab924c6b --- /dev/null +++ b/Documents/LaTeX/AOAI221_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI221_circuit.tex +%% +%% Purpose: Circuit File for AOAI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{9}{7}{9}{9} % wire between AND and OR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin B + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAI221_manpage.tex b/Documents/LaTeX/AOAI221_manpage.tex new file mode 100644 index 00000000..f7f3e12f --- /dev/null +++ b/Documents/LaTeX/AOAI221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI221_manpage.tex +%% +%% Purpose: Manual Page File for AOAI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAI221} +\paragraph{Cell} +\begin{quote} + \textbf{AOAI221} - a 2-2-1-input AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAI221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAI221_circuit.tex} +%\input{AOAI221_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI311_circuit.tex b/Documents/LaTeX/AOAI311_circuit.tex similarity index 71% rename from Documents/LaTeX/AOI311_circuit.tex rename to Documents/LaTeX/AOAI311_circuit.tex index 1f94e723..35d0711b 100644 --- a/Documents/LaTeX/AOI311_circuit.tex +++ b/Documents/LaTeX/AOAI311_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI211.tex +%% File: StdCellLib/Documents/LaTeX/AOAI311_circuit.tex %% -%% Purpose: Circuit File for AOI211 +%% Purpose: Circuit File for AOAI311 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,20 +34,21 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{10} + \begin{circuitdiagram}{25}{10} + \usgate + \gate[\inputs{3}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C0} % pin C0 + \pin{1}{5}{L}{C} % pin C \pin{1}{7}{L}{C1} % pin C1 \pin{1}{9}{L}{C2} % pin C2 - \gate[\inputs{3}]{and}{5}{7}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{9}{7}{9}{5} % wire between AND and NOR - \pin{17}{3}{R}{Z} % pin Z + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \pin{24}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOAI311_manpage.tex b/Documents/LaTeX/AOAI311_manpage.tex new file mode 100644 index 00000000..b891005a --- /dev/null +++ b/Documents/LaTeX/AOAI311_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAI311_manpage.tex +%% +%% Purpose: Manual Page File for AOAI311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAI311} +\paragraph{Cell} +\begin{quote} + \textbf{AOAI311} - a 3-1-1-input AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAI311(Z, C2, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAI311_circuit.tex} +%\input{AOAI311_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAI311_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAO2111_circuit.tex b/Documents/LaTeX/AOAO2111_circuit.tex new file mode 100644 index 00000000..056fd2bf --- /dev/null +++ b/Documents/LaTeX/AOAO2111_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO2111_circuit.tex +%% +%% Purpose: Circuit File for AOAO2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAO2111_manpage.tex b/Documents/LaTeX/AOAO2111_manpage.tex new file mode 100644 index 00000000..5d763cb0 --- /dev/null +++ b/Documents/LaTeX/AOAO2111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO2111_manpage.tex +%% +%% Purpose: Manual Page File for AOAO2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAO2111} +\paragraph{Cell} +\begin{quote} + \textbf{AOAO2111} - a 2-1-1-1-input AND-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAO2111(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAO2111_circuit.tex} +%\input{AOAO2111_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAO2111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAO2211_circuit.tex b/Documents/LaTeX/AOAO2211_circuit.tex new file mode 100644 index 00000000..b73d7e3f --- /dev/null +++ b/Documents/LaTeX/AOAO2211_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO2211_circuit.tex +%% +%% Purpose: Circuit File for AOAO2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{13}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between AND and OR + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAO2211_manpage.tex b/Documents/LaTeX/AOAO2211_manpage.tex new file mode 100644 index 00000000..5dfc366e --- /dev/null +++ b/Documents/LaTeX/AOAO2211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO2211_manpage.tex +%% +%% Purpose: Manual Page File for AOAO2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAO2211} +\paragraph{Cell} +\begin{quote} + \textbf{AOAO2211} - a 2-2-1-1-input AND-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAO2211(Z, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAO2211_circuit.tex} +%\input{AOAO2211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAO2211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAO3211_circuit.tex b/Documents/LaTeX/AOAO3211_circuit.tex new file mode 100644 index 00000000..b6139dc8 --- /dev/null +++ b/Documents/LaTeX/AOAO3211_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO3211_circuit.tex +%% +%% Purpose: Circuit File for AOAO3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \pin{1}{13}{L}{D2} % pin D2 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between OR and AND + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAO3211_manpage.tex b/Documents/LaTeX/AOAO3211_manpage.tex new file mode 100644 index 00000000..2edce95a --- /dev/null +++ b/Documents/LaTeX/AOAO3211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAO3211_manpage.tex +%% +%% Purpose: Manual Page File for AOAO3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAO3211} +\paragraph{Cell} +\begin{quote} + \textbf{AOAO3211} - a 3-2-1-1-input AND-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAO3211(Z, D2, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAO3211_circuit.tex} +%\input{AOAO3211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAO3211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAOAO211111_circuit.tex b/Documents/LaTeX/AOAOAO211111_circuit.tex new file mode 100644 index 00000000..0cb31fcf --- /dev/null +++ b/Documents/LaTeX/AOAOAO211111_circuit.tex @@ -0,0 +1,64 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOAO211111_circuit.tex +%% +%% Purpose: Circuit File for AOAOAO211111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{52}{16} + \usgate + \gate[\inputs{2}]{and}{5}{13}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{26}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{33}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{40}{3}{R}{}{} % NOR + \gate{not}{47}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{9}{L}{E} % pin E + \pin{1}{11}{L}{F} % pin F + \pin{1}{15}{L}{F1} % pin F1 + \wire{2}{1}{37}{1} % wire from pin A + \wire{2}{3}{30}{3} % wire from pin B + \wire{2}{5}{23}{5} % wire from pin C + \wire{2}{7}{16}{7} % wire from pin D + \wire{2}{9}{10}{9} % wire from pin E + \pin{51}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAOAO211111_manpage.tex b/Documents/LaTeX/AOAOAO211111_manpage.tex new file mode 100644 index 00000000..00e2970c --- /dev/null +++ b/Documents/LaTeX/AOAOAO211111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOAO211111_manpage.tex +%% +%% Purpose: Manual Page File for AOAOAO211111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAOAO211111} +\paragraph{Cell} +\begin{quote} + \textbf{AOAOAO211111} - a 2-1-1-1-1-1-input AND-OR-AND-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAOAO211111(Z, F1, F, E, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAOAO211111_circuit.tex} +%\input{AOAOAO211111_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAOAO211111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAOAOI211111_circuit.tex b/Documents/LaTeX/AOAOAOI211111_circuit.tex new file mode 100644 index 00000000..a3cef8c7 --- /dev/null +++ b/Documents/LaTeX/AOAOAOI211111_circuit.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOAOI211111_circuit.tex +%% +%% Purpose: Circuit File for AOAOAOI211111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{46}{16} + \usgate + \gate[\inputs{2}]{and}{5}{13}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{26}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{33}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{40}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{9}{L}{E} % pin E + \pin{1}{11}{L}{F} % pin F + \pin{1}{15}{L}{F1} % pin F1 + \wire{2}{1}{37}{1} % wire from pin A + \wire{2}{3}{30}{3} % wire from pin B + \wire{2}{5}{23}{5} % wire from pin C + \wire{2}{7}{16}{7} % wire from pin D + \wire{2}{9}{10}{9} % wire from pin E + \pin{45}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAOAOI211111_manpage.tex b/Documents/LaTeX/AOAOAOI211111_manpage.tex new file mode 100644 index 00000000..dcca1d91 --- /dev/null +++ b/Documents/LaTeX/AOAOAOI211111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOAOI211111_manpage.tex +%% +%% Purpose: Manual Page File for AOAOAOI211111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAOAOI211111} +\paragraph{Cell} +\begin{quote} + \textbf{AOAOAOI211111} - a 2-1-1-1-1-1-input AND-OR-AND-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAOAOI211111(Y, F1, F, E, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAOAOI211111_circuit.tex} +%\input{AOAOAOI211111_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAOAOI211111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AO2111_circuit.tex b/Documents/LaTeX/AOAOI2111_circuit.tex similarity index 68% rename from Documents/LaTeX/AO2111_circuit.tex rename to Documents/LaTeX/AOAOI2111_circuit.tex index 1383adc8..9850fd6d 100644 --- a/Documents/LaTeX/AO2111_circuit.tex +++ b/Documents/LaTeX/AOAOI2111_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AO2111.tex +%% File: StdCellLib/Documents/LaTeX/AOAOI2111_circuit.tex %% -%% Purpose: Circuit File for AO2111 +%% Purpose: Circuit File for AOAOI2111 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{24}{12} + \begin{circuitdiagram}{32}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D0} % pin D0 + \pin{1}{7}{L}{D} % pin D \pin{1}{11}{L}{D1} % pin D1 - \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR gate -> right - \gate{not}{19}{4}{R}{}{} % NOT gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{2}{5}{9}{5} % wire from pin C - \wire{9}{9}{9}{7} % wire between AND and NOR - \pin{23}{4}{R}{Z} % pin Z + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \pin{31}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOAOI2111_manpage.tex b/Documents/LaTeX/AOAOI2111_manpage.tex new file mode 100644 index 00000000..09d9cade --- /dev/null +++ b/Documents/LaTeX/AOAOI2111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOI2111_manpage.tex +%% +%% Purpose: Manual Page File for AOAOI2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAOI2111} +\paragraph{Cell} +\begin{quote} + \textbf{AOAOI2111} - a 2-1-1-1-input AND-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAOI2111(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAOI2111_circuit.tex} +%\input{AOAOI2111_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAOI2111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAOI2211_circuit.tex b/Documents/LaTeX/AOAOI2211_circuit.tex new file mode 100644 index 00000000..ef997ede --- /dev/null +++ b/Documents/LaTeX/AOAOI2211_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOI2211_circuit.tex +%% +%% Purpose: Circuit File for AOAOI2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{32}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{13}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between AND and OR + \pin{31}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAOI2211_manpage.tex b/Documents/LaTeX/AOAOI2211_manpage.tex new file mode 100644 index 00000000..a4c2dcc2 --- /dev/null +++ b/Documents/LaTeX/AOAOI2211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOI2211_manpage.tex +%% +%% Purpose: Manual Page File for AOAOI2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAOI2211} +\paragraph{Cell} +\begin{quote} + \textbf{AOAOI2211} - a 2-2-1-1-input AND-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAOI2211(Z, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAOI2211_circuit.tex} +%\input{AOAOI2211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAOI2211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOAOI3211_circuit.tex b/Documents/LaTeX/AOAOI3211_circuit.tex new file mode 100644 index 00000000..4898e6ce --- /dev/null +++ b/Documents/LaTeX/AOAOI3211_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOI3211_circuit.tex +%% +%% Purpose: Circuit File for AOAOI3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{32}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{3}]{or}{12}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{19}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{26}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \pin{1}{13}{L}{D2} % pin D2 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between AND and OR + \pin{31}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOAOI3211_manpage.tex b/Documents/LaTeX/AOAOI3211_manpage.tex new file mode 100644 index 00000000..aaa31460 --- /dev/null +++ b/Documents/LaTeX/AOAOI3211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOAOI3211_manpage.tex +%% +%% Purpose: Manual Page File for AOAOI3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOAOI3211} +\paragraph{Cell} +\begin{quote} + \textbf{AOAOI3211} - a 3-2-1-1-input AND-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOAOI3211(Z, D2, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{AOAOI3211_circuit.tex} +%\input{AOAOI3211_schematic.tex} + +\paragraph{Truth Table} +%\input{AOAOI3211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI211_manpage.tex b/Documents/LaTeX/AOI211_manpage.tex deleted file mode 100644 index fb12e8da..00000000 --- a/Documents/LaTeX/AOI211_manpage.tex +++ /dev/null @@ -1,64 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI211.tex -%% -%% Purpose: Manual Page File for AOI211 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI211} -\paragraph{Cell} -\begin{quote} - \textbf{AOI211} - a 2-1-1-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI211(Z, C1, C0, B, A) -\end{quote} - -\paragraph{Description} -\input{AOI211_circuit.tex} -\input{AOI211_schematic.tex} - -\paragraph{Truth Table} -\input{AOI211_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI311 - a 3-1-1-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI21_circuit.tex b/Documents/LaTeX/AOI21_circuit.tex index a61f1bdd..df9446f0 100644 --- a/Documents/LaTeX/AOI21_circuit.tex +++ b/Documents/LaTeX/AOI21_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI21.tex +%% File: StdCellLib/Documents/LaTeX/AOI21_circuit.tex %% %% Purpose: Circuit File for AOI21 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -37,13 +37,14 @@ \begin{figure}[h] %\caption{Circuit} \begin{center} \begin{circuitdiagram}{18}{8} + \usgate + \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \gate[\inputs{2}]{and}{5}{5}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \pin{17}{3}{R}{Z} % pin Z + \wire{2}{1}{9}{1} % wire from pin A + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI221_manpage.tex b/Documents/LaTeX/AOI221_manpage.tex deleted file mode 100644 index bb47530e..00000000 --- a/Documents/LaTeX/AOI221_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI221.tex -%% -%% Purpose: Manual Page File for AOI221 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI221} -\paragraph{Cell} -\begin{quote} - \textbf{AOI221} - a 2-2-1-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI221(Z, C1, C0, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{AOI221_circuit.tex} -\input{AOI221_schematic.tex} - -\paragraph{Truth Table} -\input{AOI221_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI321 - a 3-2-1-input AND-OR-Invert gate \\ - AOI331 - a 3-3-1-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI222_manpage.tex b/Documents/LaTeX/AOI222_manpage.tex deleted file mode 100644 index 29831545..00000000 --- a/Documents/LaTeX/AOI222_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI222.tex -%% -%% Purpose: Manual Page File for AOI222 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI222} -\paragraph{Cell} -\begin{quote} - \textbf{AOI222} - a 2-2-2-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI222(Z, C1, C0, B1, B0, A1, A0) -\end{quote} - -\paragraph{Description} -\input{AOI222_circuit.tex} -\input{AOI222_schematic.tex} - -\paragraph{Truth Table} -\input{AOI222_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI322 - a 3-2-2-input AND-OR-Invert gate \\ - AOI332 - a 3-3-2-input AND-OR-Invert gate \\ - AOI333 - a 3-3-3-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI22_circuit.tex b/Documents/LaTeX/AOI22_circuit.tex index 60818db2..1972c559 100644 --- a/Documents/LaTeX/AOI22_circuit.tex +++ b/Documents/LaTeX/AOI22_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI22.tex +%% File: StdCellLib/Documents/LaTeX/AOI22_circuit.tex %% %% Purpose: Circuit File for AOI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,19 +34,20 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{11}{L}{B1} % pin B1 - \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR gate -> right - \wire{9}{3}{9}{4} % wire between AND and NOR - \wire{9}{9}{9}{8} % wire between AND and NOR - \pin{17}{6}{R}{Z} % pin Z + \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{2}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{9}{5}{9}{7} % wire between OR and NAND + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI22_manpage.tex b/Documents/LaTeX/AOI22_manpage.tex index c40faede..d551ad30 100644 --- a/Documents/LaTeX/AOI22_manpage.tex +++ b/Documents/LaTeX/AOI22_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI22.tex +%% File: StdCellLib/Documents/LaTeX/AOI22_manpage.tex %% %% Purpose: Manual Page File for AOI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,15 +40,15 @@ \paragraph{Synopsys} \begin{quote} - AOI22(Z, B1, B0, A1, A0) + AOI22(Z, B1, B, A1, A) \end{quote} \paragraph{Description} \input{AOI22_circuit.tex} -\input{AOI22_schematic.tex} +%\input{AOI22_schematic.tex} \paragraph{Truth Table} -\input{AOI22_truthtable.tex} +%\input{AOI22_truthtable.tex} \paragraph{Usage} @@ -57,8 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI33 - a 3-3-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI23_circuit.tex b/Documents/LaTeX/AOI23_circuit.tex new file mode 100644 index 00000000..11b8dc51 --- /dev/null +++ b/Documents/LaTeX/AOI23_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI23_circuit.tex +%% +%% Purpose: Circuit File for AOI23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{2}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{9}{7}{9}{9} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOI23_manpage.tex b/Documents/LaTeX/AOI23_manpage.tex new file mode 100644 index 00000000..18cce3d8 --- /dev/null +++ b/Documents/LaTeX/AOI23_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI23_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AOI23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AOI23 - a 2-3-input AND-OR-Invert gate} \label{logical:AOI23} + +\paragraph{Synopsys} +\begin{quote} + AOI23 (Z B1 B A2 A1 A) +\end{quote} + +\paragraph{Description} +\input{AOI23_circuit.tex} +%\input{AOI23_schematic.tex} + +\paragraph{Truth Table} +%\input{AOI23_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOI311_manpage.tex b/Documents/LaTeX/AOI311_manpage.tex deleted file mode 100644 index 26924d68..00000000 --- a/Documents/LaTeX/AOI311_manpage.tex +++ /dev/null @@ -1,64 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI311.tex -%% -%% Purpose: Manual Page File for AOI311 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI311} -\paragraph{Cell} -\begin{quote} - \textbf{AOI311} - a 3-1-1-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI311(Z, C2, C1, C0, B, A) -\end{quote} - -\paragraph{Description} -\input{AOI311_circuit.tex} -\input{AOI311_schematic.tex} - -\paragraph{Truth Table} -\input{AOI311_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI211 - a 2-1-1-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI311_schematic.tex b/Documents/LaTeX/AOI311_schematic.tex deleted file mode 100644 index a71a87d3..00000000 --- a/Documents/LaTeX/AOI311_schematic.tex +++ /dev/null @@ -1,79 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI311.tex -%% -%% Purpose: Schematic File for AOI311 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\begin{center} - Schematic (one stage, 3$T_{p}$/3$T_{n}$ stacked, 10T total) - \begin{figure}[h] %\caption{Schematic} - \begin{center} - \begin{circuitdiagram}{36}{39} - \pin{2}{14.5}{L}{A} % pin A, n-channel - \pin{14}{14.5}{L}{B} % pin B, n-channel - \pin{26}{2.5}{L}{C2} % pin C2, n-channel - \pin{26}{8.5}{L}{C1} % pin C1, n-channel - \pin{26}{14.5}{L}{C0} % pin C0, p-channel - \pin{2}{23.5}{L}{A} % pin A, p-channel - \pin{2}{29.5}{L}{B} % pin B, p-channel - \pin{2}{35.5}{L}{C0} % pin C0, p-channel - \pin{14}{35.5}{L}{C1} % pin C1, p-channel - \pin{26}{35.5}{L}{C2} % pin C2, p-channel - \trans[\wireU{0.5}]{nenh*}{6}{16}{R}{$M_{NA}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{16}{R}{$M_{NB}$}{} - \trans[\wireU{0.5}]{nenh*}{30}{4}{R}{$M_{NC2}$}{} - \trans[\wireUD{0.5}]{nenh*}{30}{10}{R}{$M_{NC1}$}{} - \trans[\wireUD{0.5}]{nenh*}{30}{16}{R}{$M_{NC0}$}{} - \trans[\wireUD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA}$} - \trans[\wireUD{0.5}]{penh*}{6}{28}{R}{}{$M_{PB}$} - \trans[\wireUD{0.5}]{penh*}{6}{34}{R}{}{$M_{PC0}$} - \trans[\wireD{0.5}]{penh*}{18}{34}{R}{}{$M_{PC1}$} - \trans[\wireD{0.5}]{penh*}{30}{34}{R}{}{$M_{PC2}$} - \ground{8}{0.5}{D} % ground below nmos - \ground{20}{0.5}{D} % ground below nmos - \ground{32}{0.5}{D} % ground below nmos - \power{8}{37.5}{U}{} % power above left pmos - \power{20}{37.5}{U}{} % power above middle pmos - \power{32}{37.5}{U}{} % power above right pmos - \wire{8}{1}{8}{14} - \wire{20}{1}{20}{14} - \wire{8}{31}{32}{31} % wire short between pmos - \wire{8}{19}{34}{19} % wire before pin Z - \junct{8}{19} - \junct{8}{31} - \junct{20}{19} - \junct{20}{31} - \junct{32}{19} - \pin{35}{19}{R}{Z} % pin Z - \end{circuitdiagram} - \end{center} - \end{figure} -\end{center} diff --git a/Documents/LaTeX/AOI31_circuit.tex b/Documents/LaTeX/AOI31_circuit.tex index e531e9e0..1d34b97c 100644 --- a/Documents/LaTeX/AOI31_circuit.tex +++ b/Documents/LaTeX/AOI31_circuit.tex @@ -44,7 +44,7 @@ \gate[\inputs{3}]{and}{5}{5}{R}{}{} % AND gate -> right \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR gate -> right \wire{2}{1}{9}{1} % wire from pin A - \pin{17}{3}{R}{Z} % pin Z + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI321_manpage.tex b/Documents/LaTeX/AOI321_manpage.tex deleted file mode 100644 index 739d1d52..00000000 --- a/Documents/LaTeX/AOI321_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI321.tex -%% -%% Purpose: Manual Page File for AOI321 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI321} -\paragraph{Cell} -\begin{quote} - \textbf{AOI321} - a 3-2-1-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI321(Z, C2, C1, C0, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{AOI321_circuit.tex} -\input{AOI321_schematic.tex} - -\paragraph{Truth Table} -\input{AOI321_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI311 - a 3-1-1-input AND-OR-Invert gate \\ - AOI331 - a 3-3-1-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI322_manpage.tex b/Documents/LaTeX/AOI322_manpage.tex deleted file mode 100644 index 90e31b88..00000000 --- a/Documents/LaTeX/AOI322_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI322.tex -%% -%% Purpose: Manual Page File for AOI322 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI322} -\paragraph{Cell} -\begin{quote} - \textbf{AOI322} - a 3-2-2-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI322(Z, C2, C1, C0, B1, B0, A1, A0) -\end{quote} - -\paragraph{Description} -\input{AOI322_circuit.tex} -\input{AOI322_schematic.tex} - -\paragraph{Truth Table} -\input{AOI322_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI222 - a 2-2-2-input AND-OR-Invert gate \\ - AOI332 - a 3-2-2-input AND-OR-Invert gate \\ - AOI333 - a 3-3-3-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI32_circuit.tex b/Documents/LaTeX/AOI32_circuit.tex index 6fbede25..3c69e4a6 100644 --- a/Documents/LaTeX/AOI32_circuit.tex +++ b/Documents/LaTeX/AOI32_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI32.tex +%% File: StdCellLib/Documents/LaTeX/AOI32_circuit.tex %% -%% Purpose: Circuit File for AOI33 +%% Purpose: Circuit File for AOI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,20 +34,21 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{9}{L}{B1} % pin B1 - \pin{1}{11}{L}{B2} % pin B2 - \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR gate -> right - \wire{9}{3}{9}{4} % wire between AND and NOR - \wire{9}{9}{9}{8} % wire between AND and NOR - \pin{17}{6}{R}{Z} % pin Z + \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{3}]{and}{5}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{9}{7}{9}{5} % wire between AND and NOR + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI32_manpage.tex b/Documents/LaTeX/AOI32_manpage.tex index 85ea6f89..d0df745a 100644 --- a/Documents/LaTeX/AOI32_manpage.tex +++ b/Documents/LaTeX/AOI32_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI32.tex +%% File: StdCellLib/Documents/LaTeX/AOI32_manpage.tex %% %% Purpose: Manual Page File for AOI32 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,7 +40,7 @@ \paragraph{Synopsys} \begin{quote} - AOI32(Z, B2, B1, B0, A1, A0) + AOI32(Z, B2, B1, B, A1, A) \end{quote} \paragraph{Description} @@ -57,9 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI22 - a 2-2-input AND-OR-Invert gate \\ - AOI33 - a 3-3-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI32_schematic.tex b/Documents/LaTeX/AOI32_schematic.tex index 25395994..d415093d 100644 --- a/Documents/LaTeX/AOI32_schematic.tex +++ b/Documents/LaTeX/AOI32_schematic.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI32.tex +%% File: StdCellLib/Documents/LaTeX/AOI32_schematic.tex %% %% Purpose: Schematic File for AOI32 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -33,42 +33,45 @@ %% %% /////////////////////////////////////////////////////////////////// \begin{center} - Schematic (one stage, 2$T_{p}$/3$T_{n}$ stacked, 10T total) + Schematic (one stage, 3$T_{p}$/3$T_{n}$ stacked, 10T total) \begin{figure}[h] %\caption{Schematic} \begin{center} - \begin{circuitdiagram}{36}{33} - \pin{2}{14.5}{L}{A0} % pin A0, n-channel - \pin{2}{8.5}{L}{A1} % pin A1, n-channel - \pin{14}{14.5}{L}{B0} % pin B0, p-channel - \pin{14}{8.5}{L}{B1} % pin B1, p-channel - \pin{14}{2.5}{L}{B2} % pin B2, n-channel - \pin{2}{23.5}{L}{A0} % pin A0, p-channel - \pin{14}{23.5}{L}{A1} % pin A1, p-channel - \pin{2}{29.5}{L}{B0} % pin B0, p-channel - \pin{14}{29.5}{L}{B1} % pin B1, p-channel - \pin{26}{29.5}{L}{B2} % pin B2, p-channel - \trans[\wireU{0.5}]{nenh*}{6}{10}{R}{$M_{NA1}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{16}{R}{$M_{NA0}$}{} - \trans[\wireUD{0.5}]{nenh*}{18}{16}{R}{$M_{NB0}$}{} - \trans[\wireUD{0.5}]{nenh*}{18}{10}{R}{$M_{NB1}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NB2}$}{} - \trans[\wireUD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA0}$} - \trans[\wireUD{0.5}]{penh*}{6}{28}{R}{}{$M_{PB0}$} - \trans[\wireD{0.5}]{penh*}{18}{28}{R}{}{$M_{PB1}$} - \trans[\wireUD{0.5}]{penh*}{18}{22}{R}{}{$M_{PA1}$} - \trans[\wireD{0.5}]{penh*}{30}{28}{R}{}{$M_{PB2}$} + \begin{circuitdiagram}{36}{39} + \pin{2}{14.5}{L}{A} % pin A, n-channel + \pin{14}{14.5}{L}{B} % pin B, n-channel + \pin{26}{2.5}{L}{C2} % pin C2, n-channel + \pin{26}{8.5}{L}{C1} % pin C1, n-channel + \pin{26}{14.5}{L}{C0} % pin C0, p-channel + \pin{2}{23.5}{L}{A} % pin A, p-channel + \pin{2}{29.5}{L}{B} % pin B, p-channel + \pin{2}{35.5}{L}{C0} % pin C0, p-channel + \pin{14}{35.5}{L}{C1} % pin C1, p-channel + \pin{26}{35.5}{L}{C2} % pin C2, p-channel + \trans[\wireU{0.5}]{nenh*}{6}{16}{R}{$M_{NA}$}{} + \trans[\wireU{0.5}]{nenh*}{18}{16}{R}{$M_{NB}$}{} + \trans[\wireU{0.5}]{nenh*}{30}{4}{R}{$M_{NC2}$}{} + \trans[\wireUD{0.5}]{nenh*}{30}{10}{R}{$M_{NC1}$}{} + \trans[\wireUD{0.5}]{nenh*}{30}{16}{R}{$M_{NC0}$}{} + \trans[\wireUD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA}$} + \trans[\wireUD{0.5}]{penh*}{6}{28}{R}{}{$M_{PB}$} + \trans[\wireUD{0.5}]{penh*}{6}{34}{R}{}{$M_{PC0}$} + \trans[\wireD{0.5}]{penh*}{18}{34}{R}{}{$M_{PC1}$} + \trans[\wireD{0.5}]{penh*}{30}{34}{R}{}{$M_{PC2}$} \ground{8}{0.5}{D} % ground below nmos \ground{20}{0.5}{D} % ground below nmos - \power{8}{31.5}{U}{} % power above left pmos - \power{20}{31.5}{U}{} % power above left pmos - \power{32}{31.5}{U}{} % power above left pmos - \wire{8}{1}{8}{7} - \wire{8}{25}{32}{25} % wire short between pmos + \ground{32}{0.5}{D} % ground below nmos + \power{8}{37.5}{U}{} % power above left pmos + \power{20}{37.5}{U}{} % power above middle pmos + \power{32}{37.5}{U}{} % power above right pmos + \wire{8}{1}{8}{14} + \wire{20}{1}{20}{14} + \wire{8}{31}{32}{31} % wire short between pmos \wire{8}{19}{34}{19} % wire before pin Z \junct{8}{19} - \junct{8}{25} - \junct{20}{25} + \junct{8}{31} \junct{20}{19} + \junct{20}{31} + \junct{32}{19} \pin{35}{19}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/AOI32_truthtable.tex b/Documents/LaTeX/AOI32_truthtable.tex index 88d812d8..98bc08c8 100644 --- a/Documents/LaTeX/AOI32_truthtable.tex +++ b/Documents/LaTeX/AOI32_truthtable.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI32.tex +%% File: StdCellLib/Documents/LaTeX/AOI32_truthtable.tex %% %% Purpose: Truth Table File for AOI32 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,19 +34,17 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} - {\(Z = \lnot ((B2 \land B1 \land B0) \lor (A1 \land A0)) \)} - \begin{table}[h] %\caption{\(Z = \lnot ((B2 \land B1 \land B0) \lor (A1 \land A0)) \)} + {\(Z = \lnot ((C2 \land C1 \land C0) \lor B \lor A) \)} + \begin{table}[h] %\caption{\(Z = \lnot ((C2 \land C1 \land C0) \lor B \lor A) \)} \begin{center} \begin{tabular}{|c|c|c|c|c||c|} \hline - B2 & B1 & B0 & A1 & A0 & Z \\ \hline\hline - 0 & X & X & 0 & X & 1\\ \hline - 0 & X & X & X & 0 & 1\\ \hline - 1 & 1 & 1 & X & X & 0\\ \hline - X & 0 & X & 0 & X & 1\\ \hline - X & 0 & X & X & 0 & 1\\ \hline - X & X & 0 & 0 & X & 1\\ \hline - X & X & 0 & X & 0 & 1\\ \hline - X & X & X & 1 & 1 & 0\\ \hline + C2 & C1 & C0 & B & A & Z \\ \hline\hline + 0 & X & X & 0 & 0 & 1 \\ \hline + 1 & 1 & 1 & X & X & 0 \\ \hline + X & 0 & X & 0 & 0 & 1 \\ \hline + X & X & 0 & 0 & 0 & 1 \\ \hline + X & X & X & 1 & X & 0 \\ \hline + X & X & X & X & 1 & 0 \\ \hline \end{tabular} \end{center} \end{table} diff --git a/Documents/LaTeX/AOI331_manpage.tex b/Documents/LaTeX/AOI331_manpage.tex deleted file mode 100644 index 13a24509..00000000 --- a/Documents/LaTeX/AOI331_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI331.tex -%% -%% Purpose: Manual Page File for AOI331 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI331} -\paragraph{Cell} -\begin{quote} - \textbf{AOI331} - a 3-3-1-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI331(Z, C2, C1, C0, B2, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{AOI331_circuit.tex} -\input{AOI331_schematic.tex} - -\paragraph{Truth Table} -\input{AOI331_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI221 - a 2-2-1-input AND-OR-Invert gate \\ - AOI321 - a 3-2-1-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI332_manpage.tex b/Documents/LaTeX/AOI332_manpage.tex deleted file mode 100644 index 6b1f73e5..00000000 --- a/Documents/LaTeX/AOI332_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI332.tex -%% -%% Purpose: Manual Page File for AOI332 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI332} -\paragraph{Cell} -\begin{quote} - \textbf{AOI332} - a 3-3-2-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI332(Z, C2, C1, C0, B2, B1, B0, A1, A0) -\end{quote} - -\paragraph{Description} -\input{AOI332_circuit.tex} -\input{AOI332_schematic.tex} - -\paragraph{Truth Table} -\input{AOI332_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI222 - a 2-2-2-input AND-OR-Invert gate \\ - AOI322 - a 3-2-2-input AND-OR-Invert gate \\ - AOI333 - a 3-3-3-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI333_manpage.tex b/Documents/LaTeX/AOI333_manpage.tex deleted file mode 100644 index 255eb86b..00000000 --- a/Documents/LaTeX/AOI333_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI333.tex -%% -%% Purpose: Manual Page File for AOI333 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{AOI333} -\paragraph{Cell} -\begin{quote} - \textbf{AOI333} - a 3-3-3-input AND-OR-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - AOI333(Z, C2, C1, C0, B2, B1, B0, A2, A1, A0) -\end{quote} - -\paragraph{Description} -\input{AOI333_circuit.tex} -\input{AOI333_schematic.tex} - -\paragraph{Truth Table} -\input{AOI333_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - AOI222 - a 2-2-2-input AND-OR-Invert gate \\ - AOI322 - a 3-2-2-input AND-OR-Invert gate \\ - AOI332 - a 3-3-2-input AND-OR-Invert gate -\end{quote} diff --git a/Documents/LaTeX/AOI33_circuit.tex b/Documents/LaTeX/AOI33_circuit.tex index 064829bb..2e0e8357 100644 --- a/Documents/LaTeX/AOI33_circuit.tex +++ b/Documents/LaTeX/AOI33_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI33.tex +%% File: StdCellLib/Documents/LaTeX/AOI33_circuit.tex %% %% Purpose: Circuit File for AOI33 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,21 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{3}{L}{A1} % pin A1 - \pin{1}{5}{L}{A2} % pin A2 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{9}{L}{B1} % pin B1 - \pin{1}{11}{L}{B2} % pin B2 - \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{and}{5}{3}{R}{}{} % AND gate -> right - \gate[\inputs{2}]{nor}{12}{6}{R}{}{} % NOR gate -> right - \wire{9}{3}{9}{4} % wire between AND and NOR - \wire{9}{9}{9}{8} % wire between AND and NOR - \pin{17}{6}{R}{Z} % pin Z + \usgate + \gate[\inputs{3}]{and}{5}{9}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin D + \pin{1}{9}{L}{B1} % pin D1 + \pin{1}{11}{L}{B2} % pin D2 + \wire{9}{7}{9}{9} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI33_manpage.tex b/Documents/LaTeX/AOI33_manpage.tex index fee27216..1bc84284 100644 --- a/Documents/LaTeX/AOI33_manpage.tex +++ b/Documents/LaTeX/AOI33_manpage.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_AOI33.tex +%% File: StdCellLib/Documents/LaTeX/AOI33_manpage.tex %% -%% Purpose: Manual Page File for AOI33 +%% Purpose: Auto-generated Manual Page for AOI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -32,23 +32,19 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{AOI33} -\paragraph{Cell} -\begin{quote} - \textbf{AOI33} - a 3-3-input AND-OR-Invert gate -\end{quote} +\subsection{AOI33 - a 3-3-input AND-OR-Invert gate} \label{logical:AOI33} \paragraph{Synopsys} \begin{quote} - AOI33(Z, B2, B1, B0, A2, A1, A0) + AOI33 (Y B2 B1 B A2 A1 A) \end{quote} \paragraph{Description} \input{AOI33_circuit.tex} -\input{AOI33_schematic.tex} +%\input{AOI33_schematic.tex} \paragraph{Truth Table} -\input{AOI33_truthtable.tex} +%\input{AOI33_truthtable.tex} \paragraph{Usage} @@ -58,8 +54,4 @@ \paragraph{Files} -\paragraph{See also} -\begin{quote} - AOI22 - a 2-2-input AND-OR-Invert gate \\ - AOI32 - a 3-2-input AND-OR-Invert gate -\end{quote} +\clearpage diff --git a/Documents/LaTeX/AOI211_circuit.tex b/Documents/LaTeX/AOI41_circuit.tex similarity index 71% rename from Documents/LaTeX/AOI211_circuit.tex rename to Documents/LaTeX/AOI41_circuit.tex index 1b43f659..308f7f89 100644 --- a/Documents/LaTeX/AOI211_circuit.tex +++ b/Documents/LaTeX/AOI41_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_AOI211.tex +%% File: StdCellLib/Documents/LaTeX/AOI41_circuit.tex %% -%% Purpose: Circuit File for AOI211 +%% Purpose: Circuit File for AOI41 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,19 +34,20 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{4}]{and}{5}{6}{R}{}{} % AND + \gate[\inputs{2}]{nor}{12}{3}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C0} % pin C0 - \pin{1}{9}{L}{C1} % pin C1 - \gate[\inputs{2}]{and}{5}{7}{R}{}{} % AND gate -> right - \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{9}{7}{9}{5} % wire between AND and NOR - \pin{17}{3}{R}{Z} % pin Z + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{B3} % pin B3 + \wire{9}{5}{9}{6} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI41_manpage.tex b/Documents/LaTeX/AOI41_manpage.tex new file mode 100644 index 00000000..dcc8c4dc --- /dev/null +++ b/Documents/LaTeX/AOI41_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI41_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AOI41 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AOI41 - a 4-1-input AND-OR-Invert gate} \label{logical:AOI41} + +\paragraph{Synopsys} +\begin{quote} + AOI41 (Z B3 B2 B1 B A) +\end{quote} + +\paragraph{Description} +\input{AOI41_circuit.tex} +%\input{AOI41_schematic.tex} + +\paragraph{Truth Table} +%\input{AOI41_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOI42_circuit.tex b/Documents/LaTeX/AOI42_circuit.tex new file mode 100644 index 00000000..36abd477 --- /dev/null +++ b/Documents/LaTeX/AOI42_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI42_circuit.tex +%% +%% Purpose: Circuit File for AOI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{4}]{and}{5}{8}{R}{}{} % AND + \gate[\inputs{3}]{nor}{12}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \pin{1}{11}{L}{B3} % pin B3 + \wire{9}{8}{9}{5} % wire between AND and NOR + \pin{17}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOI42_manpage.tex b/Documents/LaTeX/AOI42_manpage.tex new file mode 100644 index 00000000..72f341cd --- /dev/null +++ b/Documents/LaTeX/AOI42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI42_manpage.tex +%% +%% Purpose: Manual Page File for AOI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOI42} +\paragraph{Cell} +\begin{quote} + \textbf{AOI42} - a 4-2-input AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOI42(Y, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOI42_circuit.tex} +%\input{AOI42_schematic.tex} + +\paragraph{Truth Table} +%\input{AOI42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/AOI43_circuit.tex b/Documents/LaTeX/AOI43_circuit.tex new file mode 100644 index 00000000..d4b21e80 --- /dev/null +++ b/Documents/LaTeX/AOI43_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI43_circuit.tex +%% +%% Purpose: Circuit File for AOI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{4}]{and}{5}{10}{R}{}{} % AND + \gate[\inputs{4}]{nor}{12}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin 42 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{7}{9}{10} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOI43_manpage.tex b/Documents/LaTeX/AOI43_manpage.tex new file mode 100644 index 00000000..5071272a --- /dev/null +++ b/Documents/LaTeX/AOI43_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOI43_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for AOI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{AOI43 - a 4-3-input AND-OR-Invert gate} \label{logical:AOI43} + +\paragraph{Synopsys} +\begin{quote} + AOI43 (Y, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOI43_circuit.tex} +%\input{AOI43_schematic.tex} + +\paragraph{Truth Table} +%\input{AOI43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOOA212_circuit.tex b/Documents/LaTeX/AOOA212_circuit.tex new file mode 100644 index 00000000..e9f7a2d5 --- /dev/null +++ b/Documents/LaTeX/AOOA212_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOA212_circuit.tex +%% +%% Purpose: Circuit File for AOOA212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{6}{R}{}{} % NAND + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between OR and NAND + \wire{16}{9}{16}{8} % wire between OR and NAND + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOOA212_manpage.tex b/Documents/LaTeX/AOOA212_manpage.tex new file mode 100644 index 00000000..79029b1d --- /dev/null +++ b/Documents/LaTeX/AOOA212_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOA212_manpage.tex +%% +%% Purpose: Manual Page File for AOOA212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOOA212} +\paragraph{Cell} +\begin{quote} + \textbf{AOOA212} - a 2-1-2-input AND-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOOA212(Z, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOOA212_circuit.tex} +%\input{AOOA212_schematic.tex} + +\paragraph{Truth Table} +%\input{AOOA212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOOA312_circuit.tex b/Documents/LaTeX/AOOA312_circuit.tex new file mode 100644 index 00000000..aed2c77b --- /dev/null +++ b/Documents/LaTeX/AOOA312_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOA312_circuit.tex +%% +%% Purpose: Circuit File for AOOA312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{6}{R}{}{} % NAND + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between OR and NAND + \wire{16}{9}{16}{8} % wire between OR and NAND + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOOA312_manpage.tex b/Documents/LaTeX/AOOA312_manpage.tex new file mode 100644 index 00000000..439d7217 --- /dev/null +++ b/Documents/LaTeX/AOOA312_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOA312_manpage.tex +%% +%% Purpose: Manual Page File for AOOA312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOOA312} +\paragraph{Cell} +\begin{quote} + \textbf{AOOA312} - a 3-1-2-input AND-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOOA312(Z, C2, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOOA312_circuit.tex} +%\input{AOOA312_schematic.tex} + +\paragraph{Truth Table} +%\input{AOOA312_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOOAI212_circuit.tex b/Documents/LaTeX/AOOAI212_circuit.tex new file mode 100644 index 00000000..d7335e63 --- /dev/null +++ b/Documents/LaTeX/AOOAI212_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOAI212_circuit.tex +%% +%% Purpose: Circuit File for AOOAI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{2}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{6}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between OR and NAND + \wire{16}{9}{16}{8} % wire between OR and NAND + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOOAI212_manpage.tex b/Documents/LaTeX/AOOAI212_manpage.tex new file mode 100644 index 00000000..647780cb --- /dev/null +++ b/Documents/LaTeX/AOOAI212_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOAI212_manpage.tex +%% +%% Purpose: Manual Page File for AOOAI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOOAI212} +\paragraph{Cell} +\begin{quote} + \textbf{AOOAI212} - a 2-1-2-input AND-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOOAI212(Z, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOOAI212_circuit.tex} +%\input{AOOAI212_schematic.tex} + +\paragraph{Truth Table} +%\input{AOOAI212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOOAI312_circuit.tex b/Documents/LaTeX/AOOAI312_circuit.tex new file mode 100644 index 00000000..0cdec2b5 --- /dev/null +++ b/Documents/LaTeX/AOOAI312_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOAI312_circuit.tex +%% +%% Purpose: Circuit File for AOOAI312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{and}{5}{11}{R}{}{} % AND + \gate[\inputs{2}]{or}{12}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{12}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{19}{6}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between OR and NAND + \wire{16}{9}{16}{8} % wire between OR and NAND + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/AOOAI312_manpage.tex b/Documents/LaTeX/AOOAI312_manpage.tex new file mode 100644 index 00000000..dc1dab17 --- /dev/null +++ b/Documents/LaTeX/AOOAI312_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/AOOAI312_manpage.tex +%% +%% Purpose: Manual Page File for AOOAI312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{AOOAI312} +\paragraph{Cell} +\begin{quote} + \textbf{AOOAI312} - a 3-1-2-input AND-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + AOOAI312(Z, C2, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{AOOAI312_circuit.tex} +%\input{AOOAI312_schematic.tex} + +\paragraph{Truth Table} +%\input{AOOAI312_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/BUF_circuit.tex b/Documents/LaTeX/BUF2_circuit.tex similarity index 82% rename from Documents/LaTeX/BUF_circuit.tex rename to Documents/LaTeX/BUF2_circuit.tex index d7a9ac97..911251ef 100644 --- a/Documents/LaTeX/BUF_circuit.tex +++ b/Documents/LaTeX/BUF2_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_BUF.tex +%% File: StdCellLib/Documents/LaTeX/BUF2_circuit.tex %% -%% Purpose: Circuit File for BUF +%% Purpose: Circuit File for BUF2 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,12 +34,12 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{14}{6} \pin{1}{3}{L}{A} % pin A - \gate{not}{5}{3}{R}{}{} % NOT gate -> right - \gate{not}{11}{3}{R}{}{} % NOT gate -> right + \gate{not}{5}{3}{R}{}{} % 1st buffer + \gate{not}{11}{3}{Rc}{}{2x} % 2nd buffer \pin{15}{3}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/BUF2_manpage.tex b/Documents/LaTeX/BUF2_manpage.tex new file mode 100644 index 00000000..7bf4ed4d --- /dev/null +++ b/Documents/LaTeX/BUF2_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/BUF2_manpage.tex +%% +%% Purpose: Manual Page File for BUF2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{BUF2} +\paragraph{Cell} +\begin{quote} + \textbf{BUF2} - a non-inverting Buffer with 2x Drive Strength +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + BUF2(Z, A) +\end{quote} + +\paragraph{Description} +\input{BUF2_circuit.tex} +\input{BUF2_schematic.tex} + +\paragraph{Truth Table} +\input{BUF2_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/BUF_schematic.tex b/Documents/LaTeX/BUF2_schematic.tex similarity index 100% rename from Documents/LaTeX/BUF_schematic.tex rename to Documents/LaTeX/BUF2_schematic.tex diff --git a/Documents/LaTeX/BUF_truthtable.tex b/Documents/LaTeX/BUF2_truthtable.tex similarity index 100% rename from Documents/LaTeX/BUF_truthtable.tex rename to Documents/LaTeX/BUF2_truthtable.tex diff --git a/Documents/LaTeX/CGN2_circuit.tex b/Documents/LaTeX/CGN2_circuit.tex new file mode 100644 index 00000000..8fb59d32 --- /dev/null +++ b/Documents/LaTeX/CGN2_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/CGN2_circuit.tex +%% +%% Purpose: Circuit File for CGN2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{26}{9} + \usgate + \flipflop[\clockin{p}]{d}{7}{5}{R}{}{} + \pin{1}{1}{L}{XI} % pin XI + \pin{1}{7}{L}{EN} % pin EN + \wire{2}{7}{3}{7} + \wire{2}{5}{3}{5} + \wire{2}{1}{2}{5} + \junct{2}{1} % clock line + \wire{2}{1}{11}{1} + \wire{11}{5}{11}{7} + \gate{nor}{14}{3}{R}{}{} % NOR + \gate{not}{21}{3}{Rc}{}{2x} % buffer + \pin{25}{3}{R}{XO} % pin XO + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/CGN2_manpage.tex b/Documents/LaTeX/CGN2_manpage.tex new file mode 100644 index 00000000..2956a607 --- /dev/null +++ b/Documents/LaTeX/CGN2_manpage.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/CGN2_manpage.tex +%% +%% Purpose: Manual Page File for CGN2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{CGN2} +\paragraph{Cell} +\begin{quote} + \textbf{CGN2} - Clock Gating Buffer for negative Clock with 2x Drive Strength +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + CGN2(XO, E, XI) +\end{quote} + +\paragraph{Description} +\input{CGN2_circuit.tex} +%\input{CGN2_schematic.tex} + +%\paragraph{Truth Table} +%\input{CGN2_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} +\begin{quote} + ? +\end{quote} + +\paragraph{Layout} + +\paragraph{Files} +%\input{CGN2_files.tex} diff --git a/Documents/LaTeX/CGP2_circuit.tex b/Documents/LaTeX/CGP2_circuit.tex new file mode 100644 index 00000000..b4ca8bf7 --- /dev/null +++ b/Documents/LaTeX/CGP2_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/CGP2_circuit.tex +%% +%% Purpose: Circuit File for CGP2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{26}{9} + \usgate + \flipflop[\clockin{n}]{d}{7}{5}{R}{}{} + \pin{1}{1}{L}{XI} % pin XI + \pin{1}{7}{L}{E} % pin E + \wire{2}{7}{3}{7} + \wire{2}{5}{3}{5} + \wire{2}{1}{2}{5} + \junct{2}{1} % clock line + \wire{2}{1}{11}{1} + \wire{11}{5}{11}{7} + \gate{nand}{14}{3}{R}{}{} % NAND + \gate{not}{21}{3}{Rc}{}{2x} % buffer + \pin{25}{3}{R}{XO} % pin XO + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/CGP2_manpage.tex b/Documents/LaTeX/CGP2_manpage.tex new file mode 100644 index 00000000..5828a58b --- /dev/null +++ b/Documents/LaTeX/CGP2_manpage.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/CGP2_manpage.tex +%% +%% Purpose: Manual Page File for CGP2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{CGP2} +\paragraph{Cell} +\begin{quote} + \textbf{CGP2} - Clock Gating Buffer for positive Clock with 2x Drive Strength +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + CGP2(XO, E, XI) +\end{quote} + +\paragraph{Description} +\input{CGP2_circuit.tex} +%\input{CGP2_schematic.tex} + +%\paragraph{Truth Table} +%\input{CGP2_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} +\begin{quote} + ? +\end{quote} + +\paragraph{Layout} + +\paragraph{Files} +%\input{CGP2_files.tex} diff --git a/Documents/LaTeX/DFFEN_circuit.tex b/Documents/LaTeX/DFFEN_circuit.tex new file mode 100644 index 00000000..333eb4e8 --- /dev/null +++ b/Documents/LaTeX/DFFEN_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFEN_circuit.tex +%% +%% Purpose: Circuit File for DFFEN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{9} + \usgate + \gate{nor}{5}{3}{R}{}{} + \flipflop[\clockin{pd}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{EN} % pin EN + \pin{1}{1}{L}{XN} % pin XN + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFEN_manpage.tex b/Documents/LaTeX/DFFEN_manpage.tex new file mode 100644 index 00000000..200a5443 --- /dev/null +++ b/Documents/LaTeX/DFFEN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFEN_manpage.tex +%% +%% Purpose: Manual Page File for DFFEN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFEN} +\paragraph{Cell} +\begin{quote} + \textbf{DFFEN} - a Negative edge-triggered D-FlipFlop with low-active Clock Enable +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFEN(Q, D, EN, XN) +\end{quote} + +\paragraph{Description} +\input{DFFEN_circuit.tex} +%\input{DFFEN_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFEN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFEP_circuit.tex b/Documents/LaTeX/DFFEP_circuit.tex new file mode 100644 index 00000000..0368540c --- /dev/null +++ b/Documents/LaTeX/DFFEP_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFEP_circuit.tex +%% +%% Purpose: Circuit File for DFFEP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{9} + \usgate + \gate{nand}{5}{3}{R}{}{} + \flipflop[\clockin{nd}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{E} % pin E + \pin{1}{1}{L}{X} % pin X + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFEP_manpage.tex b/Documents/LaTeX/DFFEP_manpage.tex new file mode 100644 index 00000000..c83e3a06 --- /dev/null +++ b/Documents/LaTeX/DFFEP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFEP_manpage.tex +%% +%% Purpose: Manual Page File for DFFEP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFEP} +\paragraph{Cell} +\begin{quote} + \textbf{DFFEP} - a Positive edge-triggered D-FlipFlop with high-active Clock Enable +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFEP(Q, D, E, X) +\end{quote} + +\paragraph{Description} +\input{DFFEP_circuit.tex} +%\input{DFFEP_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFEP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFERN_circuit.tex b/Documents/LaTeX/DFFERN_circuit.tex new file mode 100644 index 00000000..9c8be495 --- /dev/null +++ b/Documents/LaTeX/DFFERN_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFERN_circuit.tex +%% +%% Purpose: Circuit File for DFFERN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{10} + \usgate + \gate{nor}{5}{4}{R}{}{} + \flipflop[\clockin{pd}\resetin{p}]{d}{15}{6}{R}{}{} + \pin{1}{8}{L}{D} % pin D + \wire{2}{8}{11}{8} + \pin{1}{6}{L}{EN} % pin EN + \pin{1}{2}{L}{XN} % pin XN + \wire{9}{4}{10}{4} + \wire{10}{4}{10}{6} + \wire{10}{6}{11}{6} + \pin{15}{1}{D}{R} % pin R + \pin{20}{8}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFERN_manpage.tex b/Documents/LaTeX/DFFERN_manpage.tex new file mode 100644 index 00000000..e25aa64c --- /dev/null +++ b/Documents/LaTeX/DFFERN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFERN_manpage.tex +%% +%% Purpose: Manual Page File for DFFERN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFERN} +\paragraph{Cell} +\begin{quote} + \textbf{DFFERN} - a Negative edge-triggered D-FlipFlop with low-active Clock Enable and high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFERN(Q, D, R, EN, XN) +\end{quote} + +\paragraph{Description} +\input{DFFERN_circuit.tex} +%\input{DFFERN_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFERN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFERP_circuit.tex b/Documents/LaTeX/DFFERP_circuit.tex new file mode 100644 index 00000000..5f90e53e --- /dev/null +++ b/Documents/LaTeX/DFFERP_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFERP_circuit.tex +%% +%% Purpose: Circuit File for DFFERP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{10} + \usgate + \gate{nand}{5}{4}{R}{}{} + \flipflop[\clockin{nd}\resetin{p}]{d}{15}{6}{R}{}{} + \pin{1}{8}{L}{D} % pin D + \wire{2}{8}{11}{8} + \pin{1}{6}{L}{E} % pin E + \pin{1}{2}{L}{X} % pin X + \wire{9}{4}{10}{4} + \wire{10}{4}{10}{6} + \wire{10}{6}{11}{6} + \pin{15}{1}{D}{R} % pin R + \pin{20}{8}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFERP_manpage.tex b/Documents/LaTeX/DFFERP_manpage.tex new file mode 100644 index 00000000..25e36b3e --- /dev/null +++ b/Documents/LaTeX/DFFERP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFERP_manpage.tex +%% +%% Purpose: Manual Page File for DFFERP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFERP} +\paragraph{Cell} +\begin{quote} + \textbf{DFFERP} - a Positive edge-triggered D-FlipFlop with high-active Clock Enable and high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFERP(Q, D, R, E, X) +\end{quote} + +\paragraph{Description} +\input{DFFERP_circuit.tex} +%\input{DFFERP_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFERP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFESN_circuit.tex b/Documents/LaTeX/DFFESN_circuit.tex new file mode 100644 index 00000000..c2cf5b71 --- /dev/null +++ b/Documents/LaTeX/DFFESN_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFESN_circuit.tex +%% +%% Purpose: Circuit File for DFFESN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{11} + \usgate + \gate{nor}{5}{3}{R}{}{} + \flipflop[\clockin{pd}\setin{n}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{EN} % pin EN + \pin{1}{1}{L}{XN} % pin XN + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{15}{10}{U}{SN}% pin SN + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFESN_manpage.tex b/Documents/LaTeX/DFFESN_manpage.tex new file mode 100644 index 00000000..86169ea4 --- /dev/null +++ b/Documents/LaTeX/DFFESN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFESN_manpage.tex +%% +%% Purpose: Manual Page File for DFFESN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFESN} +\paragraph{Cell} +\begin{quote} + \textbf{DFFESN} - a Negative edge-triggered D-FlipFlop with low-active Clock Enable and low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFESN(Q, D, SN, EN, XN) +\end{quote} + +\paragraph{Description} +\input{DFFESN_circuit.tex} +%\input{DFFESN_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFESN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFESP_circuit.tex b/Documents/LaTeX/DFFESP_circuit.tex new file mode 100644 index 00000000..edb699f7 --- /dev/null +++ b/Documents/LaTeX/DFFESP_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFESP_circuit.tex +%% +%% Purpose: Circuit File for DFFESP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{11} + \usgate + \gate{nand}{5}{3}{R}{}{} + \flipflop[\clockin{nd}\setin{n}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{E} % pin E + \pin{1}{1}{L}{X} % pin X + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{15}{10}{U}{SN}% pin SN + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFESP_manpage.tex b/Documents/LaTeX/DFFESP_manpage.tex new file mode 100644 index 00000000..d8353b92 --- /dev/null +++ b/Documents/LaTeX/DFFESP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFESP_manpage.tex +%% +%% Purpose: Manual Page File for DFFESP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFESP} +\paragraph{Cell} +\begin{quote} + \textbf{DFFESP} - a Positive edge-triggered D-FlipFlop with high-active Clock Enable and low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFESP(Q, D, SN, E, X) +\end{quote} + +\paragraph{Description} +\input{DFFESP_circuit.tex} +%\input{DFFESP_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFESP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFN_circuit.tex b/Documents/LaTeX/DFFN_circuit.tex new file mode 100644 index 00000000..7e73c4d4 --- /dev/null +++ b/Documents/LaTeX/DFFN_circuit.tex @@ -0,0 +1,48 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFN_circuit.tex +%% +%% Purpose: Circuit File for DFFN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{8} + \usgate + \flipflop[\clockin{nd}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{XN} % pin XN + \pin{1}{6}{L}{D} % pin D + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFN_manpage.tex b/Documents/LaTeX/DFFN_manpage.tex new file mode 100644 index 00000000..558ecfb6 --- /dev/null +++ b/Documents/LaTeX/DFFN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFN_manpage.tex +%% +%% Purpose: Manual Page File for DFFN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFN} +\paragraph{Cell} +\begin{quote} + \textbf{DFFN} - a Negative edge-triggered D-FlipFlop +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFN(Q, D, XN) +\end{quote} + +\paragraph{Description} +\input{DFFN_circuit.tex} +%\input{DFFN_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/DFFP_circuit.tex b/Documents/LaTeX/DFFP_circuit.tex new file mode 100644 index 00000000..a98c65d2 --- /dev/null +++ b/Documents/LaTeX/DFFP_circuit.tex @@ -0,0 +1,48 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFP_circuit.tex +%% +%% Purpose: Circuit File for DFFP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{8} + \usgate + \flipflop[\clockin{pd}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{X} % pin X + \pin{1}{6}{L}{D} % pin D + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/DFFP_manpage.tex b/Documents/LaTeX/DFFP_manpage.tex new file mode 100644 index 00000000..ab8b5700 --- /dev/null +++ b/Documents/LaTeX/DFFP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/DFFP_manpage.tex +%% +%% Purpose: Manual Page File for DFFP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{DFFP} +\paragraph{Cell} +\begin{quote} + \textbf{DFFP} - a Positive edge-triggered D-FlipFlop +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + DFFP(Q, D, X) +\end{quote} + +\paragraph{Description} +\input{DFFP_circuit.tex} +%\input{DFFP_schematic.tex} + +\paragraph{Truth Table} +%\input{DFFP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/INV_circuit.tex b/Documents/LaTeX/INV_circuit.tex index e3b6b373..48704434 100644 --- a/Documents/LaTeX/INV_circuit.tex +++ b/Documents/LaTeX/INV_circuit.tex @@ -39,7 +39,7 @@ \begin{circuitdiagram}{11}{6} \pin{1}{3}{L}{A} % pin A \gate{not}{5}{3}{R}{}{} % NOT gate -> right - \pin{9}{3}{R}{Z} % pin Z + \pin{9}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/LATEN_circuit.tex b/Documents/LaTeX/LATEN_circuit.tex new file mode 100644 index 00000000..287a8f52 --- /dev/null +++ b/Documents/LaTeX/LATEN_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATEN_circuit.tex +%% +%% Purpose: Circuit File for LATEN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{9} + \usgate + \gate{nor}{5}{3}{R}{}{} + \flipflop[\clockin{p}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{EN} % pin EN + \pin{1}{1}{L}{XN} % pin XN + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATEN_manpage.tex b/Documents/LaTeX/LATEN_manpage.tex new file mode 100644 index 00000000..24d47d5e --- /dev/null +++ b/Documents/LaTeX/LATEN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATEN_manpage.tex +%% +%% Purpose: Manual Page File for LATEN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATEN} +\paragraph{Cell} +\begin{quote} + \textbf{LATEN} - a Low-active D-Latch with low-active Clock Enable +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATEN(Q, D, EN, XN) +\end{quote} + +\paragraph{Description} +\input{LATEN_circuit.tex} +%\input{LATEN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATEN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATEP_circuit.tex b/Documents/LaTeX/LATEP_circuit.tex new file mode 100644 index 00000000..6ed4f2f9 --- /dev/null +++ b/Documents/LaTeX/LATEP_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATEP_circuit.tex +%% +%% Purpose: Circuit File for LATEP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{9} + \usgate + \gate{nand}{5}{3}{R}{}{} + \flipflop[\clockin{n}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{E} % pin E + \pin{1}{1}{L}{X} % pin X + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATEP_manpage.tex b/Documents/LaTeX/LATEP_manpage.tex new file mode 100644 index 00000000..dd461c5c --- /dev/null +++ b/Documents/LaTeX/LATEP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATEP_manpage.tex +%% +%% Purpose: Manual Page File for LATEP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATEP} +\paragraph{Cell} +\begin{quote} + \textbf{LATEP} - a High-active D-Latch with high-active Clock Enable +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATEP(Q, D, E, X) +\end{quote} + +\paragraph{Description} +\input{LATEP_circuit.tex} +%\input{LATEP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATEP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATERN_circuit.tex b/Documents/LaTeX/LATERN_circuit.tex new file mode 100644 index 00000000..8324926e --- /dev/null +++ b/Documents/LaTeX/LATERN_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATERN_circuit.tex +%% +%% Purpose: Circuit File for LATERN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{10} + \usgate + \gate{nor}{5}{4}{R}{}{} + \flipflop[\clockin{p}\resetin{p}]{d}{15}{6}{R}{}{} + \pin{1}{8}{L}{D} % pin D + \wire{2}{8}{11}{8} + \pin{1}{6}{L}{EN} % pin EN + \pin{1}{2}{L}{XN} % pin XN + \wire{9}{4}{10}{4} + \wire{10}{4}{10}{6} + \wire{10}{6}{11}{6} + \pin{15}{1}{D}{R} % pin R + \pin{20}{8}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATERN_manpage.tex b/Documents/LaTeX/LATERN_manpage.tex new file mode 100644 index 00000000..1d32ba9a --- /dev/null +++ b/Documents/LaTeX/LATERN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATERN_manpage.tex +%% +%% Purpose: Manual Page File for LATERN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATERN} +\paragraph{Cell} +\begin{quote} + \textbf{LATERN} - a Low-active D-Latch with low-active Clock Enable and high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATERN(Q, D, R, EN, XN) +\end{quote} + +\paragraph{Description} +\input{LATERN_circuit.tex} +%\input{LATERN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATERN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATERP_circuit.tex b/Documents/LaTeX/LATERP_circuit.tex new file mode 100644 index 00000000..07e261e5 --- /dev/null +++ b/Documents/LaTeX/LATERP_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATERP_circuit.tex +%% +%% Purpose: Circuit File for LATERP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{10} + \usgate + \gate{nand}{5}{4}{R}{}{} + \flipflop[\clockin{n}\resetin{p}]{d}{15}{6}{R}{}{} + \pin{1}{8}{L}{D} % pin D + \wire{2}{8}{11}{8} + \pin{1}{6}{L}{E} % pin E + \pin{1}{2}{L}{X} % pin X + \wire{9}{4}{10}{4} + \wire{10}{4}{10}{6} + \wire{10}{6}{11}{6} + \pin{15}{1}{D}{R} % pin R + \pin{20}{8}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATERP_manpage.tex b/Documents/LaTeX/LATERP_manpage.tex new file mode 100644 index 00000000..abfa368d --- /dev/null +++ b/Documents/LaTeX/LATERP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATERP_manpage.tex +%% +%% Purpose: Manual Page File for LATERP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATERP} +\paragraph{Cell} +\begin{quote} + \textbf{LATERP} - a High-active D-Latch with high-active Clock Enable and high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATERP(Q, D, R, E, X) +\end{quote} + +\paragraph{Description} +\input{LATERP_circuit.tex} +%\input{LATERP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATERP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATESN_circuit.tex b/Documents/LaTeX/LATESN_circuit.tex new file mode 100644 index 00000000..634bcb00 --- /dev/null +++ b/Documents/LaTeX/LATESN_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATESN_circuit.tex +%% +%% Purpose: Circuit File for LATESN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{11} + \usgate + \gate{nor}{5}{3}{R}{}{} + \flipflop[\clockin{p}\setin{n}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{EN} % pin EN + \pin{1}{1}{L}{XN} % pin XN + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{15}{10}{U}{SN}% pin SN + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATESN_manpage.tex b/Documents/LaTeX/LATESN_manpage.tex new file mode 100644 index 00000000..8557fe18 --- /dev/null +++ b/Documents/LaTeX/LATESN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATESN_manpage.tex +%% +%% Purpose: Manual Page File for LATESN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATESN} +\paragraph{Cell} +\begin{quote} + \textbf{LATESN} - a Low-active D-Latch with low-active Clock Enable and low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATESN(Q, D, SN, EN, XN) +\end{quote} + +\paragraph{Description} +\input{LATESN_circuit.tex} +%\input{LATESN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATESN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATESP_circuit.tex b/Documents/LaTeX/LATESP_circuit.tex new file mode 100644 index 00000000..bad25287 --- /dev/null +++ b/Documents/LaTeX/LATESP_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATESP_circuit.tex +%% +%% Purpose: Circuit File for LATESP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{21}{11} + \usgate + \gate{nand}{5}{3}{R}{}{} + \flipflop[\clockin{n}\setin{n}]{d}{15}{5}{R}{}{} + \pin{1}{7}{L}{D} % pin D + \wire{2}{7}{11}{7} + \pin{1}{5}{L}{E} % pin E + \pin{1}{1}{L}{X} % pin X + \wire{9}{3}{10}{3} + \wire{10}{3}{10}{5} + \wire{10}{5}{11}{5} + \pin{15}{10}{U}{SN}% pin SN + \pin{20}{7}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATESP_manpage.tex b/Documents/LaTeX/LATESP_manpage.tex new file mode 100644 index 00000000..c1aab23a --- /dev/null +++ b/Documents/LaTeX/LATESP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATESP_manpage.tex +%% +%% Purpose: Manual Page File for LATESP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATESP} +\paragraph{Cell} +\begin{quote} + \textbf{LATESP} - a High-active D-Latch with high-active Clock Enable and low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATESP(Q, D, SN, E, X) +\end{quote} + +\paragraph{Description} +\input{LATESP_circuit.tex} +%\input{LATESP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATESP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATN_circuit.tex b/Documents/LaTeX/LATN_circuit.tex new file mode 100644 index 00000000..e883682f --- /dev/null +++ b/Documents/LaTeX/LATN_circuit.tex @@ -0,0 +1,48 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATN_circuit.tex +%% +%% Purpose: Circuit File for LATN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{8} + \usgate + \flipflop[\clockin{n}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{XN} % pin XN + \pin{1}{6}{L}{D} % pin D + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATN_manpage.tex b/Documents/LaTeX/LATN_manpage.tex new file mode 100644 index 00000000..51dbd1f5 --- /dev/null +++ b/Documents/LaTeX/LATN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATN_manpage.tex +%% +%% Purpose: Manual Page File for LATN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATN} +\paragraph{Cell} +\begin{quote} + \textbf{LATN} - a Low-active D-Latch +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATN(Q, D, XN) +\end{quote} + +\paragraph{Description} +\input{LATN_circuit.tex} +%\input{LATN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATP_circuit.tex b/Documents/LaTeX/LATP_circuit.tex new file mode 100644 index 00000000..df9f2c79 --- /dev/null +++ b/Documents/LaTeX/LATP_circuit.tex @@ -0,0 +1,48 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATP_circuit.tex +%% +%% Purpose: Circuit File for LATP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{8} + \usgate + \flipflop[\clockin{p}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{X} % pin X + \pin{1}{6}{L}{D} % pin D + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATP_manpage.tex b/Documents/LaTeX/LATP_manpage.tex new file mode 100644 index 00000000..d1188406 --- /dev/null +++ b/Documents/LaTeX/LATP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATP_manpage.tex +%% +%% Purpose: Manual Page File for LATP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATP} +\paragraph{Cell} +\begin{quote} + \textbf{LATP} - a High-active D-Latch +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATP(Q, D, X) +\end{quote} + +\paragraph{Description} +\input{LATP_circuit.tex} +%\input{LATP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI211_truthtable.tex b/Documents/LaTeX/LATRN_circuit.tex similarity index 67% rename from Documents/LaTeX/OAI211_truthtable.tex rename to Documents/LaTeX/LATRN_circuit.tex index ed138f33..30c47a58 100644 --- a/Documents/LaTeX/OAI211_truthtable.tex +++ b/Documents/LaTeX/LATRN_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI211.tex +%% File: StdCellLib/Documents/LaTeX/LATRN_circuit.tex %% -%% Purpose: Truth Table File for OAI211 +%% Purpose: Circuit File for LATRN %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -32,19 +32,18 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// - \begin{center} - {\(Z = \lnot ((C1 \lor C0) \land B \land A) \)} - \begin{table}[h] %\caption{\(Z = \lnot ((C1 \lor C0) \land B \land A) \)} + Circuit + \begin{figure}[h] \begin{center} - \begin{tabular}{|c|c|c|c||c|} \hline - C1 & C0 & B & A & Z \\ \hline\hline - 0 & 0 & X & X & 1 \\ \hline - 1 & X & 1 & 1 & 0 \\ \hline - X & 1 & 1 & 1 & 0 \\ \hline - X & X & 0 & X & 1 \\ \hline - X & X & X & 0 & 1 \\ \hline - \end{tabular} + \begin{circuitdiagram}{12}{10} + \usgate + \flipflop[\clockin{n}\resetin{p}]{d}{6}{6}{R}{}{} + \pin{1}{6}{L}{XN} % pin XN + \pin{1}{8}{L}{D} % pin D + \pin{6}{1}{D}{R} % pin R + \pin{11}{8}{R}{Q} % pin Q + \end{circuitdiagram} \end{center} - \end{table} + \end{figure} \end{center} diff --git a/Documents/LaTeX/LATRN_manpage.tex b/Documents/LaTeX/LATRN_manpage.tex new file mode 100644 index 00000000..ff9b7d09 --- /dev/null +++ b/Documents/LaTeX/LATRN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATRN_manpage.tex +%% +%% Purpose: Manual Page File for LATRN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATRN} +\paragraph{Cell} +\begin{quote} + \textbf{LATRN} - a Low-active D-Latch with high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATRN(Q, D, R, XN) +\end{quote} + +\paragraph{Description} +\input{LATRN_circuit.tex} +%\input{LATRN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATRN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATRP_circuit.tex b/Documents/LaTeX/LATRP_circuit.tex new file mode 100644 index 00000000..584ac497 --- /dev/null +++ b/Documents/LaTeX/LATRP_circuit.tex @@ -0,0 +1,49 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATRP_circuit.tex +%% +%% Purpose: Circuit File for LATRP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{10} + \usgate + \flipflop[\clockin{p}\resetin{p}]{d}{6}{6}{R}{}{} + \pin{1}{6}{L}{X} % pin X + \pin{1}{8}{L}{D} % pin D + \pin{6}{1}{D}{R} % pin R + \pin{11}{8}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATRP_manpage.tex b/Documents/LaTeX/LATRP_manpage.tex new file mode 100644 index 00000000..e855d2c4 --- /dev/null +++ b/Documents/LaTeX/LATRP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATRP_manpage.tex +%% +%% Purpose: Manual Page File for LATRP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATRP} +\paragraph{Cell} +\begin{quote} + \textbf{LATRP} - a High-active D-Latch with high-active asynchronous Reset +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATRP(Q, D, R, X) +\end{quote} + +\paragraph{Description} +\input{LATRP_circuit.tex} +%\input{LATRP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATRP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATSN_circuit.tex b/Documents/LaTeX/LATSN_circuit.tex new file mode 100644 index 00000000..087dfaf6 --- /dev/null +++ b/Documents/LaTeX/LATSN_circuit.tex @@ -0,0 +1,49 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATSN_circuit.tex +%% +%% Purpose: Circuit File for LATSN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{10} + \usgate + \flipflop[\clockin{n}\setin{n}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{XN} % pin XN + \pin{1}{6}{L}{D} % pin D + \pin{6}{9}{U}{SN} % pin SN + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATSN_manpage.tex b/Documents/LaTeX/LATSN_manpage.tex new file mode 100644 index 00000000..66510911 --- /dev/null +++ b/Documents/LaTeX/LATSN_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATSN_manpage.tex +%% +%% Purpose: Manual Page File for LATSN +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATSN} +\paragraph{Cell} +\begin{quote} + \textbf{LATSN} - a Low-active D-Latch with low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATSN(Q, D, SN, XN) +\end{quote} + +\paragraph{Description} +\input{LATSN_circuit.tex} +%\input{LATSN_schematic.tex} + +\paragraph{Truth Table} +%\input{LATSN_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/LATSP_circuit.tex b/Documents/LaTeX/LATSP_circuit.tex new file mode 100644 index 00000000..e4c66f26 --- /dev/null +++ b/Documents/LaTeX/LATSP_circuit.tex @@ -0,0 +1,49 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATSP_circuit.tex +%% +%% Purpose: Circuit File for LATSP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{12}{10} + \usgate + \flipflop[\clockin{p}\setin{n}]{d}{6}{4}{R}{}{} + \pin{1}{4}{L}{X} % pin X + \pin{1}{6}{L}{D} % pin D + \pin{6}{9}{U}{SN} % pin SN + \pin{11}{6}{R}{Q} % pin Q + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/LATSP_manpage.tex b/Documents/LaTeX/LATSP_manpage.tex new file mode 100644 index 00000000..c3d7e87d --- /dev/null +++ b/Documents/LaTeX/LATSP_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/LATSP_manpage.tex +%% +%% Purpose: Manual Page File for LATSP +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{LATSP} +\paragraph{Cell} +\begin{quote} + \textbf{LATSP} - a High-active D-Latch with low-active asynchronous Set +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + LATSP(Q, D, SN, X) +\end{quote} + +\paragraph{Description} +\input{LATSP_circuit.tex} +%\input{LATSP_schematic.tex} + +\paragraph{Truth Table} +%\input{LATSP_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/NAND2_circuit.tex b/Documents/LaTeX/NAND2_circuit.tex index cbbcb9ab..faf31a41 100644 --- a/Documents/LaTeX/NAND2_circuit.tex +++ b/Documents/LaTeX/NAND2_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_NAND2.tex +%% File: StdCellLib/Documents/LaTeX/NAND2_circuit.tex %% %% Purpose: Circuit File for NAND2 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,13 +34,14 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{11}{6} + \usgate + \gate[\inputs{2}]{nand}{5}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{5}{L}{B} % pin B - \gate[\inputs{2}]{nand}{5}{3}{R}{}{} % NAND gate -> right - \pin{10}{3}{R}{Z} % pin Z + \pin{1}{5}{L}{A1} % pin A1 + \pin{10}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/NAND2_manpage.tex b/Documents/LaTeX/NAND2_manpage.tex index 9b18f42a..916f8572 100644 --- a/Documents/LaTeX/NAND2_manpage.tex +++ b/Documents/LaTeX/NAND2_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,7 +36,7 @@ \subsection{NAND2 - a 2-input Not-AND (or NAND) gate} \label{logical:NAND2} \paragraph{Synopsys} \begin{quote} - NAND2 (Z B A) + NAND2 (Z A1 A) \end{quote} \paragraph{Description} @@ -54,9 +54,4 @@ \subsection{NAND2 - a 2-input Not-AND (or NAND) gate} \label{logical:NAND2} \paragraph{Files} -\paragraph{See also} -\begin{quote} - NAND3 - a 3-input Not-AND (or NAND) gate -\end{quote} - \clearpage diff --git a/Documents/LaTeX/NAND3_circuit.tex b/Documents/LaTeX/NAND3_circuit.tex index 7d74f17e..22b17a2f 100644 --- a/Documents/LaTeX/NAND3_circuit.tex +++ b/Documents/LaTeX/NAND3_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_NAND3.tex +%% File: StdCellLib/Documents/LaTeX/NAND3_circuit.tex %% %% Purpose: Circuit File for NAND3 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,14 +34,15 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{11}{6} + \usgate + \gate[\inputs{3}]{nand}{5}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \gate[\inputs{3}]{nand}{5}{3}{R}{}{} % NAND gate -> right - \pin{10}{3}{R}{Z} % pin Z + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{10}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/NAND3_manpage.tex b/Documents/LaTeX/NAND3_manpage.tex index 56f8805c..521cbe13 100644 --- a/Documents/LaTeX/NAND3_manpage.tex +++ b/Documents/LaTeX/NAND3_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,7 +36,7 @@ \subsection{NAND3 - a 3-input Not-AND (or NAND) gate} \label{logical:NAND3} \paragraph{Synopsys} \begin{quote} - NAND3 (Z C B A) + NAND3 (Z A2 A1 A) \end{quote} \paragraph{Description} @@ -54,9 +54,4 @@ \subsection{NAND3 - a 3-input Not-AND (or NAND) gate} \label{logical:NAND3} \paragraph{Files} -\paragraph{See also} -\begin{quote} - NAND2 - a 2-input Not-AND (or NAND) gate -\end{quote} - \clearpage diff --git a/Documents/LaTeX/NAND4_circuit.tex b/Documents/LaTeX/NAND4_circuit.tex new file mode 100644 index 00000000..afdc4a92 --- /dev/null +++ b/Documents/LaTeX/NAND4_circuit.tex @@ -0,0 +1,50 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/NAND4_circuit.tex +%% +%% Purpose: Circuit File for NAND4 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{11}{8} + \usgate + \gate[\inputs{4}]{nand}{5}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{10}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/NAND4_manpage.tex b/Documents/LaTeX/NAND4_manpage.tex new file mode 100644 index 00000000..28bcc36c --- /dev/null +++ b/Documents/LaTeX/NAND4_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/NAND4_manpage.tex +%% +%% Purpose: Manual Page File for NAND4 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{NAND4} +\paragraph{Cell} +\begin{quote} + \textbf{NAND4} - a 4-input Not-AND (or NAND) gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + NAND4(Z, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{NAND4_circuit.tex} +%\input{NAND4_schematic.tex} + +\paragraph{Truth Table} +%\input{NAND4_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/NOR2_circuit.tex b/Documents/LaTeX/NOR2_circuit.tex index e785fb74..8e895127 100644 --- a/Documents/LaTeX/NOR2_circuit.tex +++ b/Documents/LaTeX/NOR2_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_NOR2.tex +%% File: StdCellLib/Documents/LaTeX/NOR2_circuit.tex %% %% Purpose: Circuit File for NOR2 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -37,10 +37,11 @@ \begin{figure}[h] %\caption{Circuit} \begin{center} \begin{circuitdiagram}{11}{6} + \usgate + \gate[\inputs{2}]{nor}{5}{3}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{5}{L}{B} % pin B - \gate[\inputs{2}]{nor}{5}{3}{R}{}{} % NOR gate -> right - \pin{10}{3}{R}{Z} % pin Z + \pin{1}{5}{L}{A1} % pin A1 + \pin{10}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/NOR2_manpage.tex b/Documents/LaTeX/NOR2_manpage.tex index 0123ab56..17b93bfd 100644 --- a/Documents/LaTeX/NOR2_manpage.tex +++ b/Documents/LaTeX/NOR2_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,7 +36,7 @@ \subsection{NOR2 - a 2-input Not-OR (or NOR) gate} \label{logical:NOR2} \paragraph{Synopsys} \begin{quote} - NOR2 (Z B A) + NOR2 (Z A1 A) \end{quote} \paragraph{Description} @@ -54,9 +54,4 @@ \subsection{NOR2 - a 2-input Not-OR (or NOR) gate} \label{logical:NOR2} \paragraph{Files} -\paragraph{See also} -\begin{quote} - NOR3 - a 3-input Not-OR (or NOR) gate -\end{quote} - \clearpage diff --git a/Documents/LaTeX/NOR3_circuit.tex b/Documents/LaTeX/NOR3_circuit.tex index 532ac88f..594e7731 100644 --- a/Documents/LaTeX/NOR3_circuit.tex +++ b/Documents/LaTeX/NOR3_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_NOR3.tex +%% File: StdCellLib/Documents/LaTeX/NOR3_circuit.tex %% %% Purpose: Circuit File for NOR3 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,14 +34,15 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{11}{6} + \usgate + \gate[\inputs{3}]{nor}{5}{3}{R}{}{} % NOR \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \gate[\inputs{3}]{nor}{5}{3}{R}{}{} % NOR gate -> right - \pin{10}{3}{R}{Z} % pin Z + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{10}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/NOR3_manpage.tex b/Documents/LaTeX/NOR3_manpage.tex index 703e703f..10f113a3 100644 --- a/Documents/LaTeX/NOR3_manpage.tex +++ b/Documents/LaTeX/NOR3_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,7 +36,7 @@ \subsection{NOR3 - a 3-input Not-OR (or NOR) gate} \label{logical:NOR3} \paragraph{Synopsys} \begin{quote} - NOR3 (Z C B A) + NOR3 (Z A2 A1 A) \end{quote} \paragraph{Description} @@ -54,9 +54,4 @@ \subsection{NOR3 - a 3-input Not-OR (or NOR) gate} \label{logical:NOR3} \paragraph{Files} -\paragraph{See also} -\begin{quote} - NOR2 - a 2-input Not-OR (or NOR) gate -\end{quote} - \clearpage diff --git a/Documents/LaTeX/NOR4_circuit.tex b/Documents/LaTeX/NOR4_circuit.tex new file mode 100644 index 00000000..44bc35bd --- /dev/null +++ b/Documents/LaTeX/NOR4_circuit.tex @@ -0,0 +1,50 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/NOR4_circuit.tex +%% +%% Purpose: Circuit File for NOR4 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{11}{8} + \usgate + \gate[\inputs{4}]{nor}{5}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{10}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/NOR4_manpage.tex b/Documents/LaTeX/NOR4_manpage.tex new file mode 100644 index 00000000..62c17d72 --- /dev/null +++ b/Documents/LaTeX/NOR4_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/NOR4_manpage.tex +%% +%% Purpose: Manual Page File for NOR4 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{NOR4} +\paragraph{Cell} +\begin{quote} + \textbf{NOR4} - a 4-input Not-OR (or NOR) gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + NOR4(Z, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{NOR4_circuit.tex} +%\input{NOR4_schematic.tex} + +\paragraph{Truth Table} +%\input{NOR4_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA21_circuit.tex b/Documents/LaTeX/OA21_circuit.tex new file mode 100644 index 00000000..c8e324ec --- /dev/null +++ b/Documents/LaTeX/OA21_circuit.tex @@ -0,0 +1,52 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA21_circuit.tex +%% +%% Purpose: Circuit File for OA21 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{8} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA21_manpage.tex b/Documents/LaTeX/OA21_manpage.tex new file mode 100644 index 00000000..5da7cccf --- /dev/null +++ b/Documents/LaTeX/OA21_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA21_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for OA21 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{OA21 - a 2-1-input OR-AND gate} \label{logical:OA21} + +\paragraph{Synopsys} +\begin{quote} + OA21 (Z B1 B A) +\end{quote} + +\paragraph{Description} +\input{OA21_circuit.tex} +%\input{OA21_schematic.tex} + +\paragraph{Truth Table} +%\input{OA21_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OA22_circuit.tex b/Documents/LaTeX/OA22_circuit.tex new file mode 100644 index 00000000..150e8159 --- /dev/null +++ b/Documents/LaTeX/OA22_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA22_circuit.tex +%% +%% Purpose: Circuit File for OA22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{2}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{9}{5}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA22_manpage.tex b/Documents/LaTeX/OA22_manpage.tex new file mode 100644 index 00000000..e189127c --- /dev/null +++ b/Documents/LaTeX/OA22_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA22_manpage.tex +%% +%% Purpose: Manual Page File for OA22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OA22} +\paragraph{Cell} +\begin{quote} + \textbf{OA22} - a 2-2-input OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OA22(Z, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OA22_circuit.tex} +%\input{OA22_schematic.tex} + +\paragraph{Truth Table} +%\input{OA22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA23_circuit.tex b/Documents/LaTeX/OA23_circuit.tex new file mode 100644 index 00000000..66cb03e8 --- /dev/null +++ b/Documents/LaTeX/OA23_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA23_circuit.tex +%% +%% Purpose: Circuit File for OA23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \gate{not}{19}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{9}{9}{7} % wire between OR and NAND + \pin{23}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA23_manpage.tex b/Documents/LaTeX/OA23_manpage.tex new file mode 100644 index 00000000..3d0b8e17 --- /dev/null +++ b/Documents/LaTeX/OA23_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA23_manpage.tex +%% +%% Purpose: Manual Page File for OA23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OA23} +\paragraph{Cell} +\begin{quote} + \textbf{OA23} - a 2-3-input OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OA23 (Z, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OA23_circuit.tex} +%\input{OA23_schematic.tex} + +\paragraph{Truth Table} +%\input{OA23_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA2111_truthtable.tex b/Documents/LaTeX/OA23_truthtable.tex similarity index 91% rename from Documents/LaTeX/OA2111_truthtable.tex rename to Documents/LaTeX/OA23_truthtable.tex index e5451f6e..eb0bbf41 100644 --- a/Documents/LaTeX/OA2111_truthtable.tex +++ b/Documents/LaTeX/OA23_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OA2111.tex +%% File: StdCellLib/Documents/LaTeX/OA23_truthtable.tex %% -%% Purpose: Truth Table File for OA2111 +%% Purpose: Truth Table File for OA23 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OA3111_truthtable.tex b/Documents/LaTeX/OA3111_truthtable.tex deleted file mode 100644 index 4f0ae59b..00000000 --- a/Documents/LaTeX/OA3111_truthtable.tex +++ /dev/null @@ -1,52 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/truthtable_OA3111.tex -%% -%% Purpose: Truth Table File for OA3111 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// - -\begin{center} - {\(Z = (D2 \lor D1 \lor D0) \land C \land B \land A \)} - \begin{table}[h] %\caption{\(Z = (D2 \lor D1 \lor D0) \land C \land B \land A \)} - \begin{center} - \begin{tabular}{|c|c|c|c|c|c||c|} \hline - D2 & D1 & D0 & C & B & A & Z \\ \hline\hline - 0 & 0 & 0 & X & X & X & 0 \\ \hline - 1 & X & X & 1 & 1 & 1 & 1 \\ \hline - X & 1 & X & 1 & 1 & 1 & 1 \\ \hline - X & X & 1 & 1 & 1 & 1 & 1 \\ \hline - X & X & X & 0 & X & X & 0 \\ \hline - X & X & X & X & 0 & X & 0 \\ \hline - X & X & X & X & X & 0 & 0 \\ \hline - \end{tabular} - \end{center} - \end{table} -\end{center} diff --git a/Documents/LaTeX/OA31_circuit.tex b/Documents/LaTeX/OA31_circuit.tex new file mode 100644 index 00000000..7fa8d27b --- /dev/null +++ b/Documents/LaTeX/OA31_circuit.tex @@ -0,0 +1,53 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA31_circuit.tex +%% +%% Purpose: Circuit File for OA31 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{8} + \usgate + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND + \gate{not}{19}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA31_manpage.tex b/Documents/LaTeX/OA31_manpage.tex new file mode 100644 index 00000000..64257861 --- /dev/null +++ b/Documents/LaTeX/OA31_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA31_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for OA31 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{OA31 - a 3-1-input OR-AND gate} \label{logical:OA31} + +\paragraph{Synopsys} +\begin{quote} + OA31 (Z B2 B1 B A) +\end{quote} + +\paragraph{Description} +\input{OA31_circuit.tex} +%\input{OA31_schematic.tex} + +\paragraph{Truth Table} +%\input{OA31_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OA32_circuit.tex b/Documents/LaTeX/OA32_circuit.tex new file mode 100644 index 00000000..29158b64 --- /dev/null +++ b/Documents/LaTeX/OA32_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA32_circuit.tex +%% +%% Purpose: Circuit File for OA32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{3}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{9}{5}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA32_manpage.tex b/Documents/LaTeX/OA32_manpage.tex new file mode 100644 index 00000000..7e89b692 --- /dev/null +++ b/Documents/LaTeX/OA32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA32_manpage.tex +%% +%% Purpose: Manual Page File for OA32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OA32} +\paragraph{Cell} +\begin{quote} + \textbf{OA32} - a 3-2-input OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OA32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OA32_circuit.tex} +%\input{OA32_schematic.tex} + +\paragraph{Truth Table} +%\input{OA32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA3111_circuit.tex b/Documents/LaTeX/OA33_circuit.tex similarity index 65% rename from Documents/LaTeX/OA3111_circuit.tex rename to Documents/LaTeX/OA33_circuit.tex index 127db690..04f5cfca 100644 --- a/Documents/LaTeX/OA3111_circuit.tex +++ b/Documents/LaTeX/OA33_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OA3111.tex +%% File: StdCellLib/Documents/LaTeX/OAI23_circuit.tex %% -%% Purpose: Circuit File for OA3111 +%% Purpose: Circuit File for OAI23 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \gate{not}{19}{4}{R}{}{} % NOT \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D0} % pin D0 - \pin{1}{9}{L}{D1} % pin D1 - \pin{1}{11}{L}{D2} % pin D2 - \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND gate -> right - \gate{not}{19}{4}{R}{}{} % NOT gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{2}{5}{9}{5} % wire from pin C - \wire{9}{9}{9}{7} % wire between OR and NAND + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{9}{9}{7} % wire between OR and NAND \pin{23}{4}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/OA33_manpage.tex b/Documents/LaTeX/OA33_manpage.tex new file mode 100644 index 00000000..3165ba39 --- /dev/null +++ b/Documents/LaTeX/OA33_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA33_manpage.tex +%% +%% Purpose: Manual Page File for OA33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OA33} +\paragraph{Cell} +\begin{quote} + \textbf{OA33} - a 3-3-input OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OA33 (Z, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OA33_circuit.tex} +%\input{OA33_schematic.tex} + +\paragraph{Truth Table} +%\input{OA33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA41_circuit.tex b/Documents/LaTeX/OA41_circuit.tex new file mode 100644 index 00000000..0ef70c59 --- /dev/null +++ b/Documents/LaTeX/OA41_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA41_circuit.tex +%% +%% Purpose: Circuit File for OA41 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{10} + \usgate + \gate[\inputs{4}]{or}{5}{6}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND + \gate{not}{19}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{B3} % pin B3 + \wire{9}{5}{9}{6} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \pin{23}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA41_manpage.tex b/Documents/LaTeX/OA41_manpage.tex new file mode 100644 index 00000000..a58b418e --- /dev/null +++ b/Documents/LaTeX/OA41_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA41_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for OA41 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{OA41 - a 4-1-input OR-AND gate} \label{logical:OA41} + +\paragraph{Synopsys} +\begin{quote} + OA41 (Z B3 B2 B1 B A) +\end{quote} + +\paragraph{Description} +\input{OA41_circuit.tex} +%\input{OA41_schematic.tex} + +\paragraph{Truth Table} +%\input{OA41_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OA43_circuit.tex b/Documents/LaTeX/OA43_circuit.tex new file mode 100644 index 00000000..f06362dd --- /dev/null +++ b/Documents/LaTeX/OA43_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA43_circuit.tex +%% +%% Purpose: Circuit File for OA43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \gate{not}{19}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{7}{9}{10} % wire between OR and NAND + \pin{23}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OA43_manpage.tex b/Documents/LaTeX/OA43_manpage.tex new file mode 100644 index 00000000..b521cc7e --- /dev/null +++ b/Documents/LaTeX/OA43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OA43_manpage.tex +%% +%% Purpose: Manual Page File for OA43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OA43} +\paragraph{Cell} +\begin{quote} + \textbf{OA43} - a 4-3-input OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OA43 (Z, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OA43_circuit.tex} +%\input{OA43_schematic.tex} + +\paragraph{Truth Table} +%\input{OA43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAAAO2232_circuit.tex b/Documents/LaTeX/OAAAO2232_circuit.tex new file mode 100644 index 00000000..d1ab625a --- /dev/null +++ b/Documents/LaTeX/OAAAO2232_circuit.tex @@ -0,0 +1,70 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAAO2232_circuit.tex +%% +%% Purpose: Circuit File for OAAAO2232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{22} + \usgate + \gate[\inputs{2}]{or}{5}{19}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{9}{R}{}{} % NOR + \gate{not}{26}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire A1 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire B2 + \pin{1}{13}{L}{C} % pin C + \wire{2}{13}{9}{13} % wire C + \pin{1}{15}{L}{C1} % pin C1 + \wire{2}{15}{9}{15} % wire C1 + \pin{1}{17}{L}{D} % pin D + \pin{1}{21}{L}{D1} % pin D1 + \wire{9}{17}{9}{19} % wire between OR and AND + \wire{16}{3}{16}{7} % wire between AND and NOR + \wire{16}{11}{16}{15}% wire between AND and NOR + \pin{30}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAAO2232_manpage.tex b/Documents/LaTeX/OAAAO2232_manpage.tex new file mode 100644 index 00000000..efdeb4ad --- /dev/null +++ b/Documents/LaTeX/OAAAO2232_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAAO2232_manpage.tex +%% +%% Purpose: Manual Page File for OAAAO2232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAAO2232} +\paragraph{Cell} +\begin{quote} + \textbf{OAAAO2232} - a 2-2-3-2-input OR-AND-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAAO2232(Z, D1, D, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAAO2232_circuit.tex} +%\input{OAAAO2232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAAO2232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAAAOI2232_circuit.tex b/Documents/LaTeX/OAAAOI2232_circuit.tex new file mode 100644 index 00000000..b2c8a4bf --- /dev/null +++ b/Documents/LaTeX/OAAAOI2232_circuit.tex @@ -0,0 +1,69 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAAOI2232_circuit.tex +%% +%% Purpose: Circuit File for OAAAOI2232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{22} + \usgate + \gate[\inputs{2}]{or}{5}{19}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{15}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{9}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire A1 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire B2 + \pin{1}{13}{L}{C} % pin C + \wire{2}{13}{9}{13} % wire C + \pin{1}{15}{L}{C1} % pin C1 + \wire{2}{15}{9}{15} % wire C1 + \pin{1}{17}{L}{D} % pin D + \pin{1}{21}{L}{D1} % pin D1 + \wire{9}{17}{9}{19} % wire between OR and AND + \wire{16}{3}{16}{7} % wire between AND and NOR + \wire{16}{11}{16}{15}% wire between AND and NOR + \pin{24}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAAOI2232_manpage.tex b/Documents/LaTeX/OAAAOI2232_manpage.tex new file mode 100644 index 00000000..148497c4 --- /dev/null +++ b/Documents/LaTeX/OAAAOI2232_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAAOI2232_manpage.tex +%% +%% Purpose: Manual Page File for OAAAOI2232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAAOI2232} +\paragraph{Cell} +\begin{quote} + \textbf{OAAAOI2232} - a 2-2-3-2-input OR-AND-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAAOI2232(Y, D1, D, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAAOI2232_circuit.tex} +%\input{OAAAOI2232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAAOI2232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAAO2121_circuit.tex b/Documents/LaTeX/OAAO2121_circuit.tex new file mode 100644 index 00000000..352e689e --- /dev/null +++ b/Documents/LaTeX/OAAO2121_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2121_circuit.tex +%% +%% Purpose: Circuit File for OAAO2121 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \gate{not}{26}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{D} % pin D + \pin{1}{15}{L}{D1} % pin D1 + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{30}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO2121_manpage.tex b/Documents/LaTeX/OAAO2121_manpage.tex new file mode 100644 index 00000000..7c1002a4 --- /dev/null +++ b/Documents/LaTeX/OAAO2121_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2121_manpage.tex +%% +%% Purpose: Manual Page File for OAAO2121 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO2121} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO2121} - a 2-1-2-1-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO2121(Z, D1, D1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAO2121_circuit.tex} +%\input{OAAO2121_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO2121_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO212_circuit.tex b/Documents/LaTeX/OAAO212_circuit.tex new file mode 100644 index 00000000..372ff74d --- /dev/null +++ b/Documents/LaTeX/OAAO212_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO212_circuit.tex +%% +%% Purpose: Circuit File for OAAO212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO212_manpage.tex b/Documents/LaTeX/OAAO212_manpage.tex new file mode 100644 index 00000000..bae09fb8 --- /dev/null +++ b/Documents/LaTeX/OAAO212_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO212_manpage.tex +%% +%% Purpose: Manual Page File for OAAO212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO212} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO212} - a 2-1-2-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO212(Z, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO212_circuit.tex} +%\input{OAAO212_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO2221_circuit.tex b/Documents/LaTeX/OAAO2221_circuit.tex new file mode 100644 index 00000000..93f39ab1 --- /dev/null +++ b/Documents/LaTeX/OAAO2221_circuit.tex @@ -0,0 +1,65 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2221_circuit.tex +%% +%% Purpose: Circuit File for OAAO2221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{27}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \gate{not}{26}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{2}{11}{9}{11} % wire pin C1 + \pin{1}{13}{L}{D} % pin D + \pin{1}{17}{L}{D1} % pin D1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{30}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO2221_manpage.tex b/Documents/LaTeX/OAAO2221_manpage.tex new file mode 100644 index 00000000..f732f75e --- /dev/null +++ b/Documents/LaTeX/OAAO2221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2221_manpage.tex +%% +%% Purpose: Manual Page File for OAAO2221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO2221} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO2221} - a 2-2-2-1-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO2221(Z, D1, D1, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAO2221_circuit.tex} +%\input{OAAO2221_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO2221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO222_circuit.tex b/Documents/LaTeX/OAAO222_circuit.tex new file mode 100644 index 00000000..46f26d85 --- /dev/null +++ b/Documents/LaTeX/OAAO222_circuit.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO222_circuit.tex +%% +%% Purpose: Circuit File for OAAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire pin A1 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO222_manpage.tex b/Documents/LaTeX/OAAO222_manpage.tex new file mode 100644 index 00000000..bdb35709 --- /dev/null +++ b/Documents/LaTeX/OAAO222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO222_manpage.tex +%% +%% Purpose: Manual Page File for OAAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO222} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO222} - a 2-2-2-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO222_circuit.tex} +%\input{OAAO222_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO2231_circuit.tex b/Documents/LaTeX/OAAO2231_circuit.tex new file mode 100644 index 00000000..3c08a56c --- /dev/null +++ b/Documents/LaTeX/OAAO2231_circuit.tex @@ -0,0 +1,67 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2231_circuit.tex +%% +%% Purpose: Circuit File for OAAO2231 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \gate{not}{26}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{5}{L}{B1} % pin B1 + \wire{2}{5}{9}{5} % wire pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \wire{2}{7}{9}{7} % wire pin B2 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{2}{11}{9}{11} % wire pin C1 + \pin{1}{13}{L}{D} % pin D + \pin{1}{17}{L}{D1} % pin D1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{30}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO2231_manpage.tex b/Documents/LaTeX/OAAO2231_manpage.tex new file mode 100644 index 00000000..f5b04e13 --- /dev/null +++ b/Documents/LaTeX/OAAO2231_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO2231_manpage.tex +%% +%% Purpose: Manual Page File for OAAO2231 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO2231} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO2231} - a 2-2-3-1-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO2231(Z, D1, D1, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAO2231_circuit.tex} +%\input{OAAO2231_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO2231_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO223_circuit.tex b/Documents/LaTeX/OAAO223_circuit.tex new file mode 100644 index 00000000..e5b72730 --- /dev/null +++ b/Documents/LaTeX/OAAO223_circuit.tex @@ -0,0 +1,65 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO223_circuit.tex +%% +%% Purpose: Circuit File for OAAO223 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO223_manpage.tex b/Documents/LaTeX/OAAO223_manpage.tex new file mode 100644 index 00000000..5bdb549b --- /dev/null +++ b/Documents/LaTeX/OAAO223_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO223_manpage.tex +%% +%% Purpose: Manual Page File for OAAO223 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO223} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO223} - a 2-2-3-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO223(Z, C1, C, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO223_circuit.tex} +%\input{OAAO223_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO223_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO232_circuit.tex b/Documents/LaTeX/OAAO232_circuit.tex new file mode 100644 index 00000000..e1a79c54 --- /dev/null +++ b/Documents/LaTeX/OAAO232_circuit.tex @@ -0,0 +1,65 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO232_circuit.tex +%% +%% Purpose: Circuit File for OAAO232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{10}{R}{}{}% AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{7}{R}{}{} % NOR + \gate{not}{26}{7}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{3}{16}{5} % wire between AND and NOR + \wire{16}{9}{16}{10} % wire between AND and NOR + \pin{30}{7}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO232_manpage.tex b/Documents/LaTeX/OAAO232_manpage.tex new file mode 100644 index 00000000..805c61cb --- /dev/null +++ b/Documents/LaTeX/OAAO232_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO232_manpage.tex +%% +%% Purpose: Manual Page File for OAAO232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO232} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO232} - a 2-3-2-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO232(Z, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO232_circuit.tex} +%\input{OAAO232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO233_circuit.tex b/Documents/LaTeX/OAAO233_circuit.tex new file mode 100644 index 00000000..e7d2126a --- /dev/null +++ b/Documents/LaTeX/OAAO233_circuit.tex @@ -0,0 +1,67 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO233_circuit.tex +%% +%% Purpose: Circuit File for OAAO233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{10}{R}{}{}% AND + \gate[\inputs{3}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{7}{R}{}{} % NOR + \gate{not}{26}{7}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{3}{16}{5} % wire between AND and NOR + \wire{16}{9}{16}{10} % wire between AND and NOR + \pin{30}{7}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO233_manpage.tex b/Documents/LaTeX/OAAO233_manpage.tex new file mode 100644 index 00000000..e61a9d89 --- /dev/null +++ b/Documents/LaTeX/OAAO233_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO233_manpage.tex +%% +%% Purpose: Manual Page File for OAAO233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO233} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO233} - a 2-3-3-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO233(Z, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO233_circuit.tex} +%\input{OAAO233_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO233_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO234_circuit.tex b/Documents/LaTeX/OAAO234_circuit.tex new file mode 100644 index 00000000..a020e74d --- /dev/null +++ b/Documents/LaTeX/OAAO234_circuit.tex @@ -0,0 +1,69 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO233_circuit.tex +%% +%% Purpose: Circuit File for OAAO233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{20} + \usgate + \gate[\inputs{2}]{or}{5}{17}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{12}{R}{}{}% AND + \gate[\inputs{4}]{and}{12}{4}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{8}{R}{}{} % NOR + \gate{not}{26}{8}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A2 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \wire{2}{7}{9}{7} % wire pin A3 + \pin{1}{9}{L}{B} % pin B + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{2}{11}{9}{11} % wire pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \wire{2}{13}{9}{13} % wire pin B2 + \pin{1}{15}{L}{C} % pin C + \pin{1}{19}{L}{C1} % pin C1 + \wire{9}{15}{9}{17} % wire between OR and AND + \wire{16}{4}{16}{6} % wire between AND and NOR + \wire{16}{10}{16}{12}% wire between AND and NOR + \pin{30}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO234_manpage.tex b/Documents/LaTeX/OAAO234_manpage.tex new file mode 100644 index 00000000..e509c2d6 --- /dev/null +++ b/Documents/LaTeX/OAAO234_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO234_manpage.tex +%% +%% Purpose: Manual Page File for OAAO234 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO234} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO234} - a 2-3-4-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO234(Z, C1, C, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO234_circuit.tex} +%\input{OAAO234_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO234_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAO312_circuit.tex b/Documents/LaTeX/OAAO312_circuit.tex new file mode 100644 index 00000000..a5884348 --- /dev/null +++ b/Documents/LaTeX/OAAO312_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO312_circuit.tex +%% +%% Purpose: Circuit File for OAAO312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \gate{not}{26}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{30}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAO312_manpage.tex b/Documents/LaTeX/OAAO312_manpage.tex new file mode 100644 index 00000000..fe04e379 --- /dev/null +++ b/Documents/LaTeX/OAAO312_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAO312_manpage.tex +%% +%% Purpose: Manual Page File for OAAO312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAO312} +\paragraph{Cell} +\begin{quote} + \textbf{OAAO312} - a 3-1-2-input OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAO312(Z, C2, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAO312_circuit.tex} +%\input{OAAO312_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAO312_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI2121_circuit.tex b/Documents/LaTeX/OAAOI2121_circuit.tex new file mode 100644 index 00000000..ffafc2ab --- /dev/null +++ b/Documents/LaTeX/OAAOI2121_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2121_circuit.tex +%% +%% Purpose: Circuit File for OAAOI2121 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{D} % pin D + \pin{1}{15}{L}{D1} % pin D1 + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{24}{5}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI2121_manpage.tex b/Documents/LaTeX/OAAOI2121_manpage.tex new file mode 100644 index 00000000..51338ad9 --- /dev/null +++ b/Documents/LaTeX/OAAOI2121_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2121_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI2121 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI2121} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI2121} - a 2-1-2-1-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI2121(Y, D1, D1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI2121_circuit.tex} +%\input{OAAOI2121_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI2121_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI212_circuit.tex b/Documents/LaTeX/OAAOI212_circuit.tex new file mode 100644 index 00000000..bd8b99b3 --- /dev/null +++ b/Documents/LaTeX/OAAOI212_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI212_circuit.tex +%% +%% Purpose: Circuit File for OAAOI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI212_manpage.tex b/Documents/LaTeX/OAAOI212_manpage.tex new file mode 100644 index 00000000..12deb135 --- /dev/null +++ b/Documents/LaTeX/OAAOI212_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI212_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI212} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI212} - a 2-1-2-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI212(Z, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI212_circuit.tex} +%\input{OAAOI212_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI2221_circuit.tex b/Documents/LaTeX/OAAOI2221_circuit.tex new file mode 100644 index 00000000..315a2465 --- /dev/null +++ b/Documents/LaTeX/OAAOI2221_circuit.tex @@ -0,0 +1,64 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2221_circuit.tex +%% +%% Purpose: Circuit File for OAAOI2221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{2}{11}{9}{11} % wire pin C1 + \pin{1}{13}{L}{D} % pin D + \pin{1}{17}{L}{D1} % pin D1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{24}{5}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI2221_manpage.tex b/Documents/LaTeX/OAAOI2221_manpage.tex new file mode 100644 index 00000000..cc3fcb30 --- /dev/null +++ b/Documents/LaTeX/OAAOI2221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2221_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI2221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI2221} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI2221} - a 2-2-2-1-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI2221(Y, D1, D1, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI2221_circuit.tex} +%\input{OAAOI2221_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI2221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI222_circuit.tex b/Documents/LaTeX/OAAOI222_circuit.tex new file mode 100644 index 00000000..532bf800 --- /dev/null +++ b/Documents/LaTeX/OAAOI222_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI222_circuit.tex +%% +%% Purpose: Circuit File for OAAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire pin A1 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI222_manpage.tex b/Documents/LaTeX/OAAOI222_manpage.tex new file mode 100644 index 00000000..ab1ea0f4 --- /dev/null +++ b/Documents/LaTeX/OAAOI222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI222_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI222} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI222} - a 2-2-2-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI222(Y, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI222_circuit.tex} +%\input{OAAOI222_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI2231_circuit.tex b/Documents/LaTeX/OAAOI2231_circuit.tex new file mode 100644 index 00000000..138defdd --- /dev/null +++ b/Documents/LaTeX/OAAOI2231_circuit.tex @@ -0,0 +1,66 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2231_circuit.tex +%% +%% Purpose: Circuit File for OAAOI2231 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{11}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{5}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{B} % pin B + \wire{2}{3}{9}{3} % wire pin B + \pin{1}{5}{L}{B1} % pin B1 + \wire{2}{5}{9}{5} % wire pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \wire{2}{7}{9}{7} % wire pin B2 + \pin{1}{9}{L}{C} % pin C + \wire{2}{9}{9}{9} % wire pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{2}{11}{9}{11} % wire pin C1 + \pin{1}{13}{L}{D} % pin D + \pin{1}{17}{L}{D1} % pin D1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{1}{16}{3} % wire between AND and NOR + \wire{16}{7}{16}{11} % wire between AND and NOR + \pin{24}{5}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI2231_manpage.tex b/Documents/LaTeX/OAAOI2231_manpage.tex new file mode 100644 index 00000000..021d8e8c --- /dev/null +++ b/Documents/LaTeX/OAAOI2231_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI2231_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI2231 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI2231} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI2231} - a 2-2-3-1-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI2231(Y, D1, D1, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI2231_circuit.tex} +%\input{OAAOI2231_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI2231_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI223_circuit.tex b/Documents/LaTeX/OAAOI223_circuit.tex new file mode 100644 index 00000000..5b21c4d1 --- /dev/null +++ b/Documents/LaTeX/OAAOI223_circuit.tex @@ -0,0 +1,64 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI223_circuit.tex +%% +%% Purpose: Circuit File for OAAOI223 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{3}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI223_manpage.tex b/Documents/LaTeX/OAAOI223_manpage.tex new file mode 100644 index 00000000..e24f0656 --- /dev/null +++ b/Documents/LaTeX/OAAOI223_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI223_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI223 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI223} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI223} - a 2-2-3-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI223(Y, C1, C, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI223_circuit.tex} +%\input{OAAOI223_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI223_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI232_circuit.tex b/Documents/LaTeX/OAAOI232_circuit.tex new file mode 100644 index 00000000..a9ead6b7 --- /dev/null +++ b/Documents/LaTeX/OAAOI232_circuit.tex @@ -0,0 +1,64 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI232_circuit.tex +%% +%% Purpose: Circuit File for OAAOI232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{10}{R}{}{}% AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{7}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{5}{L}{A1} % pin A1 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{3}{16}{5} % wire between AND and NOR + \wire{16}{9}{16}{10} % wire between AND and NOR + \pin{24}{7}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI232_manpage.tex b/Documents/LaTeX/OAAOI232_manpage.tex new file mode 100644 index 00000000..77e0cf4c --- /dev/null +++ b/Documents/LaTeX/OAAOI232_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI232_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI232} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI232} - a 2-3-2-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI232(Y, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI232_circuit.tex} +%\input{OAAOI232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI233_circuit.tex b/Documents/LaTeX/OAAOI233_circuit.tex new file mode 100644 index 00000000..564f884d --- /dev/null +++ b/Documents/LaTeX/OAAOI233_circuit.tex @@ -0,0 +1,66 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI233_circuit.tex +%% +%% Purpose: Circuit File for OAAOI233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{10}{R}{}{}% AND + \gate[\inputs{3}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{7}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A2 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{B} % pin B + \wire{2}{7}{9}{7} % wire pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{2}{9}{9}{9} % wire pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{11}{9}{11} % wire pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{13}{9}{15} % wire between OR and AND + \wire{16}{3}{16}{5} % wire between AND and NOR + \wire{16}{9}{16}{10} % wire between AND and NOR + \pin{24}{7}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI233_manpage.tex b/Documents/LaTeX/OAAOI233_manpage.tex new file mode 100644 index 00000000..2e07ec1c --- /dev/null +++ b/Documents/LaTeX/OAAOI233_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI233_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI233} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI233} - a 2-3-3-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI233(Y, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI233_circuit.tex} +%\input{OAAOI233_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI233_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI234_circuit.tex b/Documents/LaTeX/OAAOI234_circuit.tex new file mode 100644 index 00000000..5c2a8dcb --- /dev/null +++ b/Documents/LaTeX/OAAOI234_circuit.tex @@ -0,0 +1,68 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI233_circuit.tex +%% +%% Purpose: Circuit File for OAAOI233 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{20} + \usgate + \gate[\inputs{2}]{or}{5}{17}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{12}{R}{}{}% AND + \gate[\inputs{4}]{and}{12}{4}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{8}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{9}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{9}{3} % wire pin A2 + \pin{1}{5}{L}{A2} % pin A2 + \wire{2}{5}{9}{5} % wire pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \wire{2}{7}{9}{7} % wire pin A3 + \pin{1}{9}{L}{B} % pin B + \wire{2}{9}{9}{9} % wire pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{2}{11}{9}{11} % wire pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \wire{2}{13}{9}{13} % wire pin B2 + \pin{1}{15}{L}{C} % pin C + \pin{1}{19}{L}{C1} % pin C1 + \wire{9}{15}{9}{17} % wire between OR and AND + \wire{16}{4}{16}{6} % wire between AND and NOR + \wire{16}{10}{16}{12}% wire between AND and NOR + \pin{24}{8}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI234_manpage.tex b/Documents/LaTeX/OAAOI234_manpage.tex new file mode 100644 index 00000000..c3c6a384 --- /dev/null +++ b/Documents/LaTeX/OAAOI234_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI234_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI234 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI234} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI234} - a 2-3-4-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI234(Y, C1, C, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI234_circuit.tex} +%\input{OAAOI234_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI234_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAAOI312_circuit.tex b/Documents/LaTeX/OAAOI312_circuit.tex new file mode 100644 index 00000000..8f58dcb4 --- /dev/null +++ b/Documents/LaTeX/OAAOI312_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI312_circuit.tex +%% +%% Purpose: Circuit File for OAAOI312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{9}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{6}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{2}{7}{9}{7} % wire pin B + \wire{16}{3}{16}{4} % wire between AND and NOR + \wire{16}{9}{16}{8} % wire between AND and NOR + \pin{24}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAAOI312_manpage.tex b/Documents/LaTeX/OAAOI312_manpage.tex new file mode 100644 index 00000000..0fda8c79 --- /dev/null +++ b/Documents/LaTeX/OAAOI312_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAAOI312_manpage.tex +%% +%% Purpose: Manual Page File for OAAOI312 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAAOI312} +\paragraph{Cell} +\begin{quote} + \textbf{OAAOI312} - a 3-1-2-input OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAAOI312(Z, C2, C1, C, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAAOI312_circuit.tex} +%\input{OAAOI312_schematic.tex} + +\paragraph{Truth Table} +%\input{OAAOI312_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAI211_manpage.tex b/Documents/LaTeX/OAI211_manpage.tex deleted file mode 100644 index f40b7fa5..00000000 --- a/Documents/LaTeX/OAI211_manpage.tex +++ /dev/null @@ -1,64 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI211.tex -%% -%% Purpose: Manual Page File for OAI211 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI211} -\paragraph{Cell} -\begin{quote} - \textbf{OAI211} - a 2-1-1-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI211(Z, C1, C0, B, A) -\end{quote} - -\paragraph{Description} -\input{OAI211_circuit.tex} -\input{OAI211_schematic.tex} - -\paragraph{Truth Table} -\input{OAI211_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI311 - a 3-1-1-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI211_schematic.tex b/Documents/LaTeX/OAI211_schematic.tex deleted file mode 100644 index eb9b3452..00000000 --- a/Documents/LaTeX/OAI211_schematic.tex +++ /dev/null @@ -1,73 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI221.tex -%% -%% Purpose: Schematic File for OAI221 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\begin{center} - Schematic (one stage, 2$T_{p}$/3$T_{n}$ stacked, 8T total) - \begin{figure}[h] %\caption{Schematic} - \begin{center} - \begin{circuitdiagram}{36}{33} - \pin{2}{2.5}{L}{C0} % pin C0, n-channel - \pin{2}{8.5}{L}{B} % pin B, n-channel - \pin{2}{14.5}{L}{A} % pin A, n-channel - \pin{14}{2.5}{L}{C1} % pin C1, n-channel - \pin{2}{23.5}{L}{A} % pin A, p-channel - \pin{14}{23.5}{L}{B} % pin B, p-channel - \pin{26}{23.5}{L}{C0} % pin C0, p-channel - \pin{26}{29.5}{L}{C1} % pin C1, p-channel - \trans[\wireU{0.5}]{nenh*}{6}{4}{R}{$M_{NC0}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{10}{R}{$M_{NB}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{16}{R}{$M_{NA}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NC1}$}{} - \trans[\wireD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA}$} - \trans[\wireD{0.5}]{penh*}{18}{22}{R}{}{$M_{PB}$} - \trans[\wireUD{0.5}]{penh*}{30}{22}{R}{}{$M_{PC0}$} - \trans[\wireD{0.5}]{penh*}{30}{28}{R}{}{$M_{PC1}$} - \ground{8}{0.5}{D} % ground below nmos - \ground{20}{0.5}{D} % ground below nmos - \power{8}{31.5}{U}{} % power above left pmos - \power{20}{31.5}{U}{} % power above middle pmos - \power{32}{31.5}{U}{} % power above right pmos - \wire{8}{24}{8}{31} - \wire{20}{24}{20}{31} - \wire{8}{7}{20}{7} % wire short between nmos - \wire{8}{19}{34}{19} % wire before pin Z - \junct{8}{19} - \junct{8}{7} - \junct{20}{19} - \junct{32}{19} - \pin{35}{19}{R}{Z} % pin Z - \end{circuitdiagram} - \end{center} - \end{figure} -\end{center} diff --git a/Documents/LaTeX/OAI21_circuit.tex b/Documents/LaTeX/OAI21_circuit.tex index e46c784e..4abaf5d2 100644 --- a/Documents/LaTeX/OAI21_circuit.tex +++ b/Documents/LaTeX/OAI21_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI21.tex +%% File: StdCellLib/Documents/LaTeX/OAI21_circuit.tex %% %% Purpose: Circuit File for OAI21 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,16 +34,17 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{8} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \pin{17}{3}{R}{Z} % pin Z + \wire{2}{1}{9}{1} % wire from pin A + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI21_manpage.tex b/Documents/LaTeX/OAI21_manpage.tex index c7aa8580..ca361eae 100644 --- a/Documents/LaTeX/OAI21_manpage.tex +++ b/Documents/LaTeX/OAI21_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -54,9 +54,4 @@ \subsection{OAI21 - a 2-1-input OR-AND-Invert gate} \label{logical:OAI21} \paragraph{Files} -\paragraph{See also} -\begin{quote} - OAI31 - a 3-1-input OR-AND-Invert gate -\end{quote} - \clearpage diff --git a/Documents/LaTeX/OAI221_manpage.tex b/Documents/LaTeX/OAI221_manpage.tex deleted file mode 100644 index 78aad943..00000000 --- a/Documents/LaTeX/OAI221_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI221.tex -%% -%% Purpose: Manual Page File for OAI221 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI221} -\paragraph{Cell} -\begin{quote} - \textbf{OAI221} - a 2-2-1-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI221(Z, C1, C0, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{OAI221_circuit.tex} -\input{OAI221_schematic.tex} - -\paragraph{Truth Table} -\input{OAI221_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI321 - a 3-2-1-input OR-AND-Invert gate \\ - OAI331 - a 3-3-1-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI222_manpage.tex b/Documents/LaTeX/OAI222_manpage.tex deleted file mode 100644 index dae12d7c..00000000 --- a/Documents/LaTeX/OAI222_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI222.tex -%% -%% Purpose: Manual Page File for OAI222 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI222} -\paragraph{Cell} -\begin{quote} - \textbf{OAI222} - a 2-2-2-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI222(Z, C1, C0, B1, B0, A1, A0) -\end{quote} - -\paragraph{Description} -\input{OAI222_circuit.tex} -\input{OAI222_schematic.tex} - -\paragraph{Truth Table} -\input{OAI222_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI322 - a 2-2-2-input OR-AND-Invert gate \\ - OAI332 - a 3-3-2-input OR-AND-Invert gate \\ - OAI333 - a 3-3-3-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI22_circuit.tex b/Documents/LaTeX/OAI22_circuit.tex index e35b9dd4..c85f7614 100644 --- a/Documents/LaTeX/OAI22_circuit.tex +++ b/Documents/LaTeX/OAI22_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI22.tex +%% File: StdCellLib/Documents/LaTeX/OAI22_circuit.tex %% %% Purpose: Circuit File for OAI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,19 +34,20 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{11}{L}{B1} % pin B1 - \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{4} % wire between OR and NAND - \wire{9}{9}{9}{8} % wire between OR and NAND - \pin{17}{6}{R}{Z} % pin Z + \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{2}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \wire{9}{5}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI22_manpage.tex b/Documents/LaTeX/OAI22_manpage.tex index 9bd3824e..6421f502 100644 --- a/Documents/LaTeX/OAI22_manpage.tex +++ b/Documents/LaTeX/OAI22_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI22.tex +%% File: StdCellLib/Documents/LaTeX/OAI22_manpage.tex %% %% Purpose: Manual Page File for OAI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,7 +40,7 @@ \paragraph{Synopsys} \begin{quote} - OAI22(Z, B1, B0, A1, A0) + OAI22(Z, B1, B0, A1, A) \end{quote} \paragraph{Description} @@ -57,9 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI32 - a 3-2-input OR-AND-Invert gate \\ - OAI33 - a 3-3-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI22_schematic.tex b/Documents/LaTeX/OAI22_schematic.tex index 98304f04..8f99c529 100644 --- a/Documents/LaTeX/OAI22_schematic.tex +++ b/Documents/LaTeX/OAI22_schematic.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI22.tex +%% File: StdCellLib/Documents/LaTeX/OAI22_schematic.tex %% %% Purpose: Schematic File for OAI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -33,37 +33,40 @@ %% %% /////////////////////////////////////////////////////////////////// \begin{center} - Schematic (one stage, 2$T_{p}$/2$T_{n}$ stacked, 8T total) + Schematic (one stage, 2$T_{p}$/3$T_{n}$ stacked, 8T total) \begin{figure}[h] %\caption{Schematic} \begin{center} - \begin{circuitdiagram}{24}{27} - \pin{2}{2.5}{L}{B0} % pin B0, n-channel left-below - \pin{2}{8.5}{L}{A0} % pin A0, n-channel left-above - \pin{14}{2.5}{L}{B1} % pin B1, n-channel right-below - \pin{14}{8.5}{L}{A1} % pin A1, n-channel right-above - \pin{2}{17.5}{L}{A0} % pin A0, p-channel left-below - \pin{14}{17.5}{L}{B0} % pin B0, p-channel right-below - \pin{2}{23.5}{L}{A1} % pin A1, p-channel left-above - \pin{14}{23.5}{L}{B1} % pin B1, p-channel right-above - \trans[\wireU{0.5}]{nenh*}{6}{4}{R}{$M_{NB0}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{10}{R}{$M_{NA0}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NB1}$}{} - \trans[\wireUD{0.5}]{nenh*}{18}{10}{R}{$M_{NA1}$}{} - \trans[\wireUD{0.5}]{penh*}{6}{16}{R}{}{$M_{PA0}$} - \trans[\wireUD{0.5}]{penh*}{18}{16}{R}{}{$M_{PB0}$} - \trans[\wireD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA1}$} - \trans[\wireD{0.5}]{penh*}{18}{22}{R}{}{$M_{PB1}$} + \begin{circuitdiagram}{36}{33} + \pin{2}{2.5}{L}{C0} % pin C0, n-channel + \pin{2}{8.5}{L}{B} % pin B, n-channel + \pin{2}{14.5}{L}{A} % pin A, n-channel + \pin{14}{2.5}{L}{C1} % pin C1, n-channel + \pin{2}{23.5}{L}{A} % pin A, p-channel + \pin{14}{23.5}{L}{B} % pin B, p-channel + \pin{26}{23.5}{L}{C0} % pin C0, p-channel + \pin{26}{29.5}{L}{C1} % pin C1, p-channel + \trans[\wireU{0.5}]{nenh*}{6}{4}{R}{$M_{NC0}$}{} + \trans[\wireUD{0.5}]{nenh*}{6}{10}{R}{$M_{NB}$}{} + \trans[\wireUD{0.5}]{nenh*}{6}{16}{R}{$M_{NA}$}{} + \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NC1}$}{} + \trans[\wireD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA}$} + \trans[\wireD{0.5}]{penh*}{18}{22}{R}{}{$M_{PB}$} + \trans[\wireUD{0.5}]{penh*}{30}{22}{R}{}{$M_{PC0}$} + \trans[\wireD{0.5}]{penh*}{30}{28}{R}{}{$M_{PC1}$} \ground{8}{0.5}{D} % ground below nmos \ground{20}{0.5}{D} % ground below nmos - \power{8}{25.5}{U}{} % power above left pmos - \power{20}{25.5}{U}{} % power above left pmos - \wire{8}{7}{20}{7} % wire short between pmos - \wire{8}{13}{22}{13} % wire before pin Z - \junct{8}{13} + \power{8}{31.5}{U}{} % power above left pmos + \power{20}{31.5}{U}{} % power above middle pmos + \power{32}{31.5}{U}{} % power above right pmos + \wire{8}{24}{8}{31} + \wire{20}{24}{20}{31} + \wire{8}{7}{20}{7} % wire short between nmos + \wire{8}{19}{34}{19} % wire before pin Z + \junct{8}{19} \junct{8}{7} - \junct{20}{13} - \junct{20}{7} - \pin{23}{13}{R}{Z} % pin Z + \junct{20}{19} + \junct{32}{19} + \pin{35}{19}{R}{Z} % pin Z \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI22_truthtable.tex b/Documents/LaTeX/OAI22_truthtable.tex index 0b30ca94..5069f46f 100644 --- a/Documents/LaTeX/OAI22_truthtable.tex +++ b/Documents/LaTeX/OAI22_truthtable.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI22.tex +%% File: StdCellLib/Documents/LaTeX/OAI22_truthtable.tex %% %% Purpose: Truth Table File for OAI22 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,17 +34,16 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} - {\(Z = \lnot ((B1 \lor B0) \land (A1 \lor A0)) \)} - \begin{table}[h] %\caption{\(Z = \lnot ((B1 \lor B0) \land (A1 \lor A0)) \)} + {\(Z = \lnot ((C1 \lor C0) \land B \land A) \)} + \begin{table}[h] %\caption{\(Z = \lnot ((C1 \lor C0) \land B \land A) \)} \begin{center} \begin{tabular}{|c|c|c|c||c|} \hline - B1 & B0 & A1 & A0 & Z \\ \hline\hline - 0 & 0 & X & X & 1 \\ \hline - 1 & X & 1 & X & 0 \\ \hline - 1 & X & X & 1 & 0 \\ \hline - X & 1 & 1 & X & 0 \\ \hline - X & 1 & X & 1 & 0 \\ \hline - X & X & 0 & 0 & 1 \\ \hline + C1 & C0 & B & A & Z \\ \hline\hline + 0 & 0 & X & X & 1 \\ \hline + 1 & X & 1 & 1 & 0 \\ \hline + X & 1 & 1 & 1 & 0 \\ \hline + X & X & 0 & X & 1 \\ \hline + X & X & X & 0 & 1 \\ \hline \end{tabular} \end{center} \end{table} diff --git a/Documents/LaTeX/OAI23_circuit.tex b/Documents/LaTeX/OAI23_circuit.tex new file mode 100644 index 00000000..621f3927 --- /dev/null +++ b/Documents/LaTeX/OAI23_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAI23_circuit.tex +%% +%% Purpose: Circuit File for OAI23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{9}{9}{7} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAI23_manpage.tex b/Documents/LaTeX/OAI23_manpage.tex new file mode 100644 index 00000000..3e37cd29 --- /dev/null +++ b/Documents/LaTeX/OAI23_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAI23_manpage.tex +%% +%% Purpose: Manual Page File for OAI23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAI23} +\paragraph{Cell} +\begin{quote} + \textbf{OAI23} - a 2-3-input OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAI23 (Z, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAI23_circuit.tex} +%\input{OAI23_schematic.tex} + +\paragraph{Truth Table} +%\input{OAI23_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI311_manpage.tex b/Documents/LaTeX/OAI311_manpage.tex deleted file mode 100644 index f6080e4f..00000000 --- a/Documents/LaTeX/OAI311_manpage.tex +++ /dev/null @@ -1,64 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI311.tex -%% -%% Purpose: Manual Page File for OAI311 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI311} -\paragraph{Cell} -\begin{quote} - \textbf{OAI311} - a 3-1-1-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI311(Z, C2, C1, C0, B, A) -\end{quote} - -\paragraph{Description} -\input{OAI311_circuit.tex} -\input{OAI311_schematic.tex} - -\paragraph{Truth Table} -\input{OAI311_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI211 - a 2-1-1-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI311_schematic.tex b/Documents/LaTeX/OAI311_schematic.tex deleted file mode 100644 index 6b12cab8..00000000 --- a/Documents/LaTeX/OAI311_schematic.tex +++ /dev/null @@ -1,79 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI311.tex -%% -%% Purpose: Schematic File for OAI311 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\begin{center} - Schematic (one stage, 3$T_{p}$/3$T_{n}$ stacked, 10T total) - \begin{figure}[h] %\caption{Schematic} - \begin{center} - \begin{circuitdiagram}{36}{39} - \pin{2}{2.5}{L}{C0} % pin C0, n-channel - \pin{2}{8.5}{L}{B} % pin B, n-channel - \pin{2}{14.5}{L}{A} % pin A, n-channel - \pin{14}{2.5}{L}{C1} % pin C1, n-channel - \pin{26}{2.5}{L}{C2} % pin C2, n-channel - \pin{2}{23.5}{L}{A} % pin A, p-channel - \pin{14}{23.5}{L}{B} % pin B, p-channel - \pin{26}{23.5}{L}{C0} % pin C0, p-channel - \pin{26}{29.5}{L}{C1} % pin C1, p-channel - \pin{26}{35.5}{L}{C2} % pin C2, p-channel - \trans[\wireU{0.5}]{nenh*}{6}{4}{R}{$M_{NC0}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{10}{R}{$M_{NB}$}{} - \trans[\wireUD{0.5}]{nenh*}{6}{16}{R}{$M_{NA}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NC1}$}{} - \trans[\wireU{0.5}]{nenh*}{30}{4}{R}{$M_{NC2}$}{} - \trans[\wireD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA}$} - \trans[\wireD{0.5}]{penh*}{18}{22}{R}{}{$M_{PB}$} - \trans[\wireUD{0.5}]{penh*}{30}{22}{R}{}{$M_{PC0}$} - \trans[\wireUD{0.5}]{penh*}{30}{28}{R}{}{$M_{PC1}$} - \trans[\wireD{0.5}]{penh*}{30}{34}{R}{}{$M_{PC2}$} - \ground{8}{0.5}{D} % ground below nmos - \ground{20}{0.5}{D} % ground below nmos - \ground{32}{0.5}{D} % ground below nmos - \power{8}{37.5}{U}{} % power above left pmos - \power{20}{37.5}{U}{} % power above middle pmos - \power{32}{37.5}{U}{} % power above right pmos - \wire{8}{24}{8}{37} - \wire{20}{24}{20}{38} - \wire{8}{7}{32}{7} % wire short between nmos - \wire{8}{19}{34}{19} % wire before pin Z - \junct{8}{19} - \junct{8}{7} - \junct{20}{7} - \junct{20}{19} - \junct{32}{19} - \pin{35}{19}{R}{Z} % pin Z - \end{circuitdiagram} - \end{center} - \end{figure} -\end{center} diff --git a/Documents/LaTeX/OAI311_truthtable.tex b/Documents/LaTeX/OAI311_truthtable.tex deleted file mode 100644 index a4352559..00000000 --- a/Documents/LaTeX/OAI311_truthtable.tex +++ /dev/null @@ -1,51 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI311.tex -%% -%% Purpose: Truth Table File for OAI311 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// - -\begin{center} - {\(Z = \lnot ((C2 \lor C1 \lor C0) \land B \land A) \)} - \begin{table}[h] %\caption{\(Z = \lnot ((C2 \lor C1 \lor C0) \land B \land A) \)} - \begin{center} - \begin{tabular}{|c|c|c|c|c||c|} \hline - C2 & C1 & C0 & B & A & Z \\ \hline\hline - 0 & 0 & 0 & X & X & 1 \\ \hline - 1 & X & X & 1 & 1 & 0 \\ \hline - X & 1 & X & 1 & 1 & 0 \\ \hline - X & X & 1 & 1 & 1 & 0 \\ \hline - X & X & X & 0 & X & 1 \\ \hline - X & X & X & X & 0 & 1 \\ \hline - \end{tabular} - \end{center} - \end{table} -\end{center} diff --git a/Documents/LaTeX/OAI31_circuit.tex b/Documents/LaTeX/OAI31_circuit.tex index 6166acea..77ad587a 100644 --- a/Documents/LaTeX/OAI31_circuit.tex +++ b/Documents/LaTeX/OAI31_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI21.tex +%% File: StdCellLib/Documents/LaTeX/OAI31_circuit.tex %% -%% Purpose: Circuit File for OAI21 +%% Purpose: Circuit File for OAI31 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,17 +34,18 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{8} + \usgate + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{5}{L}{B1} % pin B1 \pin{1}{7}{L}{B2} % pin B2 - \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \pin{17}{3}{R}{Z} % pin Z + \wire{2}{1}{9}{1} % wire from pin A + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI31_manpage.tex b/Documents/LaTeX/OAI31_manpage.tex index fb9b7172..9ebe7ee8 100644 --- a/Documents/LaTeX/OAI31_manpage.tex +++ b/Documents/LaTeX/OAI31_manpage.tex @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI321_manpage.tex b/Documents/LaTeX/OAI321_manpage.tex deleted file mode 100644 index 81682fdf..00000000 --- a/Documents/LaTeX/OAI321_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI321.tex -%% -%% Purpose: Manual Page File for OAI321 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI321} -\paragraph{Cell} -\begin{quote} - \textbf{OAI321} - a 3-2-1-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI321(Z, C2, C1, C0, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{OAI321_circuit.tex} -\input{OAI321_schematic.tex} - -\paragraph{Truth Table} -\input{OAI321_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI221 - a 2-2-1-input OR-AND-Invert gate \\ - OAI331 - a 3-3-1-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI32_circuit.tex b/Documents/LaTeX/OAI32_circuit.tex index ef021e06..30743bf7 100644 --- a/Documents/LaTeX/OAI32_circuit.tex +++ b/Documents/LaTeX/OAI32_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI32.tex +%% File: StdCellLib/Documents/LaTeX/OAI32_circuit.tex %% -%% Purpose: Circuit File for OAI33 +%% Purpose: Circuit File for OAI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,20 +34,21 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{9}{L}{B1} % pin B1 - \pin{1}{11}{L}{B2} % pin B2 - \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{4} % wire between OR and NAND - \wire{9}{9}{9}{8} % wire between OR and NAND - \pin{17}{6}{R}{Z} % pin Z + \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{3}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{9}{5}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI32_manpage.tex b/Documents/LaTeX/OAI32_manpage.tex index 865d1b1f..63b4db8b 100644 --- a/Documents/LaTeX/OAI32_manpage.tex +++ b/Documents/LaTeX/OAI32_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI32.tex +%% File: StdCellLib/Documents/LaTeX/OAI32_manpage.tex %% %% Purpose: Manual Page File for OAI32 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,15 +40,15 @@ \paragraph{Synopsys} \begin{quote} - OAI32(Z, B2, B1, B0, A1, A0) + OAI32(Z, B2, B1, B, A1, A) \end{quote} \paragraph{Description} \input{OAI32_circuit.tex} -\input{OAI32_schematic.tex} +%\input{OAI32_schematic.tex} \paragraph{Truth Table} -\input{OAI32_truthtable.tex} +%\input{OAI32_truthtable.tex} \paragraph{Usage} @@ -57,9 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI22 - a 2-2-input OR-AND-Invert gate \\ - OAI33 - a 3-3-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI331_manpage.tex b/Documents/LaTeX/OAI331_manpage.tex deleted file mode 100644 index 68692831..00000000 --- a/Documents/LaTeX/OAI331_manpage.tex +++ /dev/null @@ -1,65 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI331.tex -%% -%% Purpose: Manual Page File for OAI331 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI331} -\paragraph{Cell} -\begin{quote} - \textbf{OAI331} - a 3-3-1-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI331(Z, C2, C1, C0, B2, B1, B0, A) -\end{quote} - -\paragraph{Description} -\input{OAI331_circuit.tex} -\input{OAI331_schematic.tex} - -\paragraph{Truth Table} -\input{OAI331_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI221 - a 2-2-1-input OR-AND-Invert gate \\ - OAI321 - a 3-2-1-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI332_manpage.tex b/Documents/LaTeX/OAI332_manpage.tex deleted file mode 100644 index fe746fa5..00000000 --- a/Documents/LaTeX/OAI332_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI332.tex -%% -%% Purpose: Manual Page File for OAI332 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI332} -\paragraph{Cell} -\begin{quote} - \textbf{OAI332} - a 3-3-2-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI332(Z, C2, C1, C0, B2, B1, B0, A1, A0) -\end{quote} - -\paragraph{Description} -\input{OAI322_circuit.tex} -\input{OAI322_schematic.tex} - -\paragraph{Truth Table} -\input{OAI322_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI222 - a 2-2-2-input OR-AND-Invert gate \\ - OAI322 - a 3-2-2-input OR-AND-Invert gate \\ - OAI333 - a 3-3-3-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI333_manpage.tex b/Documents/LaTeX/OAI333_manpage.tex deleted file mode 100644 index bfaff9d9..00000000 --- a/Documents/LaTeX/OAI333_manpage.tex +++ /dev/null @@ -1,66 +0,0 @@ -%% ************ LibreSilicon's StdCellLibrary ******************* -%% -%% Organisation: Chipforge -%% Germany / European Union -%% -%% Profile: Chipforge focus on fine System-on-Chip Cores in -%% Verilog HDL Code which are easy understandable and -%% adjustable. For further information see -%% www.chipforge.org -%% there are projects from small cores up to PCBs, too. -%% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI333.tex -%% -%% Purpose: Manual Page File for OAI333 -%% -%% ************ LaTeX with circdia.sty package *************** -%% -%% /////////////////////////////////////////////////////////////////// -%% -%% Copyright (c) 2018 by chipforge -%% All rights reserved. -%% -%% This Standard Cell Library is licensed under the Libre Silicon -%% public license; you can redistribute it and/or modify it under -%% the terms of the Libre Silicon public license as published by -%% the Libre Silicon alliance, either version 1 of the License, or -%% (at your option) any later version. -%% -%% This design is distributed in the hope that it will be useful, -%% but WITHOUT ANY WARRANTY; without even the implied warranty of -%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -%% See the Libre Silicon Public License for more details. -%% -%% /////////////////////////////////////////////////////////////////// -\label{OAI333} -\paragraph{Cell} -\begin{quote} - \textbf{OAI333} - a 3-3-3-input OR-AND-Invert gate -\end{quote} - -\paragraph{Synopsys} -\begin{quote} - OAI333(Z, C2, C1, C0, B2, B1, B0, A2, A1, A0) -\end{quote} - -\paragraph{Description} -\input{OAI333_circuit.tex} -\input{OAI333_schematic.tex} - -\paragraph{Truth Table} -\input{OAI333_truthtable.tex} - -\paragraph{Usage} - -\paragraph{Fan-in / Fan-out} - -\paragraph{Layout} - -\paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI222 - a 2-2-2-input OR-AND-Invert gate \\ - OAI322 - a 3-2-2-input OR-AND-Invert gate \\ - OAI332 - a 3-3-2-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI33_circuit.tex b/Documents/LaTeX/OAI33_circuit.tex index bf53a89c..c48ec4be 100644 --- a/Documents/LaTeX/OAI33_circuit.tex +++ b/Documents/LaTeX/OAI33_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI33.tex +%% File: StdCellLib/Documents/LaTeX/OAI23_circuit.tex %% -%% Purpose: Circuit File for OAI33 +%% Purpose: Circuit File for OAI23 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,21 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{12} - \pin{1}{1}{L}{A0} % pin A0 - \pin{1}{3}{L}{A1} % pin A1 - \pin{1}{5}{L}{A2} % pin A2 - \pin{1}{7}{L}{B0} % pin B0 - \pin{1}{9}{L}{B1} % pin B1 - \pin{1}{11}{L}{B2} % pin B2 - \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{4} % wire between OR and NAND - \wire{9}{9}{9}{8} % wire between OR and NAND - \pin{17}{6}{R}{Z} % pin Z + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{9}{9}{7} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI33_manpage.tex b/Documents/LaTeX/OAI33_manpage.tex index 38934d0c..7adc22e7 100644 --- a/Documents/LaTeX/OAI33_manpage.tex +++ b/Documents/LaTeX/OAI33_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI33.tex +%% File: StdCellLib/Documents/LaTeX/OAI33_manpage.tex %% %% Purpose: Manual Page File for OAI33 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,15 +40,15 @@ \paragraph{Synopsys} \begin{quote} - OAI33(Z, B2, B1, B0, A2, A1, A0) + OAI33 (Z, B2, B1, B, A2, A1, A) \end{quote} \paragraph{Description} \input{OAI33_circuit.tex} -\input{OAI33_schematic.tex} +%\input{OAI33_schematic.tex} \paragraph{Truth Table} -\input{OAI33_truthtable.tex} +%\input{OAI33_truthtable.tex} \paragraph{Usage} @@ -57,9 +57,3 @@ \paragraph{Layout} \paragraph{Files} - -\paragraph{See also} -\begin{quote} - OAI22 - a 2-2-input OR-AND-Invert gate \\ - OAI32 - a 3-2-input OR-AND-Invert gate -\end{quote} diff --git a/Documents/LaTeX/OAI211_circuit.tex b/Documents/LaTeX/OAI41_circuit.tex similarity index 70% rename from Documents/LaTeX/OAI211_circuit.tex rename to Documents/LaTeX/OAI41_circuit.tex index e93ab170..8ab5fe8c 100644 --- a/Documents/LaTeX/OAI211_circuit.tex +++ b/Documents/LaTeX/OAI41_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI211.tex +%% File: StdCellLib/Documents/LaTeX/OAI41_circuit.tex %% -%% Purpose: Circuit File for OAI211 +%% Purpose: Circuit File for OAI41 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,19 +34,20 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{10} + \usgate + \gate[\inputs{4}]{or}{5}{6}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C0} % pin C0 - \pin{1}{9}{L}{C1} % pin C2 - \gate[\inputs{2}]{or}{5}{7}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{3}{R}{}{} % NAND gate -> right - \wire{9}{5}{9}{7} % wire between OR and NAND - \wire{2}{1}{9}{1} % wire between pin and NAND - \wire{2}{3}{9}{3} % wire between pin and NAND - \pin{17}{3}{R}{Z} % pin Z + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{B3} % pin B3 + \wire{9}{5}{9}{6} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire from pin A + \pin{17}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AO3111_manpage.tex b/Documents/LaTeX/OAI41_manpage.tex similarity index 78% rename from Documents/LaTeX/AO3111_manpage.tex rename to Documents/LaTeX/OAI41_manpage.tex index faa8bcd6..56ffd925 100644 --- a/Documents/LaTeX/AO3111_manpage.tex +++ b/Documents/LaTeX/OAI41_manpage.tex @@ -9,9 +9,9 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_AO3111.tex +%% File: StdCellLib/Documents/LaTeX/OAI41_manpage.tex %% -%% Purpose: Manual Page File for AO3111 +%% Purpose: Auto-generated Manual Page for OAI41 %% %% ************ LaTeX with circdia.sty package *************** %% @@ -32,23 +32,19 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{AO3111} -\paragraph{Cell} -\begin{quote} - \textbf{AO3111} - a 3-1-1-1-input AND-OR gate -\end{quote} +\subsection{OAI41 - a 4-1-input OR-AND-Invert gate} \label{logical:OAI41} \paragraph{Synopsys} \begin{quote} - AO3111(Z, D2, D1, D0, C, B, A) + OAI41 (Z B3 B2 B1 B A) \end{quote} \paragraph{Description} -\input{AO3111_circuit.tex} -%\input{AO3111_schematic.tex} +\input{OAI41_circuit.tex} +%\input{OAI41_schematic.tex} \paragraph{Truth Table} -\input{AO3111_truthtable.tex} +%\input{OAI41_truthtable.tex} \paragraph{Usage} @@ -58,7 +54,4 @@ \paragraph{Files} -\paragraph{See also} -\begin{quote} - AO2111 - a 2-1-1-1-input AND-OR gate -\end{quote} +\clearpage diff --git a/Documents/LaTeX/OAI43_circuit.tex b/Documents/LaTeX/OAI43_circuit.tex new file mode 100644 index 00000000..9c5328c0 --- /dev/null +++ b/Documents/LaTeX/OAI43_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAI23_circuit.tex +%% +%% Purpose: Circuit File for OAI23 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{2}{1}{9}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin A2 + \wire{9}{7}{9}{10} % wire between OR and NAND + \pin{17}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAI43_manpage.tex b/Documents/LaTeX/OAI43_manpage.tex new file mode 100644 index 00000000..51c37d86 --- /dev/null +++ b/Documents/LaTeX/OAI43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAI43_manpage.tex +%% +%% Purpose: Manual Page File for OAI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAI43} +\paragraph{Cell} +\begin{quote} + \textbf{OAI43} - a 4-3-input OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAI43 (Z, D3, D2, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAI43_circuit.tex} +%\input{OAI43_schematic.tex} + +\paragraph{Truth Table} +%\input{OAI43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO211_circuit.tex b/Documents/LaTeX/OAO211_circuit.tex new file mode 100644 index 00000000..ae7cb5d7 --- /dev/null +++ b/Documents/LaTeX/OAO211_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO211_circuit.tex +%% +%% Purpose: Circuit File for OAO211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{10} + \usgate + \gate[\inputs{2}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{9}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO211_manpage.tex b/Documents/LaTeX/OAO211_manpage.tex new file mode 100644 index 00000000..4a97937e --- /dev/null +++ b/Documents/LaTeX/OAO211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO211_manpage.tex +%% +%% Purpose: Manual Page File for OAO211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO211} +\paragraph{Cell} +\begin{quote} + \textbf{OAO211} - a 2-1-1-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO211(Z, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAO211_circuit.tex} +%\input{OAO211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO212_circuit.tex b/Documents/LaTeX/OAO212_circuit.tex new file mode 100644 index 00000000..84a09c74 --- /dev/null +++ b/Documents/LaTeX/OAO212_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO212_circuit.tex +%% +%% Purpose: Circuit File for OAO212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{16}{7}{16}{5} % wire between AND and NOR + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO212_manpage.tex b/Documents/LaTeX/OAO212_manpage.tex new file mode 100644 index 00000000..bf3f7fd0 --- /dev/null +++ b/Documents/LaTeX/OAO212_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO212_manpage.tex +%% +%% Purpose: Manual Page File for OAO212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO212} +\paragraph{Cell} +\begin{quote} + \textbf{OAO212} - a 2-1-2-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO212(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAO212_circuit.tex} +%\input{OAO212_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO221_circuit.tex b/Documents/LaTeX/OAO221_circuit.tex new file mode 100644 index 00000000..294a4040 --- /dev/null +++ b/Documents/LaTeX/OAO221_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO221_circuit.tex +%% +%% Purpose: Circuit File for OAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{9}{7}{9}{9} % wire between OR and AND + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO221_manpage.tex b/Documents/LaTeX/OAO221_manpage.tex new file mode 100644 index 00000000..8f030745 --- /dev/null +++ b/Documents/LaTeX/OAO221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO221_manpage.tex +%% +%% Purpose: Manual Page File for OAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO221} +\paragraph{Cell} +\begin{quote} + \textbf{OAO221} - a 2-2-1-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAO221_circuit.tex} +%\input{OAO221_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO222_circuit.tex b/Documents/LaTeX/OAO222_circuit.tex new file mode 100644 index 00000000..cd4489c2 --- /dev/null +++ b/Documents/LaTeX/OAO222_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO222_circuit.tex +%% +%% Purpose: Circuit File for OAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{12} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{9}{9}{9}{11} % wire between OR and AND + \wire{16}{5}{16}{7} % wire between AND and NOR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin B + \wire{2}{7}{9}{7} % wire from pin B1 + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO222_manpage.tex b/Documents/LaTeX/OAO222_manpage.tex new file mode 100644 index 00000000..e4247ab7 --- /dev/null +++ b/Documents/LaTeX/OAO222_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO222_manpage.tex +%% +%% Purpose: Manual Page File for OAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO222} +\paragraph{Cell} +\begin{quote} + \textbf{OAO222} - a 2-2-2-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAO222_circuit.tex} +%\input{OAO222_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO232_circuit.tex b/Documents/LaTeX/OAO232_circuit.tex new file mode 100644 index 00000000..53b06e3c --- /dev/null +++ b/Documents/LaTeX/OAO232_circuit.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO232_circuit.tex +%% +%% Purpose: Circuit File for OAO232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{16}{3} % wire pin A1 + \pin{1}{5}{L}{B} % pin B + \wire{2}{5}{9}{5} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{2}{9}{9}{9} % wire pin B2 + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{5}{16}{8} % wire between AND and NOR + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO232_manpage.tex b/Documents/LaTeX/OAO232_manpage.tex new file mode 100644 index 00000000..83b498ba --- /dev/null +++ b/Documents/LaTeX/OAO232_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO232_manpage.tex +%% +%% Purpose: Manual Page File for OAO232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO232} +\paragraph{Cell} +\begin{quote} + \textbf{OAO232} - a 2-3-2-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO232(Z, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAO232_circuit.tex} +%\input{OAO232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAO311_circuit.tex b/Documents/LaTeX/OAO311_circuit.tex new file mode 100644 index 00000000..34db03d3 --- /dev/null +++ b/Documents/LaTeX/OAO311_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO311_circuit.tex +%% +%% Purpose: Circuit File for OAO311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{10} + \usgate + \gate[\inputs{3}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \gate{not}{26}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \pin{30}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAO311_manpage.tex b/Documents/LaTeX/OAO311_manpage.tex new file mode 100644 index 00000000..fe734faf --- /dev/null +++ b/Documents/LaTeX/OAO311_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAO311_manpage.tex +%% +%% Purpose: Manual Page File for OAO311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAO311} +\paragraph{Cell} +\begin{quote} + \textbf{OAO311} - a 3-1-1-input OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAO311(Z, C2, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAO311_circuit.tex} +%\input{OAO311_schematic.tex} + +\paragraph{Truth Table} +%\input{OAO311_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOA2111_circuit.tex b/Documents/LaTeX/OAOA2111_circuit.tex new file mode 100644 index 00000000..2466d6b0 --- /dev/null +++ b/Documents/LaTeX/OAOA2111_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA2111_circuit.tex +%% +%% Purpose: Circuit File for OAOA2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOA2111_manpage.tex b/Documents/LaTeX/OAOA2111_manpage.tex new file mode 100644 index 00000000..30480b4d --- /dev/null +++ b/Documents/LaTeX/OAOA2111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA2111_manpage.tex +%% +%% Purpose: Manual Page File for OAOA2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOA2111} +\paragraph{Cell} +\begin{quote} + \textbf{OAOA2111} - a 2-1-1-1-input OR-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOA2111(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOA2111_circuit.tex} +%\input{OAOA2111_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOA2111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOA2211_circuit.tex b/Documents/LaTeX/OAOA2211_circuit.tex new file mode 100644 index 00000000..0cdf32dd --- /dev/null +++ b/Documents/LaTeX/OAOA2211_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA2211_circuit.tex +%% +%% Purpose: Circuit File for OAOA2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{13}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between AND and OR + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOA2211_manpage.tex b/Documents/LaTeX/OAOA2211_manpage.tex new file mode 100644 index 00000000..32e17f15 --- /dev/null +++ b/Documents/LaTeX/OAOA2211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA2211_manpage.tex +%% +%% Purpose: Manual Page File for OAOA2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOA2211} +\paragraph{Cell} +\begin{quote} + \textbf{OAOA2211} - a 2-2-1-1-input OR-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOA2211(Z, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOA2211_circuit.tex} +%\input{OAOA2211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOA2211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOA3211_circuit.tex b/Documents/LaTeX/OAOA3211_circuit.tex new file mode 100644 index 00000000..2e2ac8fb --- /dev/null +++ b/Documents/LaTeX/OAOA3211_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA3211_circuit.tex +%% +%% Purpose: Circuit File for OAOA3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{38}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND + \gate{not}{33}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \pin{1}{13}{L}{D2} % pin D2 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between AND and OR + \pin{37}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOA3211_manpage.tex b/Documents/LaTeX/OAOA3211_manpage.tex new file mode 100644 index 00000000..4bd1d5ac --- /dev/null +++ b/Documents/LaTeX/OAOA3211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOA3211_manpage.tex +%% +%% Purpose: Manual Page File for OAOA3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOA3211} +\paragraph{Cell} +\begin{quote} + \textbf{OAOA3211} - a 3-2-1-1-input OR-AND-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOA3211(Z, D2, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOA3211_circuit.tex} +%\input{OAOA3211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOA3211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OA2111_circuit.tex b/Documents/LaTeX/OAOAI2111_circuit.tex similarity index 68% rename from Documents/LaTeX/OA2111_circuit.tex rename to Documents/LaTeX/OAOAI2111_circuit.tex index f87cc64d..1f848a1f 100644 --- a/Documents/LaTeX/OA2111_circuit.tex +++ b/Documents/LaTeX/OAOAI2111_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OA2111.tex +%% File: StdCellLib/Documents/LaTeX/OAOAI2111_circuit.tex %% -%% Purpose: Circuit File for OA2111 +%% Purpose: Circuit File for OAOAI2111 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} - \begin{circuitdiagram}{24}{12} + \begin{circuitdiagram}{32}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A \pin{1}{3}{L}{B} % pin B \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D0} % pin D0 + \pin{1}{7}{L}{D} % pin D \pin{1}{11}{L}{D1} % pin D1 - \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{4}]{nand}{12}{4}{R}{}{} % NAND gate -> right - \gate{not}{19}{4}{R}{}{} % NOT gate -> right - \wire{2}{1}{9}{1} % wire from pin A - \wire{2}{3}{9}{3} % wire from pin B - \wire{2}{5}{9}{5} % wire from pin C - \wire{9}{9}{9}{7} % wire between OR and NAND - \pin{23}{4}{R}{Z} % pin Z + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \pin{31}{3}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAOAI2111_manpage.tex b/Documents/LaTeX/OAOAI2111_manpage.tex new file mode 100644 index 00000000..15032ff7 --- /dev/null +++ b/Documents/LaTeX/OAOAI2111_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOAI2111_manpage.tex +%% +%% Purpose: Manual Page File for OAOAI2111 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOAI2111} +\paragraph{Cell} +\begin{quote} + \textbf{OAOAI2111} - a 2-1-1-1-input OR-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOAI2111(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOAI2111_circuit.tex} +%\input{OAOAI2111_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOAI2111_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOAI2211_circuit.tex b/Documents/LaTeX/OAOAI2211_circuit.tex new file mode 100644 index 00000000..e87f4fa4 --- /dev/null +++ b/Documents/LaTeX/OAOAI2211_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOAI2211_circuit.tex +%% +%% Purpose: Circuit File for OAOAI2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{32}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{13}{L}{D1} % pin D1 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between OR and AND + \pin{31}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOAI2211_manpage.tex b/Documents/LaTeX/OAOAI2211_manpage.tex new file mode 100644 index 00000000..04994943 --- /dev/null +++ b/Documents/LaTeX/OAOAI2211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOAI2211_manpage.tex +%% +%% Purpose: Manual Page File for OAOAI2211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOAI2211} +\paragraph{Cell} +\begin{quote} + \textbf{OAOAI2211} - a 2-2-1-1-input OR-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOAI2211(Z, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOAI2211_circuit.tex} +%\input{OAOAI2211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOAI2211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOAI3211_circuit.tex b/Documents/LaTeX/OAOAI3211_circuit.tex new file mode 100644 index 00000000..c627660b --- /dev/null +++ b/Documents/LaTeX/OAOAI3211_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOAI3211_circuit.tex +%% +%% Purpose: Circuit File for OAOAI3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{32}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{2}]{or}{19}{5}{R}{}{} % OR + \gate[\inputs{2}]{nand}{26}{3}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \pin{1}{13}{L}{D2} % pin D2 + \wire{2}{1}{23}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{2}{7}{9}{7} % wire from pin C1 + \wire{9}{9}{9}{11} % wire between OR and AND + \pin{31}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOAI3211_manpage.tex b/Documents/LaTeX/OAOAI3211_manpage.tex new file mode 100644 index 00000000..db64cd1f --- /dev/null +++ b/Documents/LaTeX/OAOAI3211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOAI3211_manpage.tex +%% +%% Purpose: Manual Page File for OAOAI3211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOAI3211} +\paragraph{Cell} +\begin{quote} + \textbf{OAOAI3211} - a 3-2-1-1-input OR-AND-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOAI3211(Z, D1, D, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOAI3211_circuit.tex} +%\input{OAOAI3211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOAI3211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI211_circuit.tex b/Documents/LaTeX/OAOI211_circuit.tex new file mode 100644 index 00000000..64eea15a --- /dev/null +++ b/Documents/LaTeX/OAOI211_circuit.tex @@ -0,0 +1,54 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI211_circuit.tex +%% +%% Purpose: Circuit File for OAOI211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{10} + \usgate + \gate[\inputs{2}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{9}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin C + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI211_manpage.tex b/Documents/LaTeX/OAOI211_manpage.tex new file mode 100644 index 00000000..6ac7e102 --- /dev/null +++ b/Documents/LaTeX/OAOI211_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI211_manpage.tex +%% +%% Purpose: Manual Page File for OAOI211 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI211} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI211} - a 2-1-1-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI211(Z, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOI211_circuit.tex} +%\input{OAOI211_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI211_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI212_circuit.tex b/Documents/LaTeX/OAOI212_circuit.tex new file mode 100644 index 00000000..7aeaa9e8 --- /dev/null +++ b/Documents/LaTeX/OAOI212_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI212_circuit.tex +%% +%% Purpose: Circuit File for OAOI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{D} % pin D + \pin{1}{11}{L}{D1} % pin D1 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin C + \wire{16}{7}{16}{5} % wire between AND and NOR + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI212_manpage.tex b/Documents/LaTeX/OAOI212_manpage.tex new file mode 100644 index 00000000..f42f5c7d --- /dev/null +++ b/Documents/LaTeX/OAOI212_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI212_manpage.tex +%% +%% Purpose: Manual Page File for OAOI212 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI212} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI212} - a 2-1-2-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI212(Z, D1, D, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOI212_circuit.tex} +%\input{OAOI212_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI212_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI221_circuit.tex b/Documents/LaTeX/OAOI221_circuit.tex new file mode 100644 index 00000000..c25e64fb --- /dev/null +++ b/Documents/LaTeX/OAOI221_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI221_circuit.tex +%% +%% Purpose: Circuit File for OAOI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \wire{9}{7}{9}{9} % wire between AND and OR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin B + \wire{2}{5}{9}{5} % wire from pin B + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI221_manpage.tex b/Documents/LaTeX/OAOI221_manpage.tex new file mode 100644 index 00000000..884f94dc --- /dev/null +++ b/Documents/LaTeX/OAOI221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI221_manpage.tex +%% +%% Purpose: Manual Page File for OAOI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI221} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI221} - a 2-2-1-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOI221_circuit.tex} +%\input{OAOI221_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI222_circuit.tex b/Documents/LaTeX/OAOI222_circuit.tex new file mode 100644 index 00000000..7f12034b --- /dev/null +++ b/Documents/LaTeX/OAOI222_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI222_circuit.tex +%% +%% Purpose: Circuit File for OAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{12} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{and}{12}{7}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{9}{9}{9}{11} % wire between OR and AND + \wire{16}{5}{16}{7} % wire between AND and NOR + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{16}{3} % wire from pin A1 + \wire{2}{5}{9}{5} % wire from pin B + \wire{2}{7}{9}{7} % wire from pin B1 + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI222_manpage.tex b/Documents/LaTeX/OAOI222_manpage.tex new file mode 100644 index 00000000..ebdba62b --- /dev/null +++ b/Documents/LaTeX/OAOI222_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI222_manpage.tex +%% +%% Purpose: Manual Page File for OAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI222} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI222} - a 2-2-2-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI222(Y, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAOI222_circuit.tex} +%\input{OAOI222_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI232_circuit.tex b/Documents/LaTeX/OAOI232_circuit.tex new file mode 100644 index 00000000..28e5b6f7 --- /dev/null +++ b/Documents/LaTeX/OAOI232_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI232_circuit.tex +%% +%% Purpose: Circuit File for OAOI232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{16} + \usgate + \gate[\inputs{2}]{or}{5}{13}{R}{}{} % OR + \gate[\inputs{4}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{3}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \wire{2}{1}{16}{1} % wire pin A + \pin{1}{3}{L}{A1} % pin A1 + \wire{2}{3}{16}{3} % wire pin A1 + \pin{1}{5}{L}{B} % pin B + \wire{2}{5}{9}{5} % wire pin B + \pin{1}{7}{L}{B1} % pin B1 + \wire{2}{7}{9}{7} % wire pin B1 + \pin{1}{9}{L}{B2} % pin B2 + \wire{2}{9}{9}{9} % wire pin B2 + \pin{1}{11}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \wire{9}{11}{9}{13} % wire between OR and AND + \wire{16}{5}{16}{8} % wire between AND and NOR + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI232_manpage.tex b/Documents/LaTeX/OAOI232_manpage.tex new file mode 100644 index 00000000..80aa508e --- /dev/null +++ b/Documents/LaTeX/OAOI232_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI232_manpage.tex +%% +%% Purpose: Manual Page File for OAOI232 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI232} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI232} - a 2-3-2-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI232(Y, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OAOI232_circuit.tex} +%\input{OAOI232_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI232_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAOI311_circuit.tex b/Documents/LaTeX/OAOI311_circuit.tex new file mode 100644 index 00000000..ef92d4bb --- /dev/null +++ b/Documents/LaTeX/OAOI311_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI311_circuit.tex +%% +%% Purpose: Circuit File for OAOI311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{10} + \usgate + \gate[\inputs{3}]{or}{5}{7}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{5}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{3}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{C} % pin C + \pin{1}{7}{L}{C1} % pin C1 + \pin{1}{9}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire from pin A + \wire{2}{3}{9}{3} % wire from pin C + \pin{24}{3}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OAOI311_manpage.tex b/Documents/LaTeX/OAOI311_manpage.tex new file mode 100644 index 00000000..412052ac --- /dev/null +++ b/Documents/LaTeX/OAOI311_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OAOI311_manpage.tex +%% +%% Purpose: Manual Page File for OAOI311 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OAOI311} +\paragraph{Cell} +\begin{quote} + \textbf{OAOI311} - a 3-1-1-input OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OAOI311(Z, C2, C1, C, B, A) +\end{quote} + +\paragraph{Description} +\input{OAOI311_circuit.tex} +%\input{OAOI311_schematic.tex} + +\paragraph{Truth Table} +%\input{OAOI311_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA221_circuit.tex b/Documents/LaTeX/OOA221_circuit.tex new file mode 100644 index 00000000..a2d7f854 --- /dev/null +++ b/Documents/LaTeX/OOA221_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA221_circuit.tex +%% +%% Purpose: Circuit File for OOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire before NAND + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA221_manpage.tex b/Documents/LaTeX/OOA221_manpage.tex new file mode 100644 index 00000000..de0f5aa3 --- /dev/null +++ b/Documents/LaTeX/OOA221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA221_manpage.tex +%% +%% Purpose: Manual Page File for OOA221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA221} +\paragraph{Cell} +\begin{quote} + \textbf{OOA221} - a 2-2-1-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOA221_circuit.tex} +%\input{OOA221_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA22_circuit.tex b/Documents/LaTeX/OOA22_circuit.tex new file mode 100644 index 00000000..58b49625 --- /dev/null +++ b/Documents/LaTeX/OOA22_circuit.tex @@ -0,0 +1,55 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA22_circuit.tex +%% +%% Purpose: Circuit File for OOA22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA22_manpage.tex b/Documents/LaTeX/OOA22_manpage.tex new file mode 100644 index 00000000..5ad75bc5 --- /dev/null +++ b/Documents/LaTeX/OOA22_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA22_manpage.tex +%% +%% Purpose: Manual Page File OOA22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA22} +\paragraph{Cell} +\begin{quote} + \textbf{OOA22} - a 2-2-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA22(Z, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA22_circuit.tex} +%\input{OOA22_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOA321_circuit.tex b/Documents/LaTeX/OOA321_circuit.tex new file mode 100644 index 00000000..2af07b19 --- /dev/null +++ b/Documents/LaTeX/OOA321_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA321_circuit.tex +%% +%% Purpose: Circuit File for OOA321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire before NAND + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA321_manpage.tex b/Documents/LaTeX/OOA321_manpage.tex new file mode 100644 index 00000000..c49dbe03 --- /dev/null +++ b/Documents/LaTeX/OOA321_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA321_manpage.tex +%% +%% Purpose: Manual Page File for OOA321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA321} +\paragraph{Cell} +\begin{quote} + \textbf{OOA321} - a 3-2-1-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOA321_circuit.tex} +%\input{OOA321_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA32_circuit.tex b/Documents/LaTeX/OOA32_circuit.tex new file mode 100644 index 00000000..be3dd326 --- /dev/null +++ b/Documents/LaTeX/OOA32_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA32_circuit.tex +%% +%% Purpose: Circuit File for OOA32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A0 + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B0 + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA32_manpage.tex b/Documents/LaTeX/OOA32_manpage.tex new file mode 100644 index 00000000..9127f420 --- /dev/null +++ b/Documents/LaTeX/OOA32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA32_manpage.tex +%% +%% Purpose: Manual Page File for OOA32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA32} +\paragraph{Cell} +\begin{quote} + \textbf{OOA32} - a 3-2-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA32_circuit.tex} +%\input{OOA32_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA331_circuit.tex b/Documents/LaTeX/OOA331_circuit.tex new file mode 100644 index 00000000..b273bdbc --- /dev/null +++ b/Documents/LaTeX/OOA331_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA331_circuit.tex +%% +%% Purpose: Circuit File for OOA331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND + \gate{not}{19}{5}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND + \wire{2}{1}{9}{1} % wire before NAND + \pin{23}{5}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA331_manpage.tex b/Documents/LaTeX/OOA331_manpage.tex new file mode 100644 index 00000000..d57da802 --- /dev/null +++ b/Documents/LaTeX/OOA331_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA331_manpage.tex +%% +%% Purpose: Manual Page File for OOA331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA331} +\paragraph{Cell} +\begin{quote} + \textbf{OOA331} - a 3-3-1-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOA331_circuit.tex} +%\input{OOA331_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA33_circuit.tex b/Documents/LaTeX/OOA33_circuit.tex new file mode 100644 index 00000000..1fcc111b --- /dev/null +++ b/Documents/LaTeX/OOA33_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA33_circuit.tex +%% +%% Purpose: Circuit File for OOA33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{12} + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A0 + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B0 + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA33_manpage.tex b/Documents/LaTeX/OOA33_manpage.tex new file mode 100644 index 00000000..31002be9 --- /dev/null +++ b/Documents/LaTeX/OOA33_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA33_manpage.tex +%% +%% Purpose: Manual Page File for OOA33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA33} +\paragraph{Cell} +\begin{quote} + \textbf{OOA33} - a 3-3-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA33(Z, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA33_circuit.tex} +%\input{OOA33_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA42_circuit.tex b/Documents/LaTeX/OOA42_circuit.tex new file mode 100644 index 00000000..caaeb211 --- /dev/null +++ b/Documents/LaTeX/OOA42_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA42_circuit.tex +%% +%% Purpose: Circuit File for OOA42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{10}{9}{8} % wire between OR and NAND + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA42_manpage.tex b/Documents/LaTeX/OOA42_manpage.tex new file mode 100644 index 00000000..22e6a7ae --- /dev/null +++ b/Documents/LaTeX/OOA42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA42_manpage.tex +%% +%% Purpose: Manual Page File for OOA42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA42} +\paragraph{Cell} +\begin{quote} + \textbf{OOA42} - a 4-2-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA42(Z, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA42_circuit.tex} +%\input{OOA42_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA43_circuit.tex b/Documents/LaTeX/OOA43_circuit.tex new file mode 100644 index 00000000..e372d9b9 --- /dev/null +++ b/Documents/LaTeX/OOA43_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA43_circuit.tex +%% +%% Purpose: Circuit File for OOA43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \gate{not}{19}{6}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{10}{9}{8} % wire between OR and NAND + \pin{23}{6}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA43_manpage.tex b/Documents/LaTeX/OOA43_manpage.tex new file mode 100644 index 00000000..706d12b3 --- /dev/null +++ b/Documents/LaTeX/OOA43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA43_manpage.tex +%% +%% Purpose: Manual Page File for OOA43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA43} +\paragraph{Cell} +\begin{quote} + \textbf{OOA43} - a 4-3-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA43(Z, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA43_circuit.tex} +%\input{OOA43_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOA44_circuit.tex b/Documents/LaTeX/OOA44_circuit.tex new file mode 100644 index 00000000..fb6fc8e9 --- /dev/null +++ b/Documents/LaTeX/OOA44_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA44_circuit.tex +%% +%% Purpose: Circuit File for OOA44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{16} + \usgate + \gate[\inputs{4}]{or}{5}{12}{R}{}{} % OR + \gate[\inputs{4}]{or}{5}{4}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{8}{R}{}{} % NAND + \gate{not}{19}{8}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{1}{9}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \pin{1}{15}{L}{B3} % pin B3 + \wire{9}{4}{9}{6} % wire between OR and NAND + \wire{9}{12}{9}{10} % wire between OR and NAND + \pin{23}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOA44_manpage.tex b/Documents/LaTeX/OOA44_manpage.tex new file mode 100644 index 00000000..3888fc13 --- /dev/null +++ b/Documents/LaTeX/OOA44_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOA44_manpage.tex +%% +%% Purpose: Manual Page File for OOA44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOA44} +\paragraph{Cell} +\begin{quote} + \textbf{OOA44} - a 4-4-input OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOA44(Z, B3, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOA44_circuit.tex} +%\input{OOA44_schematic.tex} + +\paragraph{Truth Table} +%\input{OOA44_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOAAO222_circuit.tex b/Documents/LaTeX/OOAAO222_circuit.tex new file mode 100644 index 00000000..f77ac023 --- /dev/null +++ b/Documents/LaTeX/OOAAO222_circuit.tex @@ -0,0 +1,63 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAAO222_circuit.tex +%% +%% Purpose: Circuit File for OOAAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{12}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{8}{R}{}{} % NOR + \gate{not}{26}{8}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{9}{14}{9}{15} % wire between OR and AND + \wire{9}{9}{9}{10} % wire between OR and AND + \wire{16}{3}{16}{6} % wire between AND and NOR + \wire{16}{10}{16}{12} % wire between AND and NOR + \pin{30}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAAO222_manpage.tex b/Documents/LaTeX/OOAAO222_manpage.tex new file mode 100644 index 00000000..ff3e4f9f --- /dev/null +++ b/Documents/LaTeX/OOAAO222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAAO222_manpage.tex +%% +%% Purpose: Manual Page File for OOAAO222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAAO222} +\paragraph{Cell} +\begin{quote} + \textbf{OOAAO222} - a 2-2-2-input OR-OR-AND-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAAO222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAAO222_circuit.tex} +%\input{OOAAO222_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAAO222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAAOI222_circuit.tex b/Documents/LaTeX/OOAAOI222_circuit.tex new file mode 100644 index 00000000..8e075587 --- /dev/null +++ b/Documents/LaTeX/OOAAOI222_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAAOI222_circuit.tex +%% +%% Purpose: Circuit File for OOAAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{18} + \usgate + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{12}{R}{}{} % AND + \gate[\inputs{2}]{and}{12}{3}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{8}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{2}{1}{9}{1} % wire pin A + \wire{2}{5}{9}{5} % wire pin A1 + \wire{9}{14}{9}{15} % wire between OR and AND + \wire{9}{9}{9}{10} % wire between OR and AND + \wire{16}{3}{16}{6} % wire between AND and NOR + \wire{16}{10}{16}{12} % wire between AND and NOR + \pin{24}{8}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAAOI222_manpage.tex b/Documents/LaTeX/OOAAOI222_manpage.tex new file mode 100644 index 00000000..e6ab4d6e --- /dev/null +++ b/Documents/LaTeX/OOAAOI222_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAAOI222_manpage.tex +%% +%% Purpose: Manual Page File for OOAAOI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAAOI222} +\paragraph{Cell} +\begin{quote} + \textbf{OOAAOI222} - a 2-2-2-input OR-OR-AND-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAAOI222(Y, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAAOI222_circuit.tex} +%\input{OOAAOI222_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAAOI222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OAI221_circuit.tex b/Documents/LaTeX/OOAI221_circuit.tex similarity index 71% rename from Documents/LaTeX/OAI221_circuit.tex rename to Documents/LaTeX/OOAI221_circuit.tex index 188fb41a..a54e2481 100644 --- a/Documents/LaTeX/OAI221_circuit.tex +++ b/Documents/LaTeX/OOAI221_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI221.tex +%% File: StdCellLib/Documents/LaTeX/OOAI221_circuit.tex %% -%% Purpose: Circuit File for OAI221 +%% Purpose: Circuit File for OOAI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,21 +34,22 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \pin{1}{9}{L}{C0} % pin C0 + \pin{1}{9}{L}{C} % pin C \pin{1}{13}{L}{C1} % pin C1 - \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND gate -> right - \wire{9}{1}{9}{3} % wire between OR and NAND - \wire{9}{11}{9}{7} % wire between OR and NAND + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND \wire{2}{1}{9}{1} % wire before NAND - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OOAI221_manpage.tex b/Documents/LaTeX/OOAI221_manpage.tex new file mode 100644 index 00000000..473afd1b --- /dev/null +++ b/Documents/LaTeX/OOAI221_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI221_manpage.tex +%% +%% Purpose: Manual Page File for OOAI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI221} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI221} - a 2-2-1-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAI221_circuit.tex} +\input{OOAI221_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI221_schematic.tex b/Documents/LaTeX/OOAI221_schematic.tex similarity index 94% rename from Documents/LaTeX/OAI221_schematic.tex rename to Documents/LaTeX/OOAI221_schematic.tex index 101491a5..9ac49a01 100644 --- a/Documents/LaTeX/OAI221_schematic.tex +++ b/Documents/LaTeX/OOAI221_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI221.tex +%% File: StdCellLib/Documents/LaTeX/OOAI221_schematic.tex %% -%% Purpose: Schematic File for OAI221 +%% Purpose: Schematic File for OOAI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI221_truthtable.tex b/Documents/LaTeX/OOAI221_truthtable.tex similarity index 91% rename from Documents/LaTeX/OAI221_truthtable.tex rename to Documents/LaTeX/OOAI221_truthtable.tex index 58f6efc3..f3ba4741 100644 --- a/Documents/LaTeX/OAI221_truthtable.tex +++ b/Documents/LaTeX/OOAI221_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI221.tex +%% File: StdCellLib/Documents/LaTeX/OOAI221_truthtable.tex %% -%% Purpose: Truth Table File for OAI221 +%% Purpose: Truth Table File for OOAI221 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI222_circuit.tex b/Documents/LaTeX/OOAI22_circuit.tex similarity index 74% rename from Documents/LaTeX/OAI222_circuit.tex rename to Documents/LaTeX/OOAI22_circuit.tex index f175d02c..6511b67a 100644 --- a/Documents/LaTeX/OAI222_circuit.tex +++ b/Documents/LaTeX/OOAI22_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI222.tex +%% File: StdCellLib/Documents/LaTeX/OOAI22_circuit.tex %% -%% Purpose: Circuit File for OAI222 +%% Purpose: Circuit File for OOAI22 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,20 +36,18 @@ Circuit \begin{figure}[h] %\caption{Circuit} \begin{center} - \begin{circuitdiagram}{18}{18} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR gate -> right + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND gate -> right \pin{1}{1}{L}{A0} % pin A0 \pin{1}{5}{L}{A1} % pin A1 \pin{1}{7}{L}{B0} % pin B0 \pin{1}{11}{L}{B1} % pin B1 - \pin{1}{13}{L}{C0} % pin C0 - \pin{1}{17}{L}{C1} % pin C1 - \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{7} % wire between OR and NAND - \wire{9}{11}{9}{15} % wire between OR and NAND - \pin{17}{9}{R}{Z} % pin Z + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{17}{6}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OOAI22_manpage.tex b/Documents/LaTeX/OOAI22_manpage.tex new file mode 100644 index 00000000..e13fa5f3 --- /dev/null +++ b/Documents/LaTeX/OOAI22_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI22_manpage.tex +%% +%% Purpose: Manual Page File for OOAI22 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI22} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI22} - a 2-2-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI22(Y, B1, B0, A1, A0) +\end{quote} + +\paragraph{Description} +\input{OOAI22_circuit.tex} +\input{OOAI22_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI22_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/AOI211_schematic.tex b/Documents/LaTeX/OOAI22_schematic.tex similarity index 50% rename from Documents/LaTeX/AOI211_schematic.tex rename to Documents/LaTeX/OOAI22_schematic.tex index 23fc51b7..a25f81e9 100644 --- a/Documents/LaTeX/AOI211_schematic.tex +++ b/Documents/LaTeX/OOAI22_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_AOI211.tex +%% File: StdCellLib/Documents/LaTeX/OOAI22_schematic.tex %% -%% Purpose: Schematic File for AOI211 +%% Purpose: Schematic File for OOAI22 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -33,40 +33,37 @@ %% %% /////////////////////////////////////////////////////////////////// \begin{center} - Schematic (one stage, 3$T_{p}$/2$T_{n}$ stacked, 8T total) + Schematic (one stage, 2$T_{p}$/2$T_{n}$ stacked, 8T total) \begin{figure}[h] %\caption{Schematic} \begin{center} - \begin{circuitdiagram}{36}{33} - \pin{2}{8.5}{L}{A} % pin A, n-channel - \pin{14}{8.5}{L}{B} % pin B, n-channel - \pin{26}{2.5}{L}{C1} % pin C1, n-channel - \pin{26}{8.5}{L}{C0} % pin C0, p-channel - \pin{2}{17.5}{L}{A} % pin A, p-channel - \pin{2}{23.5}{L}{B} % pin B, p-channel - \pin{2}{29.5}{L}{C0} % pin C0, p-channel - \pin{14}{29.5}{L}{C1} % pin C1, p-channel - \trans[\wireU{0.5}]{nenh*}{6}{10}{R}{$M_{NA}$}{} - \trans[\wireU{0.5}]{nenh*}{18}{10}{R}{$M_{NB}$}{} - \trans[\wireUD{0.5}]{nenh*}{30}{10}{R}{$M_{NC0}$}{} - \trans[\wireU{0.5}]{nenh*}{30}{4}{R}{$M_{NC1}$}{} - \trans[\wireUD{0.5}]{penh*}{6}{16}{R}{}{$M_{PA}$} - \trans[\wireUD{0.5}]{penh*}{6}{22}{R}{}{$M_{PB}$} - \trans[\wireUD{0.5}]{penh*}{6}{28}{R}{}{$M_{PC0}$} - \trans[\wireUD{0.5}]{penh*}{18}{28}{R}{}{$M_{PC1}$} + \begin{circuitdiagram}{24}{27} + \pin{2}{2.5}{L}{B0} % pin B0, n-channel left-below + \pin{2}{8.5}{L}{A0} % pin A0, n-channel left-above + \pin{14}{2.5}{L}{B1} % pin B1, n-channel right-below + \pin{14}{8.5}{L}{A1} % pin A1, n-channel right-above + \pin{2}{17.5}{L}{A0} % pin A0, p-channel left-below + \pin{14}{17.5}{L}{B0} % pin B0, p-channel right-below + \pin{2}{23.5}{L}{A1} % pin A1, p-channel left-above + \pin{14}{23.5}{L}{B1} % pin B1, p-channel right-above + \trans[\wireU{0.5}]{nenh*}{6}{4}{R}{$M_{NB0}$}{} + \trans[\wireUD{0.5}]{nenh*}{6}{10}{R}{$M_{NA0}$}{} + \trans[\wireU{0.5}]{nenh*}{18}{4}{R}{$M_{NB1}$}{} + \trans[\wireUD{0.5}]{nenh*}{18}{10}{R}{$M_{NA1}$}{} + \trans[\wireUD{0.5}]{penh*}{6}{16}{R}{}{$M_{PA0}$} + \trans[\wireUD{0.5}]{penh*}{18}{16}{R}{}{$M_{PB0}$} + \trans[\wireD{0.5}]{penh*}{6}{22}{R}{}{$M_{PA1}$} + \trans[\wireD{0.5}]{penh*}{18}{22}{R}{}{$M_{PB1}$} \ground{8}{0.5}{D} % ground below nmos \ground{20}{0.5}{D} % ground below nmos - \ground{32}{0.5}{D} % ground below nmos - \power{8}{31.5}{U}{} % power above left pmos - \power{20}{31.5}{U}{} % power above left pmos - \wire{8}{1}{8}{8} - \wire{20}{1}{20}{8} - \wire{8}{25}{20}{25} % wire short between pmos - \wire{8}{13}{34}{13} % wire before pin Z + \power{8}{25.5}{U}{} % power above left pmos + \power{20}{25.5}{U}{} % power above left pmos + \wire{8}{7}{20}{7} % wire short between pmos + \wire{8}{13}{22}{13} % wire before pin Z \junct{8}{13} - \junct{8}{25} + \junct{8}{7} \junct{20}{13} - \junct{32}{13} - \pin{35}{13}{R}{Z} % pin Z + \junct{20}{7} + \pin{23}{13}{R}{Z} % pin Z \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/AOI211_truthtable.tex b/Documents/LaTeX/OOAI22_truthtable.tex similarity index 70% rename from Documents/LaTeX/AOI211_truthtable.tex rename to Documents/LaTeX/OOAI22_truthtable.tex index 72f9a0b5..6ab9bd71 100644 --- a/Documents/LaTeX/AOI211_truthtable.tex +++ b/Documents/LaTeX/OOAI22_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI211.tex +%% File: StdCellLib/Documents/LaTeX/OOAI22_truthtable.tex %% -%% Purpose: Truth Table File for AOI211 +%% Purpose: Truth Table File for OOAI22 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,16 +34,17 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} - {\(Z = \lnot ((C1 \land C0) \lor B \lor A \))} - \begin{table}[h] %\caption{\(Z = \lnot ((C1 \land C0) \lor B \lor A \))} + {\(Z = \lnot ((B1 \lor B0) \land (A1 \lor A0)) \)} + \begin{table}[h] %\caption{\(Z = \lnot ((B1 \lor B0) \land (A1 \lor A0)) \)} \begin{center} \begin{tabular}{|c|c|c|c||c|} \hline - C1 & C0 & B & A & Z \\ \hline\hline - 0 & X & 0 & 0 & 1 \\ \hline - 1 & 1 & X & X & 0 \\ \hline - X & 0 & 0 & 0 & 1 \\ \hline - X & X & 1 & X & 0 \\ \hline - X & X & X & 1 & 0 \\ \hline + B1 & B0 & A1 & A0 & Z \\ \hline\hline + 0 & 0 & X & X & 1 \\ \hline + 1 & X & 1 & X & 0 \\ \hline + 1 & X & X & 1 & 0 \\ \hline + X & 1 & 1 & X & 0 \\ \hline + X & 1 & X & 1 & 0 \\ \hline + X & X & 0 & 0 & 1 \\ \hline \end{tabular} \end{center} \end{table} diff --git a/Documents/LaTeX/OAI321_circuit.tex b/Documents/LaTeX/OOAI321_circuit.tex similarity index 68% rename from Documents/LaTeX/OAI321_circuit.tex rename to Documents/LaTeX/OOAI321_circuit.tex index 7d8c1f73..8a43d623 100644 --- a/Documents/LaTeX/OAI321_circuit.tex +++ b/Documents/LaTeX/OOAI321_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI321.tex +%% File: StdCellLib/Documents/LaTeX/OOAI321_circuit.tex %% -%% Purpose: Circuit File for OAI321 +%% Purpose: Circuit File for OOAI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,22 +34,23 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{7}{L}{B1} % pin B1 - \pin{1}{9}{L}{C0} % pin C0 - \pin{1}{11}{L}{C1} % pin C1 - \pin{1}{13}{L}{C2} % pin C2 - \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND gate -> right - \wire{9}{1}{9}{3} % wire between OR and NAND - \wire{9}{11}{9}{7} % wire between OR and NAND + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND \wire{2}{1}{9}{1} % wire before NAND - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OOAI321_manpage.tex b/Documents/LaTeX/OOAI321_manpage.tex new file mode 100644 index 00000000..c486688b --- /dev/null +++ b/Documents/LaTeX/OOAI321_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI321_manpage.tex +%% +%% Purpose: Manual Page File for OOAI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI321} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI321} - a 3-2-1-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAI321_circuit.tex} +\input{OOAI321_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI321_schematic.tex b/Documents/LaTeX/OOAI321_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI321_schematic.tex rename to Documents/LaTeX/OOAI321_schematic.tex index 0db93890..ba51aa8e 100644 --- a/Documents/LaTeX/OAI321_schematic.tex +++ b/Documents/LaTeX/OOAI321_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI321.tex +%% File: StdCellLib/Documents/LaTeX/OOAI321_schematic.tex %% -%% Purpose: Schematic File for OAI321 +%% Purpose: Schematic File for OOAI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI321_truthtable.tex b/Documents/LaTeX/OOAI321_truthtable.tex similarity index 92% rename from Documents/LaTeX/OAI321_truthtable.tex rename to Documents/LaTeX/OOAI321_truthtable.tex index ccfcfa23..f5f39a61 100644 --- a/Documents/LaTeX/OAI321_truthtable.tex +++ b/Documents/LaTeX/OOAI321_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI321.tex +%% File: StdCellLib/Documents/LaTeX/OOAI321_truthtable.tex %% -%% Purpose: Truth Table File for OAI321 +%% Purpose: Truth Table File for OOAI321 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI332_circuit.tex b/Documents/LaTeX/OOAI32_circuit.tex similarity index 70% rename from Documents/LaTeX/OAI332_circuit.tex rename to Documents/LaTeX/OOAI32_circuit.tex index d5edf9d6..17782032 100644 --- a/Documents/LaTeX/OAI332_circuit.tex +++ b/Documents/LaTeX/OOAI32_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI332.tex +%% File: StdCellLib/Documents/LaTeX/OOAI32_circuit.tex %% -%% Purpose: Circuit File for OAI332 +%% Purpose: Circuit File for OOAI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -36,22 +36,19 @@ Circuit \begin{figure}[h] %\caption{Circuit} \begin{center} - \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND gate -> right + \pin{1}{1}{L}{A} % pin A \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{9}{L}{B1} % pin B1 \pin{1}{11}{L}{B2} % pin B2 - \pin{1}{13}{L}{C0} % pin C0 - \pin{1}{15}{L}{C1} % pin C1 - \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{7} % wire between OR and NAND - \wire{9}{11}{9}{15} % wire between OR and NAND - \pin{17}{9}{R}{Z} % pin Z + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{17}{6}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OOAI32_manpage.tex b/Documents/LaTeX/OOAI32_manpage.tex new file mode 100644 index 00000000..1c252fc9 --- /dev/null +++ b/Documents/LaTeX/OOAI32_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI32_manpage.tex +%% +%% Purpose: Manual Page File for OOAI32 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI32} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI32} - a 3-2-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI32(Z, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAI32_circuit.tex} +\input{OOAI32_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI32_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI32_schematic.tex b/Documents/LaTeX/OOAI32_schematic.tex similarity index 94% rename from Documents/LaTeX/OAI32_schematic.tex rename to Documents/LaTeX/OOAI32_schematic.tex index 167bad2e..d714a272 100644 --- a/Documents/LaTeX/OAI32_schematic.tex +++ b/Documents/LaTeX/OOAI32_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI32.tex +%% File: StdCellLib/Documents/LaTeX/OOAI32_schematic.tex %% -%% Purpose: Schematic File for OAI32 +%% Purpose: Schematic File for OOAI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI32_truthtable.tex b/Documents/LaTeX/OOAI32_truthtable.tex similarity index 91% rename from Documents/LaTeX/OAI32_truthtable.tex rename to Documents/LaTeX/OOAI32_truthtable.tex index f71e38ae..f127eb93 100644 --- a/Documents/LaTeX/OAI32_truthtable.tex +++ b/Documents/LaTeX/OOAI32_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI32.tex +%% File: StdCellLib/Documents/LaTeX/OOAI32_truthtable.tex %% -%% Purpose: Truth Table File for OAI32 +%% Purpose: Truth Table File for OOAI32 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI331_circuit.tex b/Documents/LaTeX/OOAI331_circuit.tex similarity index 69% rename from Documents/LaTeX/OAI331_circuit.tex rename to Documents/LaTeX/OOAI331_circuit.tex index b37187f6..55871182 100644 --- a/Documents/LaTeX/OAI331_circuit.tex +++ b/Documents/LaTeX/OOAI331_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI331.tex +%% File: StdCellLib/Documents/LaTeX/OOAI331_circuit.tex %% -%% Purpose: Circuit File for OAI331 +%% Purpose: Circuit File for OOAI331 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,23 +34,24 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B0} % pin B0 + \pin{1}{3}{L}{B} % pin B \pin{1}{5}{L}{B1} % pin B1 \pin{1}{7}{L}{B2} % pin B2 - \pin{1}{9}{L}{C0} % pin C0 - \pin{1}{11}{L}{C1} % pin C1 - \pin{1}{13}{L}{C2} % pin C2 - \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{5}{R}{}{} % NAND gate -> right - \wire{9}{1}{9}{3} % wire between OR and NAND - \wire{9}{11}{9}{7} % wire between OR and NAND + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{9}{1}{9}{3} % wire between OR and NAND + \wire{9}{11}{9}{7} % wire between OR and NAND \wire{2}{1}{9}{1} % wire before NAND - \pin{17}{5}{R}{Z} % pin Z + \pin{17}{5}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OOAI331_manpage.tex b/Documents/LaTeX/OOAI331_manpage.tex new file mode 100644 index 00000000..bb415bb9 --- /dev/null +++ b/Documents/LaTeX/OOAI331_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI331_manpage.tex +%% +%% Purpose: Manual Page File for OOAI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI331} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI331} - a 3-3-1-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAI331_circuit.tex} +\input{OOAI331_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI331_schematic.tex b/Documents/LaTeX/OOAI331_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI331_schematic.tex rename to Documents/LaTeX/OOAI331_schematic.tex index c4a41ab9..e3b97c06 100644 --- a/Documents/LaTeX/OAI331_schematic.tex +++ b/Documents/LaTeX/OOAI331_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI331.tex +%% File: StdCellLib/Documents/LaTeX/OOAI331_schematic.tex %% -%% Purpose: Schematic File for OAI331 +%% Purpose: Schematic File for OOAI331 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI331_truthtable.tex b/Documents/LaTeX/OOAI331_truthtable.tex similarity index 92% rename from Documents/LaTeX/OAI331_truthtable.tex rename to Documents/LaTeX/OOAI331_truthtable.tex index 9ed47f11..d885329d 100644 --- a/Documents/LaTeX/OAI331_truthtable.tex +++ b/Documents/LaTeX/OOAI331_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI331.tex +%% File: StdCellLib/Documents/LaTeX/OOAI331_truthtable.tex %% -%% Purpose: Truth Table File for OAI331 +%% Purpose: Truth Table File for OOAI331 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OOAI33_circuit.tex b/Documents/LaTeX/OOAI33_circuit.tex new file mode 100644 index 00000000..035a7d91 --- /dev/null +++ b/Documents/LaTeX/OOAI33_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI33_circuit.tex +%% +%% Purpose: Circuit File for OOAI33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{12} + \usgate + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A0 + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B0 + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{9}{9}{8} % wire between OR and NAND + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAI33_manpage.tex b/Documents/LaTeX/OOAI33_manpage.tex new file mode 100644 index 00000000..dfa855c3 --- /dev/null +++ b/Documents/LaTeX/OOAI33_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI33_manpage.tex +%% +%% Purpose: Manual Page File for OOAI33 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI33} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI33} - a 3-3-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI33(Z, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAI33_circuit.tex} +\input{OOAI33_schematic.tex} + +\paragraph{Truth Table} +\input{OOAI33_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI33_schematic.tex b/Documents/LaTeX/OOAI33_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI33_schematic.tex rename to Documents/LaTeX/OOAI33_schematic.tex index 7c3097c1..a688e4b5 100644 --- a/Documents/LaTeX/OAI33_schematic.tex +++ b/Documents/LaTeX/OOAI33_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI33.tex +%% File: StdCellLib/Documents/LaTeX/OOAI33_schematic.tex %% -%% Purpose: Schematic File for OAI33 +%% Purpose: Schematic File for OOAI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI33_truthtable.tex b/Documents/LaTeX/OOAI33_truthtable.tex similarity index 92% rename from Documents/LaTeX/OAI33_truthtable.tex rename to Documents/LaTeX/OOAI33_truthtable.tex index 47cf5340..f86771ff 100644 --- a/Documents/LaTeX/OAI33_truthtable.tex +++ b/Documents/LaTeX/OOAI33_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI33.tex +%% File: StdCellLib/Documents/LaTeX/OOAI33_truthtable.tex %% -%% Purpose: Truth Table File for OAI33 +%% Purpose: Truth Table File for OOAI33 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OOAI42_circuit.tex b/Documents/LaTeX/OOAI42_circuit.tex new file mode 100644 index 00000000..ffe0f054 --- /dev/null +++ b/Documents/LaTeX/OOAI42_circuit.tex @@ -0,0 +1,56 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI42_circuit.tex +%% +%% Purpose: Circuit File for OOAI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{10}{9}{8} % wire between OR and NAND + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAI42_manpage.tex b/Documents/LaTeX/OOAI42_manpage.tex new file mode 100644 index 00000000..ea4bb0f1 --- /dev/null +++ b/Documents/LaTeX/OOAI42_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI42_manpage.tex +%% +%% Purpose: Manual Page File for OOAI42 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI42} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI42} - a 4-2-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI42(Y, B3, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAI42_circuit.tex} +%\input{OOAI42_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAI42_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOAI43_circuit.tex b/Documents/LaTeX/OOAI43_circuit.tex new file mode 100644 index 00000000..a6d0dc1d --- /dev/null +++ b/Documents/LaTeX/OOAI43_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI43_circuit.tex +%% +%% Purpose: Circuit File for OOAI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{14} + \usgate + \gate[\inputs{4}]{or}{5}{10}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{6}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{B3} % pin B3 + \wire{9}{3}{9}{4} % wire between OR and NAND + \wire{9}{10}{9}{8} % wire between OR and NAND + \pin{17}{6}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAI43_manpage.tex b/Documents/LaTeX/OOAI43_manpage.tex new file mode 100644 index 00000000..63529184 --- /dev/null +++ b/Documents/LaTeX/OOAI43_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI43_manpage.tex +%% +%% Purpose: Manual Page File for OOAI43 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI43} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI43} - a 4-3-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI43(Y, B3, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAI43_circuit.tex} +%\input{OOAI43_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAI43_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOAI44_circuit.tex b/Documents/LaTeX/OOAI44_circuit.tex new file mode 100644 index 00000000..a7c8fece --- /dev/null +++ b/Documents/LaTeX/OOAI44_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI44_circuit.tex +%% +%% Purpose: Circuit File for OOAI44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{16} + \usgate + \gate[\inputs{4}]{or}{5}{12}{R}{}{} % OR + \gate[\inputs{4}]{or}{5}{4}{R}{}{} % OR + \gate[\inputs{2}]{nand}{12}{8}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 + \pin{1}{9}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{B2} % pin B2 + \pin{1}{15}{L}{B3} % pin B3 + \wire{9}{4}{9}{6} % wire between OR and NAND + \wire{9}{12}{9}{10} % wire between OR and NAND + \pin{17}{8}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAI44_manpage.tex b/Documents/LaTeX/OOAI44_manpage.tex new file mode 100644 index 00000000..34d3314a --- /dev/null +++ b/Documents/LaTeX/OOAI44_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAI44_manpage.tex +%% +%% Purpose: Manual Page File for OOAI44 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAI44} +\paragraph{Cell} +\begin{quote} + \textbf{OOAI44} - a 4-4-input OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAI44(Y, B3, B2, B1, B, A3, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOAI44_circuit.tex} +%\input{OOAI44_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAI44_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOAO221_circuit.tex b/Documents/LaTeX/OOAO221_circuit.tex new file mode 100644 index 00000000..168256c3 --- /dev/null +++ b/Documents/LaTeX/OOAO221_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO221_circuit.tex +%% +%% Purpose: Circuit File for OOAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAO221_manpage.tex b/Documents/LaTeX/OOAO221_manpage.tex new file mode 100644 index 00000000..fdad275e --- /dev/null +++ b/Documents/LaTeX/OOAO221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO221_manpage.tex +%% +%% Purpose: Manual Page File for OOAO221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAO221} +\paragraph{Cell} +\begin{quote} + \textbf{OOAO221} - a 2-2-1-input OR-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAO221(Z, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAO221_circuit.tex} +%\input{OOAO221_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAO221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAO321_circuit.tex b/Documents/LaTeX/OOAO321_circuit.tex new file mode 100644 index 00000000..6d81f550 --- /dev/null +++ b/Documents/LaTeX/OOAO321_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO321_circuit.tex +%% +%% Purpose: Circuit File for OOAO321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAO321_manpage.tex b/Documents/LaTeX/OOAO321_manpage.tex new file mode 100644 index 00000000..43534366 --- /dev/null +++ b/Documents/LaTeX/OOAO321_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO321_manpage.tex +%% +%% Purpose: Manual Page File for OOAO321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAO321} +\paragraph{Cell} +\begin{quote} + \textbf{OOAO321} - a 3-2-1-input OR-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAO321(Z, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAO321_circuit.tex} +%\input{OOAO321_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAO321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAO331_circuit.tex b/Documents/LaTeX/OOAO331_circuit.tex new file mode 100644 index 00000000..0d741eab --- /dev/null +++ b/Documents/LaTeX/OOAO331_circuit.tex @@ -0,0 +1,62 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO331_circuit.tex +%% +%% Purpose: Circuit File for OOAO331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{31}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \gate{not}{26}{4}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{30}{4}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAO331_manpage.tex b/Documents/LaTeX/OOAO331_manpage.tex new file mode 100644 index 00000000..f5473a40 --- /dev/null +++ b/Documents/LaTeX/OOAO331_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAO331_manpage.tex +%% +%% Purpose: Manual Page File for OOAO331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAO331} +\paragraph{Cell} +\begin{quote} + \textbf{OOAO331} - a 3-3-1-input OR-OR-AND-OR gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAO331(Z, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAO331_circuit.tex} +%\input{OOAO331_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAO331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAOI221_circuit.tex b/Documents/LaTeX/OOAOI221_circuit.tex new file mode 100644 index 00000000..359974b3 --- /dev/null +++ b/Documents/LaTeX/OOAOI221_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI221_circuit.tex +%% +%% Purpose: Circuit File for OOAOI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{2}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{13}{L}{C1} % pin C1 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAOI221_manpage.tex b/Documents/LaTeX/OOAOI221_manpage.tex new file mode 100644 index 00000000..e3dc9483 --- /dev/null +++ b/Documents/LaTeX/OOAOI221_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI221_manpage.tex +%% +%% Purpose: Manual Page File for OOAOI221 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAOI221} +\paragraph{Cell} +\begin{quote} + \textbf{OOAOI221} - a 2-2-1-input OR-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAOI221(Y, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAOI221_circuit.tex} +%\input{OOAOI221_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAOI221_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAOI321_circuit.tex b/Documents/LaTeX/OOAOI321_circuit.tex new file mode 100644 index 00000000..bbe9658f --- /dev/null +++ b/Documents/LaTeX/OOAOI321_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI321_circuit.tex +%% +%% Purpose: Circuit File for OOAOI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{7}{L}{B1} % pin B1 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAOI321_manpage.tex b/Documents/LaTeX/OOAOI321_manpage.tex new file mode 100644 index 00000000..3c9ae4e5 --- /dev/null +++ b/Documents/LaTeX/OOAOI321_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI321_manpage.tex +%% +%% Purpose: Manual Page File for OOAOI321 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAOI321} +\paragraph{Cell} +\begin{quote} + \textbf{OOAOI321} - a 3-2-1-input OR-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAOI321(Y, C2, C1, C, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAOI321_circuit.tex} +%\input{OOAOI321_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAOI321_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOAOI331_circuit.tex b/Documents/LaTeX/OOAOI331_circuit.tex new file mode 100644 index 00000000..342ff4b1 --- /dev/null +++ b/Documents/LaTeX/OOAOI331_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI331_circuit.tex +%% +%% Purpose: Circuit File for OOAOI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{25}{14} + \usgate + \gate[\inputs{3}]{or}{5}{11}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{5}{R}{}{} % OR + \gate[\inputs{2}]{and}{12}{8}{R}{}{} % AND + \gate[\inputs{2}]{nor}{19}{4}{R}{}{} % NOR + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{B} % pin B + \pin{1}{5}{L}{B1} % pin B1 + \pin{1}{7}{L}{B2} % pin B2 + \pin{1}{9}{L}{C} % pin C + \pin{1}{11}{L}{C1} % pin C1 + \pin{1}{13}{L}{C2} % pin C2 + \wire{2}{1}{16}{1} % wire pin A + \wire{9}{5}{9}{6} % wire between OR and AND + \wire{9}{10}{9}{11} % wire between OR and AND + \wire{16}{1}{16}{2} % wire between AND and NOR + \wire{16}{6}{16}{8} % wire between AND and NOR + \pin{24}{4}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOAOI331_manpage.tex b/Documents/LaTeX/OOAOI331_manpage.tex new file mode 100644 index 00000000..11e05d93 --- /dev/null +++ b/Documents/LaTeX/OOAOI331_manpage.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOAOI331_manpage.tex +%% +%% Purpose: Manual Page File for OOAOI331 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOAOI331} +\paragraph{Cell} +\begin{quote} + \textbf{OOAOI331} - a 3-3-1-input OR-OR-AND-OR-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOAOI331(Y, C2, C1, C, B2, B1, B, A) +\end{quote} + +\paragraph{Description} +\input{OOAOI331_circuit.tex} +%\input{OOAOI331_schematic.tex} + +\paragraph{Truth Table} +%\input{OOAOI331_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OOOA222_circuit.tex b/Documents/LaTeX/OOOA222_circuit.tex new file mode 100644 index 00000000..6193cc3f --- /dev/null +++ b/Documents/LaTeX/OOOA222_circuit.tex @@ -0,0 +1,58 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA222_circuit.tex +%% +%% Purpose: Circuit File for OOOA222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOA222_manpage.tex b/Documents/LaTeX/OOOA222_manpage.tex new file mode 100644 index 00000000..c1d1e5d6 --- /dev/null +++ b/Documents/LaTeX/OOOA222_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA222_manpage.tex +%% +%% Purpose: Manual Page File for OOOA222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOA222} +\paragraph{Cell} +\begin{quote} + \textbf{OOOA222} - a 2-2-2-input OR-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOA222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOA222_circuit.tex} +%\input{OOOA222_schematic.tex} + +\paragraph{Truth Table} +%\input{OOOA222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOOA322_circuit.tex b/Documents/LaTeX/OOOA322_circuit.tex new file mode 100644 index 00000000..533f3395 --- /dev/null +++ b/Documents/LaTeX/OOOA322_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA322_circuit.tex +%% +%% Purpose: Circuit File for OOOA322 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOA322_manpage.tex b/Documents/LaTeX/OOOA322_manpage.tex new file mode 100644 index 00000000..7a626b07 --- /dev/null +++ b/Documents/LaTeX/OOOA322_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA322_manpage.tex +%% +%% Purpose: Manual Page File for OOOA322 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOA322} +\paragraph{Cell} +\begin{quote} + \textbf{OOOA322} - a 3-2-2-input OR-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOA322(Z, C2, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOA322_circuit.tex} +%\input{OOOA322_schematic.tex} + +\paragraph{Truth Table} +%\input{OOOA322_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOOA332_circuit.tex b/Documents/LaTeX/OOOA332_circuit.tex new file mode 100644 index 00000000..005e1271 --- /dev/null +++ b/Documents/LaTeX/OOOA332_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA332_circuit.tex +%% +%% Purpose: Circuit File for OOOA332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOA332_manpage.tex b/Documents/LaTeX/OOOA332_manpage.tex new file mode 100644 index 00000000..3f991677 --- /dev/null +++ b/Documents/LaTeX/OOOA332_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA332_manpage.tex +%% +%% Purpose: Manual Page File for OOOA332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOA332} +\paragraph{Cell} +\begin{quote} + \textbf{OOOA332} - a 3-3-2-input OR-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOA332(Z, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOA332_circuit.tex} +%\input{OOOA332_schematic.tex} + +\paragraph{Truth Table} +%\input{OOOA332_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOOA333_circuit.tex b/Documents/LaTeX/OOOA333_circuit.tex new file mode 100644 index 00000000..f564ea69 --- /dev/null +++ b/Documents/LaTeX/OOOA333_circuit.tex @@ -0,0 +1,61 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA333_circuit.tex +%% +%% Purpose: Circuit File for OOOA333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{24}{18} + \usgate + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \gate{not}{19}{9}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{23}{9}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOA333_manpage.tex b/Documents/LaTeX/OOOA333_manpage.tex new file mode 100644 index 00000000..510dbaf2 --- /dev/null +++ b/Documents/LaTeX/OOOA333_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOA333_manpage.tex +%% +%% Purpose: Manual Page File for OOOA333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOA333} +\paragraph{Cell} +\begin{quote} + \textbf{OOOA333} - a 3-3-3-input OR-OR-OR-AND gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOA333(Z, C2, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOA333_circuit.tex} +%\input{OOOA333_schematic.tex} + +\paragraph{Truth Table} +%\input{OOOA333_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OOOAI222_circuit.tex b/Documents/LaTeX/OOOAI222_circuit.tex new file mode 100644 index 00000000..1511a605 --- /dev/null +++ b/Documents/LaTeX/OOOAI222_circuit.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI222_circuit.tex +%% +%% Purpose: Circuit File for OOOAI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{18} + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{11}{L}{B1} % pin B1 + \pin{1}{13}{L}{C} % pin C + \pin{1}{17}{L}{C1} % pin C1 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{17}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOAI222_manpage.tex b/Documents/LaTeX/OOOAI222_manpage.tex new file mode 100644 index 00000000..075e15a2 --- /dev/null +++ b/Documents/LaTeX/OOOAI222_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI222_manpage.tex +%% +%% Purpose: Manual Page File for OOOAI222 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOAI222} +\paragraph{Cell} +\begin{quote} + \textbf{OOOAI222} - a 2-2-2-input OR-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOAI222(Z, C1, C, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOAI222_circuit.tex} +\input{OOOAI222_schematic.tex} + +\paragraph{Truth Table} +\input{OOOAI222_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI222_schematic.tex b/Documents/LaTeX/OOOAI222_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI222_schematic.tex rename to Documents/LaTeX/OOOAI222_schematic.tex index c191044e..f599d583 100644 --- a/Documents/LaTeX/OAI222_schematic.tex +++ b/Documents/LaTeX/OOOAI222_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI222.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI222_schematic.tex %% -%% Purpose: Schematic File for OAI222 +%% Purpose: Schematic File for OOOAI222 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI222_truthtable.tex b/Documents/LaTeX/OOOAI222_truthtable.tex similarity index 92% rename from Documents/LaTeX/OAI222_truthtable.tex rename to Documents/LaTeX/OOOAI222_truthtable.tex index 54e36bfa..b9693427 100644 --- a/Documents/LaTeX/OAI222_truthtable.tex +++ b/Documents/LaTeX/OOOAI222_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI222.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI222_truthtable.tex %% -%% Purpose: Truth Table File for OAI222 +%% Purpose: Truth Table File for OOOAI222 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI322_circuit.tex b/Documents/LaTeX/OOOAI322_circuit.tex similarity index 68% rename from Documents/LaTeX/OAI322_circuit.tex rename to Documents/LaTeX/OOOAI322_circuit.tex index 7433cdf2..43eab800 100644 --- a/Documents/LaTeX/OAI322_circuit.tex +++ b/Documents/LaTeX/OOOAI322_circuit.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OAI322.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI322_circuit.tex %% -%% Purpose: Circuit File for OAI322 +%% Purpose: Circuit File for OOOAI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,23 +34,24 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{18}{18} - \pin{1}{1}{L}{A0} % pin A0 + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A \pin{1}{5}{L}{A1} % pin A1 - \pin{1}{7}{L}{B0} % pin B0 + \pin{1}{7}{L}{B} % pin B \pin{1}{11}{L}{B1} % pin B1 - \pin{1}{13}{L}{C0} % pin C0 + \pin{1}{13}{L}{C} % pin C \pin{1}{15}{L}{C1} % pin C1 \pin{1}{17}{L}{C2} % pin C2 - \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR gate -> right - \gate[\inputs{2}]{or}{5}{9}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR gate -> right - \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND gate -> right - \wire{9}{3}{9}{7} % wire between OR and NAND - \wire{9}{11}{9}{15} % wire between OR and NAND - \pin{17}{9}{R}{Z} % pin Z + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{17}{9}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/OAI322_manpage.tex b/Documents/LaTeX/OOOAI322_manpage.tex similarity index 81% rename from Documents/LaTeX/OAI322_manpage.tex rename to Documents/LaTeX/OOOAI322_manpage.tex index 4b4b9759..5866d54d 100644 --- a/Documents/LaTeX/OAI322_manpage.tex +++ b/Documents/LaTeX/OOOAI322_manpage.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OAI322.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI322_manpage.tex %% -%% Purpose: Manual Page File for OAI322 +%% Purpose: Manual Page File for OOOAI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -32,23 +32,23 @@ %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// -\label{OAI322} +\label{OOOAI322} \paragraph{Cell} \begin{quote} - \textbf{OAI322} - a 3-2-2-input OR-AND-Invert gate + \textbf{OOOAI322} - a 3-2-2-input OR-OR-OR-AND-Invert gate \end{quote} \paragraph{Synopsys} \begin{quote} - OAI322(Z, C2, C1, C0, B1, B0, A1, A0) + OOOAI322(Z, C2, C1, C, B1, B, A1, A) \end{quote} \paragraph{Description} -\input{OAI322_circuit.tex} -\input{OAI322_schematic.tex} +\input{OOOAI322_circuit.tex} +\input{OOOAI322_schematic.tex} \paragraph{Truth Table} -\input{OAI322_truthtable.tex} +\input{OOOAI322_truthtable.tex} \paragraph{Usage} diff --git a/Documents/LaTeX/OAI322_schematic.tex b/Documents/LaTeX/OOOAI322_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI322_schematic.tex rename to Documents/LaTeX/OOOAI322_schematic.tex index c0cc2a01..e7088c15 100644 --- a/Documents/LaTeX/OAI322_schematic.tex +++ b/Documents/LaTeX/OOOAI322_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI322.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI322_schematic.tex %% -%% Purpose: Schematic File for OAI322 +%% Purpose: Schematic File for OOOAI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI322_truthtable.tex b/Documents/LaTeX/OOOAI322_truthtable.tex similarity index 93% rename from Documents/LaTeX/OAI322_truthtable.tex rename to Documents/LaTeX/OOOAI322_truthtable.tex index 50701025..4876a9ca 100644 --- a/Documents/LaTeX/OAI322_truthtable.tex +++ b/Documents/LaTeX/OOOAI322_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI322.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI322_truthtable.tex %% -%% Purpose: Truth Table File for OAI322 +%% Purpose: Truth Table File for OOOAI322 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OOOAI332_circuit.tex b/Documents/LaTeX/OOOAI332_circuit.tex new file mode 100644 index 00000000..7d3f55d6 --- /dev/null +++ b/Documents/LaTeX/OOOAI332_circuit.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI332_circuit.tex +%% +%% Purpose: Circuit File for OOOAI332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{18} + \usgate + \gate[\inputs{2}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{17}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOAI332_manpage.tex b/Documents/LaTeX/OOOAI332_manpage.tex new file mode 100644 index 00000000..78c8a9a5 --- /dev/null +++ b/Documents/LaTeX/OOOAI332_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI332_manpage.tex +%% +%% Purpose: Manual Page File for OOOAI332 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOAI332} +\paragraph{Cell} +\begin{quote} + \textbf{OOOAI332} - a 3-3-2-input OR-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOAI332(Z, C2, C1, C, B2, B1, B, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOAI332_circuit.tex} +\input{OOOAI332_schematic.tex} + +\paragraph{Truth Table} +\input{OOOAI332_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI332_schematic.tex b/Documents/LaTeX/OOOAI332_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI332_schematic.tex rename to Documents/LaTeX/OOOAI332_schematic.tex index a68e2d0b..c64733b7 100644 --- a/Documents/LaTeX/OAI332_schematic.tex +++ b/Documents/LaTeX/OOOAI332_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI332.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI332_schematic.tex %% -%% Purpose: Schematic File for OAI332 +%% Purpose: Schematic File for OOOAI332 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI332_truthtable.tex b/Documents/LaTeX/OOOAI332_truthtable.tex similarity index 94% rename from Documents/LaTeX/OAI332_truthtable.tex rename to Documents/LaTeX/OOOAI332_truthtable.tex index 8fe8610d..4a85853f 100644 --- a/Documents/LaTeX/OAI332_truthtable.tex +++ b/Documents/LaTeX/OOOAI332_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI332.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI332_truthtable.tex %% -%% Purpose: Truth Table File for OAI332 +%% Purpose: Truth Table File for OOOAI332 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OOOAI333_circuit.tex b/Documents/LaTeX/OOOAI333_circuit.tex new file mode 100644 index 00000000..04f5b292 --- /dev/null +++ b/Documents/LaTeX/OOOAI333_circuit.tex @@ -0,0 +1,60 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI333_circuit.tex +%% +%% Purpose: Circuit File for OOOAI333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{18}{18} + \usgate + \gate[\inputs{3}]{or}{5}{3}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{9}{R}{}{} % OR + \gate[\inputs{3}]{or}{5}{15}{R}{}{} % OR + \gate[\inputs{3}]{nand}{12}{9}{R}{}{} % NAND + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{B} % pin B + \pin{1}{9}{L}{B1} % pin B1 + \pin{1}{11}{L}{B2} % pin B2 + \pin{1}{13}{L}{C} % pin C + \pin{1}{15}{L}{C1} % pin C1 + \pin{1}{17}{L}{C2} % pin C2 + \wire{9}{3}{9}{7} % wire between OR and NAND + \wire{9}{11}{9}{15} % wire between OR and NAND + \pin{17}{9}{R}{Y} % pin Y + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OOOAI333_manpage.tex b/Documents/LaTeX/OOOAI333_manpage.tex new file mode 100644 index 00000000..f2c5d92e --- /dev/null +++ b/Documents/LaTeX/OOOAI333_manpage.tex @@ -0,0 +1,59 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OOOAI333_manpage.tex +%% +%% Purpose: Manual Page File for OOOAI333 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\label{OOOAI333} +\paragraph{Cell} +\begin{quote} + \textbf{OOOAI333} - a 3-3-3-input OR-OR-OR-AND-Invert gate +\end{quote} + +\paragraph{Synopsys} +\begin{quote} + OOOAI333(Z, C2, C1, C, B2, B1, B, A2, A1, A) +\end{quote} + +\paragraph{Description} +\input{OOOAI333_circuit.tex} +\input{OOOAI333_schematic.tex} + +\paragraph{Truth Table} +\input{OOOAI333_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} diff --git a/Documents/LaTeX/OAI333_schematic.tex b/Documents/LaTeX/OOOAI333_schematic.tex similarity index 95% rename from Documents/LaTeX/OAI333_schematic.tex rename to Documents/LaTeX/OOOAI333_schematic.tex index c7366390..2d9a51ac 100644 --- a/Documents/LaTeX/OAI333_schematic.tex +++ b/Documents/LaTeX/OOOAI333_schematic.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/schematic_OAI333.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI333_schematic.tex %% -%% Purpose: Schematic File for OAI333 +%% Purpose: Schematic File for OOOAI333 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OAI333_truthtable.tex b/Documents/LaTeX/OOOAI333_truthtable.tex similarity index 95% rename from Documents/LaTeX/OAI333_truthtable.tex rename to Documents/LaTeX/OOOAI333_truthtable.tex index e84a0fba..616ceb10 100644 --- a/Documents/LaTeX/OAI333_truthtable.tex +++ b/Documents/LaTeX/OOOAI333_truthtable.tex @@ -9,15 +9,15 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_OAI333.tex +%% File: StdCellLib/Documents/LaTeX/OOOAI333_truthtable.tex %% -%% Purpose: Truth Table File for OAI333 +%% Purpose: Truth Table File for OOOAI333 %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon diff --git a/Documents/LaTeX/OR2_circuit.tex b/Documents/LaTeX/OR2_circuit.tex new file mode 100644 index 00000000..9c7b10a3 --- /dev/null +++ b/Documents/LaTeX/OR2_circuit.tex @@ -0,0 +1,49 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OR2_circuit.tex +%% +%% Purpose: Circuit File for OR2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{17}{6} + \usgate + \gate[\inputs{2}]{nor}{5}{3}{R}{}{} % NOR + \gate{not}{12}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{5}{L}{A1} % pin A1 + \pin{16}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OR2_manpage.tex b/Documents/LaTeX/OR2_manpage.tex new file mode 100644 index 00000000..ee175aff --- /dev/null +++ b/Documents/LaTeX/OR2_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OR2_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for OR2 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{OR2 - a 2-input OR gate} \label{logical:OR2} + +\paragraph{Synopsys} +\begin{quote} + OR2 (Z A1 A) +\end{quote} + +\paragraph{Description} +\input{OR2_circuit.tex} +%\input{OR2_schematic.tex} + +\paragraph{Truth Table} +%\input{OR2_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OR3_circuit.tex b/Documents/LaTeX/OR3_circuit.tex new file mode 100644 index 00000000..f67578a7 --- /dev/null +++ b/Documents/LaTeX/OR3_circuit.tex @@ -0,0 +1,50 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OR3_circuit.tex +%% +%% Purpose: Circuit File for OR3 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\begin{center} + Circuit + \begin{figure}[h] + \begin{center} + \begin{circuitdiagram}{17}{6} + \usgate + \gate[\inputs{3}]{nor}{5}{3}{R}{}{} % NOR + \gate{not}{12}{3}{R}{}{} % NOT + \pin{1}{1}{L}{A} % pin A + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{16}{3}{R}{Z} % pin Z + \end{circuitdiagram} + \end{center} + \end{figure} +\end{center} diff --git a/Documents/LaTeX/OR3_manpage.tex b/Documents/LaTeX/OR3_manpage.tex new file mode 100644 index 00000000..c519cba3 --- /dev/null +++ b/Documents/LaTeX/OR3_manpage.tex @@ -0,0 +1,57 @@ +%% ************ LibreSilicon's StdCellLibrary ******************* +%% +%% Organisation: Chipforge +%% Germany / European Union +%% +%% Profile: Chipforge focus on fine System-on-Chip Cores in +%% Verilog HDL Code which are easy understandable and +%% adjustable. For further information see +%% www.chipforge.org +%% there are projects from small cores up to PCBs, too. +%% +%% File: StdCellLib/Documents/LaTeX/OR3_manpage.tex +%% +%% Purpose: Auto-generated Manual Page for OR3 +%% +%% ************ LaTeX with circdia.sty package *************** +%% +%% /////////////////////////////////////////////////////////////////// +%% +%% Copyright (c) 2019 by chipforge +%% All rights reserved. +%% +%% This Standard Cell Library is licensed under the Libre Silicon +%% public license; you can redistribute it and/or modify it under +%% the terms of the Libre Silicon public license as published by +%% the Libre Silicon alliance, either version 1 of the License, or +%% (at your option) any later version. +%% +%% This design is distributed in the hope that it will be useful, +%% but WITHOUT ANY WARRANTY; without even the implied warranty of +%% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +%% See the Libre Silicon Public License for more details. +%% +%% /////////////////////////////////////////////////////////////////// +\subsection{OR3 - a 3-input OR gate} \label{logical:OR3} + +\paragraph{Synopsys} +\begin{quote} + OR3 (Z A2 A1 A) +\end{quote} + +\paragraph{Description} +\input{OR3_circuit.tex} +%\input{OR3_schematic.tex} + +\paragraph{Truth Table} +%\input{OR3_truthtable.tex} + +\paragraph{Usage} + +\paragraph{Fan-in / Fan-out} + +\paragraph{Layout} + +\paragraph{Files} + +\clearpage diff --git a/Documents/LaTeX/OR4_circuit.tex b/Documents/LaTeX/OR4_circuit.tex index adc43366..0ef855ae 100644 --- a/Documents/LaTeX/OR4_circuit.tex +++ b/Documents/LaTeX/OR4_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_OR4.tex +%% File: StdCellLib/Documents/LaTeX/OR4_circuit.tex %% %% Purpose: Circuit File for OR4 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,15 +34,16 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{17}{8} + \usgate + \gate[\inputs{4}]{nor}{5}{4}{R}{}{} % NOR + \gate{not}{12}{4}{R}{}{} % NOT \pin{1}{1}{L}{A} % pin A - \pin{1}{3}{L}{B} % pin B - \pin{1}{5}{L}{C} % pin C - \pin{1}{7}{L}{D} % pin D - \gate[\inputs{4}]{nor}{5}{4}{R}{}{} % OR gate -> right - \gate{not}{12}{4}{R}{}{} % NOT gate -> right + \pin{1}{3}{L}{A1} % pin A1 + \pin{1}{5}{L}{A2} % pin A2 + \pin{1}{7}{L}{A3} % pin A3 \pin{16}{4}{R}{Z} % pin Z \end{circuitdiagram} \end{center} diff --git a/Documents/LaTeX/OR4_manpage.tex b/Documents/LaTeX/OR4_manpage.tex index 1b5c2e5d..59ef1c79 100644 --- a/Documents/LaTeX/OR4_manpage.tex +++ b/Documents/LaTeX/OR4_manpage.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/manpage_OR4.tex +%% File: StdCellLib/Documents/LaTeX/OR4_mannpage.tex %% %% Purpose: Manual Page File for OR4 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -40,15 +40,15 @@ \paragraph{Synopsys} \begin{quote} - OR4(Z, D, C, B, A) + OR4(Z, A3, A2, A1, A) \end{quote} \paragraph{Description} \input{OR4_circuit.tex} -\input{OR4_schematic.tex} +%\input{OR4_schematic.tex} \paragraph{Truth Table} -\input{OR4_truthtable.tex} +%\input{OR4_truthtable.tex} \paragraph{Usage} @@ -58,8 +58,4 @@ \paragraph{Files} -\paragraph{See also} -\begin{quote} - AND4 - a 4-input AND gate -\end{quote} - +\clearpage diff --git a/Documents/LaTeX/StdCellLib.tex b/Documents/LaTeX/StdCellLib.tex index 2afd3523..83272374 100644 --- a/Documents/LaTeX/StdCellLib.tex +++ b/Documents/LaTeX/StdCellLib.tex @@ -107,9 +107,11 @@ \section{Logical Cells} \input{AOI331_manpage.tex} \input{AOI332_manpage.tex} \input{AOI333_manpage.tex} -\input{BUF_manpage.tex} \input{EQ2_manpage.tex} \input{INV_manpage.tex} +\input{LATP_manpage.tex} +\input{LATRP_manpage.tex} +\input{LATSP_manpage.tex} \input{MUXI2_manpage.tex} \input{NAND2_manpage.tex} \input{NAND3_manpage.tex} @@ -144,6 +146,12 @@ \section{Logical Cells} \input{XOR2_manpage.tex} +\section{Distribution Cells} + +\input{BUF2_manpage.tex} +\input{CGN2_manpage.tex} +\input{CGP2_manpage.tex} + \section{Physical Cells} \input{TIE0_manpage.tex} diff --git a/Documents/LaTeX/TIE0_circuit.tex b/Documents/LaTeX/TIE0_circuit.tex index 8b2fcc41..153a1d1f 100644 --- a/Documents/LaTeX/TIE0_circuit.tex +++ b/Documents/LaTeX/TIE0_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_TIE0.tex +%% File: StdCellLib/Documents/LaTeX/TIE0_circuit.tex %% %% Purpose: Circuit File for TIE0 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,13 +34,13 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{8}{8} \resis{2}{4}{V}{R}{} % pull down R \ground{2}{0.5}{D} - \wire{2}{7}{6}{7} % pin Z - \pin{7}{7}{R}{Z} % pin Z + \wire{2}{7}{6}{7} % pin Y + \pin{7}{7}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/Documents/LaTeX/TIE1_circuit.tex b/Documents/LaTeX/TIE1_circuit.tex index 721d5654..c5d096f8 100644 --- a/Documents/LaTeX/TIE1_circuit.tex +++ b/Documents/LaTeX/TIE1_circuit.tex @@ -9,7 +9,7 @@ %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/circuit_TIE1.tex +%% File: StdCellLib/Documents/LaTeX/TIE1_circuit.tex %% %% Purpose: Circuit File for TIE1 %% @@ -17,7 +17,7 @@ %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -34,13 +34,13 @@ %% /////////////////////////////////////////////////////////////////// \begin{center} Circuit - \begin{figure}[h] %\caption{Circuit} + \begin{figure}[h] \begin{center} \begin{circuitdiagram}{8}{8} \resis{2}{4}{V}{R}{} % pull up R \power{2}{7.5}{U}{} - \wire{2}{1}{6}{1} % pin Z - \pin{7}{1}{R}{Z} % pin Z + \wire{2}{1}{6}{1} % pin Y + \pin{7}{1}{R}{Y} % pin Y \end{circuitdiagram} \end{center} \end{figure} diff --git a/GNUmakefile b/GNUmakefile index b75d08f3..c1612fbb 100644 --- a/GNUmakefile +++ b/GNUmakefile @@ -37,12 +37,20 @@ include include.mk -DISTRIBUTION = $(CATALOGDIR)/*.cell \ +DISTRIBUTION = $(CATALOGDIR)/ \ $(DOCUMENTSDIR)/*.pdf \ - $(SIMULATIONDIR) \ + $(TECHDIR) \ +# $(RELEASEDIR) \ +# $(SIMULATIONDIR) \ $(SOURCESDIR) \ $(SYNTHESISDIR) \ - $(TBENCHDIR) + $(TBENCHDIR) \ + + +# collect available cells + +IGNORE := $(wildcard $(CATALOGDIR)/*.mk $(CATALOGDIR)/GNUmakefile) +CELLS := $(notdir $(filter-out $(IGNORE), $(wildcard $(CATALOGDIR)/*))) # ---------------------------------------------------------------- # DEFAULT TARGETS @@ -65,6 +73,7 @@ help: $(ECHO) " doc - generate data book" $(ECHO) "" $(ECHO) " alf [CELL=] - generate ALF export" + $(ECHO) " record [CELL=] - measure / characterize cell" $(ECHO) " magic [CELL=] - generate MAGIC layout" $(ECHO) " spice [CELL=] - generate SPICE models" $(ECHO) " svg [CELL=] - generate SVG layout" @@ -81,8 +90,11 @@ help: .PHONY: dist dist: clean + echo 1 >Catalog/.done + cd Catalog && ../Tools/perl/buildreport.pl && cd .. $(ECHO) "---- build a tarball with all important files ----" $(TAR) -cvf $(PROJECT)_$(DATE).tgz $(DISTRIBUTION) + echo $(PROJECT)_$(DATE).tgz has been written. # well, 'clean' directories before distributing @@ -99,7 +111,7 @@ clean: # prepare Popcorn before usage -.PHONY: tools +.PHONY: tools tools: $(MAKE) -C $(TOOLSDIR)/popcorn -f GNUmakefile $@ @@ -116,13 +128,21 @@ catalog: tools $(MAKE) -C $(CATALOGDIR) -f GNUmakefile $@ # ---------------------------------------------------------------- -# GENERATION TARGETS +# CELL TARGETS # ---------------------------------------------------------------- +# generate truth table + .PHONY: table-file table-file: $(MAKE) -f simulation.mk CELL=$(CELL) table-file +# measure / characterize cells + +.PHONY: record +record: + $(MAKE) -f simulation.mk CELL=$(CELL) record + # ---------------------------------------------------------------- # DOCUMENTATION TARGETS # ---------------------------------------------------------------- diff --git a/LICENSE b/LICENSE new file mode 100644 index 00000000..261eeb9e --- /dev/null +++ b/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/README.md b/README.md index db91b07d..1d09335d 100644 --- a/README.md +++ b/README.md @@ -1,82 +1,50 @@ # StdCellLib -This Repository contains all Sources for LibreSilicons's Standard Cell Library. -Started once as manual work, given slow progress, the focus was shifted to the Standard Cell Generator which was named "Popcorn". -Many Sources are now generated by Popcorn and still Work-in-Progress. -Check regulary for updates. +This Repository contains all Sources for LibreSilicons's Standard Cell Library Generator. +The process starts with the PDK from the semiconductor factory as an input. +In the first step you can either use "Popcorn" to grow the netlists for all cells out of a single inverter. +Or you could import the netlists from a given existing standard cell library. +The second step is the automatic generation (layouting, characterization) of all the standard cells. +In the final step, all the files are collected into the library files together that can then be used by e.g. qflow, yosys to go from RTL to GDS. -And please, do not hesitate to contact the Authors of Standard Cell Library for Patches, Feature additions or Questions. -Any feedback welcome under [Email](mailto://stdcelllib@nospam.chipforge.org "stdcelllib@nospam.chipforge.org"). ## Requirements -### LaTeX - -The Standard Cell Library uses LaTeX for Documentation. On Debian based system LaTeX can be installed with - -``` -apt-get install texlive-latex-extra texlive-extra-utils texlive-latex-recommended -``` - -or shorter - -``` -apt-get install texlive-full -``` - -which installs the complete (and usefull) LaTeX Environment. -Additionally we use the great CirDia LaTeX package for drawing circuit diagrams by Dr. Stefan Krause (Saarbrücken/Germany). Please download [CirDia](http://www.taylorgruppe.de/circdia "http://www.taylorgruppe.de/circdia"), unzip it, and run mktexlsr in the directory. Many Thanks to Stefan for the excellent work! - -### Scheme - -Popcorn (as the tool which does the Voodoo stuff and generates the Standard Cells) is written in R7RS Scheme. While this Standard is already a couple of years old, not so many tools supporting them. Chibi-Scheme as a pre-build package is not available on most systems, so we are using Gauche Scheme (or gosh) in Version 0.9.6 or higher. - -``` -apt-get install gauche -``` +### Linux (Debian/Ubuntu or derivative) -Please check the correct Version by +For Debian/Ubuntu based distributions (with Python >=3.6, e.g. Debian Buster) we are currently offering an installation script that installs all the necessary requirements: ``` -gosh -V +wget https://pdk.libresilicon.com/tools.sh +bash tools.sh ``` -some more "conservative" distributions with Long-time support (LTS) probably stuck at older versions. - -### Magic +It will download, build and install all required tools, and at the end try to build a standard cell library. -Another software for the Popcorn tool, which should be installed before usage, is [Magic](http://opencircuitdesign.com/magic "http://opencircuitdesign.com/magic"). Magic is Open Source, but not part of all Linux distributions (lacks on OpenSuse, Arch Linux etc). On Debian based systems - -``` -apt-get install magic -``` -works. +For other operating systems it is likely quite some work to get it running due to the high number of dependencies. But any ports to other systems are very welcome! ## Usage Please build and use the Standard Cells (and the cell generator) with the GNUmakefile system. ``` +cd StdCellLib/Catalog make +make catalog +make layout +make docs ``` -shows e.g. a help screen with available targets. - -### Popcorn Preparing - -Please prepare Popcorn first by typing +make alone shows e.g. a help screen with available targets. +make popcorn will prepare Popcorn and generate the very useful Manual Pages about the tool and the formats, Popcorn is using. Please read them. -``` -make popcorn -``` - -this will generate the very usefull Manual Pages about the tool and the formats, Popcorn is using. Please read them. ### Generate Cell Descriptions Once Popcorn is installed, you might run ``` +cd Catalog make catalog ``` @@ -84,9 +52,27 @@ which re-generates the majority of Cell Description Catalog; and overwrites olde Please re-generate the Catalog only, if you know what you're doing and have strong reasons for that. +Instead of Generating Cell Descriptions you can also import them from qflow: + +``` +cd Catalog +make importQflow +``` + ### Generate Cell Layouts -t.b.d +After you have generated and/or imported the cell description netlists, you can generate the layout: +``` +make layout +``` +In the future you will be able to parallelize it with make -j4 to have several cells being calculated at the same time + +While the generation is running you can continuously generate the build-report every 10 seconds by running +``` +bash ../Tools/reporter.sh +``` +You can then view the build-report in the file buildreport.html +An example build report is available here: https://pdk.libresilicon.com/dist/StdCellLib_20200417_LS1U/Catalog/buildreport.html ### Generate Library Documentation @@ -113,6 +99,28 @@ make dist generates a compresses Archive (.tgz) of all important files, named with the current date. If you're sure nothing left, this is the file to ditstribute as Standard Cell Library and to store into your repository (and to tag them as Release). +You can also use +``` +make qflow +``` +to install the standard cell library into qflow as "libresilicon" + BTW, the Tooling should *not* be part of the Distribution. + Congratulations! You generated a Standard Cell Library :-) There aren't many people who can say they've done that. + +# How to help +Please test it and report any issues, or in the respective repositories of the partner-projects. +And please, do not hesitate to contact the Authors of Standard Cell Library for Patches, Feature additions or Questions. +Any feedback welcome under [Email](mailto://stdcelllib@nospam.chipforge.org "stdcelllib@nospam.chipforge.org"). + +### Partner Tools + +We use LibreCell from Thomas Kramer https://codeberg.org/tok/librecell/ for Layouting and Characterization of the standard cells. +We use Magic from Tim Edwards: http://opencircuitdesign.com/magic/ for Popcorn, parasitic extraction and visualisation. Thanks a lot for your help! +We use the great CircDia LaTeX package for drawing circuit diagrams by Dr. Stefan Krause (Saarbrücken/Germany). (http://www.taylorgruppe.de/circdia "http://www.taylorgruppe.de/circdia") + +### Scheme + +Popcorn (as the tool which does the Voodoo stuff and generates the Standard Cells) is written in R^7RS Scheme. While this Standard is already a couple of years old, not so many tools supporting them. Chibi-Scheme as a pre-build package is not available on most systems, so we are using Gauche Scheme (or gosh) in Version 0.9.6 or higher. diff --git a/Sources/geda/BUF2.sch b/Sources/geda/BUF2.sch new file mode 100644 index 00000000..f5f38047 --- /dev/null +++ b/Sources/geda/BUF2.sch @@ -0,0 +1,181 @@ +v 20130925 2 +T 50100 40100 9 10 1 0 0 0 1 +1 +T 51700 40100 9 10 1 0 0 0 1 +1 +C 51600 43000 1 0 0 asic-nmos-1.sym +{ +T 53000 43800 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 52400 43800 5 10 1 1 0 0 1 +refdes=M2 +T 52400 43600 5 8 1 1 0 0 1 +model-name=nmos4 +T 52400 43300 5 8 1 0 0 0 1 +w='Wunit' +T 52400 43100 5 8 1 0 0 0 1 +l=1u +} +C 54000 43000 1 0 0 asic-nmos-1.sym +{ +T 55400 43800 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 54800 43800 5 10 1 1 0 0 1 +refdes=M4 +T 54800 43600 5 8 1 1 0 0 1 +model-name=nmos4 +T 54800 43300 5 8 1 0 0 0 1 +w='2*Wunit' +T 54800 43100 5 8 1 0 0 0 1 +l=1u +} +C 51600 44500 1 0 0 asic-pmos-1.sym +{ +T 53000 45300 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 52400 45300 5 10 1 1 0 0 1 +refdes=M1 +T 52400 45100 5 8 1 1 0 0 1 +model-name=pmos4 +T 52400 44800 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 52400 44600 5 8 1 0 0 0 1 +l=1u +} +C 54000 44500 1 0 0 asic-pmos-1.sym +{ +T 55400 45300 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 54800 45300 5 10 1 1 0 0 1 +refdes=M3 +T 54800 45100 5 8 1 1 0 0 1 +model-name=pmos4 +T 54800 44800 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 54800 44600 5 8 1 0 0 0 1 +l=1u +} +C 49500 40000 1 0 0 cvstitleblock-1.sym +{ +T 50100 40400 5 10 1 1 0 0 1 +date=2019-08-21 +T 54000 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 54000 40100 5 10 1 1 0 0 1 +auth= +T 50100 40700 5 10 1 1 0 0 1 +fname=BUF2.sch +T 52900 41100 5 14 1 1 0 4 1 +title=BUF2 - non-inverting Buffer, 2x driver strength +} +C 48000 46500 1 0 0 spice-model-1.sym +{ +T 48100 47100 5 10 1 1 0 0 1 +refdes=A1 +T 49300 46800 5 10 1 1 0 0 1 +model-name=nmos4 +T 48500 46600 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 51300 46500 1 0 0 spice-model-1.sym +{ +T 51400 47100 5 10 1 1 0 0 1 +refdes=A2 +T 52600 46800 5 10 1 1 0 0 1 +model-name=pmos4 +T 51800 46600 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 55400 44000 1 0 0 spice-subcircuit-IO-1.sym +{ +T 55800 44600 5 10 1 1 180 0 1 +refdes=P1 +} +C 50900 44600 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50500 44500 5 10 1 1 0 0 1 +refdes=P2 +} +N 51300 45000 51600 45000 4 +N 51600 43500 51300 43500 4 +N 51300 43500 51300 45000 4 +N 52200 44500 52200 44000 4 +N 53700 45000 54000 45000 4 +N 54000 43500 53700 43500 4 +N 53700 43500 53700 45000 4 +N 52200 44300 53700 44300 4 +N 54600 46000 54600 45500 4 +N 54600 44500 54600 44000 4 +N 54600 43000 54600 42400 4 +N 54600 44300 55600 44300 4 +{ +T 55200 44400 5 10 1 1 0 0 1 +netname=Z +} +N 50700 44300 51300 44300 4 +{ +T 50900 44400 5 10 1 1 0 0 1 +netname=A +} +N 50600 46000 54800 46000 4 +{ +T 50900 46100 5 10 1 1 0 0 1 +netname=VDD +} +N 50700 42400 54800 42400 4 +{ +T 51000 42500 5 10 1 1 0 0 1 +netname=GND +} +T 51900 41900 9 10 1 0 0 0 2 +1. Stage: +- common inverter +T 53800 41900 9 10 1 0 0 0 2 +2. Stage: +- inverter with higher (2x) driving strength +N 54800 45000 54800 46000 4 +N 54700 45000 54800 45000 4 +N 54800 42400 54800 43500 4 +N 54700 43500 54800 43500 4 +N 52200 45500 52200 46000 4 +N 52300 45000 52400 45000 4 +N 52400 45000 52400 46000 4 +N 52200 43000 52200 42400 4 +N 52300 43500 52400 43500 4 +N 52400 43500 52400 42400 4 +C 48000 45100 1 0 0 spice-directive-1.sym +{ +T 48100 45400 5 10 0 1 0 0 1 +device=directive +T 48100 45500 5 10 1 1 0 0 1 +refdes=A4 +T 48100 45200 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 48000 44500 1 0 0 spice-directive-1.sym +{ +T 48100 44800 5 10 0 1 0 0 1 +device=directive +T 48100 44900 5 10 1 1 0 0 1 +refdes=A5 +T 48100 44600 5 10 1 1 0 0 1 +value=.PARAM PNratio=2 +} +C 51100 42100 1 0 0 gnd-1.sym +C 54600 46700 1 0 0 spice-subcircuit-LL-1.sym +{ +T 54700 47100 5 10 1 1 0 0 1 +refdes=A3 +T 54700 46800 5 10 1 1 0 0 1 +model-name=BUF2 +} +C 50800 46300 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50400 46200 5 10 1 1 0 0 1 +refdes=P3 +} +C 50900 42700 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50500 42600 5 10 1 1 0 0 1 +refdes=P4 +} diff --git a/Sources/geda/BUF2.sym b/Sources/geda/BUF2.sym new file mode 100644 index 00000000..9abd91ba --- /dev/null +++ b/Sources/geda/BUF2.sym @@ -0,0 +1,60 @@ +v 20130925 2 +L 300 100 300 700 3 0 0 0 -1 -1 +L 300 100 800 400 3 0 0 0 -1 -1 +L 300 700 800 400 3 0 0 0 -1 -1 +P 1100 400 800 400 1 0 0 +{ +T 800 450 5 10 0 0 0 6 1 +pintype=out +T 800 450 5 10 0 0 0 6 1 +pinseq=1 +T 742 392 9 10 0 1 0 6 1 +pinlabel=Z +T 892 442 5 10 0 1 0 0 1 +pinnumber=1 +} +P 0 400 300 400 1 0 0 +{ +T 100 450 5 10 0 0 0 0 1 +pintype=in +T 100 450 5 10 0 0 0 0 1 +pinseq=2 +T 358 392 9 10 0 1 0 0 1 +pinlabel=A +T 208 442 5 10 0 1 0 6 1 +pinnumber=2 +} +P 600 800 600 500 1 0 0 +{ +T 650 700 5 10 0 0 270 0 1 +pintype=pwr +T 650 700 5 10 0 0 270 0 1 +pinseq=3 +T 600 445 9 10 0 1 90 6 1 +pinlabel=VDD +T 550 595 5 10 0 1 90 0 1 +pinnumber=3 +} +P 600 0 600 300 1 0 0 +{ +T 550 100 5 10 0 0 90 0 1 +pintype=pwr +T 550 100 5 10 0 0 90 0 1 +pinseq=4 +T 600 355 9 10 0 1 90 0 1 +pinlabel=GND +T 550 205 5 10 0 1 90 6 1 +pinnumber=4 +} +T 292 292 5 16 1 1 0 0 1 +device=BUF2 +T 1292 2092 8 10 0 1 0 0 1 +description=BUF2 - Non-inverting Buffer (2x) +T 292 789 5 10 1 1 0 0 1 +refdes=X? +T 1892 1192 8 10 0 0 0 0 1 +footprint=none +T -8 -208 8 10 0 1 0 0 1 +source=BUF2.sch +T 600 -100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/CGN2.sch b/Sources/geda/CGN2.sch new file mode 100644 index 00000000..cbfba913 --- /dev/null +++ b/Sources/geda/CGN2.sch @@ -0,0 +1,538 @@ +v 20130925 2 +T 55400 40200 9 10 1 0 0 0 1 +1 +T 57000 40200 9 10 1 0 0 0 1 +1 +N 44800 43300 44800 47800 4 +N 44900 48700 61700 48700 4 +{ +T 45000 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 45700 48700 45700 48300 4 +N 45900 47800 45800 47800 4 +N 45900 47800 45900 48700 4 +N 44800 42400 61700 42400 4 +{ +T 45000 42500 5 10 1 1 0 0 1 +netname=GND +} +C 45100 47300 1 0 0 asic-pmos-1.sym +{ +T 46500 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 45900 48100 5 10 1 1 0 0 1 +refdes=M1 +T 45900 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 45900 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 45900 47400 5 8 1 0 0 0 1 +l=1u +} +T 48100 41000 9 10 1 0 0 0 2 +see LATP (Q + QN stages) which latches (low-active) Clock Enable signal +and Gated Clock / Clock Gating Buffer for concept +B 48000 40500 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 54800 40100 1 0 0 cvstitleblock-1.sym +{ +T 55400 40500 5 10 1 1 0 0 1 +date=2019-09-05 +T 59300 40500 5 10 1 1 0 0 1 +rev=$Revision$ +T 59300 40200 5 10 1 1 0 0 1 +auth= +T 55400 40800 5 10 1 1 0 0 1 +fname=CGN2.sch +T 58600 41200 5 14 1 1 0 4 1 +title=CGN2 - Clock Gating Buffer for negative Clock, Drive 2x +} +C 45700 48900 1 0 0 spice-model-1.sym +{ +T 45800 49500 5 10 1 1 0 0 1 +refdes=A1 +T 47000 49200 5 10 1 1 0 0 1 +model-name=nmos4 +T 46200 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 49000 48900 1 0 0 spice-model-1.sym +{ +T 49100 49500 5 10 1 1 0 0 1 +refdes=A2 +T 50300 49200 5 10 1 1 0 0 1 +model-name=pmos4 +T 49500 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 50300 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50100 45900 5 10 1 1 0 0 1 +refdes=P2 +} +C 44700 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 44500 45900 5 10 1 1 0 0 1 +refdes=P3 +} +C 45100 49000 1 180 0 spice-subcircuit-IO-1.sym +{ +T 45100 49000 5 10 1 1 0 0 1 +refdes=P4 +} +C 45000 42700 1 180 0 spice-subcircuit-IO-1.sym +{ +T 45000 42700 5 10 1 1 0 0 1 +refdes=P5 +} +C 52300 49100 1 0 0 spice-subcircuit-LL-1.sym +{ +T 52400 49500 5 10 1 1 0 0 1 +refdes=A3 +T 52400 49200 5 10 1 1 0 0 1 +model-name=CGN2 +} +C 55700 49100 1 0 0 spice-directive-1.sym +{ +T 55800 49400 5 10 0 1 0 0 1 +device=directive +T 55800 49500 5 10 1 1 0 0 1 +refdes=A4 +T 55800 49200 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 58800 49100 1 0 0 spice-directive-1.sym +{ +T 58900 49400 5 10 0 1 0 0 1 +device=directive +T 58900 49500 5 10 1 1 0 0 1 +refdes=A5 +T 58900 49200 5 10 1 1 0 0 1 +value=.PARAM PNratio=2 +} +C 47100 47300 1 0 0 asic-pmos-1.sym +{ +T 48500 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 47900 48100 5 10 1 1 0 0 1 +refdes=M3 +T 47900 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 47900 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 47900 47400 5 8 1 0 0 0 1 +l=1u +} +C 47100 42800 1 0 0 asic-nmos-1.sym +{ +T 48500 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 47900 43600 5 10 1 1 0 0 1 +refdes=M4 +T 47900 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 47900 43100 5 8 1 0 0 0 1 +w='Wunit' +T 47900 42900 5 8 1 0 0 0 1 +l=1u +} +C 45100 42800 1 0 0 asic-nmos-1.sym +{ +T 46500 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 45900 43600 5 10 1 1 0 0 1 +refdes=M2 +T 45900 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 45900 43100 5 8 1 0 0 0 1 +w='Wunit' +T 45900 42900 5 8 1 0 0 0 1 +l=1u +} +N 44500 45600 44800 45600 4 +{ +T 44500 45700 5 10 1 1 0 0 1 +netname=XI +} +N 44800 47800 45100 47800 4 +N 44800 43300 45100 43300 4 +N 45700 42800 45700 42400 4 +N 45800 43300 45900 43300 4 +N 45900 43300 45900 42400 4 +N 45700 47300 45700 43800 4 +N 46800 47800 47100 47800 4 +N 46800 43300 47100 43300 4 +N 46800 47800 46800 43300 4 +N 45700 45600 46800 45600 4 +{ +T 46100 45700 5 10 1 1 0 0 1 +netname=clk180 +} +N 47700 47300 47700 43800 4 +N 47700 48300 47700 48700 4 +N 47700 42800 47700 42400 4 +N 47800 47800 47900 47800 4 +N 47900 47800 47900 48700 4 +N 47800 43300 47900 43300 4 +N 47900 43300 47900 42400 4 +N 47700 45600 48500 45600 4 +{ +T 48000 45700 5 10 1 1 0 0 1 +netname=clk360 +} +C 50800 45800 1 0 0 asic-pmos-1.sym +{ +T 52200 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 46600 5 10 1 1 0 0 1 +refdes=M6 +T 51600 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 51600 45900 5 8 1 0 0 0 1 +l=1u +} +C 50800 44300 1 0 0 asic-nmos-1.sym +{ +T 52200 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 45100 5 10 1 1 0 0 1 +refdes=M7 +T 51600 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 44400 5 8 1 0 0 0 1 +l=1u +} +C 50800 42800 1 0 0 asic-nmos-1.sym +{ +T 52200 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 43600 5 10 1 1 0 0 1 +refdes=M8 +T 51600 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 43100 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 42900 5 8 1 0 0 0 1 +l=1u +} +C 50800 47300 1 0 0 asic-pmos-1.sym +{ +T 52200 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 48100 5 10 1 1 0 0 1 +refdes=M5 +T 51600 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 51600 47400 5 8 1 0 0 0 1 +l=1u +} +N 50800 47800 49900 47800 4 +{ +T 50200 47900 5 10 1 1 0 0 1 +netname=clk180 +} +N 50800 43300 49900 43300 4 +{ +T 50200 43400 5 10 1 1 0 0 1 +netname=clk360 +} +N 50500 46300 50800 46300 4 +N 50800 44800 50500 44800 4 +N 50500 44800 50500 46300 4 +N 50100 45600 50500 45600 4 +{ +T 50100 45700 5 10 1 1 0 0 1 +netname=EN +} +N 51400 48300 51400 48700 4 +N 51400 47300 51400 46800 4 +N 51400 45800 51400 45300 4 +N 51400 44300 51400 43800 4 +N 51400 42800 51400 42400 4 +T 45700 41700 9 10 1 0 0 0 3 +Double Clock Buffering: +- de-coupling high load +- 2-phase clock generation +C 53200 45800 1 0 0 asic-pmos-1.sym +{ +T 54600 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 54000 46600 5 10 1 1 0 0 1 +refdes=M9 +T 54000 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 54000 46100 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 54000 45900 5 8 1 0 0 0 1 +l=1u +} +C 53200 44300 1 0 0 asic-nmos-1.sym +{ +T 54600 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 54000 45100 5 10 1 1 0 0 1 +refdes=M10 +T 54000 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 54000 44600 5 8 1 0 0 0 1 +w='Wunit' +T 54000 44400 5 8 1 0 0 0 1 +l=1u +} +N 52900 46300 53200 46300 4 +N 53200 44800 52900 44800 4 +N 52900 44800 52900 46300 4 +N 53800 45800 53800 45300 4 +C 55600 45800 1 0 0 asic-pmos-1.sym +{ +T 57000 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 56400 46600 5 10 1 1 0 0 1 +refdes=M12 +T 56400 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 56400 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 56400 45900 5 8 1 0 0 0 1 +l=1u +} +C 55600 44300 1 0 0 asic-nmos-1.sym +{ +T 57000 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56400 45100 5 10 1 1 0 0 1 +refdes=M13 +T 56400 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 56400 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 56400 44400 5 8 1 0 0 0 1 +l=1u +} +C 55600 42800 1 0 0 asic-nmos-1.sym +{ +T 57000 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56400 43600 5 10 1 1 0 0 1 +refdes=M14 +T 56400 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 56400 43100 5 8 1 0 0 0 1 +w='2*Wunit' +T 56400 42900 5 8 1 0 0 0 1 +l=1u +} +C 55600 47300 1 0 0 asic-pmos-1.sym +{ +T 57000 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 56400 48100 5 10 1 1 0 0 1 +refdes=M11 +T 56400 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 56400 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 56400 47400 5 8 1 0 0 0 1 +l=1u +} +N 55600 47800 54700 47800 4 +{ +T 55000 47900 5 10 1 1 0 0 1 +netname=clk360 +} +N 55600 43300 54700 43300 4 +{ +T 55000 43400 5 10 1 1 0 0 1 +netname=clk180 +} +N 55300 46300 55600 46300 4 +N 55600 44800 55300 44800 4 +N 55300 44800 55300 46300 4 +N 53800 45600 55300 45600 4 +N 56200 48300 56200 48700 4 +N 56200 47300 56200 46800 4 +N 56200 45800 56200 45300 4 +N 56200 44300 56200 43800 4 +N 56200 42800 56200 42400 4 +N 55000 44100 55000 45600 4 +N 51400 45600 52900 45600 4 +N 52300 45600 52300 47100 4 +N 52300 47100 57200 47100 4 +{ +T 54800 47200 5 10 1 1 0 0 1 +netname=qn +} +N 56200 45600 57200 45600 4 +N 57200 45600 57200 47100 4 +T 50100 41700 9 10 1 0 0 0 3 +Data input switch: +- (inverting) tri-state driver +- high-active transparent +T 53500 41900 9 10 1 0 0 0 2 +Q Stage: +- inverter +T 54900 41700 9 10 1 0 0 0 3 +QN Stage: +- (inverting) tri-state driver +- low-active transparent +N 51500 47800 51600 47800 4 +N 51600 46300 51600 48700 4 +N 51500 46300 51600 46300 4 +N 56300 47800 56400 47800 4 +N 56400 46300 56400 48700 4 +N 56300 46300 56400 46300 4 +N 56300 43300 56400 43300 4 +N 56400 42400 56400 44800 4 +N 56300 44800 56400 44800 4 +N 53800 46800 53800 48700 4 +N 53900 46300 54000 46300 4 +N 54000 46300 54000 48700 4 +N 53800 44300 53800 42400 4 +N 53900 44800 54000 44800 4 +N 54000 44800 54000 42400 4 +N 51500 43300 51600 43300 4 +N 51600 42400 51600 44800 4 +N 51500 44800 51600 44800 4 +C 58400 45800 1 0 0 asic-pmos-1.sym +{ +T 59800 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 59200 46600 5 10 1 1 0 0 1 +refdes=M16 +T 59200 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 59200 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 59200 45900 5 8 1 0 0 0 1 +l=1u +} +C 58400 44300 1 0 0 asic-nmos-1.sym +{ +T 59800 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 59200 45100 5 10 1 1 0 0 1 +refdes=M17 +T 59200 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 59200 44600 5 8 1 0 0 0 1 +w='Wunit' +T 59200 44400 5 8 1 0 0 0 1 +l=1u +} +C 60700 42800 1 0 1 asic-nmos-1.sym +{ +T 59300 43600 5 8 0 0 0 6 1 +device=NMOS_TRANSISTOR +T 59900 43600 5 10 1 1 0 6 1 +refdes=M18 +T 59900 43400 5 8 1 1 0 6 1 +model-name=nmos4 +T 59900 43100 5 8 1 0 0 6 1 +w='Wunit' +T 59900 42900 5 8 1 0 0 6 1 +l=1u +} +N 58100 44100 58100 46300 4 +N 58100 46300 58400 46300 4 +N 58100 44800 58400 44800 4 +C 61900 45300 1 0 0 spice-subcircuit-IO-1.sym +{ +T 62400 45900 5 10 1 1 180 0 1 +refdes=P1 +} +N 55000 44100 58100 44100 4 +{ +T 57100 44200 5 10 1 1 0 0 1 +netname=\_enable\_ +} +N 61500 42400 61500 44300 4 +N 59100 44800 59200 44800 4 +N 59200 44800 59200 42400 4 +N 60100 42800 60100 42400 4 +N 59000 44300 59000 42400 4 +N 60000 43300 59900 43300 4 +N 59900 43300 59900 42400 4 +N 59000 45800 59000 45300 4 +C 58400 47300 1 0 0 asic-pmos-1.sym +{ +T 59800 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 59200 48100 5 10 1 1 0 0 1 +refdes=M15 +T 59200 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 59200 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 59200 47400 5 8 1 0 0 0 1 +l=1u +} +N 59000 46800 59000 47300 4 +C 60900 45800 1 0 0 asic-pmos-1.sym +{ +T 62300 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 61700 46600 5 10 1 1 0 0 1 +refdes=M19 +T 61700 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 61700 45900 5 8 1 0 0 0 1 +l=1u +T 61700 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +} +C 60900 44300 1 0 0 asic-nmos-1.sym +{ +T 62300 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 61700 45100 5 10 1 1 0 0 1 +refdes=M20 +T 61700 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 61700 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 61700 44400 5 8 1 0 0 0 1 +l=1u +} +N 60600 46300 60900 46300 4 +N 60600 44800 60900 44800 4 +N 61600 44800 61700 44800 4 +N 61500 45800 61500 45300 4 +N 62100 45600 61500 45600 4 +{ +T 61800 45700 5 10 1 1 0 0 1 +netname=XO +} +N 60600 46300 60600 44800 4 +N 59000 45600 60600 45600 4 +N 60100 45600 60100 43800 4 +N 61700 44800 61700 42400 4 +N 61700 48700 61700 46300 4 +N 61600 46300 61700 46300 4 +N 61500 46800 61500 48700 4 +N 59000 48300 59000 48700 4 +N 58400 47800 58000 47800 4 +{ +T 58200 47900 5 10 1 1 0 0 1 +netname=XI +} +N 60900 43300 60700 43300 4 +{ +T 60700 43400 5 10 1 1 0 0 1 +netname=XI +} +N 59100 46300 59200 46300 4 +N 59200 46300 59200 48700 4 +T 57600 41700 9 10 1 0 0 0 3 +Clock Gate: +- gate Clock input with latched Enable + (via NOR) +T 61000 41900 9 10 1 0 0 0 2 +Clock Output Buffer: +- higher driving strength +N 59100 47800 59200 47800 4 diff --git a/Sources/geda/CGN2.sym b/Sources/geda/CGN2.sym new file mode 100644 index 00000000..21748006 --- /dev/null +++ b/Sources/geda/CGN2.sym @@ -0,0 +1,69 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=XO +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=EN +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 358 592 9 10 1 1 0 0 1 +pinlabel=XI +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=CGN2 +T 1292 2292 8 10 0 1 0 0 1 +description=Clock Gating Buffer for negative Clock, Drive 2x +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=CGN2.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/CGP2.sch b/Sources/geda/CGP2.sch new file mode 100644 index 00000000..3409804c --- /dev/null +++ b/Sources/geda/CGP2.sch @@ -0,0 +1,537 @@ +v 20130925 2 +T 52800 40100 9 10 1 0 0 0 1 +1 +T 54200 40100 9 10 1 0 0 0 1 +1 +N 42200 43200 42200 47700 4 +N 42000 48600 59100 48600 4 +{ +T 42100 48700 5 10 1 1 0 0 1 +netname=VDD +} +N 43100 48600 43100 48200 4 +N 43300 47700 43200 47700 4 +N 43300 47700 43300 48600 4 +N 41900 42300 59100 42300 4 +{ +T 42100 42400 5 10 1 1 0 0 1 +netname=GND +} +C 42500 47200 1 0 0 asic-pmos-1.sym +{ +T 43900 48000 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 43300 48000 5 10 1 1 0 0 1 +refdes=M1 +T 43300 47800 5 8 1 1 0 0 1 +model-name=pmos4 +T 43300 47500 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 43300 47300 5 8 1 0 0 0 1 +l=1u +} +T 45500 40900 9 10 1 0 0 0 2 +see LATN (Q + QN stages) which latches Clock Enable signal +and Gated Clock / Clock Gating Buffer for concept +B 45300 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 52100 40000 1 0 0 cvstitleblock-1.sym +{ +T 52700 40400 5 10 1 1 0 0 1 +date=2019-09-04 +T 56600 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 56600 40100 5 10 1 1 0 0 1 +auth= +T 52700 40700 5 10 1 1 0 0 1 +fname=CGP2.sch +T 55900 41100 5 14 1 1 0 4 1 +title=CGP2 - Clock Gating Buffer for positive Clock, Drive 2x +} +C 43800 48800 1 0 0 spice-model-1.sym +{ +T 43900 49400 5 10 1 1 0 0 1 +refdes=A1 +T 45100 49100 5 10 1 1 0 0 1 +model-name=nmos4 +T 44300 48900 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 47100 48800 1 0 0 spice-model-1.sym +{ +T 47200 49400 5 10 1 1 0 0 1 +refdes=A2 +T 48400 49100 5 10 1 1 0 0 1 +model-name=pmos4 +T 47600 48900 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 47600 45800 1 180 0 spice-subcircuit-IO-1.sym +{ +T 47400 45800 5 10 1 1 0 0 1 +refdes=P2 +} +C 42100 45800 1 180 0 spice-subcircuit-IO-1.sym +{ +T 41900 45800 5 10 1 1 0 0 1 +refdes=P3 +} +C 42200 48900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 42200 48900 5 10 1 1 0 0 1 +refdes=P4 +} +C 42100 42600 1 180 0 spice-subcircuit-IO-1.sym +{ +T 42100 42600 5 10 1 1 0 0 1 +refdes=P5 +} +C 50400 49000 1 0 0 spice-subcircuit-LL-1.sym +{ +T 50500 49400 5 10 1 1 0 0 1 +refdes=A3 +T 50500 49100 5 10 1 1 0 0 1 +model-name=CGP2 +} +C 53500 49000 1 0 0 spice-directive-1.sym +{ +T 53600 49300 5 10 0 1 0 0 1 +device=directive +T 53600 49400 5 10 1 1 0 0 1 +refdes=A4 +T 53600 49100 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 56300 49000 1 0 0 spice-directive-1.sym +{ +T 56400 49300 5 10 0 1 0 0 1 +device=directive +T 56400 49400 5 10 1 1 0 0 1 +refdes=A5 +T 56400 49100 5 10 1 1 0 0 1 +value=.PARAM PNratio=2 +} +C 44500 47200 1 0 0 asic-pmos-1.sym +{ +T 45900 48000 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 45300 48000 5 10 1 1 0 0 1 +refdes=M3 +T 45300 47800 5 8 1 1 0 0 1 +model-name=pmos4 +T 45300 47500 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 45300 47300 5 8 1 0 0 0 1 +l=1u +} +C 44500 42700 1 0 0 asic-nmos-1.sym +{ +T 45900 43500 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 45300 43500 5 10 1 1 0 0 1 +refdes=M4 +T 45300 43300 5 8 1 1 0 0 1 +model-name=nmos4 +T 45300 43000 5 8 1 0 0 0 1 +w='Wunit' +T 45300 42800 5 8 1 0 0 0 1 +l=1u +} +C 42500 42700 1 0 0 asic-nmos-1.sym +{ +T 43900 43500 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 43300 43500 5 10 1 1 0 0 1 +refdes=M2 +T 43300 43300 5 8 1 1 0 0 1 +model-name=nmos4 +T 43300 43000 5 8 1 0 0 0 1 +w='Wunit' +T 43300 42800 5 8 1 0 0 0 1 +l=1u +} +N 41900 45500 42200 45500 4 +{ +T 41900 45600 5 10 1 1 0 0 1 +netname=XI +} +N 42200 47700 42500 47700 4 +N 42200 43200 42500 43200 4 +N 43100 42700 43100 42300 4 +N 43200 43200 43300 43200 4 +N 43300 43200 43300 42300 4 +N 43100 47200 43100 43700 4 +N 44200 47700 44500 47700 4 +N 44200 43200 44500 43200 4 +N 44200 47700 44200 43200 4 +N 43100 45500 44200 45500 4 +{ +T 43500 45600 5 10 1 1 0 0 1 +netname=clk180 +} +N 45100 47200 45100 43700 4 +N 45100 48200 45100 48600 4 +N 45100 42700 45100 42300 4 +N 45200 47700 45300 47700 4 +N 45300 47700 45300 48600 4 +N 45200 43200 45300 43200 4 +N 45300 43200 45300 42300 4 +N 45100 45500 45900 45500 4 +{ +T 45400 45600 5 10 1 1 0 0 1 +netname=clk360 +} +C 48100 45700 1 0 0 asic-pmos-1.sym +{ +T 49500 46500 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 48900 46500 5 10 1 1 0 0 1 +refdes=M6 +T 48900 46300 5 8 1 1 0 0 1 +model-name=pmos4 +T 48900 46000 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 48900 45800 5 8 1 0 0 0 1 +l=1u +} +C 48100 44200 1 0 0 asic-nmos-1.sym +{ +T 49500 45000 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 48900 45000 5 10 1 1 0 0 1 +refdes=M7 +T 48900 44800 5 8 1 1 0 0 1 +model-name=nmos4 +T 48900 44500 5 8 1 0 0 0 1 +w='2*Wunit' +T 48900 44300 5 8 1 0 0 0 1 +l=1u +} +C 48100 42700 1 0 0 asic-nmos-1.sym +{ +T 49500 43500 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 48900 43500 5 10 1 1 0 0 1 +refdes=M8 +T 48900 43300 5 8 1 1 0 0 1 +model-name=nmos4 +T 48900 43000 5 8 1 0 0 0 1 +w='2*Wunit' +T 48900 42800 5 8 1 0 0 0 1 +l=1u +} +C 48100 47200 1 0 0 asic-pmos-1.sym +{ +T 49500 48000 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 48900 48000 5 10 1 1 0 0 1 +refdes=M5 +T 48900 47800 5 8 1 1 0 0 1 +model-name=pmos4 +T 48900 47500 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 48900 47300 5 8 1 0 0 0 1 +l=1u +} +N 48100 47700 47200 47700 4 +{ +T 47500 47800 5 10 1 1 0 0 1 +netname=clk360 +} +N 48100 43200 47200 43200 4 +{ +T 47500 43300 5 10 1 1 0 0 1 +netname=clk180 +} +N 47800 46200 48100 46200 4 +N 48100 44700 47800 44700 4 +N 47800 44700 47800 46200 4 +N 47400 45500 47800 45500 4 +{ +T 47400 45600 5 10 1 1 0 0 1 +netname=E +} +N 48700 48200 48700 48600 4 +N 48700 47200 48700 46700 4 +N 48700 45700 48700 45200 4 +N 48700 44200 48700 43700 4 +N 48700 42700 48700 42300 4 +T 43100 41600 9 10 1 0 0 0 3 +Double Clock Buffering: +- de-coupling high load +- 2-phase clock generation +C 50500 45700 1 0 0 asic-pmos-1.sym +{ +T 51900 46500 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51300 46500 5 10 1 1 0 0 1 +refdes=M9 +T 51300 46300 5 8 1 1 0 0 1 +model-name=pmos4 +T 51300 46000 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 51300 45800 5 8 1 0 0 0 1 +l=1u +} +C 50500 44200 1 0 0 asic-nmos-1.sym +{ +T 51900 45000 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51300 45000 5 10 1 1 0 0 1 +refdes=M10 +T 51300 44800 5 8 1 1 0 0 1 +model-name=nmos4 +T 51300 44500 5 8 1 0 0 0 1 +w='Wunit' +T 51300 44300 5 8 1 0 0 0 1 +l=1u +} +N 50200 46200 50500 46200 4 +N 50500 44700 50200 44700 4 +N 50200 44700 50200 46200 4 +N 51100 45700 51100 45200 4 +C 52900 45700 1 0 0 asic-pmos-1.sym +{ +T 54300 46500 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 53700 46500 5 10 1 1 0 0 1 +refdes=M12 +T 53700 46300 5 8 1 1 0 0 1 +model-name=pmos4 +T 53700 46000 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 53700 45800 5 8 1 0 0 0 1 +l=1u +} +C 52900 44200 1 0 0 asic-nmos-1.sym +{ +T 54300 45000 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 53700 45000 5 10 1 1 0 0 1 +refdes=M13 +T 53700 44800 5 8 1 1 0 0 1 +model-name=nmos4 +T 53700 44500 5 8 1 0 0 0 1 +w='2*Wunit' +T 53700 44300 5 8 1 0 0 0 1 +l=1u +} +C 52900 42700 1 0 0 asic-nmos-1.sym +{ +T 54300 43500 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 53700 43500 5 10 1 1 0 0 1 +refdes=M14 +T 53700 43300 5 8 1 1 0 0 1 +model-name=nmos4 +T 53700 43000 5 8 1 0 0 0 1 +w='2*Wunit' +T 53700 42800 5 8 1 0 0 0 1 +l=1u +} +C 52900 47200 1 0 0 asic-pmos-1.sym +{ +T 54300 48000 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 53700 48000 5 10 1 1 0 0 1 +refdes=M11 +T 53700 47800 5 8 1 1 0 0 1 +model-name=pmos4 +T 53700 47500 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 53700 47300 5 8 1 0 0 0 1 +l=1u +} +N 52900 47700 52000 47700 4 +{ +T 52300 47800 5 10 1 1 0 0 1 +netname=clk180 +} +N 52900 43200 52000 43200 4 +{ +T 52300 43300 5 10 1 1 0 0 1 +netname=clk360 +} +N 52600 46200 52900 46200 4 +N 52900 44700 52600 44700 4 +N 52600 44000 52600 46200 4 +N 51100 45500 52600 45500 4 +N 53500 48200 53500 48600 4 +N 53500 47200 53500 46700 4 +N 53500 45700 53500 45200 4 +N 53500 44200 53500 43700 4 +N 53500 42700 53500 42300 4 +N 48700 45500 50200 45500 4 +N 49600 45500 49600 47000 4 +N 49600 47000 54500 47000 4 +{ +T 52100 47100 5 10 1 1 0 0 1 +netname=qn +} +N 53500 45500 54500 45500 4 +N 54500 45500 54500 47000 4 +T 47900 41600 9 10 1 0 0 0 3 +Data input switch: +- (inverting) tri-state driver +- low-active transparent +T 50800 41800 9 10 1 0 0 0 2 +Q Stage: +- inverter +T 52200 41600 9 10 1 0 0 0 3 +QN Stage: +- (inverting) tri-state driver +- high-active transparent +N 48800 47700 48900 47700 4 +N 48900 46200 48900 48600 4 +N 48800 46200 48900 46200 4 +N 53600 47700 53700 47700 4 +N 53700 46200 53700 48600 4 +N 53600 46200 53700 46200 4 +N 53600 43200 53700 43200 4 +N 53700 42300 53700 44700 4 +N 53600 44700 53700 44700 4 +N 51100 46700 51100 48600 4 +N 51200 46200 51300 46200 4 +N 51300 46200 51300 48600 4 +N 51100 44200 51100 42300 4 +N 51200 44700 51300 44700 4 +N 51300 44700 51300 42300 4 +N 48800 43200 48900 43200 4 +N 48900 42300 48900 44700 4 +N 48800 44700 48900 44700 4 +C 55800 45700 1 0 0 asic-pmos-1.sym +{ +T 57200 46500 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 56600 46500 5 10 1 1 0 0 1 +refdes=M16 +T 56600 46300 5 8 1 1 0 0 1 +model-name=pmos4 +T 56600 45800 5 8 1 0 0 0 1 +l=1u +T 56600 46000 5 8 1 0 0 0 1 +w='PNratio*Wunit' +} +C 55800 44200 1 0 0 asic-nmos-1.sym +{ +T 57200 45000 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56600 45000 5 10 1 1 0 0 1 +refdes=M17 +T 56600 44800 5 8 1 1 0 0 1 +model-name=nmos4 +T 56600 44300 5 8 1 0 0 0 1 +l=1u +T 56600 44500 5 8 1 0 0 0 1 +w='2*Wunit' +} +N 56400 45700 56400 45200 4 +N 56400 46700 56400 48600 4 +N 56500 46200 56600 46200 4 +N 56600 46200 56600 48600 4 +N 56500 44700 56600 44700 4 +N 56600 44700 56600 42300 4 +T 54900 41600 9 10 1 0 0 0 3 +Clock Gate: +- gate Clock input with latched Enable + (via NAND) +C 58300 45700 1 0 0 asic-pmos-1.sym +{ +T 59700 46500 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 59100 46500 5 10 1 1 0 0 1 +refdes=M19 +T 59100 46300 5 8 1 1 0 0 1 +model-name=pmos4 +T 59100 45800 5 8 1 0 0 0 1 +l=1u +T 59100 46000 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +} +C 58300 44200 1 0 0 asic-nmos-1.sym +{ +T 59700 45000 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 59100 45000 5 10 1 1 0 0 1 +refdes=M20 +T 59100 44800 5 8 1 1 0 0 1 +model-name=nmos4 +T 59100 44300 5 8 1 0 0 0 1 +l=1u +T 59100 44500 5 8 1 0 0 0 1 +w='2*Wunit' +} +N 58900 45700 58900 45200 4 +N 58900 46700 58900 48600 4 +N 59000 46200 59100 46200 4 +N 59100 46200 59100 48600 4 +N 58900 44200 58900 42300 4 +N 59000 44700 59100 44700 4 +N 59100 44700 59100 42300 4 +T 58100 41800 9 10 1 0 0 0 2 +Clock Output Buffer: +- higher driving strength +N 55500 44000 55500 46200 4 +N 58000 46200 58000 44700 4 +N 55500 46200 55800 46200 4 +N 55500 44700 55800 44700 4 +N 58000 46200 58300 46200 4 +N 58000 44700 58300 44700 4 +C 55800 42700 1 0 0 asic-nmos-1.sym +{ +T 57200 43500 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56600 43500 5 10 1 1 0 0 1 +refdes=M18 +T 56600 43300 5 8 1 1 0 0 1 +model-name=nmos4 +T 56600 43000 5 8 1 0 0 0 1 +w='2*Wunit' +T 56600 42800 5 8 1 0 0 0 1 +l=1u +} +N 56400 44200 56400 43700 4 +N 56400 42700 56400 42300 4 +N 56500 43200 56600 43200 4 +N 55400 43200 55800 43200 4 +{ +T 55500 43300 5 10 1 1 0 0 1 +netname=XI +} +N 56400 45500 58000 45500 4 +C 59300 45200 1 0 0 spice-subcircuit-IO-1.sym +{ +T 59700 45700 5 10 1 1 180 0 1 +refdes=P1 +} +N 58900 45500 59500 45500 4 +{ +T 59100 45600 5 10 1 1 0 0 1 +netname=XO +} +N 52600 44000 55500 44000 4 +{ +T 54600 44100 5 10 1 1 0 0 1 +netname=enable +} +C 58000 47200 1 0 1 asic-pmos-1.sym +{ +T 56600 48000 5 8 0 0 0 6 1 +device=PMOS_TRANSISTOR +T 57200 48000 5 10 1 1 0 6 1 +refdes=M15 +T 57200 47800 5 8 1 1 0 6 1 +model-name=pmos4 +T 57200 47500 5 8 1 0 0 6 1 +w='PNratio*Wunit' +T 57200 47300 5 8 1 0 0 6 1 +l=1u +} +N 57400 48200 57400 48600 4 +N 57300 47700 57200 47700 4 +N 57200 47700 57200 48600 4 +N 58400 47700 58000 47700 4 +{ +T 58200 47800 5 10 1 1 0 0 1 +netname=XI +} +N 57400 47200 57400 45500 4 diff --git a/Sources/geda/CGP2.sym b/Sources/geda/CGP2.sym new file mode 100644 index 00000000..ee219ed7 --- /dev/null +++ b/Sources/geda/CGP2.sym @@ -0,0 +1,69 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=XO +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=E +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 358 592 9 10 1 1 0 0 1 +pinlabel=XI +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=CGP2 +T 1292 2292 8 10 0 1 0 0 1 +description=Clock Gating Buffer for positive Clock, Drive 2x +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=CGP2.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/DFFN.sch b/Sources/geda/DFFN.sch new file mode 100644 index 00000000..810b4670 --- /dev/null +++ b/Sources/geda/DFFN.sch @@ -0,0 +1,629 @@ +v 20130925 2 +T 57900 40100 9 10 1 0 0 0 1 +1 +T 59500 40100 9 10 1 0 0 0 1 +1 +N 44900 43300 44900 47800 4 +N 44800 48700 64300 48700 4 +{ +T 44900 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 45800 48700 45800 48300 4 +N 46000 47800 45900 47800 4 +N 46000 47800 46000 48700 4 +N 44800 42400 64300 42400 4 +{ +T 45000 42500 5 10 1 1 0 0 1 +netname=GND +} +C 45200 47300 1 0 0 asic-pmos-1.sym +{ +T 46600 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 46000 48100 5 10 1 1 0 0 1 +refdes=M1 +T 46000 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 46000 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 46000 47400 5 8 1 0 0 0 1 +l=1u +} +T 50600 40500 9 10 1 0 0 0 4 +see [UYEMURA, 1992] +Uyemura, John P.: +"Circuit Design for CMOS VLSI." 1st Edition, 1992. +Figure 5.23, Page 187. +B 50500 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 57300 40000 1 0 0 cvstitleblock-1.sym +{ +T 57900 40400 5 10 1 1 0 0 1 +date=2019-09-06 +T 61800 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 61800 40100 5 10 1 1 0 0 1 +auth= +T 57900 40700 5 10 1 1 0 0 1 +fname=DFFN.sch +T 60300 41100 5 14 1 1 0 4 1 +title=DFFN - Negative edge-triggered D-FlipFlop +} +C 48300 48900 1 0 0 spice-model-1.sym +{ +T 48400 49500 5 10 1 1 0 0 1 +refdes=A1 +T 49600 49200 5 10 1 1 0 0 1 +model-name=nmos4 +T 48800 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 51600 48900 1 0 0 spice-model-1.sym +{ +T 51700 49500 5 10 1 1 0 0 1 +refdes=A2 +T 52900 49200 5 10 1 1 0 0 1 +model-name=pmos4 +T 52100 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 50300 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50100 45900 5 10 1 1 0 0 1 +refdes=P2 +} +C 44800 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 44600 45900 5 10 1 1 0 0 1 +refdes=P3 +} +C 45000 49000 1 180 0 spice-subcircuit-IO-1.sym +{ +T 45000 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64300 42900 5 8 1 0 0 0 1 +l=1u +} +C 63500 47300 1 0 0 asic-pmos-1.sym +{ +T 64900 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 64300 48100 5 10 1 1 0 0 1 +refdes=M21 +T 64300 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 64300 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 64300 47400 5 8 1 0 0 0 1 +l=1u +} +N 63500 47800 62600 47800 4 +{ +T 62900 47900 5 10 1 1 0 0 1 +netname=clk180 +} +N 63500 43300 62600 43300 4 +{ +T 62900 43400 5 10 1 1 0 0 1 +netname=clk360 +} +N 63200 46300 63500 46300 4 +N 63500 44800 63200 44800 4 +N 63200 44800 63200 46300 4 +N 61700 45600 63200 45600 4 +{ +T 62700 45700 5 10 1 1 0 0 1 +netname=Q +} +N 64100 48300 64100 48700 4 +N 64100 47300 64100 46800 4 +N 64100 45800 64100 45300 4 +N 64100 44300 64100 43800 4 +N 64100 42800 64100 42400 4 +N 62900 44700 62900 45600 4 +N 59300 45600 60800 45600 4 +N 60200 45600 60200 47100 4 +N 60200 47100 65100 47100 4 +{ +T 62700 47200 5 10 1 1 0 0 1 +netname=\_qs\_ +} +N 64100 45600 65100 45600 4 +N 65100 45600 65100 47100 4 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b/Sources/geda/DFFN.sym @@ -0,0 +1,72 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 700 400 600 3 0 0 0 -1 -1 +L 400 600 300 500 3 0 0 0 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=Q +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=D +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 200 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 450 550 9 10 1 1 0 0 1 +pinlabel=XN +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=DFFN +T 1292 2292 8 10 0 1 0 0 1 +description=Low-active D-FLipFlop +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATN.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/DFFP.sch b/Sources/geda/DFFP.sch new file mode 100644 index 00000000..9feea909 --- /dev/null +++ b/Sources/geda/DFFP.sch @@ -0,0 +1,629 @@ +v 20130925 2 +T 57900 40100 9 10 1 0 0 0 1 +1 +T 59500 40100 9 10 1 0 0 0 1 +1 +N 44900 43300 44900 47800 4 +N 44800 48700 64300 48700 4 +{ +T 44900 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 45800 48700 45800 48300 4 +N 46000 47800 45900 47800 4 +N 46000 47800 46000 48700 4 +N 44800 42400 64300 42400 4 +{ +T 45000 42500 5 10 1 1 0 0 1 +netname=GND +} +C 45200 47300 1 0 0 asic-pmos-1.sym +{ +T 46600 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 46000 48100 5 10 1 1 0 0 1 +refdes=M1 +T 46000 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 46000 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 46000 47400 5 8 1 0 0 0 1 +l=1u +} +T 50600 40500 9 10 1 0 0 0 4 +see [UYEMURA, 1992] +Uyemura, John P.: +"Circuit Design for CMOS VLSI." 1st Edition, 1992. +Figure 5.23, Page 187. +B 50500 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 57300 40000 1 0 0 cvstitleblock-1.sym +{ +T 57900 40400 5 10 1 1 0 0 1 +date=2019-09-07 +T 61800 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 61800 40100 5 10 1 1 0 0 1 +auth= +T 57900 40700 5 10 1 1 0 0 1 +fname=DFFP.sch +T 60300 41100 5 14 1 1 0 4 1 +title=DFFP - Positive edge-triggered D-FlipFlop +} +C 48300 48900 1 0 0 spice-model-1.sym +{ +T 48400 49500 5 10 1 1 0 0 1 +refdes=A1 +T 49600 49200 5 10 1 1 0 0 1 +model-name=nmos4 +T 48800 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 51600 48900 1 0 0 spice-model-1.sym +{ +T 51700 49500 5 10 1 1 0 0 1 +refdes=A2 +T 52900 49200 5 10 1 1 0 0 1 +model-name=pmos4 +T 52100 49000 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 50300 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50100 45900 5 10 1 1 0 0 1 +refdes=P2 +} +C 44800 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 44600 45900 5 10 1 1 0 0 1 +refdes=P3 +} +C 45000 49000 1 180 0 spice-subcircuit-IO-1.sym +{ +T 45000 49000 5 10 1 1 0 0 1 +refdes=P4 +} +C 45000 42700 1 180 0 spice-subcircuit-IO-1.sym +{ +T 45000 42700 5 10 1 1 0 0 1 +refdes=P5 +} +C 54900 49100 1 0 0 spice-subcircuit-LL-1.sym +{ +T 55000 49500 5 10 1 1 0 0 1 +refdes=A3 +T 55000 49200 5 10 1 1 0 0 1 +model-name=DFFP +} +C 58200 49100 1 0 0 spice-directive-1.sym +{ +T 58300 49400 5 10 0 1 0 0 1 +device=directive +T 58300 49500 5 10 1 1 0 0 1 +refdes=A4 +T 58300 49200 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 61300 49100 1 0 0 spice-directive-1.sym +{ +T 61400 49400 5 10 0 1 0 0 1 +device=directive +T 61400 49500 5 10 1 1 0 0 1 +refdes=A5 +T 61400 49200 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5 10 1 1 0 0 1 +netname=clk360 +} +N 55300 46300 55600 46300 4 +N 55600 44800 55300 44800 4 +N 55300 44800 55300 46300 4 +N 53800 45600 55300 45600 4 +{ +T 54800 45700 5 10 1 1 0 0 1 +netname=qm +} +N 56200 48300 56200 48700 4 +N 56200 47300 56200 46800 4 +N 56200 45800 56200 45300 4 +N 56200 44300 56200 43800 4 +N 56200 42800 56200 42400 4 +N 55000 44100 55000 45600 4 +N 51400 45600 52900 45600 4 +N 52300 45600 52300 47100 4 +N 52300 47100 57200 47100 4 +{ +T 54800 47200 5 10 1 1 0 0 1 +netname=\_qm\_ +} +N 56200 45600 57200 45600 4 +N 57200 45600 57200 47100 4 +T 50100 41700 9 10 1 0 0 0 3 +Master Latch input switch: +- (inverting) tri-state driver +- low-active transparent +T 53500 41900 9 10 1 0 0 0 2 +Master Q Stage: +- inverter +T 54900 41700 9 10 1 0 0 0 3 +Master QN Stage: +- (inverting) tri-state driver +- high-active transparent +N 51500 47800 51600 47800 4 +N 51600 46300 51600 48700 4 +N 51500 46300 51600 46300 4 +N 56300 47800 56400 47800 4 +N 56400 46300 56400 48700 4 +N 56300 46300 56400 46300 4 +N 56300 43300 56400 43300 4 +N 56400 42400 56400 44800 4 +N 56300 44800 56400 44800 4 +N 53800 46800 53800 48700 4 +N 53900 46300 54000 46300 4 +N 54000 46300 54000 48700 4 +N 53800 44300 53800 42400 4 +N 53900 44800 54000 44800 4 +N 54000 44800 54000 42400 4 +N 51500 43300 51600 43300 4 +N 51600 42400 51600 44800 4 +N 51500 44800 51600 44800 4 +C 62600 44900 1 270 0 spice-subcircuit-IO-1.sym +{ +T 63100 44500 5 10 1 1 90 0 1 +refdes=P1 +} +C 58700 45800 1 0 0 asic-pmos-1.sym +{ +T 60100 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 59500 46600 5 10 1 1 0 0 1 +refdes=M16 +T 59500 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 59500 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 59500 45900 5 8 1 0 0 0 1 +l=1u +} +C 58700 44300 1 0 0 asic-nmos-1.sym +{ +T 60100 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 59500 45100 5 10 1 1 0 0 1 +refdes=M17 +T 59500 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 59500 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 59500 44400 5 8 1 0 0 0 1 +l=1u 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64100 48300 64100 48700 4 +N 64100 47300 64100 46800 4 +N 64100 45800 64100 45300 4 +N 64100 44300 64100 43800 4 +N 64100 42800 64100 42400 4 +N 62900 44700 62900 45600 4 +N 59300 45600 60800 45600 4 +N 60200 45600 60200 47100 4 +N 60200 47100 65100 47100 4 +{ +T 62700 47200 5 10 1 1 0 0 1 +netname=\_qs\_ +} +N 64100 45600 65100 45600 4 +N 65100 45600 65100 47100 4 +N 59400 47800 59500 47800 4 +N 59500 46300 59500 48700 4 +N 59400 46300 59500 46300 4 +N 64200 47800 64300 47800 4 +N 64300 46300 64300 48700 4 +N 64200 46300 64300 46300 4 +N 64200 43300 64300 43300 4 +N 64300 42400 64300 44800 4 +N 64200 44800 64300 44800 4 +N 61700 46800 61700 48700 4 +N 61800 46300 61900 46300 4 +N 61900 46300 61900 48700 4 +N 61700 44300 61700 42400 4 +N 61800 44800 61900 44800 4 +N 61900 44800 61900 42400 4 +N 59400 43300 59500 43300 4 +N 59500 42400 59500 44800 4 +N 59400 44800 59500 44800 4 +T 58000 41700 9 10 1 0 0 0 3 +Slave Latch input switch: +- (inverting) tri-state driver +- high-active transparent +T 61400 41900 9 10 1 0 0 0 2 +Slave Q Stage: +- inverter +T 62800 41700 9 10 1 0 0 0 3 +Slave QN Stage: +- (inverting) tri-state driver +- low-active transparent +N 58000 44100 58000 45600 4 +N 58000 44100 55000 44100 4 diff --git a/Sources/geda/DFFP.sym b/Sources/geda/DFFP.sym new file mode 100644 index 00000000..e5a98af3 --- /dev/null +++ b/Sources/geda/DFFP.sym @@ -0,0 +1,71 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +L 300 700 400 600 3 0 0 0 -1 -1 +L 400 600 300 500 3 0 0 0 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=Q +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=D +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 450 550 9 10 1 1 0 0 1 +pinlabel=X +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=DFFP +T 1292 2292 8 10 0 1 0 0 1 +description=High-active D-FlipFlop +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATP.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/FO4.sch b/Sources/geda/FO4.sch new file mode 100644 index 00000000..e310a367 --- /dev/null +++ b/Sources/geda/FO4.sch @@ -0,0 +1,190 @@ +v 20130925 2 +C 51600 43000 1 0 0 asic-nmos-1.sym +{ +T 53000 43800 5 8 0 0 0 0 1 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0 0 0 1 +w='Fan*Fan*PNratio*Wunit' +T 54800 44600 5 8 1 0 0 0 1 +l=1u +} +C 49500 40000 1 0 0 cvstitleblock-1.sym +{ +T 50100 40400 5 10 1 1 0 0 1 +date=2019-08-27 +T 54000 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 54000 40100 5 10 1 1 0 0 1 +auth= +T 50100 40700 5 10 1 1 0 0 1 +fname=FO4.sch +T 52900 41100 5 14 1 1 0 4 1 +title=FO4 - TBench Load with high (4x) fan-in +} +C 48000 46500 1 0 0 spice-model-1.sym +{ +T 48100 47100 5 10 1 1 0 0 1 +refdes=A1 +T 49300 46800 5 10 1 1 0 0 1 +model-name=nmos4 +T 48500 46600 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 51300 46500 1 0 0 spice-model-1.sym +{ +T 51400 47100 5 10 1 1 0 0 1 +refdes=A2 +T 52600 46800 5 10 1 1 0 0 1 +model-name=pmos4 +T 51800 46600 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 55400 44000 1 0 0 spice-subcircuit-IO-1.sym +{ +T 55800 44600 5 10 1 1 180 0 1 +refdes=P1 +} +C 50900 44600 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50500 44500 5 10 1 1 0 0 1 +refdes=P2 +} +N 51300 45000 51600 45000 4 +N 51600 43500 51300 43500 4 +N 51300 43500 51300 45000 4 +N 52200 44500 52200 44000 4 +N 53700 45000 54000 45000 4 +N 54000 43500 53700 43500 4 +N 53700 43500 53700 45000 4 +N 52200 44300 53700 44300 4 +N 54600 46000 54600 45500 4 +N 54600 44500 54600 44000 4 +N 54600 43000 54600 42400 4 +N 54600 44300 55600 44300 4 +{ +T 55200 44400 5 10 1 1 0 0 1 +netname=Z +} +N 50700 44300 51300 44300 4 +{ +T 50900 44400 5 10 1 1 0 0 1 +netname=A +} +N 50600 46000 54800 46000 4 +{ +T 50900 46100 5 10 1 1 0 0 1 +netname=VDD +} +N 50700 42400 54800 42400 4 +{ +T 51000 42500 5 10 1 1 0 0 1 +netname=GND +} +T 51700 41900 9 10 1 0 0 0 2 +1. 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650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=5 +T 358 592 9 10 1 1 0 0 1 +pinlabel=XN +T 208 642 5 10 0 1 0 6 1 +pinnumber=5 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=6 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=6 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=7 +T 1250 300 5 10 0 0 270 6 1 +pinseq=7 +} +T 392 992 5 16 1 1 0 0 1 +device=LATESN +T 1292 2292 8 10 0 1 0 0 1 +description=Low-active D-Latch w/ clock-enable + low-active Set +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATESN.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/LATESP.sch b/Sources/geda/LATESP.sch new file mode 100644 index 00000000..c2289b69 --- /dev/null +++ b/Sources/geda/LATESP.sch @@ -0,0 +1,503 @@ +v 20130925 2 +T 53100 40100 9 10 1 0 0 0 1 +1 +T 51700 40100 9 10 1 0 0 0 1 +1 +N 43300 43300 43300 47800 4 +N 42800 48700 57900 48700 4 +{ +T 42900 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 44200 48700 44200 48300 4 +N 44400 47800 44300 47800 4 +N 44400 47800 44400 48700 4 +N 42700 42400 57900 42400 4 +{ +T 42900 42500 5 10 1 1 0 0 1 +netname=GND +} +C 43600 47300 1 0 0 asic-pmos-1.sym +{ +T 45000 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 44400 48100 5 10 1 1 0 0 1 +refdes=M1 +T 44400 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 44400 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 44400 47400 5 8 1 0 0 0 1 +l=1u +} +T 42800 41100 9 10 1 0 0 0 1 +set LATEP and LATSP +B 42700 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 51000 40000 1 0 0 cvstitleblock-1.sym +{ +T 51600 40400 5 10 1 1 0 0 1 +date=2019-09-04 +T 55500 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 55500 40100 5 10 1 1 0 0 1 +auth= +T 51600 40700 5 10 1 1 0 0 1 +fname=LATESP.sch +T 55000 41100 5 14 1 1 0 4 1 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asic-pmos-1.sym +{ +T 52200 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 46600 5 10 1 1 0 0 1 +refdes=M8 +T 51600 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 51600 45900 5 8 1 0 0 0 1 +l=1u +} +C 50800 44300 1 0 0 asic-nmos-1.sym +{ +T 52200 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 45100 5 10 1 1 0 0 1 +refdes=M9 +T 51600 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 44400 5 8 1 0 0 0 1 +l=1u +} +C 50800 42800 1 0 0 asic-nmos-1.sym +{ +T 52200 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 43600 5 10 1 1 0 0 1 +refdes=M10 +T 51600 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 43100 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 42900 5 8 1 0 0 0 1 +l=1u +} +C 50800 47300 1 0 0 asic-pmos-1.sym +{ +T 52200 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 48100 5 10 1 1 0 0 1 +refdes=M7 +T 51600 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 47600 5 8 1 0 0 0 1 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20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +V 700 1950 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=Q +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=D +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 700 2200 700 2000 1 0 0 +{ +T 650 1900 5 10 0 0 90 6 1 +pintype=in +T 700 1845 9 10 1 1 90 6 1 +pinlabel=SN +T 650 1995 5 10 0 1 90 0 1 +pinnumber=3 +T 650 1900 5 10 0 0 90 6 1 +pinseq=3 +} +P 0 1300 300 1300 1 0 0 +{ +T 100 1350 5 10 0 0 0 0 1 +pintype=in +T 100 1350 5 10 0 0 0 0 1 +pinseq=4 +T 358 1292 9 10 1 1 0 0 1 +pinlabel=E +T 208 1242 5 10 0 1 0 6 1 +pinnumber=4 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=5 +T 358 592 9 10 1 1 0 0 1 +pinlabel=X +T 208 642 5 10 0 1 0 6 1 +pinnumber=5 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=6 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=6 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=7 +T 1250 300 5 10 0 0 270 6 1 +pinseq=7 +} +T 392 992 5 16 1 1 0 0 1 +device=LATESP +T 1292 2292 8 10 0 1 0 0 1 +description=High-active D-Latch w/ clock-enable + low-active Set +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATESP.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/LATN.sch b/Sources/geda/LATN.sch new file mode 100644 index 00000000..59669b11 --- /dev/null +++ b/Sources/geda/LATN.sch @@ -0,0 +1,412 @@ +v 20130925 2 +T 50100 40100 9 10 1 0 0 0 1 +1 +T 51700 40100 9 10 1 0 0 0 1 +1 +N 44100 43300 44100 47800 4 +N 43300 48700 56400 48700 4 +{ +T 43400 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 45000 48700 45000 48300 4 +N 45200 47800 45100 47800 4 +N 45200 47800 45200 48700 4 +N 43200 42400 56400 42400 4 +{ +T 43400 42500 5 10 1 1 0 0 1 +netname=GND +} +C 44400 47300 1 0 0 asic-pmos-1.sym +{ +T 45800 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 45200 48100 5 10 1 1 0 0 1 +refdes=M1 +T 45200 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 45200 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 45200 47400 5 8 1 0 0 0 1 +l=1u +} +T 42800 40500 9 10 1 0 0 0 4 +see [WESTE, 1992] +Weste, H.E. Neil; ESHRAGHIAN, Kamran: +"Principles of CMOS VLSI Design: A Systems Perspective." 2nd Edition, 1992. +Figure 5.53, Page 326. +B 42700 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 49500 40000 1 0 0 cvstitleblock-1.sym +{ +T 50100 40400 5 10 1 1 0 0 1 +date=2019-09-02 +T 54000 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 54000 40100 5 10 1 1 0 0 1 +auth= +T 50100 40700 5 10 1 1 0 0 1 +fname=LATN.sch +T 52900 41100 5 14 1 1 0 4 1 +title=LATN - Low-active D-Latch +} +C 44000 49200 1 0 0 spice-model-1.sym +{ +T 44100 49800 5 10 1 1 0 0 1 +refdes=A1 +T 45300 49500 5 10 1 1 0 0 1 +model-name=nmos4 +T 44500 49300 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 47300 49200 1 0 0 spice-model-1.sym +{ +T 47400 49800 5 10 1 1 0 0 1 +refdes=A2 +T 48600 49500 5 10 1 1 0 0 1 +model-name=pmos4 +T 47800 49300 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 54700 44900 1 270 0 spice-subcircuit-IO-1.sym +{ +T 54700 44700 5 10 1 1 90 0 1 +refdes=P1 +} +C 50300 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50100 45900 5 10 1 1 0 0 1 +refdes=P2 +} +C 44000 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43800 45900 5 10 1 1 0 0 1 +refdes=P3 +} +C 43500 49000 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43500 49000 5 10 1 1 0 0 1 +refdes=P4 +} +C 43400 42700 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43400 42700 5 10 1 1 0 0 1 +refdes=P5 +} +C 50600 49400 1 0 0 spice-subcircuit-LL-1.sym +{ +T 50700 49800 5 10 1 1 0 0 1 +refdes=A3 +T 50700 49500 5 10 1 1 0 0 1 +model-name=LATN +} +C 40700 47500 1 0 0 spice-directive-1.sym +{ +T 40800 47800 5 10 0 1 0 0 1 +device=directive +T 40800 47900 5 10 1 1 0 0 1 +refdes=A4 +T 40800 47600 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 40700 46700 1 0 0 spice-directive-1.sym +{ +T 40800 47000 5 10 0 1 0 0 1 +device=directive +T 40800 47100 5 10 1 1 0 0 1 +refdes=A5 +T 40800 46800 5 10 1 1 0 0 1 +value=.PARAM PNratio=2 +} +C 46400 47300 1 0 0 asic-pmos-1.sym +{ +T 47800 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 47200 48100 5 10 1 1 0 0 1 +refdes=M3 +T 47200 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 47200 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 47200 47400 5 8 1 0 0 0 1 +l=1u +} +C 46400 42800 1 0 0 asic-nmos-1.sym +{ +T 47800 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 47200 43600 5 10 1 1 0 0 1 +refdes=M4 +T 47200 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 47200 43100 5 8 1 0 0 0 1 +w='Wunit' +T 47200 42900 5 8 1 0 0 0 1 +l=1u +} +C 44400 42800 1 0 0 asic-nmos-1.sym +{ +T 45800 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 45200 43600 5 10 1 1 0 0 1 +refdes=M2 +T 45200 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 45200 43100 5 8 1 0 0 0 1 +w='Wunit' +T 45200 42900 5 8 1 0 0 0 1 +l=1u +} +N 43800 45600 44100 45600 4 +{ +T 43800 45700 5 10 1 1 0 0 1 +netname=XN +} +N 44100 47800 44400 47800 4 +N 44100 43300 44400 43300 4 +N 45000 42800 45000 42400 4 +N 45100 43300 45200 43300 4 +N 45200 43300 45200 42400 4 +N 45000 47300 45000 43800 4 +N 46100 47800 46400 47800 4 +N 46100 43300 46400 43300 4 +N 46100 47800 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45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56400 45100 5 10 1 1 0 0 1 +refdes=M13 +T 56400 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 56400 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 56400 44400 5 8 1 0 0 0 1 +l=1u +} +C 55600 42800 1 0 0 asic-nmos-1.sym +{ +T 57000 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 56400 43600 5 10 1 1 0 0 1 +refdes=M14 +T 56400 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 56400 43100 5 8 1 0 0 0 1 +w='2*Wunit' +T 56400 42900 5 8 1 0 0 0 1 +l=1u +} +C 55600 47300 1 0 0 asic-pmos-1.sym +{ +T 57000 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 56400 48100 5 10 1 1 0 0 1 +refdes=M11 +T 56400 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 56400 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 56400 47400 5 8 1 0 0 0 1 +l=1u +} +N 55600 47800 54700 47800 4 +{ +T 55000 47900 5 10 1 1 0 0 1 +netname=clk180 +} +N 55600 43300 54700 43300 4 +{ +T 55000 43400 5 10 1 1 0 0 1 +netname=clk360 +} +N 55300 46300 55600 46300 4 +N 55600 44800 55300 44800 4 +N 55300 44800 55300 46300 4 +N 53800 45600 55300 45600 4 +{ +T 54800 45700 5 10 1 1 0 0 1 +netname=Q +} +N 56200 48300 56200 48700 4 +N 56200 47300 56200 46800 4 +N 56200 45800 56200 45300 4 +N 56200 44300 56200 43800 4 +N 56200 42800 56200 42400 4 +N 55000 44700 55000 45600 4 +N 51400 45600 52900 45600 4 +N 52300 45600 52300 47100 4 +N 52300 47100 57200 47100 4 +{ +T 54800 47200 5 10 1 1 0 0 1 +netname=qn +} +N 56200 45600 57200 45600 4 +N 57200 45600 57200 47100 4 +T 50100 41700 9 10 1 0 0 0 3 +Data input switch: +- (inverting) tri-state driver +- low-active transparent +T 53500 41900 9 10 1 0 0 0 2 +Q Stage: +- inverter +T 54900 41700 9 10 1 0 0 0 3 +QN Stage: +- (inverting) tri-state driver +- high-active transparent +N 51500 47800 51600 47800 4 +N 51600 46300 51600 48700 4 +N 51500 46300 51600 46300 4 +N 56300 47800 56400 47800 4 +N 56400 46300 56400 48700 4 +N 56300 46300 56400 46300 4 +N 56300 43300 56400 43300 4 +N 56400 42400 56400 44800 4 +N 56300 44800 56400 44800 4 +N 53800 46800 53800 48700 4 +N 53900 46300 54000 46300 4 +N 54000 46300 54000 48700 4 +N 53800 44300 53800 42400 4 +N 53900 44800 54000 44800 4 +N 54000 44800 54000 42400 4 +N 51500 43300 51600 43300 4 +N 51600 42400 51600 44800 4 +N 51500 44800 51600 44800 4 diff --git a/Sources/geda/LATN.sym b/Sources/geda/LATN.sym new file mode 100644 index 00000000..dba68cc6 --- /dev/null +++ b/Sources/geda/LATN.sym @@ -0,0 +1,70 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +V 250 600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=Q +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=D +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 200 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 350 550 9 10 1 1 0 0 1 +pinlabel=XN +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=LATN +T 1292 2292 8 10 0 1 0 0 1 +description=Low-active D-Latch +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATN.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/LATP.sch b/Sources/geda/LATP.sch new file mode 100644 index 00000000..a0cc5dc3 --- /dev/null +++ b/Sources/geda/LATP.sch @@ -0,0 +1,412 @@ +v 20130925 2 +T 50100 40100 9 10 1 0 0 0 1 +1 +T 51700 40100 9 10 1 0 0 0 1 +1 +N 44100 43300 44100 47800 4 +N 43300 48700 56400 48700 4 +{ +T 43400 48800 5 10 1 1 0 0 1 +netname=VDD +} +N 45000 48700 45000 48300 4 +N 45200 47800 45100 47800 4 +N 45200 47800 45200 48700 4 +N 43200 42400 56400 42400 4 +{ +T 43400 42500 5 10 1 1 0 0 1 +netname=GND +} +C 44400 47300 1 0 0 asic-pmos-1.sym +{ +T 45800 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 45200 48100 5 10 1 1 0 0 1 +refdes=M1 +T 45200 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 45200 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 45200 47400 5 8 1 0 0 0 1 +l=1u +} +T 42800 40500 9 10 1 0 0 0 4 +see [WESTE, 1992] +Weste, H.E. Neil; ESHRAGHIAN, Kamran: +"Principles of CMOS VLSI Design: A Systems Perspective." 2nd Edition, 1992. +Figure 5.53, Page 326. +B 42700 40400 6500 1000 19 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +C 49500 40000 1 0 0 cvstitleblock-1.sym +{ +T 50100 40400 5 10 1 1 0 0 1 +date=2019-09-02 +T 54000 40400 5 10 1 1 0 0 1 +rev=$Revision$ +T 54000 40100 5 10 1 1 0 0 1 +auth= +T 50100 40700 5 10 1 1 0 0 1 +fname=LATP.sch +T 52900 41100 5 14 1 1 0 4 1 +title=LATP - High-active D-Latch +} +C 44000 49200 1 0 0 spice-model-1.sym +{ +T 44100 49800 5 10 1 1 0 0 1 +refdes=A1 +T 45300 49500 5 10 1 1 0 0 1 +model-name=nmos4 +T 44500 49300 5 10 1 1 0 0 1 +file=Technology/spice/ls1unmos.mod +} +C 47300 49200 1 0 0 spice-model-1.sym +{ +T 47400 49800 5 10 1 1 0 0 1 +refdes=A2 +T 48600 49500 5 10 1 1 0 0 1 +model-name=pmos4 +T 47800 49300 5 10 1 1 0 0 1 +file=Technology/spice/ls1upmos.mod +} +C 54700 44900 1 270 0 spice-subcircuit-IO-1.sym +{ +T 54700 44700 5 10 1 1 90 0 1 +refdes=P1 +} +C 50300 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 50100 45900 5 10 1 1 0 0 1 +refdes=P2 +} +C 44000 45900 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43800 45900 5 10 1 1 0 0 1 +refdes=P3 +} +C 43500 49000 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43500 49000 5 10 1 1 0 0 1 +refdes=P4 +} +C 43400 42700 1 180 0 spice-subcircuit-IO-1.sym +{ +T 43400 42700 5 10 1 1 0 0 1 +refdes=P5 +} +C 50600 49400 1 0 0 spice-subcircuit-LL-1.sym +{ +T 50700 49800 5 10 1 1 0 0 1 +refdes=A3 +T 50700 49500 5 10 1 1 0 0 1 +model-name=LATP +} +C 40700 47500 1 0 0 spice-directive-1.sym +{ +T 40800 47800 5 10 0 1 0 0 1 +device=directive +T 40800 47900 5 10 1 1 0 0 1 +refdes=A4 +T 40800 47600 5 10 1 1 0 0 1 +value=.PARAM Wunit=1.5u +} +C 40700 46700 1 0 0 spice-directive-1.sym +{ +T 40800 47000 5 10 0 1 0 0 1 +device=directive +T 40800 47100 5 10 1 1 0 0 1 +refdes=A5 +T 40800 46800 5 10 1 1 0 0 1 +value=.PARAM PNratio=2 +} +C 46400 47300 1 0 0 asic-pmos-1.sym +{ +T 47800 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 47200 48100 5 10 1 1 0 0 1 +refdes=M3 +T 47200 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 47200 47600 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 47200 47400 5 8 1 0 0 0 1 +l=1u +} +C 46400 42800 1 0 0 asic-nmos-1.sym +{ +T 47800 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 47200 43600 5 10 1 1 0 0 1 +refdes=M4 +T 47200 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 47200 43100 5 8 1 0 0 0 1 +w='Wunit' +T 47200 42900 5 8 1 0 0 0 1 +l=1u +} +C 44400 42800 1 0 0 asic-nmos-1.sym +{ +T 45800 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 45200 43600 5 10 1 1 0 0 1 +refdes=M2 +T 45200 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 45200 43100 5 8 1 0 0 0 1 +w='Wunit' +T 45200 42900 5 8 1 0 0 0 1 +l=1u +} +N 43800 45600 44100 45600 4 +{ +T 43800 45700 5 10 1 1 0 0 1 +netname=X +} +N 44100 47800 44400 47800 4 +N 44100 43300 44400 43300 4 +N 45000 42800 45000 42400 4 +N 45100 43300 45200 43300 4 +N 45200 43300 45200 42400 4 +N 45000 47300 45000 43800 4 +N 46100 47800 46400 47800 4 +N 46100 43300 46400 43300 4 +N 46100 47800 46100 43300 4 +N 45000 45600 46100 45600 4 +{ +T 45400 45700 5 10 1 1 0 0 1 +netname=clk180 +} +N 47000 47300 47000 43800 4 +N 47000 48300 47000 48700 4 +N 47000 42800 47000 42400 4 +N 47100 47800 47200 47800 4 +N 47200 47800 47200 48700 4 +N 47100 43300 47200 43300 4 +N 47200 43300 47200 42400 4 +N 47000 45600 47800 45600 4 +{ +T 47300 45700 5 10 1 1 0 0 1 +netname=clk360 +} +C 50800 45800 1 0 0 asic-pmos-1.sym +{ +T 52200 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 46600 5 10 1 1 0 0 1 +refdes=M6 +T 51600 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 51600 45900 5 8 1 0 0 0 1 +l=1u +} +C 50800 44300 1 0 0 asic-nmos-1.sym +{ +T 52200 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 45100 5 10 1 1 0 0 1 +refdes=M7 +T 51600 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 44600 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 44400 5 8 1 0 0 0 1 +l=1u +} +C 50800 42800 1 0 0 asic-nmos-1.sym +{ +T 52200 43600 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 51600 43600 5 10 1 1 0 0 1 +refdes=M8 +T 51600 43400 5 8 1 1 0 0 1 +model-name=nmos4 +T 51600 43100 5 8 1 0 0 0 1 +w='2*Wunit' +T 51600 42900 5 8 1 0 0 0 1 +l=1u +} +C 50800 47300 1 0 0 asic-pmos-1.sym +{ +T 52200 48100 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 51600 48100 5 10 1 1 0 0 1 +refdes=M5 +T 51600 47900 5 8 1 1 0 0 1 +model-name=pmos4 +T 51600 47600 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 51600 47400 5 8 1 0 0 0 1 +l=1u +} +N 50800 47800 49900 47800 4 +{ +T 50200 47900 5 10 1 1 0 0 1 +netname=clk180 +} +N 50800 43300 49900 43300 4 +{ +T 50200 43400 5 10 1 1 0 0 1 +netname=clk360 +} +N 50500 46300 50800 46300 4 +N 50800 44800 50500 44800 4 +N 50500 44800 50500 46300 4 +N 50100 45600 50500 45600 4 +{ +T 50100 45700 5 10 1 1 0 0 1 +netname=D +} +N 51400 48300 51400 48700 4 +N 51400 47300 51400 46800 4 +N 51400 45800 51400 45300 4 +N 51400 44300 51400 43800 4 +N 51400 42800 51400 42400 4 +T 45000 41700 9 10 1 0 0 0 3 +Double Clock Buffering: +- de-coupling high load +- 2-phase clock generation +C 53200 45800 1 0 0 asic-pmos-1.sym +{ +T 54600 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 54000 46600 5 10 1 1 0 0 1 +refdes=M9 +T 54000 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 54000 46100 5 8 1 0 0 0 1 +w='PNratio*Wunit' +T 54000 45900 5 8 1 0 0 0 1 +l=1u +} +C 53200 44300 1 0 0 asic-nmos-1.sym +{ +T 54600 45100 5 8 0 0 0 0 1 +device=NMOS_TRANSISTOR +T 54000 45100 5 10 1 1 0 0 1 +refdes=M10 +T 54000 44900 5 8 1 1 0 0 1 +model-name=nmos4 +T 54000 44600 5 8 1 0 0 0 1 +w='Wunit' +T 54000 44400 5 8 1 0 0 0 1 +l=1u +} +N 52900 46300 53200 46300 4 +N 53200 44800 52900 44800 4 +N 52900 44800 52900 46300 4 +N 53800 45800 53800 45300 4 +C 55600 45800 1 0 0 asic-pmos-1.sym +{ +T 57000 46600 5 8 0 0 0 0 1 +device=PMOS_TRANSISTOR +T 56400 46600 5 10 1 1 0 0 1 +refdes=M12 +T 56400 46400 5 8 1 1 0 0 1 +model-name=pmos4 +T 56400 46100 5 8 1 0 0 0 1 +w='2*PNratio*Wunit' +T 56400 45900 5 8 1 0 0 0 1 +l=1u +} +C 55600 44300 1 0 0 asic-nmos-1.sym +{ +T 57000 45100 5 8 0 0 0 0 1 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4 +{ +T 54800 45700 5 10 1 1 0 0 1 +netname=Q +} +N 56200 48300 56200 48700 4 +N 56200 47300 56200 46800 4 +N 56200 45800 56200 45300 4 +N 56200 44300 56200 43800 4 +N 56200 42800 56200 42400 4 +N 55000 44700 55000 45600 4 +N 51400 45600 52900 45600 4 +N 52300 45600 52300 47100 4 +N 52300 47100 57200 47100 4 +{ +T 54800 47200 5 10 1 1 0 0 1 +netname=qn +} +N 56200 45600 57200 45600 4 +N 57200 45600 57200 47100 4 +T 50100 41700 9 10 1 0 0 0 3 +Data input switch: +- (inverting) tri-state driver +- high-active transparent +T 53500 41900 9 10 1 0 0 0 2 +Q Stage: +- inverter +T 54900 41700 9 10 1 0 0 0 3 +QN Stage: +- (inverting) tri-state driver +- low-active transparent +N 51500 47800 51600 47800 4 +N 51600 46300 51600 48700 4 +N 51500 46300 51600 46300 4 +N 56300 47800 56400 47800 4 +N 56400 46300 56400 48700 4 +N 56300 46300 56400 46300 4 +N 56300 43300 56400 43300 4 +N 56400 42400 56400 44800 4 +N 56300 44800 56400 44800 4 +N 53800 46800 53800 48700 4 +N 53900 46300 54000 46300 4 +N 54000 46300 54000 48700 4 +N 53800 44300 53800 42400 4 +N 53900 44800 54000 44800 4 +N 54000 44800 54000 42400 4 +N 51500 43300 51600 43300 4 +N 51600 42400 51600 44800 4 +N 51500 44800 51600 44800 4 diff --git a/Sources/geda/LATP.sym b/Sources/geda/LATP.sym new file mode 100644 index 00000000..f033d9c4 --- /dev/null +++ b/Sources/geda/LATP.sym @@ -0,0 +1,69 @@ +v 20130925 2 +B 300 300 1200 1600 3 10 1 0 -1 -1 0 -1 -1 -1 -1 -1 +P 1800 1600 1500 1600 1 0 0 +{ +T 1500 1650 5 10 0 0 0 6 1 +pintype=out +T 1442 1592 9 10 1 1 0 6 1 +pinlabel=Q +T 1592 1642 5 10 0 1 0 0 1 +pinnumber=1 +T 1500 1650 5 10 0 0 0 6 1 +pinseq=1 +} +P 0 1600 300 1600 1 0 0 +{ +T 100 1650 5 10 0 0 0 0 1 +pintype=in +T 100 1650 5 10 0 0 0 0 1 +pinseq=2 +T 358 1592 9 10 1 1 0 0 1 +pinlabel=D +T 208 1542 5 10 0 1 0 6 1 +pinnumber=2 +} +P 0 600 300 600 1 0 0 +{ +T 100 650 5 10 0 0 0 0 1 +pintype=clk +T 100 650 5 10 0 0 0 0 1 +pinseq=3 +T 350 550 9 10 1 1 0 0 1 +pinlabel=X +T 208 642 5 10 0 1 0 6 1 +pinnumber=3 +} +P 1200 2200 1200 1900 1 0 0 +{ +T 1150 1900 5 10 0 0 90 6 1 +pintype=pwr +T 1200 1845 9 10 1 1 90 6 1 +pinlabel=VDD +T 1150 1995 5 10 0 1 90 0 1 +pinnumber=4 +T 1150 1900 5 10 0 0 90 6 1 +pinseq=4 +} +P 1200 0 1200 300 1 0 0 +{ +T 1250 300 5 10 0 0 270 6 1 +pintype=pwr +T 1200 355 9 10 1 1 90 0 1 +pinlabel=GND +T 1150 205 5 10 0 1 90 6 1 +pinnumber=5 +T 1250 300 5 10 0 0 270 6 1 +pinseq=5 +} +T 492 992 5 16 1 1 0 0 1 +device=LATP +T 1292 2292 8 10 0 1 0 0 1 +description=High-active D-Latch +T 292 1989 5 10 1 1 0 0 1 +refdes=X? +T 1892 1392 8 10 0 0 0 0 1 +footprint=none +T -8 -8 8 10 0 1 0 0 1 +source=LATP.sch +T 600 100 9 10 0 0 0 0 1 +numslots=0 diff --git a/Sources/geda/LATRN.sch b/Sources/geda/LATRN.sch new file mode 100644 index 00000000..5ae41376 --- /dev/null +++ b/Sources/geda/LATRN.sch @@ -0,0 +1,458 @@ +v 20130925 2 +T 53200 40100 9 10 1 0 0 0 1 +1 +T 51700 40100 9 10 1 0 0 0 1 +1 +N 44100 43300 44100 47800 4 +N 43300 48700 57900 48700 4 +{ +T 43400 48800 5 10 1 1 0 0 1 +netname=VDD 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'SUPPLY' +} +C 48700 38900 1 0 0 cvstitleblock-1.sym +{ +T 49300 39300 5 10 1 1 0 0 1 +date=2019-08-23 +T 53200 39300 5 10 1 1 0 0 1 +rev=$Revision$ +T 53200 39000 5 10 1 1 0 0 1 +auth= +T 49300 39600 5 10 1 1 0 0 1 +fname=BUF2_tb.sch +T 51900 40100 5 14 1 1 0 4 1 +title=BUF2 - non-inverting Buffer, 2x driver strength +} +T 49300 39000 9 10 1 0 0 0 1 +1 +T 50800 39000 9 10 1 0 0 0 1 +1 +C 42100 41500 1 0 0 spice-include-1.sym +{ +T 42200 41800 5 10 0 1 0 0 1 +device=include +T 42200 41900 5 10 1 1 0 0 1 +refdes=A4 +T 42600 41600 5 10 1 1 0 0 1 +file=TBench/spice/BUF2_tb.cmd +} +C 42100 44100 1 0 0 spice-directive-1.sym +{ +T 42200 44400 5 10 0 1 0 0 1 +device=directive +T 42200 44500 5 10 1 1 0 0 1 +refdes=A1 +T 42200 44200 5 10 1 1 0 0 1 +value=.PARAM SUPPLY=5.0 +} +C 42100 43100 1 0 0 spice-model-1.sym +{ +T 42200 43700 5 10 1 1 0 0 1 +refdes=A2 +T 43400 43400 5 10 1 1 0 0 1 +model-name=BUF2 +T 42600 43200 5 10 1 1 0 0 1 +file=Library/spice/BUF2.cir +} +C 47800 41100 1 0 0 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+netname=resp +} +N 55700 42500 55700 42300 4 +N 55700 41400 55700 41300 4 +N 48100 42500 49700 42500 4 +{ +T 48700 42600 5 10 1 1 0 0 1 +netname=stim +} +N 50800 42500 51500 42500 4 +{ +T 51100 42600 5 10 1 1 0 0 1 +netname=A +} +N 52600 42500 53200 42500 4 +{ +T 52800 42600 5 10 1 1 0 0 1 +netname=Z +} +N 54300 42500 54500 42500 4 +C 49700 42100 1 0 0 BUF2.sym +{ +T 49992 42392 5 16 1 1 0 0 1 +device=BUF2 +T 49992 42889 5 10 1 1 0 0 1 +refdes=X1 +T 51592 43292 5 10 0 0 0 0 1 +footprint=none +T 49700 42100 5 10 0 1 0 0 1 +value=BUF2 +} +C 51500 42100 1 0 0 BUF2.sym +{ +T 51792 42392 5 16 1 1 0 0 1 +device=BUF2 +T 51792 42889 5 10 1 1 0 0 1 +refdes=XUT +T 53392 43292 5 10 0 0 0 0 1 +footprint=none +T 51500 42100 5 10 0 1 0 0 1 +value=BUF2 +} +N 50300 42100 53800 42100 4 +N 50300 42900 53800 42900 4 +C 52000 41800 1 0 0 gnd-1.sym +N 46100 44300 52100 44300 4 +N 52100 44300 52100 42900 4 +C 53200 42100 1 0 0 FO4.sym +{ +T 53492 42392 5 16 1 1 0 0 1 +device=FO4 +T 53492 42889 5 10 1 1 0 0 1 +refdes=X2 +T 55092 43292 5 10 0 0 0 0 1 +footprint=none +T 53200 42100 5 10 0 0 0 0 1 +value=FO4 +} +C 42100 42300 1 0 0 spice-model-1.sym +{ +T 42200 42900 5 10 1 1 0 0 1 +refdes=A3 +T 43400 42600 5 10 1 1 0 0 1 +model-name=FO4 +T 42600 42400 5 10 1 1 0 0 1 +file=Library/spice/FO4.cir +} diff --git a/TBench/geda/DFFN_tb.sch b/TBench/geda/DFFN_tb.sch new file mode 100644 index 00000000..3393a0dd --- /dev/null +++ b/TBench/geda/DFFN_tb.sch @@ -0,0 +1,209 @@ +v 20130925 2 +C 46000 43000 1 0 0 vdc-1.sym +{ +T 46700 43650 5 10 1 1 0 0 1 +refdes=VDD +T 46700 43850 5 10 0 0 0 0 1 +device=VOLTAGE_SOURCE +T 46700 44050 5 10 0 0 0 0 1 +footprint=none +T 46700 43450 5 10 1 1 0 0 1 +value=DC 'SUPPLY' +} +C 48700 38900 1 0 0 cvstitleblock-1.sym +{ +T 49300 39300 5 10 1 1 0 0 1 +date=2019-09-08 +T 53200 39300 5 10 1 1 0 0 1 +rev=$Revision$ +T 53200 39000 5 10 1 1 0 0 1 +auth= +T 49300 39600 5 10 1 1 0 0 1 +fname=DFFN_tb.sch +T 51700 40000 5 14 1 1 0 4 1 +title=DFFN - Negative edge-triggered D-FlipFlop +} +T 49300 39000 9 10 1 0 0 0 1 +1 +T 50800 39000 9 10 1 0 0 0 1 +1 +C 43200 40300 1 0 0 spice-include-1.sym +{ +T 43300 40600 5 10 0 1 0 0 1 +device=include +T 43300 40700 5 10 1 1 0 0 1 +refdes=A5 +T 43700 40400 5 10 1 1 0 0 1 +file=TBench/spice/DFFN_tb.cmd +} +C 43200 43900 1 0 0 spice-directive-1.sym +{ +T 43300 44200 5 10 0 1 0 0 1 +device=directive +T 43300 44300 5 10 1 1 0 0 1 +refdes=A1 +T 43300 44000 5 10 0 1 0 0 1 +file=unknown +T 43300 44000 5 10 1 1 0 0 1 +value=.param SUPPLY=5.0 +} +C 43200 43000 1 0 0 spice-model-1.sym +{ +T 43300 43600 5 10 1 1 0 0 1 +refdes=A2 +T 44500 43300 5 10 1 1 0 0 1 +model-name=DFFN +T 43700 43100 5 10 1 1 0 0 1 +file=Library/spice/DFFN.cir +} +C 47800 40000 1 0 0 vpulse-1.sym +{ +T 48500 40650 5 10 1 1 0 0 1 +refdes=V3 +T 48500 40850 5 10 0 0 0 0 1 +device=vpulse +T 48500 41050 5 10 0 0 0 0 1 +footprint=none +T 45300 40650 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 0.5n 7.5n 7.5n 7.5n 30n +} +N 52500 42700 52200 42700 4 +{ +T 52300 42800 5 10 1 1 0 0 1 +netname=Q +} +N 47400 42700 48000 42700 4 +N 48100 41700 49000 41700 4 +N 49100 42700 50400 42700 4 +{ +T 49600 42800 5 10 1 1 0 0 1 +netname=D +} +N 50100 41700 50400 41700 4 +{ +T 50100 41800 5 10 1 1 0 0 1 +netname=X +} +N 48100 41200 48100 41700 4 +C 47100 41300 1 0 0 vpulse-1.sym +{ +T 47800 41950 5 10 1 1 0 0 1 +refdes=V2 +T 47800 42150 5 10 0 0 0 0 1 +device=vpulse +T 47800 42350 5 10 0 0 0 0 1 +footprint=none +T 44400 42050 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 5n 7.5n 7.5n 30n 120n +} +N 47400 42500 47400 42700 4 +C 46100 44400 1 0 0 vdd-1.sym +C 46200 42500 1 0 0 gnd-1.sym +N 46300 44400 46300 44200 4 +{ +T 46300 44400 5 10 1 1 0 0 1 +netname=VDD +} +N 46300 42800 46300 43000 4 +{ +T 46300 42800 5 10 1 1 0 0 1 +netname=GND +} +C 48000 39600 1 0 0 gnd-1.sym +C 47300 41000 1 0 0 gnd-1.sym +N 48100 39900 48100 40000 4 +C 54900 41200 1 0 0 gnd-1.sym +C 54800 42500 1 270 0 capacitor-1.sym +{ +T 55500 42300 5 10 0 0 270 0 1 +device=CAPACITOR +T 55300 42300 5 10 1 1 270 0 1 +refdes=CL +T 55700 42300 5 10 0 0 270 0 1 +symversion=0.1 +T 55100 41800 5 10 1 1 0 0 1 +value=10n +} +C 53800 42600 1 0 0 resistor-2.sym +{ +T 54200 42950 5 10 0 0 0 0 1 +device=RESISTOR +T 54000 42900 5 10 1 1 0 0 1 +refdes=RL +T 54000 42600 5 10 1 1 0 0 1 +value=100k +} +N 53600 42700 53800 42700 4 +N 54700 42700 55000 42700 4 +N 55000 42700 55000 42500 4 +N 55000 41600 55000 41500 4 +C 48000 42300 1 0 0 BUF2.sym +{ +T 48292 42592 5 16 1 1 0 0 1 +device=BUF2 +T 48292 43089 5 10 1 1 0 0 1 +refdes=XD +T 49892 43492 5 10 0 0 0 0 1 +footprint=none +T 48000 42300 5 10 0 0 0 0 1 +value=BUF2 +} +C 49000 41300 1 0 0 BUF2.sym +{ +T 49292 41592 5 16 1 1 0 0 1 +device=BUF2 +T 49292 42089 5 10 1 1 0 0 1 +refdes=XX +T 50892 42492 5 10 0 0 0 0 1 +footprint=none +T 49000 41300 5 10 0 0 0 0 1 +value=BUF2 +} +C 52500 42300 1 0 0 FO4.sym +{ +T 52792 42592 5 16 1 1 0 0 1 +device=FO4 +T 52792 43089 5 10 1 1 0 0 1 +refdes=XQ +T 54392 43492 5 10 0 0 0 0 1 +footprint=none +T 52500 42300 5 10 0 0 0 0 1 +value=FO4 +} +C 48400 43100 1 0 0 vdd-1.sym +C 49400 42100 1 0 0 vdd-1.sym +C 51400 43300 1 0 0 vdd-1.sym +C 52900 43100 1 0 0 vdd-1.sym +C 48500 42000 1 0 0 gnd-1.sym +C 49500 41000 1 0 0 gnd-1.sym +C 51500 40800 1 0 0 gnd-1.sym +C 53000 42000 1 0 0 gnd-1.sym +C 43200 42100 1 0 0 spice-model-1.sym +{ +T 43300 42700 5 10 1 1 0 0 1 +refdes=A3 +T 44500 42400 5 10 1 1 0 0 1 +model-name=BUF2 +T 43700 42200 5 10 1 1 0 0 1 +file=Library/spice/BUF2.cir +} +C 43200 41100 1 0 0 spice-model-1.sym +{ +T 43300 41700 5 10 1 1 0 0 1 +refdes=A4 +T 44500 41400 5 10 1 1 0 0 1 +model-name=FO4 +T 43700 41200 5 10 1 1 0 0 1 +file=Library/spice/FO4.cir +} +C 50400 41100 1 0 0 DFFN.sym +{ +T 50892 42092 5 16 1 1 0 0 1 +device=DFFN +T 50692 43089 5 10 1 1 0 0 1 +refdes=XUT +T 52292 42492 5 10 0 0 0 0 1 +footprint=none +T 50400 41100 5 10 0 0 0 0 1 +value=DFFN +} diff --git a/TBench/geda/DFFP_tb.sch b/TBench/geda/DFFP_tb.sch new file mode 100644 index 00000000..a7e1779f --- /dev/null +++ b/TBench/geda/DFFP_tb.sch @@ -0,0 +1,209 @@ +v 20130925 2 +C 46000 43000 1 0 0 vdc-1.sym +{ +T 46700 43650 5 10 1 1 0 0 1 +refdes=VDD +T 46700 43850 5 10 0 0 0 0 1 +device=VOLTAGE_SOURCE +T 46700 44050 5 10 0 0 0 0 1 +footprint=none +T 46700 43450 5 10 1 1 0 0 1 +value=DC 'SUPPLY' +} +C 48700 38900 1 0 0 cvstitleblock-1.sym +{ +T 49300 39300 5 10 1 1 0 0 1 +date=2019-09-08 +T 53200 39300 5 10 1 1 0 0 1 +rev=$Revision$ +T 53200 39000 5 10 1 1 0 0 1 +auth= +T 49300 39600 5 10 1 1 0 0 1 +fname=DFFP_tb.sch +T 51700 40000 5 14 1 1 0 4 1 +title=DFFP - Positive edge-triggered D-FlipFlop +} +T 49300 39000 9 10 1 0 0 0 1 +1 +T 50800 39000 9 10 1 0 0 0 1 +1 +C 43200 40300 1 0 0 spice-include-1.sym +{ +T 43300 40600 5 10 0 1 0 0 1 +device=include +T 43300 40700 5 10 1 1 0 0 1 +refdes=A5 +T 43700 40400 5 10 1 1 0 0 1 +file=TBench/spice/DFFP_tb.cmd +} +C 43200 43900 1 0 0 spice-directive-1.sym +{ +T 43300 44200 5 10 0 1 0 0 1 +device=directive +T 43300 44300 5 10 1 1 0 0 1 +refdes=A1 +T 43300 44000 5 10 0 1 0 0 1 +file=unknown +T 43300 44000 5 10 1 1 0 0 1 +value=.param SUPPLY=5.0 +} +C 43200 43000 1 0 0 spice-model-1.sym +{ +T 43300 43600 5 10 1 1 0 0 1 +refdes=A2 +T 44500 43300 5 10 1 1 0 0 1 +model-name=DFFP +T 43700 43100 5 10 1 1 0 0 1 +file=Library/spice/DFFP.cir +} +C 47800 40000 1 0 0 vpulse-1.sym +{ +T 48500 40650 5 10 1 1 0 0 1 +refdes=V3 +T 48500 40850 5 10 0 0 0 0 1 +device=vpulse +T 48500 41050 5 10 0 0 0 0 1 +footprint=none +T 45300 40650 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 0.5n 7.5n 7.5n 7.5n 30n +} +N 52500 42700 52200 42700 4 +{ +T 52300 42800 5 10 1 1 0 0 1 +netname=Q +} +N 47400 42700 48000 42700 4 +N 48100 41700 49000 41700 4 +N 49100 42700 50400 42700 4 +{ +T 49600 42800 5 10 1 1 0 0 1 +netname=D +} +N 50100 41700 50400 41700 4 +{ +T 50100 41800 5 10 1 1 0 0 1 +netname=X +} +N 48100 41200 48100 41700 4 +C 47100 41300 1 0 0 vpulse-1.sym +{ +T 47800 41950 5 10 1 1 0 0 1 +refdes=V2 +T 47800 42150 5 10 0 0 0 0 1 +device=vpulse +T 47800 42350 5 10 0 0 0 0 1 +footprint=none +T 44400 42050 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 5n 7.5n 7.5n 30n 120n +} +N 47400 42500 47400 42700 4 +C 46100 44400 1 0 0 vdd-1.sym +C 46200 42500 1 0 0 gnd-1.sym +N 46300 44400 46300 44200 4 +{ +T 46300 44400 5 10 1 1 0 0 1 +netname=VDD +} +N 46300 42800 46300 43000 4 +{ +T 46300 42800 5 10 1 1 0 0 1 +netname=GND +} +C 48000 39600 1 0 0 gnd-1.sym +C 47300 41000 1 0 0 gnd-1.sym +N 48100 39900 48100 40000 4 +C 54900 41200 1 0 0 gnd-1.sym +C 54800 42500 1 270 0 capacitor-1.sym +{ +T 55500 42300 5 10 0 0 270 0 1 +device=CAPACITOR +T 55300 42300 5 10 1 1 270 0 1 +refdes=CL +T 55700 42300 5 10 0 0 270 0 1 +symversion=0.1 +T 55100 41800 5 10 1 1 0 0 1 +value=10n +} +C 53800 42600 1 0 0 resistor-2.sym +{ +T 54200 42950 5 10 0 0 0 0 1 +device=RESISTOR +T 54000 42900 5 10 1 1 0 0 1 +refdes=RL +T 54000 42600 5 10 1 1 0 0 1 +value=100k +} +N 53600 42700 53800 42700 4 +N 54700 42700 55000 42700 4 +N 55000 42700 55000 42500 4 +N 55000 41600 55000 41500 4 +C 48000 42300 1 0 0 BUF2.sym +{ +T 48292 42592 5 16 1 1 0 0 1 +device=BUF2 +T 48292 43089 5 10 1 1 0 0 1 +refdes=XD +T 49892 43492 5 10 0 0 0 0 1 +footprint=none +T 48000 42300 5 10 0 0 0 0 1 +value=BUF2 +} +C 49000 41300 1 0 0 BUF2.sym +{ +T 49292 41592 5 16 1 1 0 0 1 +device=BUF2 +T 49292 42089 5 10 1 1 0 0 1 +refdes=XX +T 50892 42492 5 10 0 0 0 0 1 +footprint=none +T 49000 41300 5 10 0 0 0 0 1 +value=BUF2 +} +C 52500 42300 1 0 0 FO4.sym +{ +T 52792 42592 5 16 1 1 0 0 1 +device=FO4 +T 52792 43089 5 10 1 1 0 0 1 +refdes=XQ +T 54392 43492 5 10 0 0 0 0 1 +footprint=none +T 52500 42300 5 10 0 0 0 0 1 +value=FO4 +} +C 48400 43100 1 0 0 vdd-1.sym +C 49400 42100 1 0 0 vdd-1.sym +C 51400 43300 1 0 0 vdd-1.sym +C 52900 43100 1 0 0 vdd-1.sym +C 48500 42000 1 0 0 gnd-1.sym +C 49500 41000 1 0 0 gnd-1.sym +C 51500 40800 1 0 0 gnd-1.sym +C 53000 42000 1 0 0 gnd-1.sym +C 43200 42100 1 0 0 spice-model-1.sym +{ +T 43300 42700 5 10 1 1 0 0 1 +refdes=A3 +T 44500 42400 5 10 1 1 0 0 1 +model-name=BUF2 +T 43700 42200 5 10 1 1 0 0 1 +file=Library/spice/BUF2.cir +} +C 43200 41100 1 0 0 spice-model-1.sym +{ +T 43300 41700 5 10 1 1 0 0 1 +refdes=A4 +T 44500 41400 5 10 1 1 0 0 1 +model-name=FO4 +T 43700 41200 5 10 1 1 0 0 1 +file=Library/spice/FO4.cir +} +C 50400 41100 1 0 0 DFFP.sym +{ +T 50892 42092 5 16 1 1 0 0 1 +device=DFFP +T 50692 43089 5 10 1 1 0 0 1 +refdes=XUT +T 52292 42492 5 10 0 0 0 0 1 +footprint=none +T 50400 41100 5 10 0 0 0 0 1 +value=DFFP +} diff --git a/TBench/geda/LATN_tb.sch b/TBench/geda/LATN_tb.sch new file mode 100644 index 00000000..17bce649 --- /dev/null +++ b/TBench/geda/LATN_tb.sch @@ -0,0 +1,209 @@ +v 20130925 2 +C 46000 43000 1 0 0 vdc-1.sym +{ +T 46700 43650 5 10 1 1 0 0 1 +refdes=VDD +T 46700 43850 5 10 0 0 0 0 1 +device=VOLTAGE_SOURCE +T 46700 44050 5 10 0 0 0 0 1 +footprint=none +T 46700 43450 5 10 1 1 0 0 1 +value=DC 'SUPPLY' +} +C 48700 38900 1 0 0 cvstitleblock-1.sym +{ +T 49300 39300 5 10 1 1 0 0 1 +date=2019-08-21 +T 53200 39300 5 10 1 1 0 0 1 +rev=$Revision$ +T 53200 39000 5 10 1 1 0 0 1 +auth= +T 49300 39600 5 10 1 1 0 0 1 +fname=LATN_tb.sch +T 51400 40100 5 14 1 1 0 4 1 +title=LATN - Low-active D-Latch +} +T 49300 39000 9 10 1 0 0 0 1 +1 +T 50800 39000 9 10 1 0 0 0 1 +1 +C 43200 40300 1 0 0 spice-include-1.sym +{ +T 43300 40600 5 10 0 1 0 0 1 +device=include +T 43300 40700 5 10 1 1 0 0 1 +refdes=A5 +T 43700 40400 5 10 1 1 0 0 1 +file=TBench/spice/LATN_tb.cmd +} +C 43200 43900 1 0 0 spice-directive-1.sym +{ +T 43300 44200 5 10 0 1 0 0 1 +device=directive +T 43300 44300 5 10 1 1 0 0 1 +refdes=A1 +T 43300 44000 5 10 0 1 0 0 1 +file=unknown +T 43300 44000 5 10 1 1 0 0 1 +value=.param SUPPLY=5.0 +} +C 43200 43000 1 0 0 spice-model-1.sym +{ +T 43300 43600 5 10 1 1 0 0 1 +refdes=A2 +T 44500 43300 5 10 1 1 0 0 1 +model-name=LATN +T 43700 43100 5 10 1 1 0 0 1 +file=Library/spice/LATN.cir +} +C 47800 40000 1 0 0 vpulse-1.sym +{ +T 48500 40650 5 10 1 1 0 0 1 +refdes=V3 +T 48500 40850 5 10 0 0 0 0 1 +device=vpulse +T 48500 41050 5 10 0 0 0 0 1 +footprint=none +T 45300 40650 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 0.5n 7.5n 7.5n 7.5n 30n +} +N 52500 42700 52200 42700 4 +{ +T 52300 42800 5 10 1 1 0 0 1 +netname=Q +} +N 47400 42700 48000 42700 4 +N 48100 41700 49000 41700 4 +N 49100 42700 50400 42700 4 +{ +T 49600 42800 5 10 1 1 0 0 1 +netname=D +} +N 50100 41700 50400 41700 4 +{ +T 50100 41800 5 10 1 1 0 0 1 +netname=XN +} +N 48100 41200 48100 41700 4 +C 47100 41300 1 0 0 vpulse-1.sym +{ +T 47800 41950 5 10 1 1 0 0 1 +refdes=V2 +T 47800 42150 5 10 0 0 0 0 1 +device=vpulse +T 47800 42350 5 10 0 0 0 0 1 +footprint=none +T 44400 42050 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 5n 7.5n 7.5n 15n 60n +} +N 47400 42500 47400 42700 4 +C 46100 44400 1 0 0 vdd-1.sym +C 46200 42500 1 0 0 gnd-1.sym +N 46300 44400 46300 44200 4 +{ +T 46300 44400 5 10 1 1 0 0 1 +netname=VDD +} +N 46300 42800 46300 43000 4 +{ +T 46300 42800 5 10 1 1 0 0 1 +netname=GND +} +C 48000 39600 1 0 0 gnd-1.sym +C 47300 41000 1 0 0 gnd-1.sym +N 48100 39900 48100 40000 4 +C 54900 41200 1 0 0 gnd-1.sym +C 54800 42500 1 270 0 capacitor-1.sym +{ +T 55500 42300 5 10 0 0 270 0 1 +device=CAPACITOR +T 55300 42300 5 10 1 1 270 0 1 +refdes=CL +T 55700 42300 5 10 0 0 270 0 1 +symversion=0.1 +T 55100 41800 5 10 1 1 0 0 1 +value=10n +} +C 53800 42600 1 0 0 resistor-2.sym +{ +T 54200 42950 5 10 0 0 0 0 1 +device=RESISTOR +T 54000 42900 5 10 1 1 0 0 1 +refdes=RL +T 54000 42600 5 10 1 1 0 0 1 +value=100k +} +N 53600 42700 53800 42700 4 +N 54700 42700 55000 42700 4 +N 55000 42700 55000 42500 4 +N 55000 41600 55000 41500 4 +C 48000 42300 1 0 0 BUF2.sym +{ +T 48292 42592 5 16 1 1 0 0 1 +device=BUF2 +T 48292 43089 5 10 1 1 0 0 1 +refdes=XD +T 49892 43492 5 10 0 0 0 0 1 +footprint=none +T 48000 42300 5 10 0 0 0 0 1 +value=BUF2 +} +C 49000 41300 1 0 0 BUF2.sym +{ +T 49292 41592 5 16 1 1 0 0 1 +device=BUF2 +T 49292 42089 5 10 1 1 0 0 1 +refdes=XXN +T 50892 42492 5 10 0 0 0 0 1 +footprint=none +T 49000 41300 5 10 0 0 0 0 1 +value=BUF2 +} +C 52500 42300 1 0 0 FO4.sym +{ +T 52792 42592 5 16 1 1 0 0 1 +device=FO4 +T 52792 43089 5 10 1 1 0 0 1 +refdes=XQ +T 54392 43492 5 10 0 0 0 0 1 +footprint=none +T 52500 42300 5 10 0 0 0 0 1 +value=FO4 +} +C 48400 43100 1 0 0 vdd-1.sym +C 49400 42100 1 0 0 vdd-1.sym +C 51400 43300 1 0 0 vdd-1.sym +C 52900 43100 1 0 0 vdd-1.sym +C 48500 42000 1 0 0 gnd-1.sym +C 49500 41000 1 0 0 gnd-1.sym +C 51500 40800 1 0 0 gnd-1.sym +C 53000 42000 1 0 0 gnd-1.sym +C 43200 42100 1 0 0 spice-model-1.sym +{ +T 43300 42700 5 10 1 1 0 0 1 +refdes=A3 +T 44500 42400 5 10 1 1 0 0 1 +model-name=BUF2 +T 43700 42200 5 10 1 1 0 0 1 +file=Library/spice/BUF2.cir +} +C 43200 41100 1 0 0 spice-model-1.sym +{ +T 43300 41700 5 10 1 1 0 0 1 +refdes=A4 +T 44500 41400 5 10 1 1 0 0 1 +model-name=FO4 +T 43700 41200 5 10 1 1 0 0 1 +file=Library/spice/FO4.cir +} +C 50400 41100 1 0 0 LATN.sym +{ +T 50892 42092 5 16 1 1 0 0 1 +device=LATN +T 50692 43089 5 10 1 1 0 0 1 +refdes=XUT +T 52292 42492 5 10 0 0 0 0 1 +footprint=none +T 50400 41100 5 10 0 0 0 0 1 +value=LATN +} diff --git a/TBench/geda/LATP_tb.sch b/TBench/geda/LATP_tb.sch new file mode 100644 index 00000000..fd18c38b --- /dev/null +++ b/TBench/geda/LATP_tb.sch @@ -0,0 +1,209 @@ +v 20130925 2 +C 46000 43000 1 0 0 vdc-1.sym +{ +T 46700 43650 5 10 1 1 0 0 1 +refdes=VDD +T 46700 43850 5 10 0 0 0 0 1 +device=VOLTAGE_SOURCE +T 46700 44050 5 10 0 0 0 0 1 +footprint=none +T 46700 43450 5 10 1 1 0 0 1 +value=DC 'SUPPLY' +} +C 48700 38900 1 0 0 cvstitleblock-1.sym +{ +T 49300 39300 5 10 1 1 0 0 1 +date=2019-08-21 +T 53200 39300 5 10 1 1 0 0 1 +rev=$Revision$ +T 53200 39000 5 10 1 1 0 0 1 +auth= +T 49300 39600 5 10 1 1 0 0 1 +fname=LATP_tb.sch +T 51400 40100 5 14 1 1 0 4 1 +title=LATP - High-active D-Latch +} +T 49300 39000 9 10 1 0 0 0 1 +1 +T 50800 39000 9 10 1 0 0 0 1 +1 +C 43200 40300 1 0 0 spice-include-1.sym +{ +T 43300 40600 5 10 0 1 0 0 1 +device=include +T 43300 40700 5 10 1 1 0 0 1 +refdes=A5 +T 43700 40400 5 10 1 1 0 0 1 +file=TBench/spice/LATP_tb.cmd +} +C 43200 43900 1 0 0 spice-directive-1.sym +{ +T 43300 44200 5 10 0 1 0 0 1 +device=directive +T 43300 44300 5 10 1 1 0 0 1 +refdes=A1 +T 43300 44000 5 10 0 1 0 0 1 +file=unknown +T 43300 44000 5 10 1 1 0 0 1 +value=.param SUPPLY=5.0 +} +C 43200 43000 1 0 0 spice-model-1.sym +{ +T 43300 43600 5 10 1 1 0 0 1 +refdes=A2 +T 44500 43300 5 10 1 1 0 0 1 +model-name=LATP +T 43700 43100 5 10 1 1 0 0 1 +file=Library/spice/LATP.cir +} +C 47800 40000 1 0 0 vpulse-1.sym +{ +T 48500 40650 5 10 1 1 0 0 1 +refdes=V3 +T 48500 40850 5 10 0 0 0 0 1 +device=vpulse +T 48500 41050 5 10 0 0 0 0 1 +footprint=none +T 45300 40650 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 0.5n 7.5n 7.5n 7.5n 30n +} +N 52500 42700 52200 42700 4 +{ +T 52300 42800 5 10 1 1 0 0 1 +netname=Q +} +N 47400 42700 48000 42700 4 +N 48100 41700 49000 41700 4 +N 49100 42700 50400 42700 4 +{ +T 49600 42800 5 10 1 1 0 0 1 +netname=D +} +N 50100 41700 50400 41700 4 +{ +T 50100 41800 5 10 1 1 0 0 1 +netname=X +} +N 48100 41200 48100 41700 4 +C 47100 41300 1 0 0 vpulse-1.sym +{ +T 47800 41950 5 10 1 1 0 0 1 +refdes=V2 +T 47800 42150 5 10 0 0 0 0 1 +device=vpulse +T 47800 42350 5 10 0 0 0 0 1 +footprint=none +T 44400 42050 5 10 1 1 0 0 1 +value=pulse 0 'SUPPLY' 5n 7.5n 7.5n 15n 60n +} +N 47400 42500 47400 42700 4 +C 46100 44400 1 0 0 vdd-1.sym +C 46200 42500 1 0 0 gnd-1.sym +N 46300 44400 46300 44200 4 +{ +T 46300 44400 5 10 1 1 0 0 1 +netname=VDD +} +N 46300 42800 46300 43000 4 +{ +T 46300 42800 5 10 1 1 0 0 1 +netname=GND +} +C 48000 39600 1 0 0 gnd-1.sym +C 47300 41000 1 0 0 gnd-1.sym +N 48100 39900 48100 40000 4 +C 54900 41200 1 0 0 gnd-1.sym +C 54800 42500 1 270 0 capacitor-1.sym +{ +T 55500 42300 5 10 0 0 270 0 1 +device=CAPACITOR +T 55300 42300 5 10 1 1 270 0 1 +refdes=CL +T 55700 42300 5 10 0 0 270 0 1 +symversion=0.1 +T 55100 41800 5 10 1 1 0 0 1 +value=10n +} +C 53800 42600 1 0 0 resistor-2.sym +{ +T 54200 42950 5 10 0 0 0 0 1 +device=RESISTOR +T 54000 42900 5 10 1 1 0 0 1 +refdes=RL +T 54000 42600 5 10 1 1 0 0 1 +value=100k +} +N 53600 42700 53800 42700 4 +N 54700 42700 55000 42700 4 +N 55000 42700 55000 42500 4 +N 55000 41600 55000 41500 4 +C 48000 42300 1 0 0 BUF2.sym +{ +T 48292 42592 5 16 1 1 0 0 1 +device=BUF2 +T 48292 43089 5 10 1 1 0 0 1 +refdes=XD +T 49892 43492 5 10 0 0 0 0 1 +footprint=none +T 48000 42300 5 10 0 0 0 0 1 +value=BUF2 +} +C 49000 41300 1 0 0 BUF2.sym +{ +T 49292 41592 5 16 1 1 0 0 1 +device=BUF2 +T 49292 42089 5 10 1 1 0 0 1 +refdes=XX +T 50892 42492 5 10 0 0 0 0 1 +footprint=none +T 49000 41300 5 10 0 0 0 0 1 +value=BUF2 +} +C 52500 42300 1 0 0 FO4.sym +{ +T 52792 42592 5 16 1 1 0 0 1 +device=FO4 +T 52792 43089 5 10 1 1 0 0 1 +refdes=XQ +T 54392 43492 5 10 0 0 0 0 1 +footprint=none +T 52500 42300 5 10 0 0 0 0 1 +value=FO4 +} +C 48400 43100 1 0 0 vdd-1.sym +C 49400 42100 1 0 0 vdd-1.sym +C 51400 43300 1 0 0 vdd-1.sym +C 52900 43100 1 0 0 vdd-1.sym +C 48500 42000 1 0 0 gnd-1.sym +C 49500 41000 1 0 0 gnd-1.sym +C 51500 40800 1 0 0 gnd-1.sym +C 53000 42000 1 0 0 gnd-1.sym +C 43200 42100 1 0 0 spice-model-1.sym +{ +T 43300 42700 5 10 1 1 0 0 1 +refdes=A3 +T 44500 42400 5 10 1 1 0 0 1 +model-name=BUF2 +T 43700 42200 5 10 1 1 0 0 1 +file=Library/spice/BUF2.cir +} +C 43200 41100 1 0 0 spice-model-1.sym +{ +T 43300 41700 5 10 1 1 0 0 1 +refdes=A4 +T 44500 41400 5 10 1 1 0 0 1 +model-name=FO4 +T 43700 41200 5 10 1 1 0 0 1 +file=Library/spice/FO4.cir +} +C 50400 41100 1 0 0 LATP.sym +{ +T 50892 42092 5 16 1 1 0 0 1 +device=LATP +T 50692 43089 5 10 1 1 0 0 1 +refdes=XUT +T 52292 42492 5 10 0 0 0 0 1 +footprint=none +T 50400 41100 5 10 0 0 0 0 1 +value=LATP +} diff --git a/TBench/spice/BUF2_tb.cmd b/TBench/spice/BUF2_tb.cmd new file mode 100644 index 00000000..ba1e50f0 --- /dev/null +++ b/TBench/spice/BUF2_tb.cmd @@ -0,0 +1,30 @@ + +.tran 100p 30n +.plot tran v(Z) v(A) + +* rising edge propagation delay +.measure tran tpdr ++ TRIG v(A) VAL='SUPPLY/2' RISE=1 ++ TARG v(Z) VAL='SUPPLY/2' CROSS=1 + +* falling edge propagation delay +.measure tran tpdf ++ TRIG v(A) VAL='SUPPLY/2' FALL=1 ++ TARG v(Z) VAL='SUPPLY/2' FALL=1 + +* average propagation delay +*.measure tran tpd param='(tpdr+tpdf)/2' + +* delta progagation delay +*.measure tran delta param='tpdr-tpdf' goal=0 + +* measure rise time +.measure tran trise ++ TRIG v(Z) VAL='0.1*SUPPLY' RISE=1 ++ TARG v(Z) VAL='0.9*SUPPLY' RISE=1 + +* measure fall time +.measure tran tfall ++ TRIG v(Z) VAL='0.9*SUPPLY' FALL=1 ++ TARG v(Z) VAL='0.1*SUPPLY' FALL=1 + diff --git a/TBench/spice/DFFN_tb.cmd b/TBench/spice/DFFN_tb.cmd new file mode 100644 index 00000000..58079e52 --- /dev/null +++ b/TBench/spice/DFFN_tb.cmd @@ -0,0 +1,4 @@ + +.tran 100p 70n +.plot tran v(Q) v(XN) v(D) + diff --git a/TBench/spice/DFFP_tb.cmd b/TBench/spice/DFFP_tb.cmd new file mode 100644 index 00000000..ec33f4f8 --- /dev/null +++ b/TBench/spice/DFFP_tb.cmd @@ -0,0 +1,4 @@ + +.tran 100p 70n +.plot tran v(Q) v(X) v(D) + diff --git a/TBench/spice/LATN_tb.cmd b/TBench/spice/LATN_tb.cmd new file mode 100644 index 00000000..da00b9ea --- /dev/null +++ b/TBench/spice/LATN_tb.cmd @@ -0,0 +1,4 @@ + +.tran 100p 70n +* .plot tran v(Q) v(X) v(D) + diff --git a/TBench/spice/LATP_tb.cmd b/TBench/spice/LATP_tb.cmd new file mode 100644 index 00000000..ec33f4f8 --- /dev/null +++ b/TBench/spice/LATP_tb.cmd @@ -0,0 +1,4 @@ + +.tran 100p 70n +.plot tran v(Q) v(X) v(D) + diff --git a/TBench/spice/tb_INV.sp b/TBench/spice/tb_INV.sp deleted file mode 100644 index ea3b9143..00000000 --- a/TBench/spice/tb_INV.sp +++ /dev/null @@ -1,88 +0,0 @@ -* tb_INV.sp -** ************ LibreSilicon's StdCellLibrary ******************* -** -** Organisation: Chipforge -** Germany / European Union -** -** Profile: Chipforge focus on fine System-on-Chip Cores in -** Verilog HDL Code which are easy understandable and -** adjustable. For further information see -** www.chipforge.org -** there are projects from small cores up to PCBs, too. -** -** File: StdCellLib/TBench/spice/tb_INV.sp -** -** Purpose: INV Testbench -** -** ************ Spice 3f.5 / July 1993 *************************** -** -** /////////////////////////////////////////////////////////////////// -** -** Copyright (c) 2018 by chipforge -** All rights reserved. -** -** This Standard Cell Library is licensed under the Libre Silicon -** public license; you can redistribute it and/or modify it under -** the terms of the Libre Silicon public license as published by -** the Libre Silicon alliance, either version 1 of the License, or -** (at your option) any later version. -** -** This design is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -** See the Libre Silicon Public License for more details. -** -** /////////////////////////////////////////////////////////////////// - -** ------------------------------------------------------------------- -** PARAMETERS & MODELS -** ------------------------------------------------------------------- - -.param SUPPLY=5.0 $ voltage -.param LAMBDA=0.5U $ half of the feature size -.temp 25 $ celsius - -* LibreSilicon 1um Technology file -.include ls1u_models.lib - -** ------------------------------------------------------------------- -** NETLIST -** ------------------------------------------------------------------- - -.subckt INV A Z -MNA Z A gnd gnd lsnmos W={1*3*LAMBDA} L={2*LAMBDA} PS={5*LAMBDA} PD={5*LAMBDA} AS={W*PS} AD={W*PD} -MPA Z A vdd vdd lspmos W={2*3*LAMBDA} L={2*LAMBDA} PS={5*LAMBDA} PD={5*LAMBDA} AS={W*PS} AD={W*PD} -.ends - -Vdd vdd gnd 'SUPPLY' -Vin a gnd PULSE 0 'SUPPLY' 0p 100p 100p 500p 1000p -X1 a b INV -X2 b c INV -X3 c d INV -X4 d e INV -X5 e f INV - -** ------------------------------------------------------------------- -** SIMULATION -** ------------------------------------------------------------------- - -.tran 1p 1000p - -* rising propagation delay -.measure tpdr -+ TRIG v(c) VAL='SUPPLY/2' FALL=1 -+ TARG v(d) VAL='SUPPLY/2' RISE=1 -* falling propagation delay -.measure tpdf -+ TRIG v(c) VAL='SUPPLY/2' RISE=1 -+ TARG v(d) VAL='SUPPLY/2' FALL=1 -* average propagation delay -.measure tpd param='(tpdr+tpdf)/2' -* rise time -.measure trise -+ TRIG v(c) VAL='0.2*SUPPLY' RISE=1 -+ TARG v(d) VAL='0.8*SUPPLY' FALL=1 -.measure tfall -+ TRIG v(c) VAL='0.8*SUPPLY' FALL=1 -+ TARG v(d) VAL='0.2*SUPPLY' RISE=1 -.end diff --git a/Tech b/Tech new file mode 120000 index 00000000..3d5e8b91 --- /dev/null +++ b/Tech @@ -0,0 +1 @@ +Tech.GF180MCU/ \ No newline at end of file diff --git a/Tech.CDTA/.gitignore b/Tech.CDTA/.gitignore new file mode 100644 index 00000000..c18dd8d8 --- /dev/null +++ b/Tech.CDTA/.gitignore @@ -0,0 +1 @@ +__pycache__/ diff --git a/Tech.CDTA/librecell_tech.py b/Tech.CDTA/librecell_tech.py new file mode 100644 index 00000000..b0f5bbad --- /dev/null +++ b/Tech.CDTA/librecell_tech.py @@ -0,0 +1,304 @@ +from lclayout.layout.layers import * +from lclayout.writer.magic_writer import MagWriter +from lclayout.writer.lef_writer import LefWriter +from lclayout.writer.gds_writer import GdsWriter + +# Physical size of one data base unit in meters. +# CDTA +# BUT GDS2 requires the database units to be in nanometers +db_unit = 1e-9 + +# Lambda - how many db_units is 1 lambda? +l = 500 +um = 1000 +nm = 1 + +# Scale transistor width. +transistor_channel_width_sizing = 1 + +# GDS2 layer numbers for final output. +my_nwell = (10, 0) # CWN +my_active = (20, 0) # CAA Diffusion and Channel area (ndiffusion+pdiffusion) +#my_ndiffusion = (1, 0) +#my_pdiffusion = (1, 7) +#my_nwell2 = (2, 1) # a copy of the nwell layer due to limitations of other tools we don't need +#my_pwell = (2, 7) +my_poly1 = (30, 0) # gate, interconnect and bottom plate of analog capacitor +my_poly2 = (35, 0) # interconnect, top plate of analog capacitor and poly resistor +my_nplus = (40, 0) # nmost source and drain +my_pplus = (45, 0) # pmost source and drain +my_contact = (50, 0) # CCC, CCG (poly_contact + diff_contact) +#my_poly_contact = (4, 0) # Both poly_contact and diff_contact are the same in Libresilicon and they are both just one layer called "CONTACT" +#my_diff_contact = (5, 0) # Both poly_contact and diff_contact are the same in Libresilicon and they are both just one layer called "CONTACT" +my_metal1 = (60, 0) +my_metal1_label = (60, 1) +my_metal1_pin = (60, 2) +my_via1 = (55, 0) # CV1,CVA +my_metal2 = (65, 0) +my_metal2_label = (65, 1) +my_metal2_pin = (65, 2) +#my_glass = (90, 0) # COG +my_iframe = (200, 0) # abutment_box = (200, 0) + +# lclayout internally uses its own layer numbering scheme. +# For the final output the layers can be remapped with a mapping +# defined in this dictioinary. +output_map = { + l_ndiffusion: my_active, + l_pdiffusion: my_active, + l_nwell: my_nwell, # [my_nwell, my_nwell2], # Map l_nwell to two output layers. + l_pwell: [], #my_pwell Output layer for pwell. Uncomment this if needed. For instance for twin-well processes. + l_poly: my_poly1, + l_poly_contact: my_contact, + l_diff_contact: my_contact, + l_metal1: my_metal1, + l_metal1_label: my_metal1_label, + l_metal1_pin: my_metal1_pin, + l_via1: my_via1, + l_metal2: my_metal2, + l_metal2_label: my_metal2_label, + l_metal2_pin: my_metal2_pin, + l_abutment_box: my_iframe +} + +# Define a list of output writers. +output_writers = [ + MagWriter( + tech_name='scmos', + scale_factor=0.004, # Scale all coordinates by this factor (rounded down to next integer). + output_map={ + l_via1: 'm2contact', + l_poly: 'polysilicon', + l_abutment_box: ['fence'], + l_metal1: 'metal1', + l_metal2: 'metal2', + l_metal1_label: 'metal1', + l_metal2_label: 'metal2', + l_ndiffusion: 'ndiffusion', # -> active ??? + l_pdiffusion: 'pdiffusion', + l_metal2_pin: 'metal2', + l_poly_contact: 'polycontact', + l_diff_contact: 'pdcontact' + } + ), + + LefWriter( + db_unit=db_unit, + output_map=output_map + ), + + GdsWriter( + db_unit=db_unit, + output_map=output_map + ) +] + +# Define how layers can be used for routing. +# Example for a layer that can be used for horizontal and vertical tracks: {'MyLayer1' : 'hv'} +# Example for a layer that can be contacted but not used for routing: {'MyLayer2' : ''} +routing_layers = { + l_ndiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_pdiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_poly: '', + l_metal1: 'hv',# hv? + l_metal2: 'hv',# hv? +} + +# Minimum spacing rules for layer pairs. +min_spacing = { + (l_ndiffusion, l_ndiffusion): 2*um, # Rule 2.2 + (l_pdiffusion, l_ndiffusion): 2*um, # Rule 2.2 + (l_pdiffusion, l_pdiffusion): 2*um, # Rule 2.2 + (l_ndiffusion, l_poly_contact): 1000*nm, # Rule 7.4 ? Was there another rule that mandated 1.5 um? + (l_pdiffusion, l_poly_contact): 1000*nm, # Rule 7.4 ? + (l_nwell, l_nwell): 4*um, # Rule 1.3 + (l_nwell, l_pwell): 10*l, # 2.2.4->12l + (l_pwell, l_pwell): 4*um, # 3 -> 10l + (l_poly, l_nwell): 1*um, + (l_poly, l_ndiffusion): 1500*nm, + (l_poly, l_pdiffusion): 1500*nm, + (l_poly, l_poly): 1500*nm, # Rule 3.2 + (l_poly, l_diff_contact): 1*um, # Rule 8.4 ? Or 2um? + (l_diff_contact, l_diff_contact): 1500*nm, # Rule 7.3 + Rule 8.3 + (l_metal1, l_metal1): 1500*nm, # Rule 9.2 + (l_metal2, l_metal2): 1500*nm, # Rule 11.2 + (l_via1, l_via1): 1500*nm, # Rule 10.2 + (l_via1, l_diff_contact): 1500*nm, # Rule 10.4 WARNING: STACKED VIAS ARE FORBIDDEN!!! + (l_via1, l_ndiffusion): 1500*nm, # Rule 10.5 + (l_via1, l_pdiffusion): 1500*nm, + (l_poly_contact, l_diff_contact): 1500*nm, +} + +# Layer for the pins. +pin_layer = l_metal2 + +# Power stripe layer +power_layer = l_metal1 + +# Layers that can be connected/merged without changing the schematic. +# This can be used to resolve spacing/notch violations by just filling the space. +connectable_layers = {l_nwell, l_pwell} +# Width of the gate polysilicon stripe. +# is reused as the minimum_width for the l_poly layer +gate_length = 1*um + +# Minimum length a polysilicon gate must overlap the silicon. +gate_extension = 1*um # Rule 3.3 + +# Minimum distance of active area to upper or lower boundary of the cell. Basically determines the y-offset of the transistors. +transistor_offset_y = 12*l + +# Standard cell dimensions. +# A 'unit cell' corresponds to the dimensions of the smallest possible cell. Usually an inverter. +# `unit_cell_width` also corresponds to the pitch of the gates because gates are spaced on a regular grid. +unit_cell_width = 8*um +unit_cell_height = 32*um # minimum 16um due to pwell width + nwell-pwell spacing +assert unit_cell_height >= 16*um, "minimum 16um due to pwell width + nwell-pwell spacing" +# due to nwell size and spacing requirements routing_grid_pitch_y * 8 # * 8 + +# Routing pitch +routing_grid_pitch_x = unit_cell_width // 2 // 1 +routing_grid_pitch_y = 1*um # unit_cell_height // 8 // 2 + +# Translate routing grid such that the bottom left grid point is at (grid_offset_x, grid_offset_y) +grid_offset_x = routing_grid_pitch_x +grid_offset_y = (routing_grid_pitch_y // 2 ) -0 + +# Width of power rail. +power_rail_width = 3*um # Minimum according to DRC rules is 1.5um , feel free to reduce below 3.um if you are sure that it is a good idea. +# Between 2 and 3 um + +# Minimum width of polysilicon gate stripes. +# It increases w and l from the spice netlist, so it must be width from the spice netlist +minimum_gate_width_nfet = 1*um +minimum_gate_width_pfet = 1*um + +# Minimum width for pins. +minimum_pin_width = 1*um + +# Width of routing wires. +wire_width = { + l_ndiffusion: 1*um, + l_pdiffusion: 1*um, + l_poly: 1*um, # Rule 3.1 + l_metal1: 1500*nm, # Rule 9.1 + l_metal2: 1500*nm, # Rule 11.1 +} + +# Width of horizontal routing wires (overwrites `wire_width`). +wire_width_horizontal = { + l_ndiffusion: 1*um, + l_pdiffusion: 1*um, + l_poly: 1*um, # Rule 3.1 + l_metal1: 1500*nm, # Rule 9.1 + l_metal2: 1500*nm, # +} + +# Side lengths of vias (square shaped). +via_size = { + l_poly_contact: 1*um, # Rule 7.1 + l_diff_contact: 1*um, # Rule 8.1 + l_via1: 1*um # Rule 10.1 +# l_via2: 10 # librecell only goes to metal2, via2 would go to metal3 +} + +# Minimum width rules. +minimum_width = { + l_ndiffusion: 1*um, # Rule 2.1 + l_pdiffusion: 1*um, # Rule 2.1 + l_poly: gate_length, # Rule 3.1 + l_metal1: 3*l, # Rule 9.1 + l_metal2: 3*l, # Rule 11.1 + l_nwell: 5*um, # Rule 1.1 +} + +# Minimum enclosure rules. +# Syntax: {(outer layer, inner layer): minimum enclosure, ...} +minimum_enclosure = { + # Via enclosure + (l_ndiffusion, l_diff_contact): 750*nm, # Rule 8.2 ? Thomas? + (l_pdiffusion, l_diff_contact): 750*nm, # Rule 8.2 ? + (l_poly, l_poly_contact): 750*nm, #Rule 7.2 + (l_metal1, l_diff_contact): 500*nm, #Rule 9.3 + (l_metal1, l_poly_contact): 500*nm, #Rule 9.3 + (l_metal1, l_via1): 500*nm, #Rule 10.3 + (l_metal2, l_via1): 500*nm, #Rule 11.3 + + # l_*well must overlap l_*diffusion + (l_nwell, l_pdiffusion): 3*um, # Rule 2.6.a + (l_pwell, l_ndiffusion): 2*l, # 2.3.3 -> 2l + (l_abutment_box, l_nwell): 0, # The nwell and pwell should not go beyond the abutment + (l_abutment_box, l_pwell): 0, +} + +# Minimum notch rules. +minimum_notch = { + l_ndiffusion: 2*um, # Rule 2.2 ??? + l_pdiffusion: 2*um, # Rule 2.2 ??? + l_poly: 1*l, # ??? + l_metal1: 1*l, + l_metal2: 1*l, + l_nwell: 1*l, + l_pwell: 1*l, +} + +# Minimum area rules. +min_area = { +# l_metal1: 100 * 100, +# l_metal2: 100 * 100, +} + +# ROUTING # + +# Cost for changing routing direction (horizontal/vertical). +# This will avoid creating zig-zag routings. +orientation_change_penalty = 100 + +# Routing edge weights per data base unit. +weights_horizontal = { + l_ndiffusion: 10000, + l_pdiffusion: 10000, + l_poly: 10, + l_metal1: 1, + l_metal2: 5, +} +weights_vertical = { + l_ndiffusion: 10000, + l_pdiffusion: 10000, + l_poly: 10, + l_metal1: 5, + l_metal2: 1, +} + +# Via weights. +via_weights = { + (l_metal1, l_ndiffusion): 500, + (l_metal1, l_pdiffusion): 500, + (l_metal1, l_poly): 500, + (l_metal1, l_metal2): 400 +} + +# Enable double vias between layers. +multi_via = { + (l_metal1, l_poly): 1, + (l_metal1, l_metal2): 1, +} + +# Ask Thomas Kramer: +# * Minimum Space between two active regions, one connected by metal +# to VDD and the other connected by metal to VSS (not illustrated). +# Rule 3.4 +# 3.5 ? +# 9.4+11.4 Big Metal rule please + +# Ask both: +# Minimum separation from a COLD N-well to N+ active (see COLD N- +# well for more detail) +# Space from N-well to N+ active outside N-well (COLD WELL) +# +#Minimum separation from a HOT N-well to N+ active (see HOT N-well +#for more detail) +#Space from N-well to N+ active outside N-well (HOT WELL) + +# Ask Djamel: 2.6 , 10.5a is missing in the graphics, explanation not clear + diff --git a/Tech.CDTA/libresilicon.m b/Tech.CDTA/libresilicon.m new file mode 100644 index 00000000..473e6e0a --- /dev/null +++ b/Tech.CDTA/libresilicon.m @@ -0,0 +1,14 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos level = 54 + +.model PMOS_VTL pmos level = 54 + +.model nmos nmos level = 54 + +.model pmos pmos level = 54 + +.model nfet nmos level = 54 + +.model pfet pmos level = 54 + diff --git a/Tech.CDTA/libresilicon.tech b/Tech.CDTA/libresilicon.tech new file mode 100644 index 00000000..62f426fb --- /dev/null +++ b/Tech.CDTA/libresilicon.tech @@ -0,0 +1,2242 @@ +# 1 "scmos.tech.out" +# 1 "" +# 1 "" +# 1 "/usr/include/stdc-predef.h" 1 3 4 +# 1 "" 2 +# 1 "scmos.tech.out" +# 351 "scmos.tech.out" +tech + format 33 + scmos +end + + + +version + version 0.1 + description "LibreSilicon process (1um)" +# 382 "scmos.tech.out" +end + +planes + well,w + implant,i + active,a + metal1,m1 + metal2,m2 + + + + metal3,m3 + metal4,m4 + oxide,ox +end + +types + + + well pwell,pw + well nwell,nw + well capwell,cwell,cw + well highvoltnwell,hvnwell,hnwell,hnw + well highvoltpwell,hvpwell,hpwell,hpw + active polysilicon,red,poly,p + active pbasepolysilicon,pbpoly,pbp + active nbasepolysilicon,nbpoly,nbp + active electrode,poly2,el,p2 + active capacitor,polycap,pcap,cap + active wellcapacitor,wellcap,wcap + active ndiffusion,ndiff,green + active pdiffusion,pdiff,brown + active highvoltndiffusion,hvndiff,hndiff + active highvoltpdiffusion,hvpdiff,hpdiff + metal1 metal1,m1,blue + metal2 metal2,m2,purple + metal3 metal3,m3,cyan + metal4 metcap,mcap + + + + active sonosntransistor,snfet + active sonosptransistor,spfet + active pbsonostransistor,pbsfet + active nbsonostransistor,nbsfet + active ntransistor,nfet + active ptransistor,pfet + active entransistor,enfet + active eptransistor,epfet + active doublentransistor,nfloating-gate,nfloatg,nfg,nffet + active doubleptransistor,pfloating-gate,pfloatg,pfg,pffet + active highvoltntransistor,hvnfet,hnfet + active highvoltptransistor,hvpfet,hpfet + active rntransistor,rnfet + active rptransistor,rpfet + + + + + active collector,coll,col,co,cl + active emitter,emit,em + + + well pbase,pb + well nbase,nb + well pnbase,pnb + well nwpbase,nwpb + well nwpnbase,nwpnb + + active pbasecontact,pbcontact,pbc + active pbasendiffusion,pbndiff,pbnd + active pbasepdiffusion,pbpdiff,pbpd + active pbasendiffcontact,pbndcontact,pbnc + active pbasepdiffcontact,pbpdcontact,pbpc + + active nbasecontact,nbcontact,nbc + active nbasendiffusion,nbndiff,nbnd + active nbasepdiffusion,nbpdiff,nbpd + active nbasendiffcontact,nbndcontact,nbnc + active nbasepdiffcontact,nbpdcontact,nbpc + + + + implant bccdiffusion,bd + active nbccdiffusion,nbd + + + active rndiffusion,rndiff,rnd + active rpdiffusion,rpdiff,rpd + active rpoly,rp,resistor,res + active polycontact,pcontact,polycut,pc + active pdpolycontact,pdpcontact,pdpolycut,pdpc + active ndpolycontact,ndpcontact,ndpolycut,ndpc + active ndcontact,ndiffcut,ndc + active pdcontact,pdiffcut,pdc + active highvoltndcontact,hndiffcut,hndc + active highvoltpdcontact,hpdiffcut,hpdc + active capcontact,ccontact,capc,cc + active electrodecontact,econtact,ec,poly2contact,p2c + active collectorcontact,colcontact,colc,coc,clc + active emittercontact,emitcontact,emc + active nbccdiffcontact,nbdc + metal1 m2contact,m2cut,m2c,via,v + + + + metal2 m3contact,m3cut,m3c,via2,v2 + + + + + + + active psubstratepcontact,ppcontact,ppc,pwcontact,pwc,psc + active nsubstratencontact,nncontact,nnc,nwcontact,nwc,nsc + active psubstratepdiff,ppdiff,pohmic,ppd,psd + active nsubstratendiff,nndiff,nohmic,nnd,nsd + + active highvoltpsubcontact,hpwcontact,hpsc + active highvoltnsubcontact,hnwcontact,hnsc + active highvoltpsubdiff,hpohmic,hpsd + active highvoltnsubdiff,hnohmic,hnsd + + + active nplusdoping,ndoping,ndop + active pplusdoping,pdoping,pdop + metal1 genericcontact,gcontact,gc + + + oxide substrateopen,subopen,open + oxide pdiffusionstop,pdiffstop,pstop + + + metal2 pad + oxide glass + metal3 silk + + active polyndiff,plndiff + active polypdiff,plpdiff + +end + +contact + + ec poly2 metal1 + cc cap metal1 + pc poly metal1 + + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + psc psd metal1 + hndc hndiff metal1 + hpdc hpdiff metal1 + hnsc hnsd metal1 + hpsc hpsd metal1 + + clc col metal1 + emc emit metal1 + + + + + + + + nbdc nbd metal1 + + m2c metal1 metal2 + + + + m3c metal2 metal3 + + + + # MAGIC: stackable! + stackable +end + +styles + styletype mos + + + cwell 10 + nwell 12 + pwell 13 + hnwell 18 + hpwell 11 + + poly 1 + poly2 14 + + ndiff 2 + pdiff 4 + psd 5 + nsd 3 + hndiff 2 + hndiff 11 + hpdiff 4 + hpdiff 18 + hpsd 5 + hpsd 11 + hnsd 3 + hnsd 18 + ndop 2 + ndop 38 + pdop 4 + pdop 38 + + rnfet 6 + rpfet 6 + snfet 6 + spfet 6 + nbsfet 6 + pbsfet 6 + nfet 6 + nfet 7 + rnfet 6 + rnfet 7 + pfet 8 + pfet 9 + rpfet 8 + rpfet 9 + + enfet 6 + enfet 30 + + epfet 8 + epfet 31 + + + nffet 6 + nffet 7 + + nffet 30 + pffet 8 + pffet 9 + + pffet 31 + + hnfet 6 + hnfet 7 + hnfet 30 + + hpfet 8 + hpfet 9 + hpfet 31 + + + pbase pdop_stripes + pbc 15 + pbc 20 + pbc 32 + pbnd 2 + pbpd 4 + pbnc 2 + pbpc 4 + pbnc 32 + pbpc 32 + + + nbase ndop_stripes + nbc 20 + nbc 32 + nbnd 2 + nbpd 4 + nbnc 2 + nbpc 4 + nbnc 32 + nbpc 32 + + + pnbase ndop_stripes + nwpnbase ndop_stripes + + nwpbase pdop_stripes + + + emit 16 + emc 16 + emc 20 + emc 32 + + col 3 + clc 3 + clc 20 + clc 32 + + cap 1 + cap 14 + wcap 6 + wcap 10 + cc 1 + cc 14 + cc 20 + cc 32 + + metal1 20 + metal2 21 + metal3 22 + metcap 23 + + gc 19 + + pcontact 26 + pcontact 32 + ec 14 + ec 20 + ec 32 + + ndpc 32 + pdpc 32 + ndc 2 + ndc 20 + ndc 32 + pdc 4 + pdc 20 + pdc 32 + psc 5 + psc 20 + psc 32 + nsc 3 + nsc 20 + nsc 32 + + hndc 2 + hndc 20 + hndc 32 + hndc 11 + hpdc 4 + hpdc 20 + hpdc 32 + hpdc 18 + hpsc 5 + hpsc 20 + hpsc 32 + hpsc 11 + hnsc 3 + hnsc 20 + hnsc 32 + hnsc 18 + + m2contact 20 + m2contact 21 + m2contact 33 + m3contact 21 + m3contact 22 + m3contact 37 + + pad 20 + pad 21 + pad 33 + pad 34 + glass 34 + + bd 17 + nbd 17 + nbd 3 + nbdc 3 + nbdc 17 + nbdc 20 + nbdc 32 + + open 2 + open 20 + pstop 8 + + error_p 42 + error_s 42 + error_ps 42 + res poly_resist poly_resist_stripes + + rnd ntransistor_stripes + rpd ptransistor_stripes + + rnfet polysilicon poly_resist_stripes + rpfet polysilicon ptransistor_stripes + + plpdiff polysilicon ptransistor_stripes + plndiff polysilicon ntransistor_stripes + pbpoly polysilicon ptransistor_stripes + nbpoly polysilicon ntransistor_stripes + silk 47 +end +compose + + compose nfet poly hndiff + compose pfet poly hpdiff + compose nfet poly ndiff + compose pfet poly pdiff + compose hnfet poly2 hndiff + compose hpfet poly2 hpdiff + compose enfet poly2 ndiff + compose epfet poly2 pdiff + compose nffet nfet poly2 + compose pffet pfet poly2 + compose nffet enfet poly + compose pffet epfet poly + compose cap poly poly2 + + + + + + paint clc col clc + paint emc emit emc + + paint emc pbase emc + paint pbnd pbase pbnd + paint pbpd pbase pbpd + paint snfet pbase pbsfet + paint spfet pbase pbsfet + paint pbsfet pbase pbsfet + paint poly pbase pbpoly + paint pbpoly pbase pbpoly + paint ndiff pbase pbnd + paint pdiff pbase pbpd + paint ndc pbase pbnc + paint pdc pbase pbpc + paint pbpc pbase pbpc + paint pbnc pbase pbnc + paint ppc pbase pbpc + paint nnc pbase pbnc + + paint nbnd pbase nbnd + paint nbpd pbase nbpd + paint nbnc pbase nbnc + paint nbpc pbase nbpc + paint nbpoly pbase nbpoly + + paint emc nwpbase emc + paint pbnd nwpbase pbnd + paint pbpd nwpbase pbpd + paint snfet nwpbase pbsfet + paint spfet nwpbase pbsfet + paint pbsfet nwpbase pbsfet + paint poly nwpbase pbpoly + paint pbpoly nwpbase pbpoly + paint ndiff nwpbase pbnd + paint pdiff nwpbase pbpd + paint ndc nwpbase pbnc + paint pdc nwpbase pbpc + paint pbpc nwpbase pbpc + paint pbnc nwpbase pbnc + paint ppc nwpbase pbpc + paint nnc nwpbase pbnc + + paint nbnd nwpbase nbnd + paint nbpd nwpbase nbpd + paint nbnc nwpbase nbnc + paint nbpc nwpbase nbpc + paint nbpoly nwpbase nbpoly + + + paint nbnd nbase nbnd + paint nbpd nbase nbpd + paint snfet nbase nbsfet + paint spfet nbase nbsfet + paint nbsfet nbase nbsfet + paint poly nbase nbpoly + paint nbpoly nbase nbpoly + paint ndiff nbase nbnd + paint pdiff nbase nbpd + paint ndc nbase nbnc + paint pdc nbase nbpc + paint nbpc nbase nbpc + paint nbnc nbase nbnc + paint ppc nbase nbpc + paint nnc nbase nbnc + + + paint nwpbase nbase nwpnbase + paint nbnd nbase nbnd + paint pbase nbase pnbase + + paint nwpbase nwell nwpbase + paint pnbase nwell nwpnbase + paint nwpnbase nwell nwpnbase + + paint nwell pbase nwpbase + paint nbase pbase pnbase + paint nwpbase pbase nwpbase + + paint nwpnbase nwpbase nwpnbase + + + paint pbase nwell nwpbase + + + paint poly2 poly cap + paint poly poly2 cap + paint poly cap cap + paint poly2 cap cap + paint cap poly cap + paint cap poly2 cap + + + paint ec poly cc + + + + paint pdc pwell ndc + paint pfet pwell nfet + paint epfet pwell enfet + paint pffet pwell nffet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint ndc nwell pdc + paint nfet nwell pfet + paint enfet nwell epfet + paint nffet nwell pffet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + + paint pdc hpwell hndc + paint epfet hpwell hnfet + paint pffet hpwell hnfet + paint pdiff hpwell hndiff + paint nsd hpwell hpsd + paint nsc hpwell hpsc + paint ndc hnwell hpdc + paint enfet hnwell hpfet + paint nffet hnwell hpfet + paint ndiff hnwell hpdiff + paint psd hnwell hnsd + paint psc hnwell hnsc +# 919 "scmos.tech.out" + paint nfet cwell wcap + paint poly wcap wcap + paint ndiff wcap wcap + paint wcap poly wcap + paint wcap ndiff wcap + erase wcap poly ndiff + erase wcap ndiff poly + erase wcap cwell nfet + paint cwell nfet wcap active + erase wcap nfet cwell well + + + paint gc m1 gc + + + paint pad m1 pad + paint pad m2 pad + paint pad m3 pad + paint pad m2c pad + + + + + paint hpdc hpwell hndc + paint hpfet hpwell hnfet + paint hpdiff hpwell hndiff + paint hnsd hpwell hpsd + paint hnsc hpwell hpsc + paint hndc hnwell hpdc + paint hnfet hnwell hpfet + paint hndiff hnwell hpdiff + paint hpsd hnwell hnsd + paint hpsc hnwell hnsc + + paint hpdc pwell ndc + paint hpfet pwell enfet + paint hpdiff pwell ndiff + paint hnsd pwell psd + paint hnsc pwell psc + paint hndc nwell pdc + paint hnfet nwell epfet + paint hndiff nwell pdiff + paint hpsd nwell nsd + paint hpsc nwell nsc + +end + +connect + + + + + + + + nwell,nsc,nsd nwell,nsc,nsd + pwell,psc,psd pwell,psc,psd + + hnwell,hnsc,hnsd hnwell,hnsc,hnsd + hpwell,hpsc,hpsd hpwell,hpsc,hpsd + + ndiff,ndc/a cwell + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc + m2,m2c/m2,m3c/m2,pad m2,m2c/m2,m3c/m2,pad + m3,m3c/m3 m3,m3c/m3 + + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly + poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet + + + + ndiff,ndc/a,ndop psd,psc/a,pdop,pstop + pdiff,pdc/a,pdop,pstop nsd,nsc/a,ndop + hndiff,hndc/a,ndop hpsd,hpsc/a,pdop,pstop + hpdiff,hpdc/a,pdop,pstop hnsd,hnsc/a,ndop + ndiff ndc + pdiff pdc + hndiff hndc + hpdiff hpdc + + nbd nbdc + + pbase pbc + collector clc,nwell + emitter emc + + gc ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a,nsd,nsc/a,psd,psc/a,hndiff,hndc/a,hpdiff,hpdc/a,metal1 + gc poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly + gc poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet + + pad pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc + pad m2,m2c/m2,m3c/m2,pad + pad m3,m3c/m3 + +end +# 1024 "scmos.tech.out" +cifoutput + + + + + + +# 1 "cif_template/objs/LSACIFout" 1 + + + style lambda=0.5(gen)(libresilicon) + scalefactor 50 5 + + templayer poly_parts polysilicon,polycontact,nfet,pfet,rpoly,polypdiff,polyndiff,ndpolycontact,pdpolycontact,nbsfet,pbsfet,spfet,snfet,pbpoly,nbpoly,hnfet,hpfet,rnfet,rpfet + + templayer silicide_stop rpoly,rnfet,rpfet,rpdiffusion,rndiffusion + grow 100 + + templayer nimplant ndiff,nfet,ndc,nnd,nnc,pbnc,pbnd,nbnc,nbnd,snfet,pbsfet,hnfet,hndc,hndiff,rndiff,rpdiff,rpfet,rnfet + + templayer nimplant_only rnd,plndiff,ndpc + grow 100 + + templayer pimplant pdiff,pfet,pdc,ppd,ppc,pbpc,pbpd,nbpc,nbpd,spfet,nbsfet,hpfet,hpdc,hpdiff + + templayer pimplant_only rpd,plpdiff,pdpc + grow 100 + + templayer contacts pc,pdc,ndc,ppc,nnc,pbc,ndpc,pdpc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,pc,pdc,ndc,ppc,nnc,pbc,hpdc,hndc + + templayer first_metal m1,contacts,m2c + + templayer first_via m2c + shrink 50 + + templayer second_metal m2,m2c,m3c + + templayer second_via m3c + shrink 50 + + templayer third_metal m3,m3c,pad,silk + + templayer pbase_parts pb,pbnc,pbpc,pbnd,pbpd,pbpoly,pbsfet,nwpnbase,nwpbase,pnbase,pbase + + templayer nbase_parts nb,nbnc,nbpc,nbnd,nbpd,nbpoly,nbsfet,nwpnbase,pnbase,nbase + + templayer sonos_parts snfet,spfet,nbsfet,pbsfet + + templayer nwell_parts nwell,pnbase,nwpnbase,nwpbase + + templayer pwell_parts pwell + + templayer implant_stop_parts rpoly + grow 100 + + templayer fox_selects nimplant,pimplant + + templayer fox_nimplant nimplant + grow 100 + + templayer fox_pimplant pimplant + grow 100 + + templayer sti_wells nwell_parts,pwell_parts + shrink 50 + + templayer sti_contacts psc,nsc + grow 50 + + layer CWN nwell_parts + calma 2 0 + + layer CWP pwell_parts + calma 3 0 + + layer CWP pbase_parts + calma 4 0 + + layer CWP nbase_parts + calma 5 0 + + layer STI sti_wells,sti_contacts + calma 6 0 + + layer FOX fox_selects + calma 7 0 + + layer CPG sonos_parts + grow 50 + calma 8 0 + + layer CPG poly_parts + calma 9 0 + + layer CPG implant_stop_parts + calma 10 0 + + layer CSN fox_nimplant,nimplant_only + calma 11 0 + + layer CSP fox_pimplant,pimplant_only + calma 12 0 + + layer CRG silicide_stop + calma 13 0 + + layer CCA contacts + shrink 50 + calma 14 0 + + layer CMF first_metal + calma 15 0 + + layer CVA first_via + calma 16 0 + + layer CMS second_metal + calma 17 0 + + layer CVS second_via + calma 18 0 + + layer CMT third_metal + calma 19 0 + + layer COG glass + calma 20 0 +# 1032 "scmos.tech.out" 2 +# 1050 "scmos.tech.out" + style plot + scalefactor 100 50 + layer CM2 m2,m2c/m2,pad/m2 + labels m2 + layer CM1 pad + grow 100 + or m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1 + labels m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1,pad/m1 + layer CP poly,pc/active,nfet,pfet + labels poly,nfet,pfet + layer CND ndiff,ndc,nfet,pwc,psd + labels ndiff + layer CPD pdiff,pdc,pfet,nwc,nsd + labels pdiff + layer CNP + bloat-or nsd,nwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 + layer CPP + bloat-or psd,pwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 + layer CV m2c + squares 100 200 300 + layer CC ndc,pdc,pc,pwc,nwc + squares 200 + layer CNW nwell + grow 400 + shrink 400 + layer CG pad + shrink 600 + or glass + labels glass + + +end +# 1093 "scmos.tech.out" +cifinput +# The following section is defined to be able to import GDS2 cells generated by librecell +# 1097 "scmos.tech.out" + style generic + scalefactor 100 + + templayer poly_parts polysilicon,polycontact,nfet,pfet,rpoly,polypdiff,polyndiff,ndpolycontact,pdpolycontact,rpdiffusion,rndiffusion,nbsfet,pbsfet,spfet,snfet,pbpoly,nbpoly,hnfet,hpfet + templayer silicide_stop rpoly,rpdiffusion,rndiffusion + templayer nimplant ndiff,nfet,ndc,nnd,nnc,pbnc,pbnd,nbnc,nbnd,snfet,pbsfet,hnfet,hndc,hndiff + templayer nimplant_only rnd,plndiff,ndpc + grow 100 + templayer pimplant pdiff,pfet,pdc,ppd,ppc,pbpc,pbpd,nbpc,nbpd,spfet,nbsfet,hpfet,hpdc,hpdiff + templayer pimplant_only rpd,plpdiff,pdpc + grow 100 + templayer contacts pc,pdc,ndc,ppc,nnc,pbc,ndpc,pdpc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,pc,pdc,ndc,ppc,nnc,pbc,hpdc,hndc + templayer first_metal m1,contacts,m2c + templayer first_via m2c + shrink 50 + templayer second_metal m2,m2c,m3c + templayer second_via m3c + shrink 50 + templayer third_metal m3,m3c,pad,silk + templayer pbase_parts pb,pbnc,pbpc,pbnd,pbpd,pbpoly,pbsfet,nwpnbase,nwpbase,pnbase,pbase + templayer nbase_parts nb,nbnc,nbpc,nbnd,nbpd,nbpoly,nbsfet,nwpnbase,pnbase,nbase + templayer sonos_parts snfet,spfet,nbsfet,pbsfet + templayer nwell_parts nwell,pnbase,nwpnbase,nwpbase + templayer pwell_parts pwell + templayer implant_stop_parts rpoly + grow 100 + templayer fox_selects nimplant,pimplant + templayer fox_nimplant nimplant + templayer fox_pimplant pimplant + templayer sti_wells nwell_parts,pwell_parts + templayer sti_contacts psc,nsc + + + layer pdiffusion pdiffusion + calma pdiffusion 1 0 + + layer nwell nwell_parts + calma nwell 2 0 + + layer pwell pwell_parts + calma pwell 2 7 + + layer poly poly + calma poly 3 0 + + layer polycontact polycontact + calma polycontact 4 0 + + layer ndcontact ndcontact + calma ndcontact 5 0 + + layer metal1 metal1 + calma metal1 6 0 + calma metal1 6 1 + labels metal1 + + + layer m2contact m2contact + calma m2contact 7 0 + labels metal2 + + layer metal2 metal2 + calma metal2 8 0 + calma metal2 8 1 + calma metal2 8 2 + labels metal2 + + layer pdcontact pdcontact + calma pdcontact 5 0 + + templayer abutment + calma abutment 200 0 + boundary + + +# 1111 "scmos.tech.out" +end + +mzrouter + style irouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + layer poly 128 128 512 1 + contact m2contact metal1 metal2 1024 + contact pcontact metal1 poly 2056 + notactive poly pcontact + style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 +end + + + +drc +# 1143 "scmos.tech.out" + edge4way (~nwell)/w nwell 10 nwell nwell 10\ + "N-Well width must be at least 10 (MOSIS rule #1.1)" + edge4way (~pwell)/w pwell 10 pwell pwell 10\ + "P-Well width must be at least 10 (MOSIS rule #1.1)" +# 1163 "scmos.tech.out" + edge4way nwell (~nwell)/w 9 (~nwell)/w (~nwell)/w 9\ + "N-Well spacing must be at least 9 (MOSIS rule #1.2)" + edge4way pwell (~pwell)/w 9 (~pwell)/w (~pwell)/w 9\ + "P-Well spacing must be at least 9 (MOSIS rule #1.2)" +# 1202 "scmos.tech.out" + width ndiff,ndc/a,nfet,enfet,nffet,wcap 2 \ + "N-type Diffusion width must be at least 2" + width pdiff,pdc/a,pfet,epfet,pffet 2 \ + "P-type Diffusion width must be at least 2" + width nsd,nsc/a,psd,psc/a 2 \ + "Ohmic diffusion width must be at least 2" +# 1218 "scmos.tech.out" + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap ndiff,ndc/a,nfet,enfet,nffet,wcap 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing pdiff,pdc/a,pfet,epfet,pffet pdiff,pdc/a,pfet,epfet,pffet 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing nsd,nsc/a nsd,nsc/a 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing psd,psc/a psd,psc/a 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + + + + + + + spacing ndiff,ndc/a pdiff,pdc/a 10 touching_illegal \ + "P-type diffusion must be 10 away from N-type diffusion (MOSIS rule #2.3a)" +# 1243 "scmos.tech.out" + spacing ndiff,ndc/a nsd,nsc/a 8 touching_illegal \ + "N-type diffusion must be 8 away from N-substrate contact (MOSIS rule #2.3a,4a)" + spacing pdiff,pdc/a psd,psc/a 8 touching_illegal \ + "P-type diffusion must be 8 away from P-substrate contact (MOSIS rule #2.3a,4a)" + + + + spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ + "Opposite well contacts must be separated by 6 (MOSIS rule #2.4)" +# 1260 "scmos.tech.out" + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap nwell 5 touching_illegal \ + "N-diffusion and N-well must be separated by 5 (MOSIS rule #2.3a)" + spacing pdiff,pdc/a,pfet,epfet,pffet pwell 5 touching_illegal \ + "P-diffusion and P-well must be separated by 5 (MOSIS rule #2.3a)" + + + + spacing nsd,nsc/a pwell 3 touching_illegal \ + "N-substrate diffusion and P-well must be separated by 3 (MOSIS rule #2.4)" + spacing psd,psc/a nwell 3 touching_illegal \ + "P-substrate diffusion and N-well must be separated by 3 (MOSIS rule #2.4)" + + + + + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap psd,psc/a 4 touching_ok \ + "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" + spacing pdiff,pdc/a,pfet,epfet,pffet nsd,nsc/a 4 touching_ok \ + "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" + + + + + + + width poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 2 \ + "Polysilicon width must be at least 2 (MOSIS rule #3.1)" + + + + + + + spacing poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 2 touching_ok \ + "Polysilicon spacing must be at least 2 (MOSIS rule #3.2a)" + + + + edge4way nfet,pfet poly,pc/act 2 poly,pc/act 0 0 \ + "Poly must overhang transistor by at least 2 (MOSIS rule #3.3)" + + + edge4way nfet,enfet ndiff,ndc/a 3 ndiff,ndc/a,nfet,enfet,nffet,wcap ndiff,ndc/a 3 \ + "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" + edge4way pfet,epfet pdiff,pdc/a 3 pdiff,pdc/a,pfet,epfet,pffet ndiff,ndc/a 3 \ + "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" + + + edge4way nfet,pfet space 1 poly 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way enfet,epfet space 1 poly2 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way nffet,pffet space 1 poly 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way nffet,pffet space 1 poly2 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a poly,pc 1 space/a 0 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge4way poly,pc ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a 1 space/a 0 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge poly,pc space/a 1 space/a space/a 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge nsd,nsc/a,psd,psc/a,ndiff,ndc/a,pdiff,pdc/a space/a 1 space/a space/a 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" +# 1349 "scmos.tech.out" + spacing pfet,epfet,pffet nsd,nsc/a 3 touching_illegal \ + "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.a)" + spacing nfet,enfet,nffet psd,psc/a 3 touching_illegal \ + "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.b)" + + edge4way psd,psc/a space/act 3 ~(nfet,enfet,nffet)/act psd,psc/a,ndiff,ndc/a 3 \ + "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.c)" + + edge4way nsd,nsc/a space/act 3 ~(pfet,epfet,pffet)/act nsd,nsc/a,pdiff,pdc/a 3 \ + "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.d)" + + edge4way psd,psc/a ~(ndiff,ndc,psc,psd)/act 4 ~(nfet,enfet)/act ~(ndiff,ndc,psc,psd)/act 4 \ + "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.e)" + + edge4way nsd,nsc/a ~(pdiff,pdc,nsc,nsd)/act 4 ~(pfet,epfet)/act ~(pdiff,pdc,nsc,nsd)/act 4 \ + "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.f)" + + + + edge4way ~(pdiff,pdc/a,pfet,epfet,pffet)/act pdiff,pdc,pfet 4 ~(nsd,nsc/a)/act pdiff,pdc/a,pfet,epfet,pffet 2 \ + "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.a)" + edge4way ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/act ndiff,ndc,nfet 4 ~(psd,psc/a)/act ndiff,ndc/a,nfet,enfet,nffet,wcap 2 \ + "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.b)" +# 1383 "scmos.tech.out" + width pc 2 \ + "Poly contact width must be at least 2 (MOSIS rule #5B.1,2,3)" + + + + + + + + edge4way poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet ~(poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet)/act 3 ~pc/act ~(poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet)/act 3 \ + "Poly contact must be at least 3 from other poly (MOSIS rule #5B.4,5)" + + + + + + spacing pc ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a 1 touching_illegal \ + "Poly contact must be 1 unit from diffusion (MOSIS rule #5B.6)" +# 1409 "scmos.tech.out" + width ndc,pdc 2 \ + "Diffusion contact width must be at least 2 (MOSIS rule #6B.1,2,3)" + width nsc,psc 4 \ + "Substrate contact width must be at least 4 (MOSIS rule #6B.1,2,3)" +# 1433 "scmos.tech.out" + edge4way ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a ~(ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a)/act 4 ~(ndc,pdc,nsc,psc)/act \ + ~(ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a)/act 4 \ + "Diffusion contacts must be 4 from other diffusions (MOSIS rule #6B.4,5)" + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc nfet,enfet,nffet,pfet,epfet,pffet 1 touching_illegal \ + "Diffusion contacts cannot touch transistors (MOSIS rule #6B.6)" + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc poly 1 touching_illegal \ + "Diffusion contact to field poly must be at least 1 (MOSIS rule #6B.7)" + + + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc pc/act 2 touching_illegal \ + "Poly contacts must be 2 away from diffusion contacts (MOSIS rule #6B.9)" +# 1458 "scmos.tech.out" + edge4way m3c/m3 ~m3c/m3 1 ~m3c/m3 (~m3c,m3c)/m3 1 \ + "Metal3 contacts must be rectangular (Magic rules)" + edge4way m2c/m2 ~m2c/m2 1 ~m2c/m2 (~m2c,m2c)/m2 1 \ + "Metal2 contacts must be rectangular (Magic rules)" + + edge4way ndc/m1 ~ndc/m1 1 ~ndc/m1 (~ndc,ndc)/m1 1 \ + "N-diffusion contacts must be rectangular (Magic rules)" + edge4way pdc/m1 ~pdc/m1 1 ~pdc/m1 (~pdc,pdc)/m1 1 \ + "P-diffusion contacts must be rectangular (Magic rules)" + edge4way psc/m1 ~psc/m1 1 ~psc/m1 (~psc,psc)/m1 1 \ + "P-substrate contacts must be rectangular (Magic rules)" + edge4way nsc/m1 ~nsc/m1 1 ~nsc/m1 (~nsc,nsc)/m1 1 \ + "N-substrate contacts must be rectangular (Magic rules)" + + edge4way pc/m1 ~pc/m1 1 ~pc/m1 (~pc,pc)/m1 1 \ + "Polysilicon contacts must be rectangular (Magic rules)" + edge4way ec/m1 ~ec/m1 1 ~ec/m1 (~ec,ec)/m1 1 \ + "Electrode contacts must be rectangular (Magic rules)" + edge4way cc/m1 ~cc/m1 1 ~cc/m1 (~cc,cc)/m1 1 \ + "Capacitor contacts must be rectangular (Magic rules)" + + edge4way emc/m1 ~emc/m1 1 ~emc/m1 (~emc,emc)/m1 1 \ + "Emitter contacts must be rectangular (Magic rules)" + edge4way clc/m1 ~clc/m1 1 ~clc/m1 (~clc,clc)/m1 1 \ + "Collector contacts must be rectangular (Magic rules)" + edge4way pbpc/m1 ~pbpc/m1 1 ~pbpc/m1 (~pbpc,pbpc)/m1 1 \ + "P-base Contacts must be rectangular (Magic rules)" + edge4way nbdc/m1 ~nbdc/m1 1 ~nbdc/m1 (~nbdc,nbdc)/m1 1 \ + "CCD-diffusion Contacts must be rectangular (Magic rules)" + + + + + + width pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 3 \ + "First-level metal width must be at least 3 (MOSIS rule #7.1)" + + + + + spacing pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 3 touching_ok \ + "First-level metal spacing must be at least 3 (MOSIS rule #7.2)" +# 1511 "scmos.tech.out" + width m2c 2 \ + "Contact width must be at least 2 (MOSIS rule #8.1,2,3)" +# 1540 "scmos.tech.out" + width m2,m2c/m2,m3c/m2,pad 3 \ + "Second-level metal width must be at least 3 (MOSIS rule #9.1)" +# 1552 "scmos.tech.out" + spacing m2,m2c/m2,m3c/m2,pad m2,m2c/m2,m3c/m2,pad 4 touching_ok \ + "Second-level metal spacing must be at least 4 (MOSIS rule #9.2a)" +# 1610 "scmos.tech.out" + width cap,capc/a 2 \ + "Electrode capacitor width must be at least 3 (MOSIS rule #11.1)" + + + spacing poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet 3 touching_ok \ + "Second-level poly spacing must be at least 3 (MOSIS rule #11.2,12.2)" + + + edge4way cap,cc space 1 0 0 0 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + edge4way cap,cc poly 2 poly poly 2 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + edge4way cap,cc poly2 2 poly2 poly2 2 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + + + edge4way nw,pw,cw ~(nw,pw,cw)/w 2 ~(cap,cc)/a ~(nw,pw,cw)/w 2 \ + "Cap must be on a flat surface (MOSIS rule #11.4)" active + edge4way ~(nw,pw,cw)/w nw,pw,cw 2 ~(cap,cc)/a nw,pw,cw 2 \ + "Cap must be on a flat surface (MOSIS rule #11.4)" active + edge4way cap ~(cap)/a 2 nfet,enfet,nffet,pfet,epfet,pffet,poly,poly2,space/a,cc/a \ + ndiff,ndc/a,pdiff,pdc/a,poly 2 "Cap must be on a flat surface (MOSIS rule #11.4)" active +# 1641 "scmos.tech.out" + width poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet 2 \ + "Electrode width must be at least 2 (MOSIS rule #12.1)" + + + + + + edge4way enfet,epfet poly2,ec/a 2 poly2,ec/a 0 0 \ + "Poly2 must overhang transistor by at least 2 (MOSIS rule #12.3)" + edge4way nffet,pffet cap 2 cap 0 0 \ + "Cap must overhang transistor by at least 2 (MOSIS rule #12.3)" + edge4way nffet ~(cap,nffet,enfet,nfet)/a 2 cap 0 0 \ + "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" + edge4way pffet ~(cap,pffet,epfet,pfet)/a 2 cap 0 0 \ + "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a el 1 space/a 0 1 \ + "Poly2 and diffusion must be separated by at least 1 (MOSIS rule #12.4)" + + + + + spacing poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet pc,ndc,pdc 2 touching_illegal \ + "Poly2 spacing to poly or diffusion contact must be at least 3 (MOSIS rule #12.6)" +# 1682 "scmos.tech.out" + width ec,capc 4 \ + "Electrode contact width must be at least 4 (MOSIS rule #13.1)" + + + + + + edge4way ec/a space 1 poly2 poly2 1 \ + "Electrode contact must be overlaped by poly2 (MOSIS rule #13.4)" + edge4way ec/a poly2 1 poly2 poly2 1 \ + "Electrode contact must be overlaped by poly2 by 1 (MOSIS rule #13.4)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a ec 2 space/a 0 2 \ + "Poly2 and diffusion contact must be separated by at least 2 (MOSIS rule #13.5)" + + + + + + + + width m3c 4 \ + "Third-level metal contact width must be at least 4 (MOSIS rule #14.1,2,3)" +# 1717 "scmos.tech.out" + width m3,m3c/m3 4 \ + "Third-level metal width must be at least 4" +# 1734 "scmos.tech.out" + spacing m3,m3c/m3 m3,m3c/m3 4 touching_ok \ + "Third-level metal spacing must be at least 4 from other third-level metal (MOSIS rule #15.2a)" + + + + edge4way m3c/m3 ~m3c/m3 1 m3 m3 1 \ + "Mimimum metal3 overlap of via must be at least 1 (MOSIS rule #15.3)" +# 1749 "scmos.tech.out" + width clc,pbc,emc 4 \ + "Transistor contact width must be at least 4 (MOSIS rule #16.1)" +# 1760 "scmos.tech.out" +# edge4way emc/a,emit pbase 4 pbase pbase 4 \ +# "Pbase overlap of emitter must be at least 4 (MOSIS rule #16.3)" + + + + spacing pbc emc/a,emit 7 touching_illegal \ + "Base must be 7 (4+2+1) away from emitter (MOSIS rule #16.3,4,11)" + + + + + + # edge4way pbc (~pbc)/a 3 pb,pbc/a pb,pbc/a 3 \ +# "Pbase overlap of base contact must be at least 3 (MOSIS rule #16.5)" +# 1782 "scmos.tech.out" + width col,clc/a 6 \ + "Collector width must be at least 6 (MOSIS rule #16.6)" + + + +# edge4way pbase space/a 6 nwell space/a 6 \ +# "Nwell overlap of Pbase must be at least 6 (MOSIS rule #16.7)" well + + +# edge4way pbase (~pbase)/a 4 ~(col,clc)/a ~(col,clc)/a 4 \ +# "Pbase must be at least 4 away from collector (MOSIS rule #16.8)" + + + edge4way clc (~clc)/a 1 col col 1 \ + "Collector overlap of contact must be at least 1 (MOSIS rule #16.9)" + + + + + + + edge4way nw ~(nw)/w 3 ~(col,clc)/a ~(nw)/w 3 \ + "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active + edge4way ~(nw)/w nw 3 ~(col,clc)/a nw 3 \ + "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active + + + width em,emc/a 4 \ + "Emitter width must be at least 4 (Magic Bipolar Transistor rule)" + + + + spacing em,emc/a em,emc/a 7 touching_ok \ + "Unrelated emitter must be at least 7 apart (Magic Bipolar transistor rule)" + + + + + +# width pbase,pbc/a 2 \ +# "Pbase width must be at least 2 (MOSIS extension rule)" + +# spacing pbase,pbc/a pbase,pbc/a 2 surround_ok \ +# "Pbase spacing must be at least 2 (MOSIS extension rule)" +# 1835 "scmos.tech.out" + width cwell 10 \ + "Cap-well width must be at least 10 (MOSIS rule #17.1)" + + + spacing cwell cwell 9 touching_ok \ + "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" + spacing cwell nwell 9 touching_illegal \ + "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" + + + edge4way cwell space 5 ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/a ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/w 5 \ + "Cap-well spacing to external active must be at least 5 (MOSIS rule #17.3)" active + edge4way cwell space 3 ~(psd,psc/a)/a ~(psd,psc/a)/w 3 \ + "P-substrate diffusion and Cap-well must be separated by 3 (MOSIS rule #17.3)" active + + + + + + edge4way space cwell 3 (space,poly,pc)/a 0 0 \ + "Cap-well overlap of diffusion must be at least 3 (MOSIS rule #17.4)" active +# 1865 "scmos.tech.out" + width wcap 3 \ + "Well-capacitor must be at least 3 (MOSIS rule #18.1)" + + + + + + edge4way wcap space 1 poly poly 1 \ + "Well-capacitor overhang is missing (MOSIS rule #18.3)" + + + edge4way wcap ndiff 3 ndiff ndiff 3 \ + "N-diffusion overlap of well-capacitor must be at least 3 (MOSIS rule #18.4)" + + + + spacing wcap pc 2 touching_illegal \ + "Well-capacitor spacing to poly contact must be at least 2 (MOSIS rule #18.5)" + + + + + spacing wcap ndc 4 touching_illegal \ + "Well-capacitor spacing to diffusion contact must be at least 4 (MOSIS rule #18.6)" + + + + + + + + width nbd,nbdc,bd/a 4 \ + "CCD channel width must be at least 4 (MOSIS rule #19.1)" + width nbdc 4 \ + "CCD contact width must be at least 4 (MOSIS rule #19.1)" +# 1910 "scmos.tech.out" + edge4way nbd,nbdc ~(bd,nbd,nbdc)/a 4 (bd,space)/i 0 0 \ + "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" implant + edge4way nbd,nbdc ~(poly,nbd,nbdc)/a 4 ~(poly,nbd,nbdc)/a ~(poly,nbd,nbdc)/a 4 \ + "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" active + + + + + + + edge4way bd space 2 nbd,poly,cap,el 0 0 \ + "CCD channel overhang is missing (MOSIS rule #19.6)" active + + + + + spacing nbdc poly,el 1 touching_illegal \ + "CCD-diffusion contact spacing to poly must be at least 1 (MOSIS CCD rule)" + edge4way nbd poly,el 1 bd 0 0 \ + "Missing Buried CCD Difussion layer (MOSIS CCD rule)" implant +# 1942 "scmos.tech.out" + edge (~hnwell)/w hnwell 10 hnwell hnwell 10\ + "High-Voltage N-Well width must be at least 10 (MOSIS rule #1.1)" + edge (~hpwell)/w hpwell 10 hpwell hpwell 10\ + "High-Voltage P-Well width must be at least 10 (MOSIS rule #1.1)" + + edge hnwell space,pw,hpw 9 space,pw,hpw space,pw,hpw 9\ + "High-Voltage N-Well spacing to N-Well must be at least 9 (MOSIS rule #1.2)" + edge hpwell space,nw,hnw 9 space,nw,hnw space,nw,hnw 9\ + "High-Voltage P-Well spacing to P-Well must be at least 9 (MOSIS rule #1.2)" + edge hnwell space,pw,hpw,nw 12 space,pw,hpw,nw space,pw,hpw,nw 12\ + "High-Voltage N-Well spacing must be at least 12 (MOSIS rule #20.1)" + edge hpwell space,nw,hnw,pw 12 space,nw,hnw,pw space,nw,hnw,pw 12\ + "High-Voltage P-Well spacing must be at least 12 (MOSIS rule #20.1)" + + + + + + + edge4way ~(hndiff,hndc/a,hpdiff,hpdc/a)/a hndiff,hndc/a,hpdiff,hpdc/a 3 hndiff,hndc/a,hpdiff,hpdc/a hndiff,hndc/a,hpdiff,hpdc/a 3\ + "High-Voltage Diffusion width must be at least 3 (MOSIS rule #2.1)" + spacing hndiff,hndc/a,hnfet hndiff,hndc/a,hnfet 5 touching_ok \ + "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" + spacing hpdiff,hpdc/a,hpfet hpdiff,hpdc/a,hpfet 5 touching_ok \ + "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" + + + + + + spacing hndiff,hndc/a hpdiff,hpdc/a 14 touching_illegal \ + "P-type diffusion must be 14 away from N-type diffusion (MOSIS rule #20.3)" + spacing hndiff,hndc/a pdiff,pdc/a 12 touching_illegal \ + "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" + spacing hpdiff,hpdc/a ndiff,ndc/a 12 touching_illegal \ + "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" + + + spacing hndiff,hnfet,hndc/a hnwell 7 touching_illegal \ + "HVN-diffusion and HVN-well must be separated by 7 (MOSIS rule #20.3)" + spacing hpdiff,hpfet,hpdc/a hpwell 7 touching_illegal \ + "HVP-diffusion and HVP-well must be separated by 7 (MOSIS rule #20.3)" + spacing nsd,nsc/a hpwell 3 touching_illegal \ + "N-substrate diffusion and HVP-well must be separated by 3 (MOSIS rule #2.4+20.3)" + spacing psd,psc/a hnwell 3 touching_illegal \ + "P-substrate diffusion and HVN-well must be separated by 3 (MOSIS rule #2.4+20.3)" +# 1996 "scmos.tech.out" + edge (~hndc)/a hndc/a 6 hndc/a hndc/a 6\ + "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" + edge (~hpdc)/a hpdc/a 6 hpdc/a hpdc/a 6\ + "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" + + + + edge hpdiff,hpdc/a hpfet 4 hpfet 0 0 \ + "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" + edge hndiff,hndc/a hnfet 4 hnfet 0 0 \ + "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" + + + + + + exact_overlap m3c,m2c,ndc,pdc,pc,psc,nsc,ec,capc,clc,emc,pbc,hndc,hpdc,hnsc,hpsc + no_overlap pfet,nfet pfet,nfet + no_overlap epfet,enfet epfet,enfet + no_overlap pffet,nffet pffet,nffet + no_overlap hpfet,hnfet hpfet,hnfet + +end + + +extract + + + + + +# 1 "./extract_template/scmosExt.tech.in" 1 +# 98 "./extract_template/scmosExt.tech.in" +# 1 "./extract_template/LibreSiliconExt1um.tech.in" 1 + + + + + + style lambda=lambda_v(libresilicon) + + + + + step 100 + sidehalo 6 + + + + + + + areacap nwell 35 + perimc nwell ~(nwell) 47 + + + areacap ndiff,nsd,ndc/a,nsc/a 0 + areacap pdiff,psd,pdc/a,psc/a 0 + + perimc ndiff,nsd,ndc/a,nsc/a space,pwell 0 + perimc pdiff,psd,pdc/a,psc/a space,nwell 0 +# 39 "./extract_template/LibreSiliconExt1um.tech.in" + areacap (poly,pc)/a 28 + overlap (poly,pc)/a nwell,pwell 28 + + perimc (poly,pc)/a ~(poly,pc)/a 38 + sideoverlap (poly,pc)/a ~(poly,pc)/a nwell,pwell 38 + sideoverlap (poly,pc)/a ~(poly,pc)/a (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 34 + sideoverlap (poly,pc)/a ~(poly,pc)/a (m2,m2c,m3c,pad)/m2 27 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + + sidewall (poly,pc)/a ~(poly,pc)/a ~(poly,pc)/a (poly,pc)/a 15 + + + + areacap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 18 + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 nwell,pwell 18 (poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 46 + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (poly,pc)/a 46 + + perimc (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 nwell,pwell 33 ((poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a) + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (poly,pc)/a 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (m2,m2c,m3c,pad)/m2 28 + + sidewall (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 27 + + + + + areacap (m2,m2c,m3c,pad)/m2 9 + overlap (m2,m2c,m3c,pad)/m2 nwell,pwell 9 (poly,pc)/a,(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a + overlap (m2,m2c,m3c,pad)/m2 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 12 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + overlap (m2,m2c,m3c,pad)/m2 (poly,pc)/a 14 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + overlap (m2,m2c,m3c,pad)/m2 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 30 + + perimc (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 22 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 nwell,pwell 22 ((m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1,(poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a) + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 20 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (poly,pc)/a 22 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 28 + + sidewall (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (m2,m2c,m3c,pad)/m2 33 + + + + + + fet pfet pdiff,pdc 2 pfet Vdd! nwell 270 623 + fet nfet ndiff,ndc 2 nfet Gnd! pwell 90 623 + fet wcap ndiff,ndc 1 wcap Gnd! pwell 300 0 + + + fetresis nfet linear 9700 + fetresis pfet linear 35700 + + + + contact pc 4 16210 + contact ndc,nsc, 4 77000 + contact pdc,psc, 4 44260 + contact m2c 4 150 + + + resist ndiff,nsd,ndc/a,nsc/a 99630 + resist pdiff,psd,pdc/a,psc/a 120000 + resist (poly,pc/act,pfet,nfet) 25000 + resist (metal1,m2c/metal1) 60 + resist (metal2,via/m2,pad) 40 + resist nwell 1500000 + + + + planeorder implant 0 + planeorder well 1 + planeorder active 2 + planeorder metal1 3 + planeorder metal2 4 + planeorder metal3 5 + planeorder metal4 6 + planeorder oxide 7 + +# 99 "./extract_template/scmosExt.tech.in" 2 + + +# 1 "./extract_template/scmosExtDiag.tech.in" 1 + + + + + + + style check_nwell + + lambda 100 + step 100 + + resist nwell 2000000 + areacap nw,nwc,nsd 100 + + + noplaneordering + + style check_pwell + + lambda 100 + step 100 + + resist pwell 2000000 + areacap pw,pwc,psd 100 + + noplaneordering + + style check_psubstr + + + + + + lambda 50 + step 200 + + areacap psd,psc 1000 + + noplaneordering + + style check_nsubstr + + + + + + lambda 50 + step 200 + + areacap nsd,nsc 1000 + + noplaneordering +# 101 "./extract_template/scmosExt.tech.in" 2 +# 2028 "scmos.tech.out" 2 +# 2833 "scmos.tech.out" +end + + +wiring + contact pdcontact 4 pdiff 0 metal1 0 + contact ndcontact 4 ndiff 0 metal1 0 + contact pcontact 4 poly 0 metal1 0 + contact ec 6 poly2 0 metal1 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 0 +end + +router + layer1 metal1 3 pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc 3 + layer2 metal2 3 m2,m2c/m2,m3c/m2,pad 4 poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet,ndiff,ndc/a,pdiff,pdc/a 1 + contacts m2contact 4 + gridspacing 8 +end + +plowing + fixed nfet,enfet,nffet,pfet,epfet,pffet,glass,pad + covered nfet,enfet,nffet,pfet,epfet,pffet + drag nfet,enfet,nffet,pfet,epfet,pffet +end + +plot + + style colorversatec + + ndiff,ndc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + ndiff,ndc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + + nsd,nsc,col,clc yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + + nsd,nsc,col,clc cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + + + pdiff,pdc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + pdiff,pdc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + pdiff,pdc magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + + + psd,psc yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + + psd,psc cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + + psd,psc magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + + + poly,pc/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + + poly2,ec/a yellow \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF + + + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + + + enfet yellow \ + BABA 7575 EAEA D5D5 \ + ABAB 5757 AEAE 5D5D \ + BABA 7575 EAEA D5D5 \ + ABAB 5757 AEAE 5D5D + + enfet cyan \ + 4141 0A0A 0505 2828 \ + 1414 A0A0 5050 8282 \ + 4141 0A0A 0505 2828 \ + 1414 A0A0 5050 8282 + + + nffet yellow \ + 8E8E 0707 8B8B D5D5 \ + E8E8 7070 B8B8 5D5D \ + 8E8E 0707 8B8B D5D5 \ + E8E8 7070 B8B8 5D5D + + nffet cyan \ + 0101 0808 1414 2828 \ + 1010 8080 4141 8282 \ + 0101 0808 1414 2828 \ + 1010 8080 4141 8282 + + nffet magenta \ + 5050 A0A0 4040 0202 \ + 0505 0A0A 0404 2020 \ + 5050 A0A0 4040 0202 \ + 0505 0A0A 0404 2020 + + + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + + + epfet yellow \ + BCBC 4F4F 2F2F D3D3 \ + CBCB F4F4 F2F2 3D3D \ + BCBC 4F4F 2F2F D3D3 \ + CBCB F4F4 F2F2 3D3D + + epfet cyan \ + 0000 A0A0 0000 2828 \ + 0000 0A0A 0000 8282 \ + 0000 A0A0 0000 2828 \ + 0000 0A0A 0000 8282 + + epfet magenta \ + 4141 0000 5050 0000 \ + 1414 0000 0505 0000 \ + 4141 0000 5050 0000 \ + 1414 0000 0505 0000 + + + pffet yellow \ + 7B7B F0F0 F0F0 E9E9 \ + B7B7 0F0F 0F0F 9E9E \ + 7B7B F0F0 F0F0 E9E9 \ + B7B7 0F0F 0F0F 9E9E + + pffet cyan \ + 0000 0101 0000 1414 \ + 0000 1010 0000 4141 \ + 0000 0101 0000 1414 \ + 0000 1010 0000 4141 + + pffet magenta \ + 8484 0A0A 2525 8282 \ + 4848 A0A0 5252 2828 \ + 8484 0A0A 2525 8282 \ + 4848 A0A0 5252 2828 + + + cap,cc/a yellow \ + 3E3E 7777 E3E3 C1C1 \ + E3E3 7777 3E3E 1C1C \ + 3E3E 7777 E3E3 C1C1 \ + E3E3 7777 3E3E 1C1C + + cap,cc/a magenta \ + 4141 8888 1414 2A2A \ + 1414 8888 4141 A2A2 \ + 4141 8888 1414 2A2A \ + 1414 8888 4141 A2A2 + + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + + + m2,m2c/m2,m3c/m2,pad cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + + m2,m2c/m2,m3c/m2,pad magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + + + m2c/m1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + + + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + + + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + + + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + + + bd yellow \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 + + bd cyan \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 + + bd magenta \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 + + + nbd,nbdc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + nbd,nbdc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + nbd,nbdc magenta \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 + + + em,emc yellow \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 + + em,emc cyan \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 + + + pbase,pbc yellow \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 + + pbase,pbc cyan \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 + + pbase,pbc magenta \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 + + + m3,m3c/m3 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + + m3,m3c/m3 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + + m3,m3c/m3 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + + + m3c/m2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + + + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + + + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + + + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + + + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + + + pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,nbdc,clc,emc,pbc X + + + style versatec + + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + + + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + + + m2c \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + + + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + + + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + + + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + + + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + + + nsd,nsc,col,clc \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + + + m2,m2c/m2,m3c/m2,pad \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + + + pdiff,pdc,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + + + psd,psc \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + + + ndiff,nfet,ndc \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + + + poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet \ + 0000 2020 5050 2020 \ + 0000 0202 0505 0202 \ + 0000 2020 5050 2020 \ + 0000 0202 0505 0202 + + + pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,nbdc,clc,emc,pbc X + + + style gremlin + pfet 9 + nfet 10 + m2c 11 + pwell 15 + nwell 16 + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 19 + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc 22 + pad,glass 23 + nsd,nsc 24 + m2,m2c/m2,m3c/m2,pad 28 + pdiff,pdc,pfet 29 + psd,psc 30 + ndiff,nfet,ndc 31 + m2c/m1,pc/m1,ndc/m1,pdc/m1,psc/m1,nsc/m1,pad/m1 X + + style postscript + + + + + 1 C0C0C0C0 C0C0C0C0 00000000 00000000 0C0C0C0C 0C0C0C0C 00000000 00000000 + 2 A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A + 3 00030003 000C000C 00300030 00C000C0 03000300 0C000C00 30003000 C000C000 + 4 00000000 00000000 C0C0C0C0 00000000 00000000 00000000 0C0C0C0C 00000000 + 5 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF + 6 07070707 0E0E0E0E 1C1C1C1C 38383838 70707070 E0E0E0E0 C1C1C1C1 83838383 + 7 18181818 30303030 60606060 C0C0C0C0 81818181 03030303 06060606 0C0C0C0C + 8 18181818 0C0C0C0C 06060606 03030303 81818181 C0C0C0C0 60606060 30303030 + 9 18181818 3C3C3C3C 3C3C3C3C 18181818 81818181 C3C3C3C3 C3C3C3C3 81818181 + 10 F0F0F0F0 60606060 06060606 0F0F0F0F 0F0F0F0F 06060606 60606060 F0F0F0F0 + 11 01000080 02000040 0C000030 F000000F 000FF000 00300C00 00400200 00800100 + 12 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + 13 00000000 00000000 33333333 33333333 00000000 00000000 CCCCCCCC CCCCCCCC + + + + + 1 47 95 111 0 + 2 223 31 223 0 + 3 0 0 0 192 + 4 31 111 31 0 + 5 31 111 255 0 + 6 63 95 191 0 + 7 255 63 255 0 + 8 0 0 0 127 + 9 223 47 223 0 + 10 0 255 255 0 + 11 0 0 255 0 + 12 191 127 0 0 + 13 95 223 63 0 + 14 0 0 0 255 + 15 191 127 63 0 + 16 111 151 244 0 + 17 23 175 183 0 + + + + + cc,pc,ndc,pdc,psc,nsc 14 X + m2c,pad,glass 14 B + pad,glass 14 11 + m2c 14 13 + m2,m2c,pad 13 10 + pdc,ndc,psc,nsc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,clc,emc,pbnd,pbpd,pbc,nbdc,m1,m2c,gc 12 9 + cap,cc,poly2 11 7 + nsd,nsc 7 1 + psd,psc 6 1 + nfet,nffet 9 8 + pfet,wcap,pffet 1 7 + poly,pc,cap,cc 10 5 + nfet 16 5 + pfet,wcap 17 5 + pdiff,pdc,pffet 1 5 + ndiff,ndc,nffet 9 5 + pwell 1 4 + nwell 2 4 + + silk 10 5 + + + + + style pnm + draw metal1 + draw metal2 + + draw metal3 + draw pwell + draw nwell + draw silk + map silk metal2 + + draw polysilicon + draw ndiffusion + draw pdiffusion + draw ntransistor + draw ptransistor + map psubstratepdiff pdiffusion + map nsubstratendiff ndiffusion + map polycontact polysilicon metal1 + map m2contact metal1 metal2 + map m3contact metal2 metal3 + map ndcontact ndiffusion metal1 + map pdcontact pdiffusion metal1 + map nsubstratencontact ndiffusion metal1 + map psubstratepcontact pdiffusion metal1 +end diff --git a/Tech.CDTA/nmos.sp b/Tech.CDTA/nmos.sp new file mode 100644 index 00000000..9e0758e0 --- /dev/null +++ b/Tech.CDTA/nmos.sp @@ -0,0 +1 @@ +w=1.0u l=1.0u diff --git a/Tech.CDTA/pmos.sp b/Tech.CDTA/pmos.sp new file mode 100644 index 00000000..0c7b022b --- /dev/null +++ b/Tech.CDTA/pmos.sp @@ -0,0 +1 @@ +w=2.7u l=1.0u diff --git a/Tech.CDTA/template.lef b/Tech.CDTA/template.lef new file mode 100755 index 00000000..1a48d636 --- /dev/null +++ b/Tech.CDTA/template.lef @@ -0,0 +1,177 @@ +# LEF file template for CDTA, likely needs to be improved. +# + +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +USEMINSPACING OBS ON ; +USEMINSPACING PIN OFF ; +CLEARANCEMEASURE EUCLIDEAN ; + + +MANUFACTURINGGRID 0.15 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER nactive + TYPE MASTERSLICE ; +END nactive + +LAYER pactive + TYPE MASTERSLICE ; +END pactive + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER cc + TYPE CUT ; + SPACING 0.9 ; +END cc + +LAYER metal1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 3.2e-05 ; +END metal1 + +LAYER via + TYPE CUT ; + SPACING 0.9 ; +END via + +LAYER metal2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 2.4 ; + OFFSET 1.2 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 1.6e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.9 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 1.5 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.05 ; + CAPACITANCE CPERSQDIST 1e-05 ; +END metal3 + +SPACING + SAMENET cc via 0.150 ; + SAMENET via via2 0.150 ; +END SPACING + +VIA M2_M1 DEFAULT + LAYER metal1 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; +END M2_M1 + +VIA M3_M2 DEFAULT + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via2 ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal3 ; + RECT -0.900 -0.900 0.900 0.900 ; +END M3_M2 + + +VIARULE viagen21 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER via ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 1.5 BY 1.5 ; +END viagen21 + +VIARULE viagen32 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + WIDTH 1.8 TO 180 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER via2 ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 2.1 BY 2.1 ; +END viagen32 + +VIARULE TURN1 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + LAYER metal1 ; + DIRECTION VERTICAL ; +END TURN1 + +VIARULE TURN2 GENERATE + LAYER metal2 ; + DIRECTION HORIZONTAL ; + LAYER metal2 ; + DIRECTION VERTICAL ; +END TURN2 + +VIARULE TURN3 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + LAYER metal3 ; + DIRECTION VERTICAL ; +END TURN3 + +SITE corner + CLASS PAD ; + SYMMETRY R90 Y ; + SIZE 300.000 BY 300.000 ; +END corner + +SITE IO + CLASS PAD ; + SYMMETRY Y ; + SIZE 90.000 BY 300.000 ; +END IO + +SITE core + CLASS CORE ; + SYMMETRY Y ; + SIZE 2.400 BY 30.000 ; +END core + diff --git a/Tech.GF180MCU/.gitignore b/Tech.GF180MCU/.gitignore new file mode 100644 index 00000000..c18dd8d8 --- /dev/null +++ b/Tech.GF180MCU/.gitignore @@ -0,0 +1 @@ +__pycache__/ diff --git a/Tech.GF180MCU/08_Topological_Truth_Table15.csv b/Tech.GF180MCU/08_Topological_Truth_Table15.csv new file mode 100644 index 00000000..0c80e02d --- /dev/null +++ b/Tech.GF180MCU/08_Topological_Truth_Table15.csv @@ -0,0 +1,97 @@ +Truth Table,3.3V/(5V)6V Process,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,Device Drawn Layers,,,,,,,,,,,,,,Marking Layers,,,,,,,,,,,,,,, +Layer Abbreviation =>,DNWELL,COMP,NWLL,LVPWELL,Dualgate,POLY2,Nplus,Pplus,Resistor ,ESD ,SAB ,FuseTop ,FuseWindow_D,POLYFUSE,RES_MK,V5_XTOR,CAP _MK&MIM_ L_MK,DIODE_MK,DRC_BJT,NAT,MOS_CAP_MK,ESD_MK,LVS_Source,WELL_DIODE_MK,EFUSE_MK,PLFUSE,MVSD,MVPSD,LDMOS_XTOR,Schottky _diode +Digitized Area Polarity =>,CL,CH,CL,CH,CH,CH,CL,CL,CL,CL,CH,CH,CL,CL,-,-,-,-,-,-,-,-,-,-,-,,,,, +(1) MOS Transistors:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +3.3V NMOS (Outside DNWELL),0,1,0,X,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3.3V NMOS (Inside DNWELL),1,1,0,1,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3.3V PMOS (Outside DNWELL),0,1,1,0,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3.3V PMOS (Inside DNWELL),1,1,X,0,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3.3V native Vt NMOS,0,1,0,0,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,1,0,0,0,X,0,0,0,0,0,0 +6V NMOS (Outside DNWELL),0,1,0,X,1,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +6V NMOS (Inside DNWELL),1,1,0,1,1,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +6V PMOS (Outside DNWELL),0,1,1,0,1,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +6V PMOS (Inside DNWELL),1,1,X,0,1,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +6V native Vt NMOS,0,1,0,0,1,1,1,0,0,0,0,X,0,0,0,0,X,0,0,1,0,0,0,X,0,0,0,0,0,0 +5V NMOS (Outside DNWELL),0,1,0,X,1,1,1,0,0,0,0,X,0,0,0,1,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +5V NMOS (Inside DNWELL),1,1,0,1,1,1,1,0,0,0,0,X,0,0,0,1,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +5V PMOS (Outside DNWELL),0,1,1,0,1,1,0,1,0,0,0,X,0,0,0,1,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +5V PMOS (Inside DNWELL),1,1,X,0,1,1,0,1,0,0,0,X,0,0,0,1,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +10V LDNMOS,0,1,0,0,1,1,1,0,0,0,0,X,0,0,0,0,X,X,0,0,0,0,0,X,0,0,1,0,1,0 +10V LDPMOS,1,1,0,0,1,1,0,1,0,0,0,X,0,0,0,0,X,X,0,0,0,0,0,X,0,0,0,1,1,0 +(2) BJT:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +VPNP (Psub as collector),0,1,1,0,0,0,1,1,0,0,0,X,0,0,0,0,X,0,1,0,0,0,0,0,0,0,0,0,0,0 +VNPN (Isolated collector),1,1,0,1,0,0,1,1,0,0,0,X,0,0,0,0,X,0,1,0,0,0,0,0,0,0,0,0,0,0 +(3) Diodes:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +N+/LVPWELL (3.3V area),X,1,0,1,0,0,1,1,0,0,0,X,0,0,0,0,X,1,0,0,0,X,X,X,0,0,0,0,0,0 +N+/LVPWELL (5V/6V area),X,1,0,1,1,0,1,1,0,0,0,X,0,0,0,X,X,1,0,0,0,X,X,X,0,0,0,0,0,0 +P+/Nwell (3.3V area),X,1,1,0,0,0,1,1,0,0,0,X,0,0,0,0,X,1,0,0,0,X,X,X,0,0,0,0,0,0 +P+/Nwell (5V/6V area),X,1,1,0,1,0,1,1,0,0,0,X,0,0,0,X,X,1,0,0,0,X,X,X,0,0,0,0,0,0 +Nwell/Psub (3.3V area),0,1,1,0,0,0,1,1,0,0,0,X,0,0,0,0,X,X,0,0,0,X,X,1,0,0,0,0,0,0 +Nwell/Psub (5V/6V area),0,1,1,0,1,0,1,1,0,0,0,X,0,0,0,X,X,X,0,0,0,X,X,1,0,0,0,0,0,0 +LVPWELL/DNWELL (3.3V area),1,1,0,1,0,0,1,1,0,0,0,X,0,0,0,0,X,X,0,0,0,X,X,1,0,0,0,0,0,0 +LVPWELL/DNWELL (5V/6V area),1,1,0,1,1,0,1,1,0,0,0,X,0,0,0,X,X,X,0,0,0,X,X,1,0,0,0,0,0,0 +DNWELL/Psub (3.3V area),1,1,1,0,0,0,1,1,0,0,0,X,0,0,0,0,X,X,0,0,0,X,X,1,0,0,0,0,0,0 +DNWELL/Psub (5V/6V area),1,1,1,0,1,0,1,1,0,0,0,X,0,0,0,X,X,X,0,0,0,X,X,1,0,0,0,0,0,X +sc_diode,1,1,X,0,X,0,1,0,0,0,0,X,0,0,0,X,X,0,0,0,0,0,0,X,0,0,0,0,0,1 +(4) Resistors:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +N+ Diffusion Unsalicided Rs (Outside DNWELL),0,1,0,X,0,0,1,0,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Diffusion Unsalicided Rs (Outside DNWELL),0,1,1,0,0,0,0,1,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +N+ Diffusion Salicided Rs (Outside DNWELL),0,1,0,X,0,0,1,0,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Diffusion Salicided Rs (Outside DNWELL),0,1,1,0,0,0,0,1,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +N+ Diffusion Unsalicided Rs (Intside DNWELL),1,1,0,1,0,0,1,0,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Diffusion Unsalicided Rs (Intside DNWELL),1,1,X,0,0,0,0,1,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +N+ Diffusion Salicided Rs (Intside DNWELL),1,1,0,1,0,0,1,0,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Diffusion Salicided Rs (Intside DNWELL),1,1,X,0,0,0,0,1,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +N+ Poly Unsalicided Rs,X,0,X,X,X,1,1,0,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Poly Unsalicided Rs,X,0,X,X,X,1,0,1,0,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +P+ Poly Salicided Rs,X,0,X,X,X,1,0,1,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +N+ Poly Salicided Rs,X,0,X,X,X,1,1,0,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +1K P+ HRS (3.3V area),X,0,X,X,0,1,0,1,1,0,1,X,0,0,1,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +1K P+ HRS (5V/6V area),X,0,X,X,1,1,0,1,1,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +2K P+ HRS (3.3V area),X,0,X,X,0,1,0,1,1,0,1,X,0,0,1,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +2K P+ HRS (5V/6V area),X,0,X,X,1,1,0,1,1,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3K P+ HRS (3.3V area),X,0,X,X,0,1,0,1,1,0,1,X,0,0,1,0,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +3K P+ HRS (5V/6V area),X,0,X,X,1,1,0,1,1,0,1,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +Nwell (under STI),0,1,1,0,0,0,1,0,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +LVPWELL (under STI),1,1,0,1,0,0,0,1,0,0,0,X,0,0,1,X,X,0,0,0,0,0,0,X,0,0,0,0,0,0 +(5) Capacitors:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +MIM capacitor,X,X,X,X,X,X,X,X,X,X,X,1,X,X,X,X,1,X,X,X,X,X,X,X,0,0,X,X,X,X +3.3V NMOS Cap (Outside DNWELL),0,1,0,X,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +3.3V NMOS Cap (Inside DNWELL),1,1,0,1,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +3.3V PMOS Cap (Outside DNWELL),0,1,1,0,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +3.3V PMOS Cap (Inside DNWELL),1,1,X,0,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"3.3V NMOS Cap_b (Inside NWELL, Outside DNWELL)",0,1,1,0,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"3.3V NMOS Cap_b (Inside NWELL, Inside DNWELL)",1,1,X,0,0,1,1,0,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"3.3V PMOS Cap_b (Inside LVPWELL, Outside DNWELL)",0,1,0,X,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"3.3V PMOS Cap_b (Inside LVPWELL, Inside DNWELL)",1,1,0,1,0,1,0,1,0,0,0,X,0,0,0,0,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +5V/6V NMOS Cap (Outside DNWELL),0,1,0,X,1,1,1,0,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +5V/6V NMOS Cap (Inside DNWELL),1,1,0,1,1,1,1,0,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +5V/6V PMOS Cap (Outside DNWELL),0,1,1,0,1,1,0,1,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +5V/6V PMOS Cap (Inside DNWELL),1,1,X,0,1,1,0,1,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"5V/6V NMOS Cap_b (Inside NWELL, Outside DNWELL)",0,1,1,0,1,1,1,0,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"5V/6V NMOS Cap_b (Inside NWELL, Inside DNWELL)",1,1,X,0,1,1,1,0,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"5V/6V PMOS Cap_b (Inside LVPWELL, Outside DNWELL)",0,1,0,X,1,1,0,1,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +"5V/6V PMOS Cap_b (Inside LVPWELL, Inside DNWELL)",1,1,0,1,1,1,0,1,0,0,0,X,0,0,0,X,X,0,0,0,1,0,0,X,0,0,0,0,0,0 +(6) Well Taps,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Nwell tap (Outside DNWELL),0,1,1,0,X,0,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +DNWELL/Nwell tap (Inside DNWELL),1,1,X,0,X,0,1,0,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +LVPWELL tap (Outside DNWELL),0,1,0,1,X,0,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +LVPWELL tap (Inside DNWELL),1,1,0,1,X,0,0,1,0,0,0,X,0,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +(7) N+ Poly Fuse (Optional):,X,0,X,X,X,1,1,0,0,X,1,X,0,1,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +(8) Metal Fuse (Optional):,X,0,X,X,X,0,X,X,X,X,X,X,1,0,0,0,X,0,0,0,0,0,0,0,0,0,0,0,0,0 +(9) ESD,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +nfet_03v3_dn_dss (SAB 3.3V NMOS inside DNWELL),1,1,0,1,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +nfet_03v3_dss (SAB 3.3V NMOS outside DNWELL),0,1,0,X,0,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +nfet_05v0_dn_dss (SAB 5V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +nfet_05v0_dss (SAB 5V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +nfet_06v0_dn_dss (SAB 6V NMOS inside DNWELL),1,1,0,1,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +nfet_06v0_dss (SAB 6V NMOS outside DNWELL),0,1,0,X,1,1,1,0,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_03v3_dn_dss (SAB 3.3V PMOS inside DNWELL),1,1,X,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_03v3_dss (SAB 3.3V PMOS outside DNWELL),0,1,1,0,0,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_05v0_dn_dss (SAB 5V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_05v0_dss (SAB 5V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,1,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_06v0_dn_dss (SAB 6V PMOS inside DNWELL),1,1,X,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +pfet_06v0_dss (SAB 6V PMOS outside DNWELL),0,1,1,0,1,1,0,1,0,X,1,X,0,0,0,0,X,0,0,0,0,1,1,X,0,0,0,0,0,0 +(10) eFuse,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +eFuse,X,0,0,X,X,1,0,1,0,0,0,0,0,0,0,X,0,0,0,0,0,0,1,0,1,1,0,0,0,0 diff --git a/Tech.GF180MCU/Makefile b/Tech.GF180MCU/Makefile new file mode 100644 index 00000000..f8ce621d --- /dev/null +++ b/Tech.GF180MCU/Makefile @@ -0,0 +1,4 @@ +libresilicon.tech: /usr/local/share/pdk/gf180mcuD/libs.tech/magic/gf180mcuD.tech + perl ../Tools/perl/drcexpander.pl /usr/local/share/pdk/gf180mcuD/libs.tech/magic/gf180mcuD.tech >libresilicon.tech + + diff --git a/Tech.GF180MCU/caravel-env.sh b/Tech.GF180MCU/caravel-env.sh new file mode 100644 index 00000000..ebee37af --- /dev/null +++ b/Tech.GF180MCU/caravel-env.sh @@ -0,0 +1,10 @@ +export STDCELLLIB="../" +#e#xport OPENLANE_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/dependencies/openlane_src" +#e#xport CARAVEL="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1" +#e#xport CARAVEL_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/gf180_stdcelllib_1/caravel" +export PDK_ROOT=/home/philipp/.volare +export PDK="gf180mcuD" +export STD_CELL_LIBRARY="gf180mcu_fd_sc_mcu9t5v0" +export STD_CELL_LIBRARY_OPT="gf180mcu_fd_sc_mcu9t5v0" +export CARAVEL_BRANCH="gfmpw-1c" +export KLAYOUT_HOME=/home/philipp/.volare/gf180mcuD/libs.tech/klayout diff --git a/Tech.GF180MCU/design.ngspice b/Tech.GF180MCU/design.ngspice new file mode 100644 index 00000000..d2ee50bb --- /dev/null +++ b/Tech.GF180MCU/design.ngspice @@ -0,0 +1,76 @@ +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +************************************************************************* +** Global Parameter Settings +************************************************************************* +** NGSPICE include file for global switches, corner parameters +** and other user-defined settings +** ********************************************************************** +** ------------------------------------------- +** MonteCarlo and matching simulation setting: +** ------------------------------------------- +** sw_stat_global +** sw_stat_mismatch +** +** -------------------------------------------------------------------------- +** | setting | sw_stat_global=0 | sw_stat_global=1 | +** -------------------------------------------------------------------------- +** | sw_stat_mismatch=0 | No statistical | Global variation is on, | +** | | modeling | but mismatch is off. | +** -------------------------------------------------------------------------- +** | sw_stat_mismatch=1 | mismacth is on, | Most realistic | +** | | global variation off | distribution. | +** -------------------------------------------------------------------------- +** +** +** (default) - sw_stat_global=1 and sw_stat_mismatch=1 +** This setting provides the most complete representation of the +** statistical variations during chip manufacturing. +** Global process variations are determined by random distributions. +** Mismatch is differentiated from global variation in that mismatch only +** includes intra-die variation, and it is especially critical for analog matching applications. +** +** mc_skew is the monte-carlo simulation variation control. +** +** +** ------------------------------------------- +** Flicker noise corner setting: +** ------------------------------------------- +** +** "fnoicor" switch is added for user to select between the best- or worst-case +** flicker noise simulation options +** fnoicor = 0 : (default) as-extracted simulation +** fnoicor = 1 : worst case simulation +** +** ***************************************************************************** +** +** Switches +** +*********** Default mc switches ********** +** +.param ++ sw_stat_global = 1 ++ sw_stat_mismatch = 1 +** +********* Default mc skew value ********* +** ++ mc_skew = 3 ++ res_mc_skew = 3 ++ cap_mc_skew = 3 +** +****** Default flicker noise corner switch ***** +** ++ fnoicor = 0 +******************************************************************************** diff --git a/Tech.GF180MCU/librecell_tech.py b/Tech.GF180MCU/librecell_tech.py new file mode 100644 index 00000000..ee7342c8 --- /dev/null +++ b/Tech.GF180MCU/librecell_tech.py @@ -0,0 +1,478 @@ +import os +from lclayout.layout.layers import * +from lclayout.writer.magic_writer import MagWriter +from lclayout.writer.lef_writer import LefWriter +from lclayout.writer.gds_writer import GdsWriter +from lclayout.writer.oasis_writer import OasisWriter + +# This Tech file was created for 5V transistors for GlobalFoundries GF180MCU. There might be one layer missing for them. We could create additional cells for 3.3V and 6V, but that would change a lot of the DRC rules + +# Physical size of one data base unit in meters. +# BUT GDS2 requires the database units to be in nanometers, and lclayout cannot convert to nanometers automatically yet +db_unit = 1e-9 + +# Lambda - how many db_units is 1 lambda? +grid = 5 # grid basis +um = 1000 +nm = 1 + +targetvoltage=os.environ.get("TARGETVOLTAGE","3.3V") # "3.3V" "5V" "6V" "10V" # unfortunately 1.8V does not seem to be available on GF180 +# "5V" => Operating Voltage VDD = 1.62 - 5.5V according to https://gf180mcu-pdk.readthedocs.io/en/latest/digital/standard_cells/gf180mcu_fd_sc_mcu7t5v0/spec/electrical.html + +tracks=int(os.environ.get("TRACKS","9")) + +use_deep_nwell =os.environ.get("DNWELL","True") + +print("GF180 standard cell configuration: TARGETVOLTAGE="+targetvoltage+" TRACKS="+str(tracks)+" DNWELL="+use_deep_nwell) + +# Scale transistor width. +transistor_channel_width_sizing = 1 + +# GDS2 layer numbers for final output. +# Keep those definitions always in mind: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07.html +# GDS2 layers are taken from: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_04_1.html +# Topological Truthtable for the layers needed in the Standard Cells: +# https://docs.google.com/spreadsheets/d/1WnX2PdoPuBb3nwg5L60u95co2R2abTH1DZLeoyPBLPY/edit#gid=523905120 + +my_ndiffusion = (22, 0) # warning: ndiffusion+pdiffusion is on the same GDS2 layer, called COMP +my_ndiffusion_label = (22, 0) +my_ndiffusion_pin = (22, 0) +my_pdiffusion = (22, 0) # warning: ndiffusion+pdiffusion is on the same GDS2 layer, called COMP +my_pdiffusion_label = (22, 0) +my_pdiffusion_pin = (22, 0) + + +my_nwell = (21, 0) +my_nwell_label = (21, 0) +my_nwell_pin = (21, 0) + +my_dnwell = (12, 0) + +my_pwell = (204, 0) # LVPWELL / Pwell implant + +my_dualgate = (55, 0) # Dualgate / 6V Gate Oxide + +my_poly = (30, 0) # "Poly2" / POLY2 gate & interconnect / poly silicium for gates -> poly + ntransistor + ptransistor +my_poly_gate = (30, 0) # poly gates? Why do we have a second layer for gates? +my_poly_label = (30, 0) + +my_mcon = (33, 0) # Contact / Metal1 to Active or Poly2 contact +my_metal1 = (34, 0) +my_metal1_label = (34, 0) +my_metal1_pin = (34, 0) +my_via1 = (35, 0) # Metal2 to Metal1 contact +my_metal2 = (36, 0) +my_metal2_label = (36, 0) +my_metal2_pin = (36, 0) +my_via2 = (38, 0) # Metal3 to Metal2 contact +my_metal3 = (42, 0) + +my_abutment_box = (63, 0) # Border + +my_pplus = (31,0) # P-Plus +my_nplus = (32,0) # N-Plus + +my_sab = (49,0) # SAB / Unsalicided poly & active regions + + +# lclayout internally uses its own layer numbering scheme. +# For the final output the layers can be remapped with a mapping +# defined in this dictioinary. +output_map = { + l_ndiffusion: my_ndiffusion, + l_pdiffusion: my_pdiffusion, + l_nwell: my_nwell, # [my_nwell, my_nwell2], # Map l_nwell to two output layers. + l_pwell: my_pwell, # Output layer for pwell. Uncomment this if needed. For instance for twin-well processes. + l_poly: my_poly, + l_poly_contact: my_mcon, + l_pdiff_contact: my_mcon, + l_ndiff_contact: my_mcon, + l_metal1: my_metal1, + l_metal1_label: my_metal1_label, + l_metal1_pin: my_metal1_pin, + l_via1: my_via1, + l_metal2: my_metal2, + l_metal2_label: my_metal2_label, + l_metal2_pin: my_metal2_pin, + l_abutment_box: my_abutment_box, + l_pplus: my_pplus, + l_nplus: my_nplus, + l_border_vertical: (142, 1), + l_border_horizontal: (142, 2), +} + +# These are only the obstruction layers, only these layers will be generated into the OBS section of the LEF files +obstruction_layers = [ + l_poly_contact, + l_pdiff_contact, + l_ndiff_contact, + l_metal1, + l_via1, + l_metal2, +] + +output_map_magic = { + l_nwell: 'nwell', + l_pwell: 'pwell', + l_via1: 'via1', + l_poly: 'poly', + l_abutment_box: ['abutment'], + l_metal1: 'met1', + l_metal2: 'met2', + l_metal1_label: 'met1', + l_metal2_label: 'met2', + l_metal1_pin: 'met1', + l_metal2_pin: 'met2', + l_ndiffusion: 'ndiffusion', + l_pdiffusion: 'pdiffusion', + l_poly_contact: 'polycont', + l_pdiff_contact: 'pdiffc', + l_ndiff_contact: 'ndiffc', + #l_nplus: 'nplus_s', + #l_pplus: 'pplus_s' +} + + +# Define a list of output writers. +output_writers = [ + MagWriter( + tech_name='gf180mcuD', + scale_factor=0.2, # Scale all coordinates by this factor (rounded down to next integer). + output_map=output_map_magic, + magscale=[1,10] + ), + + LefWriter( + db_unit=1e-6, # LEF Fileformat always needs Microns + obstruction_layers=obstruction_layers, + output_map=output_map_magic, # Not supported yet but will be soon + use_rectangles_only=True, + site="unit" + ), + + GdsWriter( + db_unit=db_unit, + output_map=output_map + ), + + OasisWriter( + db_unit=db_unit, + output_map=output_map + ) + +] + +# Define how layers can be used for routing. +# Example for a layer that can be used for horizontal and vertical tracks: {'MyLayer1' : 'hv'} +# Example for a layer that can be contacted but not used for routing: {'MyLayer2' : ''} +routing_layers = { + l_ndiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_pdiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_poly: 'v', # We dont want horizontal rouing on poly + l_metal1: 'hv', + l_metal2: 'hv', +} + +# Minimum spacing rules for layer pairs. +min_spacing = { + (l_ndiffusion, l_ndiffusion): 280*nm if targetvoltage=='3.3V' else 360*nm, # DF.3a for 5V https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + #(l_ndiffusion, l_outline): 360/2*nm, # DF.3a for 5V https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + (l_pdiffusion, l_ndiffusion): 280*nm if targetvoltage=='3.3V' else 360*nm, # DF.3a for 5V https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + #(l_pdiffusion, l_outline): 360/2*nm, # DF.3a for 5V https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + (l_pdiffusion, l_pdiffusion): 280*nm if targetvoltage=='3.3V' else 360*nm, # DF.3a for 5V https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + (l_ndiffusion, l_poly_contact): 170*nm, # CO.8 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_pdiffusion, l_poly_contact): 170*nm, # CO.8 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_nwell, l_nwell): 600*nm if targetvoltage=='3.3V' else 740*nm, # NW.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_05.html + (l_nwell, l_pwell): 0*nm, # NW.4 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_05.html + (l_pwell, l_pwell): 860*nm, # LPW.2b # If it would be the same potential, we could go down to 860*nm according to LPW.2b, if it is different potential we would have to go up to 1.7 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html + #(l_poly, l_ndiffusion): 300*nm, # PL.5b This is only needed when the poly isn't rectangular, and it doesn't mean the poly that is directly on top of diffusion + #(l_poly, l_pdiffusion): 300*nm, # PL.5b https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + (l_poly, l_poly): 240*nm, # PL.3a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + #(l_poly, l_outline): 240/2*nm, # PL.3a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + (l_poly, l_pdiff_contact): 150*nm, # CO.7 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_poly, l_ndiff_contact): 150*nm, # CO.7 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_pdiff_contact, l_pdiff_contact): 250*nm, # CO.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + #(l_pdiff_contact, l_outline): 270/2*nm, # (difftap.3) + (l_ndiff_contact, l_ndiff_contact): 250*nm, # CO.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + #(l_ndiff_contact, l_outline): 270/2*nm, # (difftap.3) + (l_pdiff_contact, l_ndiff_contact): 250*nm, # CO.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_metal1, l_metal1): 230*nm, # Mn.2a ! This was 250nm?!? DRC rule says 230nm. WARNING: Spacing to huge_met1 (>=10um) needs to be 300nm ! But we most likely wont have huge metal1 inside a standard cell https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + #(l_metal1, l_outline): 170/2*nm, # (li.3) # !!!! WARNING: Spacing to huge_met1 (>=?nm) needs to be 280nm ! +# (l_metal1, l_border_vertical): 190*nm, # To move the VIAs at the right place +# (l_metal2, l_border_vertical): 190*nm, # To move the VIAs at the right place + + (l_metal2, l_metal2): 280*nm, # Mn.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + # We need metal2 at the border for the power lanes, so we dont put border rules + (l_via1, l_via1): 260*nm, # Vn.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html + #(l_via1, l_outline): 190/2*nm, # (ct.2) + #(l_via1, l_diff_contact): 2*l, # NO RULES FOR LICON-MCON spacing found + #(l_via1, l_ndiffusion): 2*l, # NO RULES FOR MCON-DIFF spacing found + #(l_via1, l_pdiffusion): 2*l, # NO RULES FOR MCON-DIFF spacing found + (l_poly_contact, l_pdiff_contact): 250*nm, # CO.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + #(l_poly_contact, l_outline): 170/2*nm, # (licon.2) + (l_poly_contact, l_ndiff_contact): 250*nm, # CO.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_ndiffusion, l_pplus): 80*nm, # OR IS IT 160nm??? PP.3 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_10.html + (l_pdiffusion, l_nplus): 80*nm, # OR IS IT 160nm??? NP.3 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_09.html + (l_nplus, l_nplus): 400*nm, # NP.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_09.html +} + +# Layer for the pins. +pin_layer = l_metal2 # lclayout.metal2 = sky130.metal1 + +# Power stripe layer +power_layer = [l_metal1, l_metal2] # lclayout.metal2 = sky130.metal1 + +# Layers that can be connected/merged without changing the schematic. +# This can be used to resolve spacing/notch violations by just filling the space. +connectable_layers = {l_pwell, l_poly, l_metal1} # l_nwell +# Width of the polysilicon stripe which forms the gate. +# is reused as the minimum_width for the l_poly layer +gate_length_nmos = 280*nm if targetvoltage=='3.3V' else 500*nm if targetvoltage=='5V' else 550*nm # PL.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html +gate_length_pmos = 280*nm if targetvoltage=='3.3V' else 600*nm if targetvoltage=='5V' else 700*nm # PL.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + +# Minimum length a polysilicon gate must overlap the silicon. +gate_extension = 220*nm # PL.4 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + +# Minimum distance of active area to upper or lower boundary of the cell. Basically determines the y-offset of the transistors. +transistor_offset_y = 340*nm # !!! This likely needs to be tuned later on # The 150/2*nm might have to be removed + +# Standard cell dimensions. +# A 'unit cell' corresponds to the dimensions of the smallest possible cell. Usually an inverter. +# `unit_cell_width` also corresponds to the pitch of the gates because gates are spaced on a regular grid. +unit_cell_width = 2*560*nm # (unit SITE) # measured from gf180mcu_fd_sc_mcu9t5v0__inv_1 -> 1.12 um = 2 Tracks = 2*0.56 nm +unit_cell_height = tracks*560*nm # (unit SITE) # measured from gf180mcu_fd_sc_mcu9t5v0__inv_1 -> 5.04 um = 9 Tracks = 9*0.56 nm + +#assert unit_cell_height >= 16*um, "minimum 16um due to pwell width + nwell-pwell spacing" +# due to nwell size and spacing requirements routing_grid_pitch_y * 8 # * 8 + +# Routing pitch +routing_grid_pitch_x = unit_cell_width // 2 # // 4 +routing_grid_pitch_y = 135*nm # unit_cell_height // 8 // 2 + +# Translate routing grid such that the bottom left grid point is at (grid_offset_x, grid_offset_y) +grid_offset_x = routing_grid_pitch_x +grid_offset_y = 0 # (routing_grid_pitch_y // 2 ) -10 + +# Width of power rail metal. +power_rail_width = 480*nm # decided by the standard cell library architect - might need to be interoperable to other cells + + +# Minimum gate widths of transistors, i.e. minimal widths of l_ndiffusion and l_pdiffusion (width of COMP). +# It increases w from the spice netlist, so it must be width from the spice netlist +minimum_gate_width_nfet = 220*nm if targetvoltage=='3.3V' else 300*nm # DF.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html +minimum_gate_width_pfet = 220*nm if targetvoltage=='3.3V' else 300*nm # DF.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + +# Minimum width for pins. +minimum_pin_width = 220*nm + +# Width of routing wires. +wire_width = { + l_ndiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_pdiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_poly: 280*nm if targetvoltage=='3.3V' else 390*nm, # PL.1 -> Magic requires 180nm -> But we want 390nm to avoid notches # Checked it again on 2024-04-23 and yes, 390nm makes sense. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + l_metal1: 230*nm, # Mn.1 voltage independent https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_metal2: 280*nm, # Mn.1 voltage independent https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html +} + +# Width of horizontal routing wires (overwrites `wire_width`). +wire_width_horizontal = { + l_ndiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_pdiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_poly: 180*nm if targetvoltage=='3.3V' else 200*nm, # PL.1 -> Magic requires 180nm -> But we want 390nm to avoid notches # Checked it again on 2024-04-23 and yes, 390nm makes sense. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + l_metal1: 230*nm, # Mn.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_metal2: 280*nm, # Mn.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html +} + +# Side lengths of vias (square shaped). +via_size = { + l_poly_contact: 230*nm, # CO.1 requires 220nm + magic extensions 2*CO.6 - so the GDS2 file should be 220nm in the end I guess? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + l_ndiff_contact: 230*nm, # CO.1 requires 220nm + magic extension 2*CO.6 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + l_pdiff_contact: 230*nm, # CO.1 requires 220nm + magic extension 2*CO.6 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + l_via1: 260*nm, # Vn.1 # Why do we not have an extension here like with poly, ndiff and pdiff? https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html + #l_via2: 260*nm # Vn.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html +} + +# Minimum width rules. +minimum_width = { + l_ndiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_pdiffusion: 220*nm if targetvoltage=='3.3V' else 300*nm, # DF.1a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_poly: 280*nm if targetvoltage=='3.3V' else 500*nm if targetvoltage=='5V' else 550*nm, # PL.2 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + l_metal1: 230*nm, # Mn.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_metal2: 280*nm, # Mn.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_nwell: 860*nm, # NW.1a (covering 3.3V, 5V, 6V) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_05.html + l_pwell: 600*nm if targetvoltage=='3.3V' else 740*nm, # LPW.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html + l_nplus: 400*nm # NP.1 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_09.html +} + +# Minimum enclosure rules. +# Syntax: {(outer layer, inner layer): minimum enclosure, ...} +minimum_enclosure = { + # Via enclosure + (l_ndiffusion, l_ndiff_contact): 70*nm, # (CO.4) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_pdiffusion, l_pdiff_contact): 70*nm, # (CO.4) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_poly, l_poly_contact): 70*nm, # (CO.3) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + # The minimum is 5nm, but since we want to do the overlap symmetrical to achieve reproducibility, when we use 40nm we evade the rule that we would have to use 60nm on the other side: + (l_metal1, l_pdiff_contact): 40*nm, # (CO.6) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_metal1, l_ndiff_contact): 40*nm, # (CO.6) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + (l_metal1, l_poly_contact): 40*nm, # (CO.6) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_13.html + # The minimum is 5nm, but since we want to do the overlap symmetrical to achieve reproducibility, when we use 40nm we evade the rule that we would have to use 60nm on the other side: + (l_metal1, l_via1): 40*nm, # Vn.3 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html + (l_metal2, l_via1): 40*nm, # V1.4 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_15.html + # l_*well must overlap l_*diffusion + +### CONTINUE HERE + + (l_nwell, l_pdiffusion): 430*nm if targetvoltage=='3.3V' else 600*nm, # (DF.4c) https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html +# (l_pwell, l_ndiffusion): 430*nm if targetvoltage=='3.3V' else 600*nm, # I CANNOT FIND A RULE FOR THIS OUTSIDE DNWELL https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + (l_nplus, l_ndiff_contact): 230*nm, # NP.5a Implicitly encodes the size of well taps. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_09.html + (l_pplus, l_pdiff_contact): 230*nm, # PP.5a Implicitly encodes the size of well taps. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_10.html + #(l_dnwell, l_pwell): 2500*nm, +} + +# Minimum notch rules. +minimum_notch = { + l_ndiffusion: 280*nm if targetvoltage=='3.3V' else 360*nm, # DF.3a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_pdiffusion: 280*nm if targetvoltage=='3.3V' else 360*nm, # DF.3a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_poly: 240*nm, # PL.3a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_08.html + l_metal1: 230*nm, # Mn.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_metal2: 280*nm, # Mn.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_nwell: 600*nm if targetvoltage=='3.3V' else 740*nm, # NW.2a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_05.html + l_pwell: 860*nm, # LPW.2b https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_04.html +} + +# Minimum area rules. +min_area = { + l_ndiffusion: 0.2025 * um * um, # DF.9 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_pdiffusion: 0.2025 * um * um, # DF.9 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_06.html + l_metal1: 0.1444 * um * um ,# Mn.3 https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + #l_metal2: 0.1444 * um * um ,# Mn.3 - We don't need to enforce it here since that will be done by Openlane https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_14.html + l_nplus: 0.35 * um * um, #NP.8a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_09.html + l_pplus: 0.35 * um * um, #PP.8a https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_10.html +} + +# ROUTING # + +# Cost for changing routing direction (horizontal/vertical). +# This will avoid creating zig-zag routings. +orientation_change_penalty = 100000 + +# Routing edge weights per data base unit. +weights_horizontal = { + l_ndiffusion: 6300, # (mohms/square) + l_pdiffusion: 7000, # (mohms/square) + l_poly: 6300, # (mohms/square) + l_metal1: 90, # (mohms/square) + l_metal2: 90, # (mohms/square) +} +weights_vertical = { + l_ndiffusion: 6300, # (mohms/square) + l_pdiffusion: 7000, # (mohms/square) + l_poly: 6300, # (mohms/square) + l_metal1: 90, # (mohms/square) + l_metal2: 90, # (mohms/square) +} + +viafactor = 1000 + +# Via weights. +via_weights = { + (l_metal1, l_ndiffusion): 6300*viafactor, # LICON + (l_metal1, l_pdiffusion): 5200*viafactor, # LICON + (l_metal1, l_poly): 5900*viafactor, # LICON + (l_metal1, l_metal2): 4500*viafactor, # MCON + (l_metal1, l_nplus): 6300*viafactor, # Contact to Well Taps, the value doesn't matter + (l_metal1, l_pplus): 5200*viafactor, + +} + +# Enable double vias between layers. +multi_via = { + (l_metal1, l_poly): 1, + (l_metal1, l_metal2): 1, +} + +if( min_spacing[(l_pdiff_contact, l_pdiff_contact)] < min_spacing[(l_pdiffusion,l_pdiffusion)]+2*minimum_enclosure[(l_pdiffusion, l_pdiff_contact)]): + newmin=min_spacing[(l_pdiffusion,l_pdiffusion)]+2*minimum_enclosure[(l_pdiffusion, l_pdiff_contact)] + print("Minimum Spacing "+str(min_spacing[(l_pdiff_contact, l_pdiff_contact)])+" for pdiff_contact too small because of pdiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_pdiffusion,l_pdiffusion)])+"+2*"+str(minimum_enclosure[(l_pdiffusion, l_pdiff_contact)])+") Fixing minimum_spacing") + min_spacing[(l_pdiff_contact, l_pdiff_contact)]=newmin + +if( min_spacing[(l_ndiff_contact, l_ndiff_contact)] < min_spacing[(l_ndiffusion,l_ndiffusion)]+2*minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]): + newmin=min_spacing[(l_ndiffusion,l_ndiffusion)]+2*minimum_enclosure[(l_ndiffusion, l_ndiff_contact)] + print("Minimum Spacing "+str(min_spacing[(l_ndiff_contact, l_ndiff_contact)])+" for ndiff_contact too small because of ndiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_ndiffusion,l_ndiffusion)])+"+2*"+str(minimum_enclosure[(l_ndiffusion, l_ndiff_contact)])+") Fixing minimum_spacing") + min_spacing[(l_ndiff_contact, l_ndiff_contact)]=newmin + +#if( min_spacing[(l_pdiff_contact, l_ndiff_contact)] < min_spacing[(l_pdiffusion,l_ndiffusion)]+minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]+minimum_enclosure[(l_pdiffusion, l_pdiff_contact)]): +# newmin=min_spacing[(l_pdiffusion,l_ndiffusion)]+minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]+minimum_enclosure[(l_pdiffusion, l_pdiff_contact)] +# print("Minimum Spacing "+str(min_spacing[(l_ndiff_contact, l_ndiff_contact)])+" for pdiff_contact - ndiff_contact too small because of ndiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_pdiffusion,l_ndiffusion)])+"+"+str(minimum_enclosure[(l_ndiffusion, l_ndiff_contact)])+"+"+str(minimum_enclosure[(l_pdiffusion, l_pdiff_contact)])+") Fixing minimum_spacing") +# min_spacing[(l_pdiff_contact, l_ndiff_contact)]=newmin + +if((l_poly_contact, l_poly_contact) in min_spacing and min_spacing[(l_poly_contact, l_poly_contact)] < min_spacing[(l_poly,l_poly)]+2*minimum_enclosure[(l_poly, l_poly_contact)]): + newmin=min_spacing[(l_poly,l_poly)]+2*minimum_enclosure[(l_poly, l_poly_contact)] + print("Minimum Spacing "+str(min_spacing[(l_poly_contact, l_poly_contact)])+" for poly_contact too small because of polysilicon, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_poly,l_poly)])+"+"+str(minimum_enclosure[(l_poly, l_poly_contact)])+"+"+str(minimum_enclosure[(l_poly, l_poly_contact)])+") Fixing minimum_spacing") + min_spacing[(l_poly_contact, l_poly_contact)]=newmin + +if((l_poly_contact, l_poly_contact) in min_spacing and min_spacing[(l_poly_contact, l_poly_contact)] < min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_poly_contact)]): + newmin=min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_poly_contact)] + print("Minimum Spacing "+str(min_spacing[(l_poly_contact, l_poly_contact)])+" for poly_contact too small because of local interconnect, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal1,l_metal1)])+"+"+str(minimum_enclosure[(l_metal1, l_poly_contact)])+"+"+str(minimum_enclosure[(l_metal1, l_poly_contact)])+") Fixing minimum_spacing") + min_spacing[(l_poly_contact, l_poly_contact)]=newmin + +#if( min_spacing[(l_via1, l_via1)] < min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_via1)]): +# newmin=min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_via1)] +# print("Minimum Spacing "+str(min_spacing[(l_via1, l_via1)])+" for via1 too small because of metal1, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal1,l_metal1)])+"+2*"+str(minimum_enclosure[(l_metal1, l_via1)])+") Fixing minimum_spacing") +# min_spacing[(l_via1, l_via1)]=newmin + +#if( min_spacing[(l_via1, l_via1)] < min_spacing[(l_metal2,l_metal2)]+2*minimum_enclosure[(l_metal2, l_via1)]): +# newmin=min_spacing[(l_metal2,l_metal2)]+2*minimum_enclosure[(l_metal2, l_via1)] +# print("Minimum Spacing "+str(min_spacing[(l_via1, l_via1)])+" for via1 too small because of metal2, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal2,l_metal2)])+"+2*"+str(minimum_enclosure[(l_metal2, l_via1)])+") Fixing minimum_spacing") +# min_spacing[(l_via1, l_via1)]=newmin + + + + #(l_poly_contact, l_pdiff_contact): 170*nm, # (licon.2) + #(l_poly_contact, l_ndiff_contact): 170*nm, # (licon.2) +#unit_cell_height=10 +#routing_grid_pitch_y=4 + +#print("unit_cell_height: "+str(unit_cell_height)) +#print("routing_grid_pitch_y: "+str(routing_grid_pitch_y)) +middle=unit_cell_height//2 +#print("Middle: "+str(middle)) +gridpoints=1+unit_cell_height//routing_grid_pitch_y +#print("gridpoints: "+str(gridpoints)) +odd=gridpoints &1 +#print("odd: "+str(odd)) + +if odd==1: + grid_offset_y=middle-((gridpoints-1)//2)*routing_grid_pitch_y +else: + grid_offset_y=middle+routing_grid_pitch_y//2-(gridpoints//2)*routing_grid_pitch_y + +print("grid_offset_y: "+str(grid_offset_y)) +print("grid_offset_x: "+str(grid_offset_x)) +print("routing_grid_pitch_x: "+str(routing_grid_pitch_x)) + +grid_ys = list(range(grid_offset_y, grid_offset_y + unit_cell_height, routing_grid_pitch_y)) + +#print("y_grid_before: "+str(grid_ys)) +#grid_ys[2] += 110*nm +#grid_ys[-3] -= 110*nm +#grid_ys[14] -= 10*nm +#grid_ys[1] = 0 +#grid_ys[-2] = unit_cell_height +#grid_ys.pop(-1) +#grid_ys.pop(0) +#print("y_grid_after: "+str(grid_ys)) + +#grid_xs = list(range(grid_offset_x, grid_offset_x + unit_cell_width, routing_grid_pitch_x)) +#print("x_grid_after: "+str(grid_xs)) +#print("grid_offset_x"+str(grid_offset_x)) +#print("unit_cell_width"+str(unit_cell_width)) +#print("routing_grid_pitch_x"+str(routing_grid_pitch_x)) + + + +#def powervias(unit_cell_width): +# return list(range(240*nm,unit_cell_width,480*nm)) + +#power_vias=powervias + diff --git a/Tech.GF180MCU/libresilicon.m b/Tech.GF180MCU/libresilicon.m new file mode 100644 index 00000000..473e6e0a --- /dev/null +++ b/Tech.GF180MCU/libresilicon.m @@ -0,0 +1,14 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos level = 54 + +.model PMOS_VTL pmos level = 54 + +.model nmos nmos level = 54 + +.model pmos pmos level = 54 + +.model nfet nmos level = 54 + +.model pfet pmos level = 54 + diff --git a/Tech.GF180MCU/libresilicon.tech b/Tech.GF180MCU/libresilicon.tech new file mode 100644 index 00000000..66f58d1d --- /dev/null +++ b/Tech.GF180MCU/libresilicon.tech @@ -0,0 +1,3498 @@ +#---------------------------------------------------------- +# Copyright (c) 2022 Efabless, Inc. +# Techfile created by R. Timothy Edwards for the Google/ +# Global Foundries Open PDK project. +# +#---------------------------------------------------------- +# This file is designed to be used with magic +# versions 8.3 or newer. +# +# Rules reflect lambda = 0.05um. Minimum grid is 0.005um +#---------------------------------------------------------- +tech + format 34 + gf180mcuD +end + +version + version 1.0.357-0-ga519523 + description "Global Foundries 180mcu: open PDK rules and DRC" + requires magic-8.3.304 +end + +#----------------------------------------------------- +# Tile planes +#----------------------------------------------------- + +planes + dwell,dw + well,w + active,a + metal1,m1 + metal2,m2 + metal3,m3 + metal4,m4 + metal5,m5 + block,b + comment,c +end + +#----------------------------------------------------- +# Tile types +#----------------------------------------------------- + +types +# Deep nwell + dwell deepnwell,dnwell,dnw + dwell isosubstrate,isosub + +# Wells outside deep nwell + well nwell,nw + well pwell,pw +# Well obstruction layer + -well obswell +# Well resistors + well rnw,rnwell + +# Transistors + active nmos,ntransistor,nfet + active pmos,ptransistor,pfet + active nnmos,nntransistor,nnfet + active mvnmos,mvntransistor,mvnfet + active mvpmos,mvptransistor,mvpfet + active mvnnmos,mvnntransistor,mvnnfet +# Diffusions + active ndiff,ndiffusion,ndif + active pdiff,pdiffusion,pdif + active mvndiff,mvndiffusion,mvndif + active mvpdiff,mvpdiffusion,mvpdif + active ndiffc,ndcontact,ndc + active pdiffc,pdcontact,pdc + active mvndiffc,mvndcontact,mvndc + active mvpdiffc,mvpdcontact,mvpdc + active psubdiff,psubstratepdiff,ppdiff,ppd,psd + active nsubdiff,nsubstratendiff,nndiff,nnd,nsd + active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd + active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd + active psubdiffcont,psubstratepcontact,psc + active nsubdiffcont,nsubstratencontact,nsc + active mvpsubdiffcont,mvpsubstratepcontact,mvpsc + active mvnsubdiffcont,mvnsubstratencontact,mvnsc + -active obsactive + -active mvobsactive + active varactor,varact,var + active mvvaractor,mvvaract,mvvar +# Poly + active polysilicon,poly,p + active polycontact,pcontact,polycut,pc,polyc +# Resistors + active npolyres,npres,rnp + active ppolyres,ppres,rpp + active npolysilicide,nsresistor,nspres,rnps + active ppolysilicide,psresistor,pspres,rpps + active nhighres,nhires,hires + active mvnhighres,mvnhires,mvhires + active ndiffres,rnd,rdn,rndiff + active pdiffres,rpd,rdp,rpdiff + active ndiffsilicide,rnds,rdns,rndiffs + active pdiffsilicide,rpds,rdps,rpdiffs + active mvndiffres,mvrnd,mvrdn,mvrndiff + active mvpdiffres,mvrpd,mvrdp,mvrpdiff + active mvndiffsilicide,mvrnds,mvrdns,mvrndiffs + active mvpdiffsilicide,mvrpds,mvrdps,mvrpdiffs +# Diodes + active pdiode,pdi + active ndiode,ndi + active nndiode,nndi + active pdiodec,pdic + active ndiodec,ndic + active nndiodec,nndic + active mvpdiode,mvpdi + active mvndiode,mvndi + active mvnndiode,mvnndi + active mvpdiodec,mvpdic + active mvndiodec,mvndic + active mvnndiodec,mvnndic + + -active filldiff + -active fillpoly + + metal1 metal1,m1,met1 + metal1 rmetal1,rm1,rmet1 + -metal1 m1hole + metal1 via1,m2contact,m2cut,m2c,via,v,v1 + -metal1 obsm1 + -metal1 fillm1 + -metal1 obsv1 + metal1 padl + + metal2 metal2,m2,met2 + metal2 rmetal2,rm2,rmet2 + -metal2 m2hole + metal2 via2,m3contact,m3cut,m3c,v2 + -metal2 obsm2 + -metal2 fillm2 + -metal2 obsv2 + metal4 mimcap,mim,capm + metal4 mimcapcontact,mimcapc,mimcc,capmc + + metal3 metal3,m3,met3 + metal3 rmetal3,rm3,rmet3 + -metal3 m3hole + -metal3 obsm3 + -metal3 fillm3 + metal3 via3,v3 + + metal4 metal4,m4,met4 + metal4 rmetal4,rm4,rmet4 + -metal4 m4hole + -metal4 obsm4 + -metal4 fillm4 + metal4 via4,v4 + + metal5 metal5,m5,met5 + metal5 rm5,rmetal5,rmet5 + -metal5 m5hole + -metal5 obsm5 + -metal5 fillm5 + + block glass + block fillblock + + -comment lvstext + comment comment + -comment obscomment + +end + +#----------------------------------------------------- +# Magic contact types +#----------------------------------------------------- + +contact + pc poly metal1 + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + psc psd metal1 + ndic ndiode metal1 + nndic nndiode metal1 + pdic pdiode metal1 + + mvndc mvndiff metal1 + mvpdc mvpdiff metal1 + mvnsc mvnsd metal1 + mvpsc mvpsd metal1 + mvndic mvndiode metal1 + mvpdic mvpdiode metal1 + mvnndic mvnndiode metal1 + + via1 metal1 metal2 + via2 metal2 metal3 + via3 metal3 metal4 + via4 metal4 metal5 + + mimcc mimcap metal5 + stackable + + padl m1 m2 m3 m4 m5 glass +end + +#----------------------------------------------------- +# Layer aliases +#----------------------------------------------------- + +aliases + + allnwell nwell,rnwell + + allpsub space/w,pwell + + # Similar to allpsub* but does not include space-on-well-plane + allpwell pwell + + # Allsubwell contains space-on-well-plane but not obstruction-on-well-plane + # Used for defining anything under a device that does not touch active/substrate + allsubwell allnwell,allpsub + # Allwells contains obstruction-on-well-plane but not space-on-well-plane + allwells allnwell,allpwell,obswell + + allnfets nfet,mvnfet,nnfet,mvnnfet + allnfetsnonnat nfet,mvnfet + allpfets pfet,mvpfet + allfets allnfets,allpfets,varactor,mvvaractor + allfetsnonnat allnfetsnonnat,allpfets,varactor,mvvaractor + allfetsmv mvnfet,mvpfet,mvnnfet,mvvaractor + + allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*mvnndiode + allnactive allnactivenonfet,allnfets + + allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode + allpactive allpactivenonfet,allpfets + + allactivenonfet allnactivenonfet,allpactivenonfet + allactive allactivenonfet,allfets + + allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres + + allndifflv *ndif,*nsd,*ndiode,*nndiode,ndiffres,nfet,nnfet + allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet + alldifflv allndifflv,allpdifflv + allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres + allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres + alldifflvnonfet allndifflvnonfet,allpdifflvnonfet + + allndiffmv *mvndif,*mvnsd,*mvndiode,mvndiffres,mvnfet,mvnnfet,mvvaractor,*mvnndiode + allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet + alldiffmv allndiffmv,allpdiffmv + allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,mvndiffres,*mvnndiode + allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres + alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet + + alldiffnonfet alldifflvnonfet,alldiffmvnonfet + alldiff alldifflv,alldiffmv + + allnactivenonhv nfet,mvnfet,nnfet,mvnnfet,varactor,mvvaractor,*ndiff,*mvndiff,*nsd,*mvnsd,*ndiode,*nndiode,*mvndiode,*mvnndiode + allpactivenonhv pfet,mvpfet,*pdiff,*mvpdiff,*psd,*mvpsd,*pdiode,*mvpdiode + allactivenonhv allnactivenonhv,allpactivenonhv + + allpolyres rpp,rnp,rpps,rnps,hires,mvhires + allpolysblkres rpp,rnp,hires,mvhires + allsblkdev rnp,rpp,rnd,rpd,hires,mvhires,mvrnd,mvrpd + + allpolynonfet *poly,allpolyres + allpolynonres *poly,allfets + + allpoly allpolynonfet,allfets + allpolynoncap *poly,allfets,allpolyres + + allndiffcontlv ndc,nsc,ndic,nndic + allpdiffcontlv pdc,psc,pdic + allndiffcontmv mvndc,mvnsc,mvndic,mvnndic + allpdiffcontmv mvpdc,mvpsc,mvpdic + allndiffcont allndiffcontlv,allndiffcontmv + allpdiffcont allpdiffcontlv,allpdiffcontmv + alldiffcontlv allndiffcontlv,allpdiffcontlv + alldiffcontmv allndiffcontmv,allpdiffcontmv + alldiffcont alldiffcontlv,alldiffcontmv + + allcont alldiffcont,pc + + allres allpolyres,allactiveres + alldiode *pdiode,*ndiode,*nndiode,*mvpdiode,*mvndiode,*mvnndiode + + allm1 *m1,rm1 + allm2 *m2,rm2 + + allm3 *m3,rm3 + + allm4 *m4,rm4,*mimcap + + allm5 *m5,rm5 + + + allpad padl +end + +#----------------------------------------------------- +# Layer drawing styles +#----------------------------------------------------- + +styles + styletype mos + dnwell cwell + isosub subcircuit + + nwell nwell + rnwell nwell ntransistor_stripes + pwell pwell + + ndiff ndiffusion + pdiff pdiffusion + nsd ndiff_in_nwell + psd pdiff_in_pwell + nfet ntransistor ntransistor_stripes + nnfet ntransistor ndiff_in_nwell + pfet ptransistor ptransistor_stripes + var polysilicon ndiff_in_nwell + ndc ndiffusion metal1 contact_X'es + pdc pdiffusion metal1 contact_X'es + nsc ndiff_in_nwell metal1 contact_X'es + psc pdiff_in_pwell metal1 contact_X'es + + mvndiff ndiffusion hvndiff_mask + mvpdiff pdiffusion hvpdiff_mask + mvnsd ndiff_in_nwell hvndiff_mask + mvpsd pdiff_in_pwell hvpdiff_mask + mvnfet ntransistor ntransistor_stripes hvndiff_mask + mvnnfet ntransistor ndiff_in_nwell hvndiff_mask + mvpfet ptransistor ptransistor_stripes + mvvar polysilicon ndiff_in_nwell hvndiff_mask + mvndc ndiffusion metal1 contact_X'es hvndiff_mask + mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask + mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask + mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask + + poly polysilicon + pc polysilicon metal1 contact_X'es + npolyres polysilicon silicide_block nselect2 + ppolyres polysilicon silicide_block pselect2 + + pdiode pdiffusion pselect2 + ndiode ndiffusion nselect2 + nndiode ndiff_in_nwell nselect2 + pdiodec pdiffusion pselect2 metal1 contact_X'es + ndiodec ndiffusion nselect2 metal1 contact_X'es + nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es + + mvpdiode pdiffusion pselect2 hvpdiff_mask + mvndiode ndiffusion nselect2 hvndiff_mask + mvnndiode ndiff_in_nwell nselect2 hvndiff_mask + mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask + mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask + mvnndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask + + metal1 metal1 + rm1 metal1 poly_resist_stripes + obsm1 metal1 + fillm1 metal1 + obsv1 metal1 metal2 via1arrow + m1hole obsmetal1 + m2c metal1 metal2 via1arrow + metal2 metal2 + rm2 metal2 poly_resist_stripes + obsm2 metal2 + fillm2 metal2 + obsv2 metal2 metal3 via2arrow + m2hole obsmetal2 + m3c metal2 metal3 via2arrow + metal3 metal3 + rm3 metal3 poly_resist_stripes + obsm3 metal3 + fillm3 metal3 + m3hole obsmetal3 + via3 metal3 metal4 via3alt + metal4 metal4 + rm4 metal4 poly_resist_stripes + obsm4 metal4 + fillm4 metal4 + m4hole obsmetal4 + via4 metal4 metal5 via4 + metal5 metal5 + rm5 metal5 poly_resist_stripes + obsm5 metal5 + fillm5 metal5 + m5hole obsmetal5 + + mimcap metal4 mems + mimcc metal4 contact_X'es mems + glass overglass + rnp poly_resist poly_resist_stripes ndop_stripes + rpp poly_resist poly_resist_stripes pdop_stripes + rnps poly_resist ndop_stripes + rpps poly_resist pdop_stripes + nhighres poly_resist silicide_block + mvnhighres poly_resist silicide_block hvndiff_mask + ndiffres ndiffusion ndop_stripes + pdiffres pdiffusion pdop_stripes + mvndiffres ndiffusion hvndiff_mask ndop_stripes + mvpdiffres pdiffusion hvpdiff_mask pdop_stripes + comment comment + lvstext comment + error_p error_waffle + error_s error_waffle + error_ps error_waffle + fillblock cwell + + obswell cwell + obsactive implant4 + filldiff ndiffusion + fillpoly polysilicon + + padl metal5 via5 overglass + + magnet substrate_field_implant + rotate via3alt + fence via5 +end + +#----------------------------------------------------- +# Special paint/erase rules +#----------------------------------------------------- + +compose + compose nfet poly ndiff + compose pfet poly pdiff + compose var poly nsd + + compose mvnfet poly mvndiff + compose mvpfet poly mvpdiff + compose var poly mvnsd + + paint mimcap m4 mimcap + paint mimcapc m4 mimcapc + paint ndc nwell pdc + paint nfet nwell pfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + paint pdc pwell ndc + paint pfet pwell nfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + + paint m1 obsm1 m1 + paint m2 obsm2 m2 + paint m3 obsm3 m3 + paint m4 obsm4 m4 + paint m5 obsm5 m5 +end + +#----------------------------------------------------- +# Electrical connectivity +#----------------------------------------------------- + +connect + nwell,*nsd,*mvnsd nwell,*nsd,*mvnsd + pwell,*psd,*mvpsd,isosub pwell,*psd,*mvpsd,isosub + *psd,*mvpsd *psd,*mvpsd + *m1 *m1 + *m2 *m2 + *m3 *m3 + *m4 *m4 + *m5 *m5 + *mimcap *mimcap + allnactivenonfet allnactivenonfet + allpactivenonfet allpactivenonfet + *poly,allfets *poly,allfets +end + +#----------------------------------------------------- +# CIF/GDS output layer definitions +#----------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +cifoutput + +#----------------------------------------------------- +style gdsii +#----------------------------------------------------- + scalefactor 50 nanometers + options calma-permissive-labels + gridlimit 5 + +# This section used for actual GDSII output + +#----------------------------------------------------- +# DNWELL +#----------------------------------------------------- + layer DNWELL dnwell + calma 12 0 + +#----------------------------------------------------- +# NWELL +#----------------------------------------------------- + layer NWELL allnwell + close 1000000 + calma 21 0 + +#----------------------------------------------------- +# PWELL (LVPWELL) +#----------------------------------------------------- + layer PWELL pwell + calma 204 0 + +#----------------------------------------------------- +# DIFF (COMP) +#----------------------------------------------------- + layer DIFF alldiff + labels alldiff + calma 22 0 + + layer DIFFFILL filldiff + labels filldiff + calma 22 4 + +#----------------------------------------------------- +# PPLUS, NPLUS +#----------------------------------------------------- + + layer RESDEF + bloat-or hires,mvhires * 280 poly 0 + grow 200 + shrink 200 + calma 110 5 + + # hires requires PPLUS around terminals + templayer HRTERM + bloat-all hires,mvhires *poly + and-not hires,mvhires + + layer SBLK + bloat-or hires,mvhires * 280 poly 100 + calma 49 0 + + # rnps requires NPLUS + # rnp requires NPLUS + # rnd requires NPLUS + + layer NPLUS + bloat-all rnps *poly + bloat-all rnp *poly + bloat-all rnd *ndiff + grow 200 + grow 200 + shrink 200 + calma 32 0 + + # standard generation of NPLUS + + templayer nwell_shrink nwell + shrink 430 + + templayer shortntap *nsd,*mvnsd + and-not dnwell + and-not nwell_shrink + grow 160 + + templayer shortdntap dnwell + and pwell + grow 430 + and *nsd,*mvnsd + grow 160 + + layer NPLUS + bloat-or *ndif,*ndiode,*nndiode,ndiffres,*mvndif,*mvndiode,*mvnndiode,mvndiffres * 20 allpactivenonfet 0 + bloat-or *nsd,*mvnsd * 20 allpactivenonfet 0 + bloat-or allnfets,var,mvvar * 230 + or shortntap,shortdntap + grow 200 + shrink 200 + calma 32 0 + + # rpps requires PPLUS + # rpp requires PPLUS + # rpd requires PPLUS + + layer PPLUS + bloat-all rpps *poly + bloat-all rpp *poly + bloat-all rpd *pdiff + grow 200 + grow 200 + shrink 200 + calma 31 0 + + # standard generation of PPLUS, including hires resistors + + templayer shortptap nwell + and-not dnwell + grow 430 + and *psd,*mvpsd + grow 160 + + templayer pwell_shrink pwell + and dnwell + shrink 430 + + templayer shortdptap *psd,*mvpsd + and dnwell + and-not pwell_shrink + grow 160 + + layer PPLUS + or HRTERM + grow 200 + and-not RESDEF + bloat-or *pdif,*pdiode,pdiffres,pfet,*mvpdif,*mvpdiode,mvpdiffres,mvpfet * 160 allnactivenonfet 0 + bloat-or *psd,*mvpsd * 20 allnactivenonfet 0 + bloat-or allpfets * 230 + or shortptap,shortdptap + grow 200 + shrink 200 + calma 31 0 + + templayer varactive + bloat-all var *nsd + +#----------------------------------------------------- +# DUALGATE (thickox) +#----------------------------------------------------- + + layer DUALGATE allfetsmv + bloat-all mvhires *poly + # Rule DV.8 (DUALGATE around poly) + grow 400 + # Rule DV.6 (DUALGATE around diff, LV substrate tap excepted) + bloat-or allndiffmv * 240 *psd 0 + bloat-or allpdiffmv * 240 + grow 219 + shrink 219 + calma 55 0 + + # DUALGATE completely covers deep nwell + layer DUALGATE + bloat-all alldiffmv dnwell + grow 500 + grow 219 + shrink 219 + calma 55 0 + +#----------------------------------------------------- +# NAT +#----------------------------------------------------- + + layer NAT + bloat-all *nndiode,nnfet *ndiff + bloat-all *mvnndiode,mvnnfet *mvndiff + grow 260 + grow 309 + shrink 309 + calma 5 0 + +#----------------------------------------------------- +# POLY +#----------------------------------------------------- + layer POLY allpoly + close 224000 + labels allpoly noport + calma 30 0 + + layer POLYTXT + labels allpoly port + calma 30 10 + + layer POLYFILL fillpoly + labels fillpoly + calma 30 4 + +#----------------------------------------------------- +# CONT +#----------------------------------------------------- +# NOTE: Contact arrays defined at 200 spacing for large array rule (4x4), +# otherwise spacing is 180 + + layer contlarge allcont + shrink 615 + grow 615 + + layer CONT allcont + and-not contlarge + squares-grid 5 220 250 + calma 33 0 + + layer CONT allcont + and contlarge + squares-grid 5 220 280 + calma 33 0 + +#----------------------------------------------------- +# MET1 +#----------------------------------------------------- + layer MET1 allm1 + labels allm1 noport + calma 34 0 + + layer MET1TXT + labels allm1 port + calma 34 10 + + layer M1BLOCK obsm1 + labels obsm1 + calma 34 5 + + layer M1FILL fillm1 + labels fillm1 + calma 34 4 + +#----------------------------------------------------- +# VIA1 +#----------------------------------------------------- + templayer via1large via1 + shrink 915 + grow 915 + + layer VIA1 via1 + and-not via1large + squares-grid 0 260 260 + calma 35 0 + + layer VIA1 via1 + and via1large + squares-grid 0 260 360 + calma 35 0 + +#----------------------------------------------------- +# MET2 +#----------------------------------------------------- + layer MET2 allm2 + labels allm2 noport + calma 36 0 + + layer MET2TXT + labels allm2 port + calma 36 10 + + layer M2BLOCK obsm2 + labels obsm2 + calma 36 5 + + layer M2FILL fillm2 + labels fillm2 + calma 36 4 + +#----------------------------------------------------- +# VIA2 +#----------------------------------------------------- + templayer via2large via2 + shrink 915 + grow 915 + + layer VIA2 via2 + and-not via2large + squares-grid 10 260 260 + calma 38 0 + + layer VIA2 via2 + and via2large + squares-grid 10 260 360 + calma 38 0 + + +#----------------------------------------------------- +# MET3 +#----------------------------------------------------- + layer MET3 allm3 + labels allm3 noport + calma 42 0 + + layer MET3TXT + labels allm3 port + calma 42 10 + + layer M3BLOCK obsm3 + labels obsm3 + calma 42 5 + + layer M3FILL fillm3 + labels fillm3 + calma 42 4 + +#----------------------------------------------------- +# VIA3 +#----------------------------------------------------- + templayer via3large via3 + shrink 915 + grow 915 + + layer VIA3 via3 + and-not via3large + squares-grid 10 260 260 + calma 40 0 + + layer VIA3 via3 + and via3large + squares-grid 10 260 360 + calma 40 0 + + +#----------------------------------------------------- +# MET4 +#----------------------------------------------------- + layer MET4 allm4 + labels allm4 noport + calma 46 0 + + layer MET4TXT + labels allm4 port + calma 46 10 + + layer M4BLOCK obsm4 + labels obsm4 + calma 46 5 + + layer M4FILL fillm4 + labels fillm4 + calma 46 4 + + +#----------------------------------------------------- +# VIA4 +#----------------------------------------------------- + templayer via4large via4 + shrink 915 + grow 915 + + layer VIA4 via4 + and-not via4large + squares-grid 10 260 260 + calma 41 0 + + layer VIA4 via4 + and via4large + squares-grid 10 260 360 + calma 41 0 + + layer VIA4 mimcapc + squares-grid 10 260 500 + calma 41 0 + + +#----------------------------------------------------- +# MET5 +#----------------------------------------------------- + layer MET5 allm5 + labels allm5 noport + calma 81 0 + + layer MET5TXT + labels allm5 port + calma 81 10 + + layer M5BLOCK obsm5 + labels obsm5 + calma 81 5 + + layer M5FILL fillm5 + labels fillm5 + calma 81 4 + + + +#----------------------------------------------------- +# GLASS +#----------------------------------------------------- + layer GLASS glass + calma 37 0 + +#----------------------------------------------------- +# PRBNDRY +#----------------------------------------------------- + layer PRBNDRY + boundary + calma 0 0 + +#----------------------------------------------------- +# CAPM +#----------------------------------------------------- +# NOTE: MiM bottom plate handled by alias "allm*" when 1 defined + + layer CAPM *mimcap + labels mimcap + calma 75 0 + + layer CAPDEF *mimcap + grow 200 + calma 117 5 + +#----------------------------------------------------- +# SBLK +#----------------------------------------------------- + + layer SBLK + bloat-or allsblkdev * 0 space/a 220 + grow 215 + shrink 215 + calma 49 0 + + # sblk from rdn/rdp of esd fet + # assume that the diff in only 0.05um + layer SBLK rdp + grow 100 + and pfet + grow 400 + calma 49 0 + + layer SBLK rdn + grow 250 + and nfet + grow 400 + calma 49 0 + +#----------------------------------------------------- +# RESDEF MARK +#----------------------------------------------------- + layer RESDEF allres + calma 110 5 + +#----------------------------------------------------- +# METAL RESISTOR IDs +#----------------------------------------------------- + layer MET1RES rm1 + calma 110 11 + + layer MET2RES rm2 + calma 110 12 + + layer MET3RES rm3 + calma 110 13 + + layer MET4RES rm4 + calma 110 14 + + layer MET5RES rm5 + calma 110 15 + + +#----------------------------------------------------- +# DIODE MARK +#----------------------------------------------------- + layer DIODE alldiode + calma 115 5 + +#----------------------------------------------------- +# MOSCAP MARK +#----------------------------------------------------- + layer MOSCAP var,mvvar + calma 166 5 + +#----------------------------------------------------- +# HRES +#----------------------------------------------------- + layer HRES + bloat-all hires,mvhires *poly + grow 400 + calma 62 0 + +#------------------------------------------------------------------------ +# FILLBLOCK (NOTE: two layers define this on active, then poly & metal) +#------------------------------------------------------------------------ + layer FILLOBS fillblock + calma 111 5 + + layer FILLOBS2 fillblock + calma 152 5 + +#---------------------------------------------------------- +style metfill +#---------------------------------------------------------- +# This section used for metal filling output by a sequence +# of cif paint commands + + scalefactor 50 nanometers + options calma-permissive-labels + gridlimit 5 + +#----------------------------------------------------- +# Fill layer geometry +#----------------------------------------------------- + + templayer fill_geometry_off0 + bbox top + slots 0 2000 1000 0 2000 1000 1000 0 + + templayer fill_geometry_off1 + bbox top + slots 0 2000 1000 0 2000 1000 1000 660 + + templayer fill_geometry_off2 + bbox top + slots 0 2000 1000 0 2000 1000 1000 1320 + + +#----------------------------------------------------- +# Obstruction geometry +#----------------------------------------------------- + + templayer obstruct_diff alldiff,filldiff,obsactive + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_poly allpoly,fillpoly + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_m1 allm1,allpad,fillm1,obsm1 + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_m2 allm2,allpad,fillm2,obsm2 + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_m3 allm3,allpad,fillm3,obsm3 + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_m4 allm4,allpad,fillm4,obsm4 + grow 2010 + shrink 500 + grow 500 + + templayer obstruct_m5 allm5,allpad,fillm5,obsm5 + grow 2010 + shrink 500 + grow 500 + + +#----------------------------------------------------- +# DIFF FILL +#----------------------------------------------------- + layer difffill fill_geometry_off0 + shrink 995 + grow 995 + +#----------------------------------------------------- +# POLY FILL +#----------------------------------------------------- + layer polyfill fill_geometry_off1 + and-not obstruct_m1 + shrink 995 + grow 995 + +#----------------------------------------------------- +# MET1 FILL +#----------------------------------------------------- + layer met1fill fill_geometry_off2 + and-not obstruct_poly + and-not obstruct_m1 + and-not obstruct_m2 + shrink 995 + grow 995 + +#----------------------------------------------------- +# MET2 FILL +#----------------------------------------------------- + layer met2fill fill_geometry_off0 + and-not obstruct_m1 + and-not obstruct_m2 + shrink 995 + grow 995 + +#----------------------------------------------------- +# MET3 FILL +#----------------------------------------------------- + layer met3fill fill_geometry_off1 + and-not obstruct_m2 + and-not obstruct_m3 + shrink 995 + grow 995 + +#----------------------------------------------------- +# MET4 FILL +#----------------------------------------------------- + layer met4fill fill_geometry_off2 + and-not obstruct_m3 + and-not obstruct_m4 + shrink 995 + grow 995 + +#----------------------------------------------------- +# MET5 FILL +#----------------------------------------------------- + layer met5fill fill_geometry_off0 + and-not obstruct_m4 + and-not obstruct_m5 + shrink 995 + grow 995 + + +#----------------------------------------------------------------------- +style drc +#----------------------------------------------------------------------- +# NOTE: this style is used for DRC only, not for GDS output +#----------------------------------------------------------------------- + + scalefactor 50 nanometers + options calma-permissive-labels + gridlimit 5 + + # Check for MV and LV devices in the same dnwell + templayer mv_dnwell + bloat-all alldiffmv dnwell + + templayer bad_dnwell + bloat-all alldifflv dnwell + and mv_dnwell + + # Check pwell in dnwell + templayer pwell_in_dnwell pwell + and dnwell + and-not mv_dnwell + + templayer mvpwell_in_dnwell pwell + and mv_dnwell + + # Check for MV and LV devices in the same nwell + templayer mv_nwell + bloat-all alldiffmv nwell + + templayer bad_nwell + bloat-all alldifflv nwell + and mv_nwell + + # Check for nwell resistor in deep nwell + templayer bad_rnw rnw + and dnwell + + # Define HRES layer for DRC checks + templayer res_hres + bloat-all mvhires,hires *poly + + # Check for contact at correct position for HIRES, LRES, PRES resistors + templayer res_cont res_hres + bloat-all rnp,rpp *poly + and pc + squares-grid 5 220 250 + + templayer res_cont_space_min mvhires,hires + # SBLK larger than defined resistor by 0.1um + grow 100 + # SBLK = resistor for rnp and rpp + or rnp,rpp + # SBLK spacing to contact + grow 220 + and res_cont + # If anything remains, contact is too close. + + templayer res_cont_space_max mvhires,hires + # SBLK larger than defined resistor by 0.1um + grow 100 + # SBLK = resistor for rnp and rpp + or rnp,rpp + # SBLK spacing to contact + grow 220 + # size of poly contact + grow 220 + and res_cont + + templayer res_no_cont res_cont + and-not res_cont_space_max + # If anything remains, contact is too far away + + # Check for HRES to poly and diffusion spacing + templayer res_hres_grow res_hres + grow 700 + + templayer res_diff_space res_hres_grow + and alldiff + # If anything remains, HRES is too close to diffusion + + templayer res_poly_space res_hres_grow + and-not res_hres + and allpoly + # If anything remains, HRES is too close to poly + + # Check for MiM cap bottom plate to other metal spacing rule (< 1.2um) + templayer mim_bottom_plate + bloat-all *mim *m4 + + templayer mim_bottom_plate_space mim_bottom_plate + grow 1200 + and m4 + and-not mim_bottom_plate + # If anything remains, bottom plate is too close + + # Check for MiM cap bottom plate surrounds contact (by 0.4um) + templayer mim_bot_cont_surround via4 + and mim_bottom_plate + squares-grid 10 260 500 + grow 400 + and-not mim_bottom_plate + # If anything remains, not enough surround + +end + +#----------------------------------------------------------------------- +cifinput +#----------------------------------------------------------------------- + +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +style import + scalefactor 50 nanometers + gridlimit 5 + + #options ignore-unknown-layer-labels options no-reconnect-labels + + ignore BJTDEF + ignore MOSCAP + ignore SRAMDEF + ignore FET5VDEF + ignore CAPDEF + ignore VTEXT + + layer pwell PWELL + labels PWELL + + layer nwell NWELL + labels NWELL + + layer dnwell DNWELL + labels DNWELL + + templayer ndiffarea DIFF + and-not POLY + and-not NWELL + and-not PPLUS + and-not SBLK + and-not DUALGATE + and NPLUS + copyup ndifcheck + + layer ndiff ndiffarea + labels DIFF + + layer filldiff DIFFFILL + labels DIFFFILL + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF + and-not POLY + and-not NWELL + and-not PPLUS + and-not SBLK + and DUALGATE + and NPLUS + copyup mvndifcheck + + layer mvndiff mvndiffarea + labels DIFF + + # Copy mvndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not DUALGATE + and-not NAT + labels DIFF + + layer nndiode DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not DUALGATE + and NAT + labels DIFF + + templayer ndiodearea DIODE + and NPLUS + and-not NWELL + and-not DUALGATE + copyup DIODE,NPLUS + + layer ndiffres DIFF + and-not POLY + and SBLK + and NPLUS + and-not DUALGATE + labels DIFF + + templayer pdiffarea DIFF + and-not POLY + and NWELL + and-not NPLUS + and-not SBLK + and-not DIODE + and PPLUS + and-not DUALGATE + copyup pdifcheck + + layer pdiff pdiffarea + labels DIFF + + layer mvndiode DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and DUALGATE + and-not NAT + labels DIFF + + layer mvnndiode DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and DUALGATE + and NAT + labels DIFF + + templayer mvndiodearea DIODE + and NPLUS + and-not NWELL + and DUALGATE + copyup DIODE,NPLUS + + layer mvndiffres DIFF + and-not POLY + and SBLK + and NPLUS + and DUALGATE + labels DIFF + + templayer mvpdiffarea DIFF + and-not POLY + and NWELL + and-not NPLUS + and-not SBLK + and-not DIODE + and DUALGATE + and PPLUS + copyup mvpdifcheck + + layer mvpdiff mvpdiffarea + labels DIFF + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not DUALGATE + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PPLUS + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer pfetarea DIFF + and-not NPLUS + and-not DUALGATE + and POLY + + layer pfet pfetarea + labels DIFF + + templayer pfetexpand pfetarea + grow 530 + + # Always force nwell under pfet + layer nwell pfetarea + grow 310 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not RESDEF + and DUALGATE + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PPLUS + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF + and DUALGATE + and-not NPLUS + and POLY + + layer mvpfet mvpfetarea + labels DIFF + + templayer mvpfetexpand mvpfetarea + grow 530 + + layer pdiff DIFF + and-not DUALGATE + and-not NPLUS + and-not POLY + and NWELL + and pfetexpand + labels DIFF + + layer pdiffres DIFF + and-not POLY + and PPLUS + and NWELL + and SBLK + labels DIFF + + layer nfet DIFF + and POLY + and-not PPLUS + and-not DUALGATE + and-not NWELL + and NPLUS + and-not NAT + labels DIFF + + layer nnfet DIFF + and POLY + and-not PPLUS + and-not DUALGATE + and-not NWELL + and NPLUS + and NAT + labels DIFF + + + templayer nsdarea DIFF + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and-not DUALGATE + + layer nsd nsdarea + labels DIFF + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea DIFF + and PPLUS + and-not DUALGATE + and-not NWELL + and-not POLY + and-not NPLUS + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels DIFF + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF + and-not NPLUS + and-not POLY + and NWELL + and DUALGATE + and mvpfetexpand + labels DIFF + + layer mvpdiffres DIFF + and-not POLY + and PPLUS + and SBLK + and DUALGATE + labels DIFF + + layer mvnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not NAT + and-not NWELL + and DUALGATE + labels DIFF + + layer mvnnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and NAT + and-not NWELL + and DUALGATE + labels DIFF + + templayer mvnsdarea DIFF + and NPLUS + and-not POLY + and-not PPLUS + and NWELL + and DUALGATE + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels DIFF + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea DIFF + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and DUALGATE + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and-not DUALGATE + and-not pfetexpand + and psdexpand + + layer nsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and NWELL + and-not DUALGATE + and nsdexpand + + layer mvpsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and-not NWELL + and DUALGATE + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and NWELL + and DUALGATE + and mvnsdexpand + + templayer polyarea POLY + and-not DIFF + and-not SBLK + and-not HRES + copyup polycheck + + layer poly polyarea,POLYTXT + and-not RESDEF + labels POLY + labels POLYTXT text + + layer fillpoly POLYFILL + labels POLYFILL + + # Copy poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer rpps POLY + and-not SBLK + and PPLUS + and RESDEF + labels POLY + + layer rnps POLY + and-not SBLK + and NPLUS + and RESDEF + labels POLY + + layer rpp POLY + and SBLK + and PPLUS + and-not HRES + and RESDEF + labels POLY + + # POLY + SBLK without RESDEF may be a salicide-blocked transistor. + # The SBLK will be regenerated on GDS output and the poly should be + # treated as regular poly. + layer poly POLY + and-not DIFF + and SBLK + and-not RESDEF + labels POLY + + layer rnp POLY + and SBLK + and NPLUS + and RESDEF + and-not HRES + labels POLY + + layer hires POLY + and SBLK + and HRES + and RESDEF + and-not DUALGATE + labels POLY + + layer mvhires POLY + and SBLK + and HRES + and RESDEF + and DUALGATE + labels POLY + + # We define poly under HRES but not under SBLK to be plain poly + layer poly POLY + and HRES + and-not SBLK + and-not RESDEF + + layer ndc CONT + and DIFF + and NPLUS + and-not NWELL + and MET1 + and-not DUALGATE + and-not DIODE + grow 145 + shrink 140 + + layer nsc CONT + and DIFF + and NPLUS + and NWELL + and MET1 + and-not DUALGATE + and-not DIODE + grow 145 + shrink 140 + + layer pdc CONT + and DIFF + and PPLUS + and NWELL + and MET1 + and-not DUALGATE + and-not DIODE + grow 145 + shrink 140 + + layer pdc CONT + and DIFF + and PPLUS + and MET1 + and-not DUALGATE + and-not DIODE + and pfetexpand + grow 145 + shrink 140 + + layer psc CONT + and DIFF + and PPLUS + and-not NWELL + and MET1 + and-not DUALGATE + and-not DIODE + and-not pfetexpand + grow 145 + shrink 140 + + layer pc CONT + and POLY + and-not DIFF + and MET1 + grow 145 + shrink 140 + + layer ndic CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not DUALGATE + and-not NAT + grow 145 + shrink 140 + + layer nndic CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not DUALGATE + and NAT + grow 145 + shrink 140 + + layer pdic CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not DUALGATE + grow 145 + shrink 140 + + layer mvndc CONT + and DIFF + and NPLUS + and-not NWELL + and MET1 + and DUALGATE + and-not DIODE + grow 145 + shrink 140 + + layer mvnsc CONT + and DIFF + and NPLUS + and MET1 + and DUALGATE + and NWELL + and-not DIODE + grow 145 + shrink 140 + + layer mvpdc CONT + and DIFF + and PPLUS + and MET1 + and DUALGATE + and NWELL + and-not DIODE + grow 145 + shrink 140 + + layer mvpdc CONT + and DIFF + and PPLUS + and MET1 + and DUALGATE + and-not DIODE + and mvpfetexpand + grow 145 + shrink 140 + + layer mvpsc CONT + and DIFF + and PPLUS + and-not NWELL + and MET1 + and DUALGATE + and-not DIODE + and-not mvpfetexpand + grow 145 + shrink 140 + + layer mvndic CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and DUALGATE + and-not NAT + grow 145 + shrink 140 + + layer mvnndic CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and DUALGATE + and NAT + grow 145 + shrink 140 + + layer mvpdic CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and DUALGATE + grow 145 + shrink 140 + + layer rm1 MET1 + and RESDEF + and MET1RES + + layer m1 MET1,MET1TXT + and-not MET1RES + labels MET1 + labels MET1TXT port + + layer obsm1 M1BLOCK + labels M1BLOCK + + layer fillm1 M1FILL + labels M1FILL + + layer m2c VIA1 + grow 130 + shrink 130 + + layer rm2 MET2 + and RESDEF + and MET2RES + + layer m2 MET2,MET2TXT + and-not MET2RES + labels MET2 + labels MET2TXT port + + layer obsm2 M2BLOCK + labels M2BLOCK + + layer fillm2 M2FILL + labels M2FILL + + layer rm3 MET3 + and RESDEF + and MET3RES + + templayer mimarea CAPDEF + and MET2 + + layer m3 MET3,MET3TXT + and-not MET3RES + labels MET3 + labels MET3TXT port + + layer obsm3 M3BLOCK + labels M3BLOCK + + layer fillm3 M3FILL + labels M3FILL + + layer m3c VIA2 + grow 140 + shrink 130 + + layer mimcc VIA2 + and MET3 + and CAPM + and CAPDEF + grow 90 + grow 250 + shrink 250 + + layer rm4 MET4 + and RESDEF + and MET4RES + + templayer mimarea CAPDEF + and MET3 + + layer m4 MET4,MET4TXT + and-not MET4RES + labels MET4 + labels MET4TXT port + + layer obsm4 M4BLOCK + labels M4BLOCK + + layer fillm4 M4FILL + labels M4FILL + + layer via3 VIA3 + and-not CAPM + and-not mimarea + grow 140 + shrink 130 + + layer mimcc VIA3 + and MET4 + and CAPM + and CAPDEF + grow 90 + grow 250 + shrink 250 + + layer rm5 MET5 + and RESDEF + and MET5RES + + templayer mimarea CAPDEF + and MET4 + + layer m5 MET5,MET5TXT + and-not MET5RES + labels MET5 + labels MET5TXT port + + layer obsm5 M5BLOCK + labels M5BLOCK + + layer fillm5 M5FILL + labels M5FILL + + layer via4 VIA4 + grow 140 + shrink 130 + + layer mimcc VIA4 + and MET5 + and CAPM + and CAPDEF + grow 90 + grow 250 + shrink 250 + + + layer mimcap CAPM + and CAPDEF + labels CAPM + + # Find diffusion not covered in + # NPLUS or PPLUS and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PPLUS + and-not NPLUS + and POLY + copyup DIFF,POLY + + templayer gendiff DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + copyup DIFF + + # Handle contacts found by copyup + + layer ndic CONT + and MET1 + and DIODE + and NPLUS + and-not DUALGATE + and-not NAT + grow 100 + shrink 100 + + layer mvndic CONT + and MET1 + and DIODE + and NPLUS + and DUALGATE + and-not NAT + grow 100 + shrink 100 + + layer mvnndic CONT + and MET1 + and DIODE + and NPLUS + and DUALGATE + and NAT + grow 100 + shrink 100 + + layer pdic CONT + and MET1 + and DIODE + and PPLUS + and-not DUALGATE + grow 100 + shrink 100 + + layer mvpdic CONT + and MET1 + and DIODE + and PPLUS + and DUALGATE + grow 100 + shrink 100 + + layer ndc CONT + and ndifcheck + grow 100 + shrink 100 + + layer mvndc CONT + and mvndifcheck + grow 100 + shrink 100 + + layer pdc CONT + and pdifcheck + grow 100 + shrink 100 + + layer mvpdc CONT + and mvpdifcheck + grow 100 + shrink 100 + + layer pc CONT + and polycheck + grow 100 + shrink 100 + + layer nsc CONT + and nsubcheck + grow 100 + shrink 100 + + layer mvnsc CONT + and mvnsubcheck + grow 100 + shrink 100 + + layer psc CONT + and psubcheck + grow 100 + shrink 100 + + layer mvpsc CONT + and mvpsubcheck + grow 100 + shrink 100 + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer gencont CONT + and MET1 + and-not DIFF + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT,MET1 + + templayer barecont CONT + and-not MET1 + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT + + layer glass GLASS + labels GLASS + + templayer cellbound BOUND,PRBOUND + boundary + + layer lvstext TTEXT + labels TTEXT text + + layer fillblock FILLOBS,FILLOBS2 + labels FILLOBS + +# MOS Varactors + + layer var POLY + and DIFF + and NPLUS + and NWELL + and-not DUALGATE + labels POLY + + layer mvvar POLY + and DIFF + and NPLUS + and NWELL + and DUALGATE + labels POLY + + calma DNWELL 12 0 + calma NWELL 21 0 + calma PWELL 204 0 + calma DIFF 22 0 + calma DIFFFILL 22 4 + calma POLY 30 0 + calma POLYFILL 30 4 + calma POLYTXT 30 10 + calma NPLUS 32 0 + calma PPLUS 31 0 + calma SBLK 49 0 + calma GLASS 37 0 + calma CONT 33 0 + calma MET1 34 0 + calma MET1TXT 34 10 + calma M1BLOCK 34 5 + calma M1FILL 34 4 + calma MET2RES 110 11 + calma VIA1 35 0 + calma MET2 36 0 + calma MET2TXT 36 10 + calma M2BLOCK 36 5 + calma M2FILL 36 4 + calma MET2RES 110 12 + calma VIA2 38 0 + calma MET3 42 0 + calma MET3TXT 42 10 + calma M3BLOCK 42 5 + calma M3FILL 42 4 + calma MET3RES 110 13 + calma VIA3 40 0 + calma MET4 46 0 + calma MET4TXT 46 10 + calma M4BLOCK 46 5 + calma M4FILL 46 4 + calma MET4RES 110 14 + calma VIA4 41 0 + calma MET5 81 0 + calma MET5TXT 81 10 + calma M5BLOCK 81 5 + calma M5FILL 81 4 + calma MET5RES 110 15 + calma HRES 62 0 + calma NAT 5 0 + calma CAPM 75 0 + calma DIODE 115 5 + calma CAPDEF 117 5 + calma BJTDEF 118 5 + calma MOSCAP 166 5 + calma BOUND 0 0 + calma PRBOUND 63 0 + calma VTEXT 63 63 + calma FILLOBS 111 5 + calma FILLOBS2 152 5 + calma TTEXT 230 * + calma RESDEF 110 * + calma DUALGATE 55 0 + calma SRAMDEF 108 5 + calma FET5VDEF 112 1 + +end + +#----------------------------------------------------- +# Digital flow maze router cost parameters +#----------------------------------------------------- + +mzrouter +end + +#----------------------------------------------------- +# Vendor DRC rules +#----------------------------------------------------- + +drc + + style drc variants (full),(fast),(routing) + + scalefactor 50 + + cifstyle drc + + variants (fast),(full) + +#----------------------------- +# NWELL +#----------------------------- + + # ORIGINAL RULE: width allnwell 860 "N-well width < %d (NW.1a)" + width allnwell 860 "N-well width < %d (NW.1a) [paint nwell,rnwell]" + spacing allnwell allnwell 600 touching_ok "N-well spacing < %d (NW.2a) [erase nwell rnwell]" + # rnw spacing is to unrelated nwell only. + spacing rnw allnwell 1400 touching_ok "N-well resistor spacing < %d (NW.4) [erase rnwell,nwell rnwell]" + # ORIGINAL RULE: width rnw 2000 "N-well resistor width < %d (NW.1b)" + width rnw 2000 "N-well resistor width < %d (NW.1b) [paint rnwell]" + + variants (full) + cifspacing mv_nwell mv_nwell 740 touching_ok "MV N-well spacing < %d (NW.2a)" + variants * + +#----------------------------- +# DNWELL (deep nwell) +#----------------------------- + + # ORIGINAL RULE: width dnwell 1700 "Deep N-well width < %d (DN.1)" + width dnwell 1700 "Deep N-well width < %d (DN.1) [paint deepnwell]" + spacing dnwell dnwell 2500 touching_ok "Deep N-well spacing < %d (DN.2a) [erase deepnwell]" + + surround pwell dnwell 2500 absence_ok "Deep N-well surround P-well < %d (LPW.3) [erase pwell,deepnwell]" + + surround nwell dnwell 500 absence_ok "Deep N-well surround N-well < %d (NW.5) [erase nwell,deepnwell]" + + variants (full) + + cifwidth pwell_in_dnwell 600 "P-well in deep N-well size < %d (LPW.1)" + cifwidth mvpwell_in_dnwell 740 "HV P-well in deep N-well size < %d (LPW.1)" + + cifspacing pwell_in_dnwell pwell_in_dnwell 860 touching_ok \ + "P-well in deep N-well spacing < %d (LPW.2b)" + cifspacing mvpwell_in_dnwell mvpwell_in_dnwell 860 touching_ok \ + "MV P-well in deep N-well spacing < %d (LPW.2b)" + + cifmaxwidth bad_dnwell 0 bend_illegal \ + "Both LV and MV devices cannot be in the same deep N-well (DN.11) + + cifmaxwidth bad_nwell 0 bend_illegal \ + "Both LV and MV devices cannot be in the same N-well (DV.9) + + cifmaxwidth bad_rnw 0 bend_illegal \ + "N-well resistor cannot be in deep N-well (DN.12) + variants * + + spacing dnwell allnwell 3100 surround_ok "Deep N-well spacing to N-well < %d (NW.3) [erase deepnwell,nwell rnwell]" + + spacing pwell dnwell 1500 surround_ok "Deep N-well spacing to P-well < %d (LPW.11) [erase pwell,deepnwell]" + +#----------------------------- +# DIFF (diffusion) +#----------------------------- + + # ORIGINAL RULE: width alldifflv 220 "Diffusion width < %d (DF.1a)" + width alldifflv 220 "Diffusion width < %d (DF.1a) [paint ndcontact,ndiffres,ndiffusion,ndiode,ndiodec,nndiode,nndiodec,nntransistor,nsubstratencontact,nsubstratendiff,ntransistor,pdcontact,pdiffres,pdiffusion,pdiode,pdiodec,psubstratepcontact,psubstratepdiff,ptransistor]" + # ORIGINAL RULE: width alldiffmv 300 "Diffusion width < %d (DF.1a)" + width alldiffmv 300 "Diffusion width < %d (DF.1a) [paint mvndcontact,mvndiffres,mvndiffusion,mvndiode,mvndiodec,mvnndiode,mvnndiodec,mvnntransistor,mvnsubstratencontact,mvnsubstratendiff,mvntransistor,mvpdcontact,mvpdiffres,mvpdiffusion,mvpdiode,mvpdiodec,mvpsubstratepcontact,mvpsubstratepdiff,mvptransistor,mvvaractor]" + area alldifflv 202500 220 "Diffusion minimum area < %a (DF.9)" + area alldiffmv 202500 300 "Diffusion minimum area < %a (DF.9)" + spacing alldifflv,var alldifflv,var 280 touching_ok "Diffusion spacing < %d (DF.3a) [erase ndcontact ndiffres ndiffusion ndiode ndiodec nndiode nndiodec nntransistor nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec psubstratepcontact psubstratepdiff ptransistor varactor]" + spacing alldiffmv,mvvar alldiffmv,mvvar 360 touching_ok "Diffusion spacing < %d (DF.3a) [erase mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnndiode mvnndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor mvvaractor]" + + spacing *ndiff,*ndiode,nfet,nnfet allnwell 430 touching_illegal "N-Diffusion spacing to N-well < %d (DF.8) [erase ndcontact ndiffusion ndiode ndiodec nntransistor ntransistor,nwell rnwell]" + spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 600 touching_illegal "N-Diffusion spacing to N-well < %d (DF.8) [erase mvndcontact mvndiffusion mvndiode mvndiodec mvnntransistor mvntransistor,nwell rnwell]" + spacing *psd allnwell 120 touching_illegal "P-Ohmic spacing to N-well < %d (DF.5) [erase psubstratepcontact psubstratepdiff,nwell rnwell]" + spacing *mvpsd allnwell 160 touching_illegal "P-Ohmic spacing to N-well < %d (DF.5) [erase mvpsubstratepcontact mvpsubstratepdiff,nwell rnwell]" + surround *nsd allnwell 120 absence_illegal "N-well overlap of N-Ohmic < %d (DF.4a) [erase nsubstratencontact nsubstratendiff,nwell rnwell]" + surround *mvnsd allnwell 160 absence_illegal "N-well overlap of N-Ohmic < %d (DF.4a) [erase mvnsubstratencontact mvnsubstratendiff,nwell rnwell]" + surround *pdiff,*pdiode,pfet allnwell 430 absence_illegal "N-well overlap of P-Diffusion < %d (DF.7) [erase pdcontact pdiffusion pdiode pdiodec ptransistor,nwell rnwell]" + surround *mvpdiff,*mvpdiode,mvpfet allnwell 600 absence_illegal "N-well overlap of P-Diffusion < %d (DF.7) [erase mvpdcontact mvpdiffusion mvpdiode mvpdiodec mvptransistor,nwell rnwell]" + surround *psd pwell 120 absence_ok "P-field overlap of P-Ohmic < %d (DF.5) [erase psubstratepcontact psubstratepdiff,pwell]" + surround *mvpsd pwell 160 absence_ok "MV P-field overlap of MV P-Ohmic < %d (DF.5) [erase mvpsubstratepcontact mvpsubstratepdiff,pwell]" + + # NAT requires additional spacing rules + spacing *nndiode,*mvnndiode *psd,*mvpsd 610 touching_illegal "NAT Diffusion spacing to TAP diffusion < %d (NAT.5 + NAT.6) [erase mvnndiode mvnndiodec nndiode nndiodec,mvpsubstratepcontact mvpsubstratepdiff psubstratepcontact psubstratepdiff]" + +#----------------------------- +# POLY +#----------------------------- + + # ORIGINAL RULE: width allpoly 180 "Poly width < %d (PL.1)" + width allpoly 180 "Poly width < %d (PL.1) [paint mvnhighres,mvnntransistor,mvntransistor,mvptransistor,mvvaractor,nhighres,nntransistor,npolyres,npolysilicide,ntransistor,polycontact,polysilicon,ppolyres,ppolysilicide,ptransistor,varactor]" + spacing allpoly allpoly 240 touching_ok "Poly spacing < %d (PL.3a) [erase mvnhighres mvnntransistor mvntransistor mvptransistor mvvaractor nhighres nntransistor npolyres npolysilicide ntransistor polycontact polysilicon ppolyres ppolysilicide ptransistor varactor]" + spacing allpolynonfet alldifflvnonfet 100 corner_ok allfets \ + "Poly spacing to diffusion < %d (PL.5a)" + spacing allpolynonfet alldiffmvnonfet 300 corner_ok allfets \ + "Poly spacing to MV diffusion < %d (PL.5a) + overhang *ndiff,rndiff nfet,nnfet 230 "N-Diffusion overhang of nmos < %d (DF.6)" + overhang *mvndiff,mvrndiff mvnfet,mvnnfet 230 \ + "N-Diffusion overhang of nmos < %d (DF.6)" + overhang *pdiff,rpdiff pfet 230 "P-Diffusion overhang of pmos < %d (DF.6)" + overhang *mvpdiff,mvrpdiff mvpfet 230 "P-Diffusion overhang of pmos < %d (DF.6)" + overhang *poly allfetsnonnat 220 "Poly overhang of transistor < %d (PL.4)" + overhang *poly nnfet,mvnnfet 350 "Poly overhang of NAT transistor < %d (NAT.6)" + + angles allfets 45-only "Only 45 degrees allowed on transistors (PL.6)" + +#----------------------------------------------------------------------------- +# SBLK - more rules to do here (note PRES refers only to unsalicided resistor) +#----------------------------------------------------------------------------- + + spacing allpolysblkres allpolysblkres 250 touching_ok \ + "Poly resistor spacing < %d (PRES.2) + + spacing allpolysblkres allpolynonres 450 touching_ok "Poly resistor spacing to unrelated poly < %d (PRES.4) [erase mvnhighres nhighres npolyres ppolyres,mvnntransistor mvntransistor mvptransistor mvvaractor nntransistor ntransistor polycontact polysilicon ptransistor varactor]" + spacing allpolysblkres allactive,allactiveres 440 touching_illegal "Poly resistor spacing to diffusion < %d (PRES.3) [erase mvnhighres nhighres npolyres ppolyres,mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnndiode mvnndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor mvvaractor ndcontact ndiffres ndiffusion ndiode ndiodec nndiode nndiodec nntransistor nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec psubstratepcontact psubstratepdiff ptransistor varactor]" + + spacing allactiveres allactiveres 400 touching_ok \ + "Diffusion resistor spacing < %d (NDRES.2) + + spacing allactiveres allactive 450 touching_ok "Diffusion resistor spacing to unrelated diffusion < %d (NDRES.3) [erase mvndiffres mvpdiffres ndiffres pdiffres,mvndcontact mvndiffusion mvndiode mvndiodec mvnndiode mvnndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor mvvaractor ndcontact ndiffusion ndiode ndiodec nndiode nndiodec nntransistor nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffusion pdiode pdiodec psubstratepcontact psubstratepdiff ptransistor varactor]" + spacing allactiveres allpoly 450 touching_ok "Diffusion resistor spacing to unrelated poly < %d (NDRES.4) [erase mvndiffres mvpdiffres ndiffres pdiffres,mvnhighres mvnntransistor mvntransistor mvptransistor mvvaractor nhighres nntransistor npolyres npolysilicide ntransistor polycontact polysilicon ppolyres ppolysilicide ptransistor varactor]" + +#----------------------------- +# CONT +#----------------------------- +# Drawn contact includes 5nm metal1 surround + width (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 230 \ + "Diffusion contact width < %d (CO.1 + 2 * CO.6)" + spacing (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 \ + (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 240 \ + touching_ok "Diffusion contact spacing < %d (CO.2a - CO.6)" + surround (ndc,nsc,pdc,psc,ndic,pdic,pc)/m1 *m1 55 directional "Metal1 overlap of contact < %d in one direction (CO.6) [erase 1 1/m1 ndiodec nsubstratencontact pdcontact pdiodec psubstratepcontact,m2contact metal1 mvndcontact mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec nndiodec nsubstratencontact padl pdcontact pdiodec polycontact psubstratepcontact]" + surround ndc/a *ndiff 65 absence_illegal "N-Diffusion overlap of contact < %d (CO.4) [erase ndcontact/a,ndcontact ndiffusion]" + surround nsc/a *nsd 65 absence_illegal "N-Diffusion overlap of contact < %d (CO.4) [erase nsubstratencontact/a,nsubstratencontact nsubstratendiff]" + surround pdc/a *pdiff 65 absence_illegal "P-Diffusion overlap of contact < %d (CO.4) [erase pdcontact/a,pdcontact pdiffusion]" + surround psc/a *psd 65 absence_illegal "P-Diffusion overlap of contact < %d (CO.4) [erase psubstratepcontact/a,psubstratepcontact psubstratepdiff]" + surround ndic/a *ndiode 65 absence_illegal "N-Diffusion overlap of contact < %d (CO.4) [erase ndiodec/a,ndiode ndiodec]" + surround pdic/a *pdiode 65 absence_illegal "P-Diffusion overlap of contact < %d (CO.4) [erase pdiodec/a,pdiode pdiodec]" + surround pc/a *poly 65 absence_illegal "Poly overlap of contact < %d (CO.3) [erase polycontact/a,polycontact polysilicon]" + + width (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 230 \ + "MV Diffusion contact width < %d (CO.1 + 2 * CO.6)" + spacing (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 \ + (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 240 touching_ok \ + "Diffusion contact spacing < %d (CO.2a - CO.6)" + surround (mvndc,mvnsc,mvpdc,mvpsc,mvndic,mvnndic,mvpdic)/m1 *m1 55 directional "Metal1 overlap of contact < %d in one direction (CO.6) [erase 1 1/m1 mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpsubstratepcontact,m2contact metal1 mvndcontact mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec nndiodec nsubstratencontact padl pdcontact pdiodec polycontact psubstratepcontact]" + surround mvndc/a *mvndiff 65 absence_illegal "MV N-Diffusion overlap of contact < %d (CO.4) [erase mvndcontact/a,mvndcontact mvndiffusion]" + surround mvnsc/a *mvnsd 65 absence_illegal "MV N-Diffusion overlap of contact < %d (CO.4) [erase mvnsubstratencontact/a,mvnsubstratencontact mvnsubstratendiff]" + surround mvpdc/a *mvpdiff 65 absence_illegal "MV P-Diffusion overlap of contact < %d (CO.4) [erase mvpdcontact/a,mvpdcontact mvpdiffusion]" + surround mvpsc/a *mvpsd 65 absence_illegal "MV P-Diffusion overlap of contact < %d (CO.4) [erase mvpsubstratepcontact/a,mvpsubstratepcontact mvpsubstratepdiff]" + surround mvndic/a *mvndiode 65 absence_illegal "MV N-Diffusion overlap of contact < %d (CO.4) [erase mvndiodec/a,mvndiode mvndiodec]" + surround mvnndic/a *mvnndiode 65 absence_illegal "MV NAT N-Diffusion overlap of contact < %d (CO.4) [erase mvnndiodec/a,mvnndiode mvnndiodec]" + surround mvpdic/a *mvpdiode 65 absence_illegal "MV P-Diffusion overlap of contact < %d (CO.4) [erase mvpdiodec/a,mvpdiode mvpdiodec]" + + spacing allpdiffcont allndiffcont 240 touching_illegal "Diffusion contact spacing < %d (CO.2a - CO.6) [erase mvpdcontact mvpdiodec mvpsubstratepcontact pdcontact pdiodec psubstratepcontact,mvndcontact mvndiodec mvnndiodec mvnsubstratencontact ndcontact ndiodec nndiodec nsubstratencontact]" + spacing allndiffcont allndiffcont 240 touching_ok "Diffusion contact spacing < %d (CO.2a - CO.6) [erase mvndcontact mvndiodec mvnndiodec mvnsubstratencontact ndcontact ndiodec nndiodec nsubstratencontact]" + spacing allpdiffcont allpdiffcont 240 touching_ok "Diffusion contact spacing < %d (CO.2a - CO.6) [erase mvpdcontact mvpdiodec mvpsubstratepcontact pdcontact pdiodec psubstratepcontact]" + spacing pc pc 240 touching_ok "Poly contact spacing < %d (CO.2a - CO.6) [erase polycontact]" + spacing pc alldiff 165 touching_illegal "Poly contact spacing to diffusion < %d (CO.8 - CO.6) [erase polycontact,mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnndiode mvnndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor mvvaractor ndcontact ndiffres ndiffusion ndiode ndiodec nndiode nndiodec nntransistor nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec psubstratepcontact psubstratepdiff ptransistor]" + spacing allpdiffcont,allndiffcont allpoly 145 touching_illegal "Diffusion contact spacing to poly < %d (CO.7 - CO.6) [erase mvndcontact mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec nndiodec nsubstratencontact pdcontact pdiodec psubstratepcontact,mvnhighres mvnntransistor mvntransistor mvptransistor mvvaractor nhighres nntransistor npolyres npolysilicide ntransistor polycontact polysilicon ppolyres ppolysilicide ptransistor varactor]" + + exact_overlap (ndc,pdc,psc,nsc,pc,ndic,pdic)/a + exact_overlap (mvndc,mvpdc,mvpsc,mvnsc,mvndic,mvnndic,mvpdic)/a + +variants * + +#----------------------------- +# METAL 1 +#----------------------------- + + # ORIGINAL RULE: width *m1,rm1 230 "Metal1 width < %d (M1.1)" + width *m1,rm1 230 "Metal1 width < %d (M1.1) [paint m2contact,metal1,mvndcontact,mvndiodec,mvnndiodec,mvnsubstratencontact,mvpdcontact,mvpdiodec,mvpsubstratepcontact,ndcontact,ndiodec,nndiodec,nsubstratencontact,padl,pdcontact,pdiodec,polycontact,psubstratepcontact,rmetal1]" + spacing allm1,obsm1 allm1,obsm1 230 touching_ok "Metal1 spacing < %d (M1.2a) [erase m2contact metal1 mvndcontact mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec nndiodec nsubstratencontact obsm1 padl pdcontact pdiodec polycontact psubstratepcontact rmetal1]" + area allm1,obsm1 144400 230 "Metal1 minimum area < %a (M1.3)" + +variants (fast),(full) + widespacing allm1,obsm1 10000 allm1,obsm1 300 touching_ok \ + "Metal1 > 10um spacing to unrelated m1 < %d (M1.2b)" + +variants * + +#-------------------------------------------------- +# VIA 1 +#-------------------------------------------------- + + # ORIGINAL RULE: width v1/m1 260 "Via1 width < %d (V1.1)" + width v1/m1 260 "Via1 width < %d (V1.1) [paint m2contact/m1]" + spacing v1 v1 260 touching_ok "Via1 spacing < %d (V1.2a) [erase m2contact]" + surround v1/m1 *m1 60 directional "Metal1 overlap of Via1 < %d in one direction (V1.3) [erase m2contact/m1,m2contact metal1 mvndcontact mvndiodec mvnndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec nndiodec nsubstratencontact padl pdcontact pdiodec polycontact psubstratepcontact]" + surround v1/m2 *m2 10 absence_illegal "Metal2 overlap of Via1 < %d (V1.4) [erase m2contact/m2,m2contact m3contact metal2 padl]" + surround v1/m2 *m2 60 directional "Metal2 overlap of Via1 < %d in one direction (V1.4i) [erase m2contact/m2,m2contact m3contact metal2 padl]" + exact_overlap v1/m2 + +#----------------------------- +# METAL 2 +#----------------------------- + + # ORIGINAL RULE: width *m2,rm2 280 "Metal2 width < %d (M2.1)" + width *m2,rm2 280 "Metal2 width < %d (M2.1) [paint m2contact,m3contact,metal2,padl,rmetal2]" + spacing allm2,obsm2 allm2,obsm2 280 touching_ok "Metal2 spacing < %d (M2.2a) [erase m2contact m3contact metal2 obsm2 padl rmetal2]" + #area allm2,obsm2 144400 280 "Metal2 minimum area < %a (M2.3)" THIS RULE IS DISABLED FOR STANDARD CELLS SINCE THEY PROVIDE THE PADS ON LAYER METAL2 BUT THERE IS NOT ENOUGH METAL THERE TO FULFILL THE RULE + +variants (fast),(full) + widespacing allm2,obsm2 10000 allm2,obsm2 300 touching_ok \ + "Metal2 > 10um spacing to unrelated m2 < %d (M2.2b)" + +variants * + +#-------------------------------------------------- +# VIA 2 +#-------------------------------------------------- + + # ORIGINAL RULE: width v2/m2 280 "Via2 width < %d (V2.1 + 2 * V2.3)" + width v2/m2 280 "Via2 width < %d (V2.1 + 2 * V2.3) [paint m3contact/m2]" + spacing v2 v2 240 touching_ok "Via2 spacing < %d (V2.2a - 2 * V2.3) [erase m3contact]" + surround v2/m2 *m2 50 directional "Metal2 overlap of Via2 < %d in one direction (V2.3i - V2.3) [erase m3contact/m2,m2contact m3contact metal2 padl]" + + exact_overlap v2/m3 + +#----------------------------- +# METAL 3 +#----------------------------- + + surround v2/m3 *m3 50 directional "Metal3 overlap of Via2 < %d in one direction (V2.4i - V2.4) [erase m3contact/m3,m3contact metal3 padl via3]" + + # ORIGINAL RULE: width *m3,rm3 280 "Metal3 width < %d (M3.1)" + width *m3,rm3 280 "Metal3 width < %d (M3.1) [paint m3contact,metal3,padl,rmetal3,via3]" + spacing allm3,obsm3 allm3,obsm3 280 touching_ok "Metal3 spacing < %d (M3.2a) [erase m3contact metal3 obsm3 padl rmetal3 via3]" + area allm3,obsm3 144400 280 "Metal3 minimum area < %a (M3.3)" + +variants (fast),(full) + widespacing allm3,obsm3 10000 allm3,obsm3 300 touching_ok \ + "Metal3 > %c spacing to unrelated m3 < %d (M3.2b)" + +variants * + +#-------------------------------------------------------------- +# VIA 3 - Requires METALS4, 1, or METALS6 Module +#-------------------------------------------------------------- + + # ORIGINAL RULE: width v3/m3 280 "Via3 width < %d (V3.1 + 2 * V3.4)" + width v3/m3 280 "Via3 width < %d (V3.1 + 2 * V3.4) [paint via3/m3]" + spacing v3 v3 240 touching_ok "Via3 spacing < %d (V3.2a - 2 * V3.4) [erase via3]" + surround v3/m3 *m3 50 directional "Metal3 overlap of Via3 < %d in one direction (V3.3i - V3.3) [erase via3/m3,m3contact metal3 padl via3]" + + exact_overlap v3/m4 + +#----------------------------- +# METAL 4 - METALS4 Module +#----------------------------- + + surround v3/m4 *m4 50 directional "Metal4 overlap of Via3 < %d in one direction (V3.4i - V3.4) [erase via3/m4,metal4 padl via3 via4]" + + # ORIGINAL RULE: width *m4,rm4 200 "Metal4 width < %d (M4.1)" + width *m4,rm4 200 "Metal4 width < %d (M4.1) [paint metal4,padl,rmetal4,via3,via4]" + spacing allm4,obsm4 allm4,obsm4 210 touching_ok "Metal4 spacing < %d (M4.2a) [erase metal4 mimcap mimcapcontact obsm4 padl rmetal4 via3 via4]" + area allm4,obsm4 144000 200 "Metal4 minimum area < %a (M4.3)" + +variants (fast),(full) + widespacing allm4,obsm4 10000 allm4,obsm4 300 touching_ok \ + "Metal4 > %c spacing to unrelated m4 < %d (M4.2b)" + +variants * + +#------------------------------------------------------ +# VIA 4 - Requires 1 Module +#------------------------------------------------------ + + # ORIGINAL RULE: width v4/m4 280 "Via4 width < %d (V4.1 + 2 * V4.4)" + width v4/m4 280 "Via4 width < %d (V4.1 + 2 * V4.4) [paint via4/m4]" + spacing v4 v4 240 touching_ok "Via4 spacing < %d (V4.2a - 2 * V4.4) [erase via4]" + exact_overlap v4/m5 + +#----------------------------- +# METALS 5 - 1 Module +#----------------------------- + + # Metal 5 is the top metal + surround v4/m4 *m4 50 directional "Metal4 overlap of Via4 < %d in one direction (V4.3i - V4.3) [erase via4/m4,metal4 padl via3 via4]" + surround v4/m5 *m5 50 directional "Metal5 overlap of Via4 < %d in one direction (V4.4i - V4.4) [erase via4/m5,metal5 mimcapcontact padl via4]" + + # ORIGINAL RULE: width *m5,rm5 360 "Metal5 width < %d (MT.1)" + width *m5,rm5 360 "Metal5 width < %d (MT.1) [paint metal5,mimcapcontact,padl,rmetal5,via4]" + spacing allm5,obsm5 allm5,obsm5 380 touching_ok "Metal5 spacing < %d (MT.2a) [erase metal5 mimcapcontact obsm5 padl rmetal5 via4]" + area allm5,obsm5 562500 360 "Metal5 minimum area < %a (MT.4)" + +variants (fast),(full) + widespacing allm5,obsm5 10000 allm5,obsm5 500 touching_ok \ + "Metal5 > %c spacing to unrelated m5 < %d (MT.2b)" + +variants * + + +#-------------------------------------------------- +# NMOS, PMOS +#-------------------------------------------------- + + # NOTE: The layer width can be used for the smaller of + # (minimum length, minimum width). However, for many + # devices, minimum width is less than minimum length. + + extend nnfet *ndiff 400 exclusive "nn Transistor length < %d (DF.2c)" + + extend mvnnfet *mvndiff 1200 exclusive "MV nn Transistor length < %d (NAT.4)" + # ORIGINAL RULE: width mvnnfet 400 "MV nn Transistor width < %d (DF.2c)" + width mvnnfet 400 "MV nn Transistor width < %d (DF.2c) [paint mvnntransistor]" + + extend pfet *pdiff 280 exclusive "Transistor length < %d (PL.1a)" + extend nfet *ndiff 280 exclusive "Transistor length < %d (PL.1a)" + width pfet 300 angles "Bent Transistor length < %d (PL.7)" + width nfet 300 angles "Bent Transistor length < %d (PL.7)" + + extend mvpfet *mvpdiff 500 exclusive "MV Transistor length < %d (PL.1a)" + extend mvnfet *mvndiff 600 exclusive "MV Transistor length < %d (PL.1a)" + width mvpfet 700 angles "Bent MV Transistor length < %d (PL.7)" + width mvnfet 700 angles "Bent MV Transistor length < %d (PL.7)" + + # NOTE: Use edge4way to deal with butted junctions + # spacing *nsd,*mvnsd pfet,mvnnfet,mvpfet 330 touching_illegal \ + # "n-ohmic spacing to PMOS gate < %d (NP.4b)" + # spacing *psd,*mvpsd nfet,nnfet,mvnfet 330 touching_illegal \ + # "p-ohmic spacing to NMOS gate < %d (NP.4c)" + + edge4way pfet,mvnnfet,mvpfet *poly/a 330 ~(*nsd,*mvnsd)/a (*pdiff,*mvpdiff)/a 300 \ + "n-ohmic spacing to PMOS gate < %d (NP.4b + PP.4c)" + edge4way nfet,nnfet,mvnfet *poly/a 330 ~(*psd,*mvpsd)/a (*ndiff,*mvndiff)/a 300 \ + "p-ohmic spacing to NMOS gate < %d (PP.4b + NP.4c)" + + # Butting junction rules (flag p/nsd distance to butting junction < 0.03um) + edge4way (*psd)/a ~(*ndiff,*psd)/a 330 ~(*ndiff)/a (*ndiff)/a 30 \ + "N-Diffusion to P-tap spacing < %d across butted junction (PP.4b + NP.4c)" + edge4way (*ndiff)/a ~(*ndiff,*psd)/a 330 ~(*psd)/a (*psd)/a 30 \ + "N-Diffusion to P-tap spacing < %d across butted junction (PP.4b + NP.4c)" + edge4way (*nsd)/a ~(*pdiff,*nsd)/a 330 ~(*pdiff)/a (*pdiff)/a 30 \ + "P-Diffusion to N-tap spacing < %d across butted junction (NP.4b + PP.4c)" + edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 330 ~(*nsd)/a (*nsd)/a 30 \ + "P-Diffusion to N-tap spacing < %d across butted junction (NP.4b + PP.4c)" + + edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 330 ~(*mvndiff)/a (*mvndiff)/a 30 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (PP.4b + NP.4c)" + edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 330 ~(*mvpsd)/a (*mvpsd)/a 30 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction (PP.4b + NP.4c)" + edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 330 ~(*mvpdiff)/a (*mvpdiff)/a 30 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (NP.4b + PP.4c)" + edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 330 ~(*mvnsd)/a (*mvnsd)/a 30 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction (NP.4b + PP.4c)" + +#-------------------------------------------------- +# RPP,RNP +#-------------------------------------------------- + # ORIGINAL RULE: width rpp 800 "ppolyres minimum width < %d (PRES.1)" + width rpp 800 "ppolyres minimum width < %d (PRES.1) [paint ppolyres]" + # ORIGINAL RULE: width rnp 800 "npolyres minimum width < %d (NRES.1)" + width rnp 800 "npolyres minimum width < %d (NRES.1) [paint npolyres]" + spacing rpp rpp 400 touching_ok "ppolyres minimum spacing < %d (PRES.2) [erase ppolyres]" + spacing rnp rnp 400 touching_ok "npolyres minimum spacing < %d (NRES.2) [erase npolyres]" + + spacing rpp pc 215 touching_illegal "rpp spacing to Cont < %d (PRES.8 - CO.6) [erase ppolyres,polycontact]" + spacing rnp pc 215 touching_illegal "rnp spacing to Cont < %d (NRES.8 - CO.6) [erase npolyres,polycontact]" + +#-------------------------------------------------- +# HIRES +#-------------------------------------------------- + # ORIGINAL RULE: width hires,mvhires 1000 "hires poly minimum width < %d (HRES.3)" + width hires,mvhires 1000 "hires poly minimum width < %d (HRES.3) [paint mvnhighres,nhighres]" + spacing hires,mvhires hires,mvhires 400 touching_ok "hires poly minimum spacing < %d (HRES.2) [erase mvnhighres nhighres]" + + variants (full) + cifmaxwidth res_diff_space 0 bend_illegal \ + "High value resistor spacing to diffusion < 0.7um (HRES.5 + HRES.4)" + cifmaxwidth res_poly_space 0 bend_illegal \ + "High value resistor spacing to poly < 0.7um (HRES.6 + HRES.4)" + + cifmaxwidth res_cont_space_min 0 bend_illegal \ + "Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)" + cifmaxwidth res_no_cont 0 bend_illegal \ + "Unsalicided resistor spacing to poly contact must be 0.22um (PRES/LRES/HRES.7)" + variants * + +#-------------------------------------------------- +# RDN,RDP (Diffusion resistors) +#-------------------------------------------------- + # ORIGINAL RULE: width rdn 300 "N-diffusion resistor width < %d (DF.1b)" + width rdn 300 "N-diffusion resistor width < %d (DF.1b) [paint ndiffres]" + # ORIGINAL RULE: width rdp 300 "P-diffusion resistor width < %d (DF.1b)" + width rdp 300 "P-diffusion resistor width < %d (DF.1b) [paint pdiffres]" + +#------------------------------------ +# MOS Varactor device rules +#------------------------------------ + + overhang *nsd var 320 \ + "N-Ohmic overhang of Varactor < %d (FIXME)" + + overhang *mvnsd mvvar 320 \ + "N-Ohmic overhang of Varactor < %d (FIXME)" + + width var,mvvar 1000 \ + "Varactor length and width < %d (DF.1c)" + +#------------------------------------------------- +# CAPM (FuseTop) +#------------------------------------------------- + + # ORIGINAL RULE: width *mimcap 5000 "MiM cap top plate width < %d (1TM.8a)" + width *mimcap 5000 "MiM cap top plate width < %d (1TM.8a) [paint mimcap,mimcapcontact]" + spacing *mimcap *mimcap 600 touching_ok "MiM cap top plate spacing < %d (1TM.6) [erase mimcap mimcapcontact]" + surround mimcc mimcap 390 absence_illegal "MiM cap must surround MiM cap contact by %d (1TM.4-VT.4) [erase mimcapcontact,mimcap]" + spacing pad *mimcap 50 touching_illegal "MiM cap cannot overlap pad (11M.X) [erase padl,mimcap mimcapcontact]" + spacing mimcc mimcc 480 touching_ok "MiM cap contact spacing < %d (1TM.9 - VT.3) [erase mimcapcontact]" + + spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (1TM.10) [erase via3,mimcap mimcapcontact]" + spacing *mimcap *m4,rm4 1200 touching_ok "MiM cap to Metal4 spacing < %d (1TM.1) [erase mimcap mimcapcontact,metal4 padl rmetal4 via3 via4]" + spacing *mimcap via4/m5 390 touching_illegal "MiM cap spacing to via4 < %d (1TM.5) [erase mimcap mimcapcontact,via4/m5]" + surround *mimcap m4 600 absence_illegal "Bottom plate overlap of MiM cap < %d (1TM.3) [erase mimcap mimcapcontact,metal4]" + # ORIGINAL RULE: width mimcapc/m5 280 "MiM Contact width < %d (VT.1+VT.3)" + width mimcapc/m5 280 "MiM Contact width < %d (VT.1+VT.3) [paint mimcapcontact/m5]" + + variants (full) + cifmaxwidth mim_bottom_plate_space 0 bend_illegal \ + "MiM bottom plate to unrelated metal < 1.2um (1TM.1)" + cifmaxwidth mim_bot_cont_surround 0 bend_illegal \ + "MiM bottom plate surrounds contact < 0.4um (1TM.2)" + +#---------------------------- +# End DRC style +#---------------------------- + + style empty + scalefactor 50 + stepsize 2000 + +end + +#---------------------------- +# LEF format definitions +#---------------------------- + +lef + + routing m1 Metal1 METAL1 MET1 m1 met1 metal1 + routing m2 Metal2 METAL2 MET2 m2 met2 metal2 + routing m3 Metal3 METAL3 MET3 m3 met3 metal3 + routing m4 Metal4 METAL4 MET4 m4 met4 metal4 + routing m5 Metal5 METAL5 MET5 m5 met5 metal5 + + cut m2c Via1 VIA1 via1 cont2 via12 + cut m3c Via2 VIA2 via2 cont3 via23 + cut via3 Via3 VIA3 via3 cont4 via34 + cut via4 Via4 VIA4 via4 cont5 via45 + + obs obsm1 Metal1 + obs obsm2 Metal2 + obs obsm3 Metal3 + obs obsm4 Metal4 + obs obsm5 Metal5 + + obs obsv1 Via1 + obs obsv2 Via2 + +end + +#----------------------------------------------------- +# Device and Parasitic extraction +#----------------------------------------------------- + +extract + style ngspice variants (),(hrhc),(lrhc),(hrlc),(lrlc) + cscale 1 + lambda 5.0 + units microns + step 7 + sidehalo 8 + fringeshieldhalo 8 + + planeorder dwell 0 + planeorder well 1 + planeorder active 2 + planeorder metal1 3 + planeorder metal2 4 + planeorder metal3 5 + planeorder metal4 6 + planeorder metal5 7 + planeorder block 8 + planeorder comment 9 + + height dnwell -0.1 0.0 + height nwell,pwell 0.0 0.0145 + height alldiff 0.0145 0.30 + height allpoly 0.32 0.2 + height alldiffcont 0.3145 0.9155 + height pc 0.52 0.71 + height allm1 1.23 0.55 + height via 1.78 0.60 + height allm2 2.38 0.55 + height via2 2.93 0.60 + height allm3 3.53 0.55 + height via3 4.08 0.60 + height allm4 4.68 0.55 + height via4 5.23 0.60 + height allm5 5.83 1.0025 + + # Antenna check parameters + # (to be completed) + model partial + antenna poly sidewall 200 none + antenna allcont surface 10 none + antenna via1 surface 20 none + antenna via2 surface 20 none + antenna via3 surface 20 none + antenna via4 surface 20 none + antenna mimcc surface 20 none + antenna m1,m2 sidewall 400 none + antenna m3 sidewall 400 none + antenna m4 sidewall 400 none + antenna m5 sidewall 400 none + + tiedown alldiffnonfet + + substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell,isosub + +# Layer resistance + +variants () + +# Resistances are in milliohms per square +# Optional 3rd argument is the corner adjustment fraction +# See document 180MCU_YI-141-EP059-01_10.pdf + + resist (nwell,dnwell)/well 1000000 + resist (pwell)/well 3250000 + + resist (*ndiff,nsd)/active 6300 + resist (*pdiff,*psd)/active 7000 + resist (*mvndiff,mvnsd)/active 6300 + resist (*mvpdiff,*mvpsd)/active 7000 + + resist (allpolynonres)/active 7300 + + resist (rnw)/well 1000000 0.5 + resist (rnd)/active 60000 0.5 + resist (rpd)/active 185000 0.5 + resist (mvrnd)/active 60000 0.5 + resist (mvrpd)/active 185000 0.5 + resist (rnds)/active 6300 0.5 + resist (rpds)/active 7000 0.5 + resist (mvrnds)/active 6300 0.5 + resist (mvrpds)/active 7000 0.5 + resist (rnps)/active 6800 0.5 + resist (rpps)/active 7300 0.5 + resist (rpp)/active 350000 0.5 + resist (rnp)/active 310000 0.5 + resist (hires,mvhires)/active 1000000 0.5 + + resist (allm1)/metal1 90 + resist (allm2)/metal2 90 + resist (allm3)/metal3 90 + + resist (allm4)/metal4 90 + + resist (allm5)/metal5 60 + + + contact ndc,nsc 6300 + contact pdc,psc 5200 + contact mvndc,mvnsc 6300 + contact mvpdc,mvpsc 5200 + contact pc 8000 + contact m2c 4500 + contact m3c 4500 + contact via3 4500 + contact via4 4500 + contact mimcc 4500 + +variants (hrhc),(hrlc) + + # High-end corner resistances (milliohms per square) + + resist (nwell,dnwell)/well 1200000 + resist (pwell)/well 3250000 + + resist (*ndiff,nsd)/active 15000 + resist (*pdiff,*psd)/active 15000 + resist (*mvndiff,mvnsd)/active 15000 + resist (*mvpdiff,*mvpsd)/active 15000 + + resist (allpolynonres)/active 15000 + + resist (rnw)/well 1200000 0.5 + resist (rnd)/active 75000 0.5 + resist (rpd)/active 225000 0.5 + resist (mvrnd)/active 75000 0.5 + resist (mvrpd)/active 225000 0.5 + resist (rnds)/active 15000 0.5 + resist (rpds)/active 15000 0.5 + resist (mvrnds)/active 15000 0.5 + resist (mvrpds)/active 15000 0.5 + resist (rnps)/active 15000 0.5 + resist (rpps)/active 15000 0.5 + resist (rpp)/active 420000 0.5 + resist (rnp)/active 370000 0.5 + resist (hires,mvhires)/active 1200000 0.5 + + resist (allm1)/metal1 104 + resist (allm2)/metal2 104 + resist (allm3)/metal3 104 + + resist (allm4)/metal4 104 + + resist (allm5)/metal5 70 + + + contact ndc,nsc 15000 + contact pdc,psc 15000 + contact mvndc,mvnsc 15000 + contact mvpdc,mvpsc 15000 + contact pc 15000 + contact m2c 15000 + contact m3c 15000 + contact via3 15000 + contact via4 15000 + contact mimcc 15000 + +variants (lrhc),(lrlc) + + # Low-end corner resistances (milliohms per square) + + resist (nwell,dnwell)/well 800000 + resist (pwell)/well 3250000 + + resist (*ndiff,nsd)/active 1000 + resist (*pdiff,*psd)/active 1000 + resist (*mvndiff,mvnsd)/active 1000 + resist (*mvpdiff,*mvpsd)/active 1000 + + resist (allpolynonres)/active 1000 + + resist (rnw)/well 8000000 0.5 + resist (rnd)/active 45000 0.5 + resist (rpd)/active 145000 0.5 + resist (mvrnd)/active 45000 0.5 + resist (mvrpd)/active 145000 0.5 + resist (rnds)/active 1000 0.5 + resist (rpds)/active 1000 0.5 + resist (mvrnds)/active 1000 0.5 + resist (mvrpds)/active 1000 0.5 + resist (rnps)/active 1000 0.5 + resist (rpps)/active 1000 0.5 + resist (rpp)/active 280000 0.5 + resist (rnp)/active 250000 0.5 + resist (hires,mvhires)/active 800000 0.5 + + resist (allm1)/metal1 76 + resist (allm2)/metal2 76 + resist (allm3)/metal3 76 + + resist (allm4)/metal4 76 + + resist (allm5)/metal5 50 + + + contact ndc,nsc 0 + contact pdc,psc 0 + contact mvndc,mvnsc 0 + contact mvpdc,mvpsc 0 + contact pc 0 + contact m2c 0 + contact m3c 0 + contact via3 0 + contact via4 0 + contact mimcc 0 + +variants * + + # These types should not be considered as electrical nodes + resist comment None + +#------------------------------------------------------------------------- +# Parasitic capacitance values: +#------------------------------------------------------------------------- +# This uses the new "default" definitions that determine the intervening +# planes from the planeorder stack, take care of the reflexive sideoverlap +# definitions, and generally clean up the section and make it more readable. +# +# Also uses "units microns" statement, so all parasitic capacitance values +# are taken directly from the source document PDS_035_03, in units of +# aF/um^2 for area caps and aF/um for perimeter and sidewall caps. +#------------------------------------------------------------------------- +# Remember that device capacitances to substrate are taken care of by the +# models. Thus, active and poly definitions ignore all "fet" types. +# fet types are excluded when computing parasitic capacitance to +# active from layers above them because poly is a shield; fet types are +# included for parasitics from layers above to poly. Resistor types +# should be removed from all parasitic capacitance calculations, or else +# they just create floating caps. Technically, the capacitance probably +# should be split between the two terminals. Unsure of the correct model. +# Because rnw is on the well plane, "defaultareacap" does not work for +# planes above diffusion because rnw cannot be removed from types on the +# well plane. Because of this, use the normal "areacap" to specify cap +# to substrate, and "defaultoverlap" to specify cap to nwell (but not rnw). +#------------------------------------------------------------------------- + +variants () +# Nominal capacitances + +#n-well +defaultareacap nwell well 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 105 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 16.46 + defaultareacap *poly active nwell,obswell,pwell well 110.677 + defaultperimeter *poly active nwell,obswell,pwell well 51.29 + +#metal1 + defaultsidewall allm1 metal1 28.01 + defaultareacap allm1 metal1 nwell,obswell,pwell well 29.3046 + defaultperimeter allm1 metal1 nwell,obswell,pwell well 25.783 + defaultoverlap allm1 metal1 nwell well 29.3046 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 39.2181 + defaultsideoverlap allm1 metal1 allactivenonfet active 30.683 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 51.4351 + defaultsideoverlap allm1 metal1 allpolynonres active 35.602 + +#metal2 + defaultsidewall allm2 metal2 30.381 + defaultareacap allm2 metal2 nwell,obswell,pwell well 15.0162 + defaultperimeter allm2 metal2 nwell,obswell,pwell well 18.263 + defaultoverlap allm2 metal2 nwell well 15.0162 +#metal2->active + defaultoverlap allm2 metal2 allactivenonfet active 17.2506 + defaultsideoverlap allm2 metal2 allactivenonfet active 20.018 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 19.2632 + defaultsideoverlap allm2 metal2 allpolynonres active 21.531 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 59.0279 + defaultsideoverlap allm2 metal2 allm1 metal1 40.880 + +#metal3 + defaultsidewall allm3 metal3 30.774 + defaultareacap allm3 metal3 nwell,obswell,pwell well 10.0944 + defaultoverlap allm3 metal3 nwell well 10.0944 + defaultperimeter allm3 metal3 nwell,obswell,pwell well 13.52 + +#metal3->active + defaultoverlap allm3 metal3 allactive active 11.0571 + defaultsideoverlap allm3 metal3 allactive active 14.36 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 11.8507 + defaultsideoverlap allm3 metal3 allpolynonres active 15.054 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 20.2381 + defaultsideoverlap allm3 metal3 allm1 metal1 21.705 + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 59.0279 + defaultsideoverlap allm3 metal3 allm2 metal2 40.482 + +#metal4 + defaultsidewall allm4 metal4 30.994 + defaultareacap allm4 metal4 nwell,obswell,pwell well 7.6025 + defaultoverlap allm4 metal4 nwell well 7.6025 + defaultperimeter allm4 metal4 well 10.649 + +#metal4->active + defaultoverlap allm4 metal4 allactivenonfet active 8.1360 + defaultsideoverlap allm4 metal4 allactivenonfet active 11.129 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 8.5577 + defaultsideoverlap allm4 metal4 allpolynonres active 11.505 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 12.2127 + defaultsideoverlap allm4 metal4 allm1 metal1 14.829 + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 20.2381 + defaultsideoverlap allm4 metal4 allm2 metal2 21.025 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 59.0279 + defaultsideoverlap allm4 metal4 allm3 metal3 39.786 + +#metal5 + defaultsidewall allm5 metal5 54.148 + + defaultareacap allm5 metal5 nwell,obswell,pwell well 5.7979 + defaultoverlap allm5 metal5 nwell well 5.7979 + defaultperimeter allm5 metal5 well 10.850 + +#metal5->active + defaultoverlap allm5 metal5 allactivenonfet active 6.1031 + defaultsideoverlap allm5 metal5 allactivenonfet active 11.258 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 6.3374 + defaultsideoverlap allm5 metal5 allpolynonres active 11.570 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 8.1418 + defaultsideoverlap allm5 metal5 allm1 metal1 13.958 + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 11.0677 + defaultsideoverlap allm5 metal5 allm2 metal2 17.640 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 17.2765 + defaultsideoverlap allm5 metal5 allm3 metal3 24.286 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 39.3519 + defaultsideoverlap allm5 metal5 allm4 metal4 39.586 + + +#------------------------------------------------------------------------- +# Parasitic capacitance values for maximum corner +#------------------------------------------------------------------------- + +variants (hrhc),(lrhc) +# Maximum corner capacitances + +#n-well +defaultareacap nwell well 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 105 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 16.56 + defaultareacap *poly active nwell,obswell,pwell well 130.2 + defaultperimeter *poly active nwell,obswell,pwell well 54.018 + +#metal1 + defaultsidewall allm1 metal1 29.294 + defaultareacap allm1 metal1 nwell,obswell,pwell well 33.126 + defaultperimeter allm1 metal1 nwell,obswell,pwell well 25.790 + defaultoverlap allm1 metal1 nwell well 33.126 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 43.636 + defaultsideoverlap allm1 metal1 allactivenonfet active 30.445 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 60.321 + defaultsideoverlap allm1 metal1 allpolynonres active 36.440 + +#metal2 + defaultsidewall allm2 metal2 31.727 + defaultareacap allm2 metal2 nwell,obswell,pwell well 16.472 + defaultperimeter allm2 metal2 nwell,obswell,pwell well 18.124 + defaultoverlap allm2 metal2 nwell well 16.472 +#metal2->active + defaultoverlap allm2 metal2 allactivenonfet active 18.713 + defaultsideoverlap allm2 metal2 allactivenonfet active 19.744 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 21.231 + defaultsideoverlap allm2 metal2 allpolynonres active 21.467 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 73.632 + defaultsideoverlap allm2 metal2 allm1 metal1 43.788 + +#metal3 + defaultsidewall allm3 metal3 32.049 + defaultoverlap allm3 metal3 nwell well 11.910 + defaultareacap allm3 metal3 nwell,obswell,pwell well 10.961 + defaultperimeter allm3 metal3 nwell,obswell,pwell well 13.270 + +#metal3->active + defaultoverlap allm3 metal3 allactive active 11.910 + defaultsideoverlap allm3 metal3 allactive active 14.034 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 12.883 + defaultsideoverlap allm3 metal3 allpolynonres active 14.812 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 22.675 + defaultsideoverlap allm3 metal3 allm1 metal1 21.903 + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 73.632 + defaultsideoverlap allm3 metal3 allm2 metal2 43.400 + +#metal4 + defaultsidewall allm4 metal4 32.265 + defaultareacap allm4 metal4 nwell,obswell,pwell well 8.213 + defaultoverlap allm4 metal4 nwell well 8.213 + defaultperimeter allm4 metal4 well 10.397 + +#metal4->active + defaultoverlap allm4 metal4 allactivenonfet active 8.735 + defaultsideoverlap allm4 metal4 allactivenonfet active 10.831 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 9.247 + defaultsideoverlap allm4 metal4 allpolynonres active 11.247 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 13.400 + defaultsideoverlap allm4 metal4 allm1 metal1 14.625 + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 22.674 + defaultsideoverlap allm4 metal4 allm2 metal2 21.263 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 73.63 + defaultsideoverlap allm4 metal4 allm3 metal3 42.64 + +#metal5 + defaultsidewall allm5 metal5 57.012 + defaultareacap allm5 metal5 nwell,obswell,pwell well 6.241 + defaultoverlap allm5 metal5 nwell well 6.241 + defaultperimeter allm5 metal5 well 10.676 + +#metal5->active + defaultoverlap allm5 metal5 allactivenonfet active 6.537 + defaultsideoverlap allm5 metal5 allactivenonfet active 11.074 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 6.820 + defaultsideoverlap allm5 metal5 allpolynonres active 11.431 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 8.841 + defaultsideoverlap allm5 metal5 allm1 metal1 13.909 + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 12.108 + defaultsideoverlap allm5 metal5 allm2 metal2 17.722 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 19.207 + defaultsideoverlap allm5 metal5 allm3 metal3 24.724 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 46.18 + defaultsideoverlap allm5 metal5 allm4 metal4 41.628 + + +#------------------------------------------------------------------------- +# Parasitic capacitance values for minimum corner +#------------------------------------------------------------------------- + +variants (hrlc),(lrlc) +# Minimum corner capacitances + +#n-well +defaultareacap nwell well 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 105 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 16.388 + defaultareacap *poly active nwell,obswell,pwell well 96.241 + defaultperimeter *poly active nwell,obswell,pwell well 48.943 + +#metal1 + defaultsidewall allm1 metal1 26.630 + defaultareacap allm1 metal1 nwell,obswell,pwell well 26.274 + defaultperimeter allm1 metal1 nwell,obswell,pwell well 25.666 + defaultoverlap allm1 metal1 nwell well 26.274 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 35.612 + defaultsideoverlap allm1 metal1 allactivenonfet active 30.684 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 44.831 + defaultsideoverlap allm1 metal1 allpolynonres active 34.738 + +#metal2 + defaultsidewall allm2 metal2 29.023 + defaultareacap allm2 metal2 nwell,obswell,pwell well 13.797 + defaultperimeter allm2 metal2 nwell,obswell,pwell well 18.332 + defaultoverlap allm2 metal2 nwell well 13.797 +#metal2->active + defaultoverlap allm2 metal2 allactivenonfet active 16.000 + defaultsideoverlap allm2 metal2 allactivenonfet active 20.206 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 17.629 + defaultsideoverlap allm2 metal2 allpolynonres active 21.511 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 49.258 + defaultsideoverlap allm2 metal2 allm1 metal1 38.718 + +#metal3 + defaultsidewall allm3 metal3 28.809 + defaultoverlap allm3 metal3 nwell well 9.355 + defaultareacap allm3 metal3 nwell,obswell,pwell well 9.355 + defaultperimeter allm3 metal3 nwell,obswell,pwell well 13.710 + +#metal3->active + defaultoverlap allm3 metal3 allactive active 10.318 + defaultsideoverlap allm3 metal3 allactive active 14.637 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 10.972 + defaultsideoverlap allm3 metal3 allpolynonres active 15.232 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 18.275 + defaultsideoverlap allm3 metal3 allm1 metal1 21.483 + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 49.258 + defaultsideoverlap allm3 metal3 allm2 metal2 38.221 + +#metal4 + defaultsidewall allm4 metal4 29.629 + defaultareacap allm4 metal4 nwell,obswell,pwell well 7.076 + defaultoverlap allm4 metal4 nwell well 7.076 + defaultperimeter allm4 metal4 well 10.870 + +#metal4->active + defaultoverlap allm4 metal4 allactivenonfet active 7.614 + defaultsideoverlap allm4 metal4 allactivenonfet active 11.375 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 7.964 + defaultsideoverlap allm4 metal4 allpolynonres active 11.720 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 11.219 + defaultsideoverlap allm4 metal4 allm1 metal1 14.805 + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 18.275 + defaultsideoverlap allm4 metal4 allm2 metal2 20.801 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 49.258 + defaultsideoverlap allm4 metal4 allm3 metal3 37.616 + +#metal5 + defaultsidewall allm5 metal5 51.169 + defaultareacap allm5 metal5 nwell,obswell,pwell well 5.414 + defaultoverlap allm5 metal5 nwell well 5.414 + defaultperimeter allm5 metal5 well 10.992 + +#metal5->active + defaultoverlap allm5 metal5 allactivenonfet active 5.723 + defaultsideoverlap allm5 metal5 allactivenonfet active 11.430 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 5.919 + defaultsideoverlap allm5 metal5 allpolynonres active 11.703 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 7.545 + defaultsideoverlap allm5 metal5 allm1 metal1 13.985 + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 10.192 + defaultsideoverlap allm5 metal5 allm2 metal2 17.610 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 15.699 + defaultsideoverlap allm5 metal5 allm3 metal3 23.834 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 34.153 + defaultsideoverlap allm5 metal5 allm4 metal4 37.782 + + +#------------------------------------------------------------------------- + +variants * + +# Devices: +# All devices except diodes are modeled as subcircuits + +# device list: +# nmos_3p3 mosfet +# pmos_3p3 mosfet +# nmos_6p0 mosfet (thick oxide) +# pmos_6p0 mosfet (thick oxide) +# nmos_6p0_nat mosfet (native Vt) +# nmos_3p3_sab mosfet (unsalicided drain) +# pmos_3p3_sab mosfet (unsalicided drain) +# nmos_6p0_sab mosfet (unsalicided drain, thick oxide) +# pmos_6p0_sab mosfet (unsalicided drain, thick oxide) +# nmos_10p0_asym LDNMOS (extended drain) +# pmos_10p0_asym LDPMOS (extended drain) +# +# np_3p3 diode (N+/pwell) +# pn_3p3 diode (P+/nwell) +# np_6p0 diode (N+/pwell, high voltage) +# pn_6p0 diode (P+/nwell, high voltage) +# nwp_3p3 diode (nwell/pwell) +# nwp_6p0 diode (nwell/pwell, high voltage) +# dnwpw diode (pwell/dnwell) +# dnwps diode (dnwll/substrate) +# sc_diode diode (Schottky) +# +# vpnp_WxL BJT (10x10, 5x5, 0.42x10, 0.42x5 emitter sizes) +# vnpn_WxL BJT (10x10, 5x5, 0.54x16, 0.54x8, 0.54x4, 0.54x2) +# +# npolyf_u resistor (N+ poly, unsalicided) +# ppolyf_u resistor (P+ poly, unsalicided) +# ppolyf_u_1k resistor (high res resistor)* +# ppolyf_u_1k_6p0 resistor (high res resistor, high voltage)* +# nplus_u resistor (N+ diffusion, unsalicided) +# pplus_u resistor (P+ diffusion, unsalicided) +# npolyf_s resistor (N+ poly, salicided) +# ppolyf_s resistor (P+ poly, salicided) +# nplus_s resistor (N+ diffusion, salicided) +# pplus_s resistor (N+ diffusion, salicided) +# nwell resistor (N-well resistor) +# rm1 resistor (metal1) +# rm2 resistor (metal2) +# rm3 resistor (metal3) +# rm4 resistor (metal4) +# rm5 resistor (metal5) +# tm6k resistor (top metal, 0.6um thick (standard))** +# tm9k resistor (top metal, 0.9um thick) +# tm11k resistor (top metal, 1.1um thick) +# tm30k resistor (top metal, 3.0um thick) +# +# nmoscap_3p3 mosfet (source-drain tied) +# pmoscap_3p3 mosfet (source-drain tied) +# nmoscap_6p0 mosfet (source-drain tied, high voltage) +# pmoscap_6p0 mosfet (source-drain tied, high voltage) +# nmoscap_3p3_b mosfet (n-varactor) +# pmoscap_3p3_b mosfet (p-varactor) +# nmoscap_6p0_b mosfet (n-varactor, high voltage) +# pmoscap_6p0_b mosfet (p-varactor, high voltage) +# +# mim_2p0fF capacitor (MiM)* + +# +# *Note that there are multiple mutually exclusive process options for the +# high sheet rho resistor and MiM capacitor. This tech file assumes the +# options 1kOhm/sq for the resistor and 2fF/um for the MiM capacitor. +# +# **The top metal may be any of metal3 to metaltp, depending on the stackup + + device msubcircuit pmos_3p3 pfet pdiff,pdc pdiff,pdc allnwell error l=l w=w + device msubcircuit nmos_3p3 nfet ndiff,ndc ndiff,ndc allpsub error l=l w=w + device msubcircuit pmos_6p0 mvpfet mvpdiff,mvpdc mvpdiff,mvpdc allnwell error l=l w=w + device msubcircuit nmos_6p0 mvnfet mvndiff,mvndc mvndiff,mvndc allpsub error l=l w=w + device msubcircuit pmos_3p3_sab pfet pdiffres pdiffres allnwell error l=l w=w + device msubcircuit nmos_3p3_sab nfet ndiffres ndiffres allpsub error l=l w=w + device msubcircuit pmos_6p0_sab mvpfet mvpdiffres mvpdiffres allnwell error l=l w=w + device msubcircuit nmos_6p0_sab mvnfet mvndiffres mvndiffres allpsub error l=l w=w + device msubcircuit nmos_6p0_nat mvnnfet mvndiff,mvndiffres,mvndc \ + mvndiff,mvndiffres,mvndc allpsub error l=l w=w + device subcircuit nmoscap_3p3 varactor *nndiff allnwell error l=l w=w + device subcircuit nmoscap_6p0 mvvaractor *mvnndiff allnwell error l=l w=w + + device rsubcircuit rm1 rm1 *m1 l=r_length w=r_width + device rsubcircuit rm2 rm2 *m2 l=r_length w=r_width + device rsubcircuit rm3 rm3 *m3 l=r_length w=r_width + device rsubcircuit rm4 rm4 *m4 l=r_length w=r_width + + device rsubcircuit tm9k rm5 *m5 l=r_length w=r_width + + device rsubcircuit ppolyf_s rpps *poly allpsub error l=r_length w=r_width + device rsubcircuit npolyf_s rnps *poly allpsub error l=r_length w=r_width + device rsubcircuit ppolyf_u rpp *poly allpsub error l=r_length w=r_width + device rsubcircuit npolyf_u rnp *poly allpsub error l=r_length w=r_width + device rsubcircuit ppolyf_u_1k hires *poly allpsub error l=r_length w=r_width + device rsubcircuit ppolyf_u_1k_6p0 mvhires *poly allpsub error l=r_length w=r_width + device rsubcircuit pplus_u rpd *pdiff allnwell error l=r_length w=r_width + device rsubcircuit nplus_u rnd *ndiff allpsub error l=r_length w=r_width + device rsubcircuit pplus_s rpds *pdiff allnwell error l=r_length w=r_width + device rsubcircuit nplus_s rnds *ndiff allpsub error l=r_length w=r_width + device rsubcircuit pplus_u mvpdiffres *mvpdiff allnwell error l=r_length w=r_width + device rsubcircuit nplus_u mvndiffres *mvndiff allpsub error l=r_length w=r_width + device rsubcircuit nwell rnw nwell allpsub error l=r_length w=r_width + + device pdiode pn_3p3 *pdiode allnwell a=area p=pj + device ndiode np_3p3 *ndiode allpsub a=area p=pj + device pdiode pn_6p0 *mvpdiode allnwell a=area p=pj + device ndiode np_6p0 *mvndiode allpsub a=area p=pj + device ndiode np_6p0_nat *mvnndiode allpsub a=area p=pj + + device csubcircuit mim_2p0fF *mimcap *m4 l=c_length w=c_width + +end + +#----------------------------------------------------- +# Wiring tool definitions +#----------------------------------------------------- + +wiring + scalefactor 50 + + contact v1 200 m1 5 45 m2 0 45 + contact v2 200 m2 0 45 m3 0 45 + contact v3 200 m3 0 45 m4 0 45 + contact v4 200 m4 0 45 m5 0 45 + + contact pdc 160 pdiff 70 70 m1 45 0 + contact ndc 160 ndiff 70 70 m1 45 0 + contact psc 160 ppdiff 70 70 m1 45 0 + contact nsc 160 nndiff 70 70 m1 45 0 + contact pc 160 poly 70 70 m1 45 0 + contact mvpdc 160 mvpdiff 70 70 m1 45 0 + contact mvndc 160 mvndiff 70 70 m1 45 0 + contact mvpsc 160 mvppdiff 70 70 m1 45 0 + contact mvnsc 160 mvnndiff 70 70 m1 45 0 + +end + +#----------------------------------------------------- +# Plain old router. . . +#----------------------------------------------------- + +router +end + +#------------------------------------------------------------ +# Plowing (restored in magic 8.2, need to fill this section) +#------------------------------------------------------------ + +plowing +end + +#----------------------------------------------------------------- +# No special plot layers defined (use default PNM color choices) +#----------------------------------------------------------------- + +plot + style pnm + default + draw fillblock no_color_at_all + draw nwell cwell + draw pwell cwell + draw dnwell cwell +end + diff --git a/Tech.GF180MCU/nmos.sp b/Tech.GF180MCU/nmos.sp new file mode 100644 index 00000000..bed9be42 --- /dev/null +++ b/Tech.GF180MCU/nmos.sp @@ -0,0 +1 @@ +w=1.83u l=0.5u diff --git a/Tech.GF180MCU/pmos.sp b/Tech.GF180MCU/pmos.sp new file mode 100644 index 00000000..6c9e09fe --- /dev/null +++ b/Tech.GF180MCU/pmos.sp @@ -0,0 +1 @@ +w=1.32u l=0.6u diff --git a/Tech.GF180MCU/sm141064.ngspice b/Tech.GF180MCU/sm141064.ngspice new file mode 100644 index 00000000..561e6345 --- /dev/null +++ b/Tech.GF180MCU/sm141064.ngspice @@ -0,0 +1,47638 @@ +* Copyright 2022 GlobalFoundries PDK Authors +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* https://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. + +******************************************************************************* +* Document No. : YI-141-SM064 +* Revision : 9 +* Process Name : 0.18um 3.3V/6V high voltage MCU process +* Process ID : TH18300G0A-PID007347 +* TH18300G1A-PID007352 +* TH183G0G6A-PID009507 +* TH18300G7A-PID009628 +* TH18300G4A-PID009792 +* TH18300G9A-PID010186 +* Wafer ID : GT3512K wf#02 (3.3V NMOS, 6.0V NMOS, 6.0V native NMOS and NMOSCAP) +* GT3512K wf#06 (3.3V PMOS, 6.0V PMOS, PMOSCAP and BJT) +* GT9755L wf#18 (PWELL/DNWELL and DNWELL/Psub diode, Vertical NPN) +* JT1042L01 (6V NMOS L=0.6um) +* TCXN39W20 W#4 schottky diode +************************************************************************************************ +* Models included in this release : +* +* ModelName Description +* --------- ----------- +* nmos_3p3 Subcircuit model for 3.3V NMOS +* pmos_3p3 Subcircuit model for 3.3V PMOS +* nmos_6p0 Subcircuit model for 6.0V NMOS +* pmos_6p0 Subcircuit model for 6.0V PMOS +* nmos_3p3_sab Subcircuit model for 3.3V NMOS with Drain side SAB +* pmos_3p3_sab Subcircuit model for 3.3V PMOS with Drain side SAB +* nmos_6p0_sab Subcircuit model for 6.0V NMOS with Drain side SAB +* pmos_6p0_sab Subcircuit model for 6.0V PMOS with Drain side SAB +* nmos_6p0_nat Subcircuit model for 6.0V native NMOS +* +* np_3p3 Model for 3.3V N+/Psub diode +* pn_3p3 Model for 3.3V P+/Nwell diode +* np_6p0 Model for 6.0V N+/Psub diode +* pn_6p0 Model for 6.0V P+/Nwell diode +* nwp_3p3 Model for 3.3V Nwell/Psub diode +* nwp_6p0 Model for 6.0V Nwell/Psub diode +* dnwpw Model for PWELL/DNWELL diode +* dnwps Model for DNWELL/Psub diode +* sc_diode Model for Schottky Diode +* +* vpnp_0p42x10 Subcircuit GP model for VPNP with emitter size of 10umx0.42um +* vpnp_0p42x5 Subcircuit GP model for VPNP with emitter size of 5umx0.42um +* vpnp_10x10 Subcircuit GP model for VPNP with emitter size of 10umx10um +* vpnp_5x5 Subcircuit GP model for VPNP with emitter size of 5umx5um +* vnpn_10x10 Subcircuit GP model for VNPN with emitter size of 10umx10um(four terminal) +* vnpn_5x5 Subcircuit GP model for VNPN with emitter size of 5umx5um(four terminal) +* vnpn_0p54x16 Subcircuit GP model for VNPN with emitter size of 0.54umx16um(four terminal) +* vnpn_0p54x8 Subcircuit GP model for VNPN with emitter size of 0.54umx8um(four terminal) +* vnpn_0p54x4 Subcircuit GP model for VNPN with emitter size of 0.54umx4um(four terminal) +* vnpn_0p54x2 Subcircuit GP model for VNPN with emitter size of 0.54umx2um(four terminal) +* +* nplus_u Subcircuit Model for 3-terminal unsalicided n+ diffusion resistor +* pplus_u Subcircuit Model for 3-terminal unsalicided P+ diffusion resistor +* nplus_s Subcircuit Model for 3-terminal salicided N+ diffusion resistor +* pplus_s Subcircuit Model for 3-terminal salicided P+ diffusion resistor +* nwell Subcircuit Model for 3-terminal nwell resistor under STI +* npolyf_u Subcircuit Model for 3-terminal unsalicided n+ poly resistor +* ppolyf_u Subcircuit Model for 3-terminal unsalicided p+ poly resistor +* npolyf_s Subcircuit Model for 3-terminal salicided n+ poly resistor +* ppolyf_s Subcircuit Model for 3-terminal salicided p+ poly resistor +* ppolyf_u_1k Subcircuit Model for 3-terminal 1k high-Rs p+ poly resistor on field oxide (3.3V area) +* ppolyf_u_2k Subcircuit Model for 3-terminal 2k high-Rs p+ poly resistor on field oxide (3.3V area) +* ppolyf_u_1k_6p0 Subcircuit Model for 3-terminal 1k high-Rs p+ poly resistor on field oxide (6.0V area) +* ppolyf_u_2k_6p0 Subcircuit Model for 3-terminal 2k high-Rs p+ poly resistor on field oxide (6.0V area) +* ppolyf_u_3k Subcircuit Model for 3-terminal 3k high-Rs p+ poly resistor on field oxide (both 3.3V & 6.0V area) +* rm1 Subcircuit Model for 2-terminal metal 1 resistor +* rm2 Subcircuit Model for 2-terminal metal 2 resistor +* rm3 Subcircuit Model for 2-terminal metal 3 resistor +* tm6k Subcircuit Model for 2-terminal top metal 6k resistor +* tm9k Subcircuit Model for 2-terminal top metal 9k resistor +* tm11k Subcircuit Model for 2-terminal top metal 11k resistor +* tm30k Subcircuit Model for 2-terminal top metal 30k resistor +* +* mim_1p5fF Subcircuit Model for 1.5fF/um2 MIM (*)-usable for Volt <=6V across capacitor +* mim_1p0fF Subcircuit Model for 1.0fF/um2 MIM (*)-usable for Volt <=20V across capacitor +* mim_2p0fF Subcircuit Model for 2fF/um2 MIM -usable for Volt <=6V across capacitor +* +* nmoscap_3p3 Subcircuit Model for 3.3v inversion-mode NMOS capacitor +* pmoscap_3p3 Subcircuit Model for 3.3v inversion-mode PMOS capacitor +* nmoscap_6p0 Subcircuit Model for 6.0V inversion-mode NMOS capacitor +* pmoscap_6p0 Subcircuit Model for 6.0V inversion-mode PMOS capacitor +* nmoscap_3p3_b Subcircuit Model for 3.3v NMOS in Nwell capacitor +* pmoscap_3p3_b Subcircuit Model for 3.3v PMOS in Pwell capacitor +* nmoscap_6p0_b Subcircuit Model for 6.0V NMOS in Nwell capacitor +* pmoscap_6p0_b Subcircuit Model for 6.0V PMOS in Pwell capacitor +* +* efuse Subcircuit model for 6V/(5V) efuse +************************************************************************************************ +* +.LIB typical + .lib 'sm141064.ngspice' nmos_3p3_t + .lib 'sm141064.ngspice' pmos_3p3_t +* + .param rsh_nplus_u_m=60 + .param rsh_pplus_u_m=185 + .param nmos_6p0_vsat = 1 + .param nmos_6p0_vth0 = 0 + .param nmos_6p0_xl = 0 + .param nmos_6p0_xw = 0 + .param nmos_6p0_tox = 0 + .param nmos_6p0_cgso = 1 + .param nmos_6p0_cgdo = 1 + .param nmos_6p0_nat_u0 = '0.070102' + .param nmos_6p0_nat_vth0 = '-0.039' + .param nmos_6p0_nat_xl = '0' + .param nmos_6p0_nat_xw = '0' + .param nmos_6p0_nat_tox = '1.52e-008' + .param nmos_6p0_nat_cgso = '1e-010' + .param nmos_6p0_nat_cgdo = '1e-010' + .param pmos_6p0_dvth0 = 0 + .param pmos_6p0_dxl = 0 + .param pmos_6p0_dxw = 0 + .param pmos_6p0_dtox = 0 + .param pmos_6p0_dcgdo = 1 + .param pmos_6p0_dcgso = 1 + + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_t + .lib 'sm141064.ngspice' nmos_6p0_nat_t + .lib 'sm141064.ngspice' noise_corner + .lib 'sm141064.ngspice' fets_mm +.ENDL +* +* +.LIB ff + .lib 'sm141064.ngspice' nmos_3p3_f + .lib 'sm141064.ngspice' pmos_3p3_f +* + .param rsh_nplus_u_m=45 + .param rsh_pplus_u_m=145 + .param nmos_6p0_vsat = 1.0846 + .param nmos_6p0_vth0 = -0.1298 + .param nmos_6p0_xl = -4.2E-8 + .param nmos_6p0_xw = 5E-8 + .param nmos_6p0_tox = -1E-9 + .param nmos_6p0_cgso = 0.9 + .param nmos_6p0_cgdo = 0.9 + .param nmos_6p0_nat_u0 = '0.118' + .param nmos_6p0_nat_vth0 = '-0.216' + .param nmos_6p0_nat_xl = '-2e-7' + .param nmos_6p0_nat_xw = '1e-7' + .param nmos_6p0_nat_tox = '1.42e-008' + .param nmos_6p0_nat_cgso = '9e-011' + .param nmos_6p0_nat_cgdo = '9e-011' + .param pmos_6p0_dvth0 = 0.1245 + .param pmos_6p0_dxl = -4.65E-8 + .param pmos_6p0_dxw = 5E-8 + .param pmos_6p0_dtox = -1E-9 + .param pmos_6p0_dcgdo = 0.9 + .param pmos_6p0_dcgso = 0.9 + + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_t + .lib 'sm141064.ngspice' nmos_6p0_nat_t + .lib 'sm141064.ngspice' noise_corner + .lib 'sm141064.ngspice' fets_mm +.ENDL +* +* +.LIB ss + .lib 'sm141064.ngspice' nmos_3p3_s + .lib 'sm141064.ngspice' pmos_3p3_s +* + .param rsh_nplus_u_m=75 + .param rsh_pplus_u_m=225 + .param nmos_6p0_vsat = 0.899 + .param nmos_6p0_vth0 = 0.1193 + .param nmos_6p0_xl = 7E-8 + .param nmos_6p0_xw = -5E-8 + .param nmos_6p0_tox = 1E-9 + .param nmos_6p0_cgso = 1.1 + .param nmos_6p0_cgdo = 1.1 + .param nmos_6p0_nat_u0 = '0.046' + .param nmos_6p0_nat_vth0 = '0.1417' + .param nmos_6p0_nat_xl = '2e-7' + .param nmos_6p0_nat_xw = '-1e-7' + .param nmos_6p0_nat_tox = '1.62e-008' + .param nmos_6p0_nat_cgso = '1.1e-010' + .param nmos_6p0_nat_cgdo = '1.1e-010' + .param pmos_6p0_dvth0 = -0.1225 + .param pmos_6p0_dxl = 6.9E-8 + .param pmos_6p0_dxw = -5E-8 + .param pmos_6p0_dtox = 1E-9 + .param pmos_6p0_dcgdo = 1.1 + .param pmos_6p0_dcgso = 1.1 + + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_t + .lib 'sm141064.ngspice' nmos_6p0_nat_t + .lib 'sm141064.ngspice' noise_corner + .lib 'sm141064.ngspice' fets_mm +.ENDL +* +* +.LIB fs + .lib 'sm141064.ngspice' nmos_3p3_fs + .lib 'sm141064.ngspice' pmos_3p3_fs +* + .param rsh_nplus_u_m=48 + .param rsh_pplus_u_m=219 + .param nmos_6p0_vsat = '0.0846*0.67+1' + .param nmos_6p0_vth0 = '-0.1298*0.75' + .param nmos_6p0_xl = '-4.2E-8*0.67' + .param nmos_6p0_xw = '5E-8*0.67' + .param nmos_6p0_tox = '-1E-9*0.75' + .param nmos_6p0_cgso = 0.93 + .param nmos_6p0_cgdo = 0.93 + .param nmos_6p0_nat_u0 = '0.102034' + .param nmos_6p0_nat_vth0 = '-0.157' + .param nmos_6p0_nat_xl = '-1.33e-7' + .param nmos_6p0_nat_xw = '6.7e-8' + .param nmos_6p0_nat_tox = '1.453e-008' + .param nmos_6p0_nat_cgso = '9.33e-011' + .param nmos_6p0_nat_cgdo = '9.33e-011' + .param pmos_6p0_dvth0 = -0.0829 + .param pmos_6p0_dxl = 4.1E-8 + .param pmos_6p0_dxw = -3.35E-8 + .param pmos_6p0_dtox = 6.7E-10 + .param pmos_6p0_dcgdo = 1.07 + .param pmos_6p0_dcgso = 1.07 + + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_t + .lib 'sm141064.ngspice' nmos_6p0_nat_t + .lib 'sm141064.ngspice' noise_corner + .lib 'sm141064.ngspice' fets_mm +.ENDL +* +* +.LIB sf + .lib 'sm141064.ngspice' nmos_3p3_sf + .lib 'sm141064.ngspice' pmos_3p3_sf +* + .param rsh_nplus_u_m=72 + .param rsh_pplus_u_m=150 + .param nmos_6p0_vsat = '1-(1-0.899)*0.67' + .param nmos_6p0_vth0 = '0.1193*0.75' + .param nmos_6p0_xl = '7E-8*0.67' + .param nmos_6p0_xw = '-5E-8*0.67' + .param nmos_6p0_tox = '1E-9*0.75' + .param nmos_6p0_cgso = 1.07 + .param nmos_6p0_cgdo = 1.07 + .param nmos_6p0_nat_u0 = '0.054034' + .param nmos_6p0_nat_vth0 = '0.08147' + .param nmos_6p0_nat_xl = '1.33e-7' + .param nmos_6p0_nat_xw = '-6.7e-8' + .param nmos_6p0_nat_tox = '1.587e-008' + .param nmos_6p0_nat_cgso = '1.067e-010' + .param nmos_6p0_nat_cgdo = '1.067e-010' + .param pmos_6p0_dvth0 = 0.0827 + .param pmos_6p0_dxl = -3.22E-8 + .param pmos_6p0_dxw = 3.35E-8 + .param pmos_6p0_dtox = -6.7E-10 + .param pmos_6p0_dcgdo = 0.93 + .param pmos_6p0_dcgso = 0.93 + + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_t + .lib 'sm141064.ngspice' nmos_6p0_nat_t + .lib 'sm141064.ngspice' noise_corner + .lib 'sm141064.ngspice' fets_mm +.ENDL +**************************************************** +* +.LIB bjt_typical +.param ++isa=1 bfa=1 rba=1 rea=1 ++rca=1 rbma=1 cjea=1 cjca=1 ++is_cor_npn =1 ++bf_cor_npn=1 ++rb_cor_npn=1 ++re_cor_npn=1 ++rc_cor_npn=1 ++rbm_cor_npn=1 ++cjc_cor_npn=1 ++cje_cor_npn=1 + ++ mc_xis_vnpn=0 ++ mc_xbf_vnpn=0 ++ mc_xrb_vnpn=0 ++ mc_xre_vnpn=0 ++ mc_xrc_vnpn=0 ++ mc_xcje_vnpn=0 ++ mc_xcjc_vnpn=0 ++ mc_xis_vpnp=0 ++ mc_xbf_vpnp=0 ++ mc_xrb_vpnp=0 ++ mc_xre_vpnp=0 ++ mc_xrc_vpnp=0 ++ mc_xcje_vpnp=0 ++ mc_xcjc_vpnp=0 +.lib 'sm141064.ngspice' bjt_mc +.ENDL +* +.LIB bjt_ss +.param ++isa=0.65 bfa=0.80 rba=1.2 rea=1.2 ++rca=1.2 rbma=1.2 cjea=1.15 cjca=1.15 ++is_cor_npn =0.4 ++bf_cor_npn=0.57 ++rb_cor_npn=1.2 ++re_cor_npn=1.2 ++rc_cor_npn=1.2 ++rbm_cor_npn=1.2 ++cjc_cor_npn=1.15 ++cje_cor_npn=1.15 + ++ mc_xis_vnpn=0 ++ mc_xbf_vnpn=0 ++ mc_xrb_vnpn=0 ++ mc_xre_vnpn=0 ++ mc_xrc_vnpn=0 ++ mc_xcje_vnpn=0 ++ mc_xcjc_vnpn=0 ++ mc_xis_vpnp=0 ++ mc_xbf_vpnp=0 ++ mc_xrb_vpnp=0 ++ mc_xre_vpnp=0 ++ mc_xrc_vpnp=0 ++ mc_xcje_vpnp=0 ++ mc_xcjc_vpnp=0 +.lib 'sm141064.ngspice' bjt_mc +.ENDL +* +.LIB bjt_ff +.param ++isa=1.35 bfa=1.2 rba=0.8 rea=0.8 ++rca=0.8 rbma=0.8 cjea=0.85 cjca=0.85 ++is_cor_npn =2.25 ++bf_cor_npn=1.31 ++rb_cor_npn=0.8 ++re_cor_npn=0.8 ++rc_cor_npn=0.8 ++rbm_cor_npn=0.8 ++cjc_cor_npn=0.85 ++cje_cor_npn=0.85 + ++ mc_xis_vnpn=0 ++ mc_xbf_vnpn=0 ++ mc_xrb_vnpn=0 ++ mc_xre_vnpn=0 ++ mc_xrc_vnpn=0 ++ mc_xcje_vnpn=0 ++ mc_xcjc_vnpn=0 ++ mc_xis_vpnp=0 ++ mc_xbf_vpnp=0 ++ mc_xrb_vpnp=0 ++ mc_xre_vpnp=0 ++ mc_xrc_vpnp=0 ++ mc_xcje_vpnp=0 ++ mc_xcjc_vpnp=0 +.lib 'sm141064.ngspice' bjt_mc +.ENDL +**************************************************** +* +.LIB diode_typical + .param + +jsa=1 rsa=1 cja=1 cjswa=1 + +jsa_sc = 0 vba_sc=0 rs_sc=1 jtuna_sc=0 cja_sc=1 + .lib 'sm141064.ngspice' dio +.ENDL +* +.LIB diode_ss + .param + +jsa=0.85 rsa=1.1 cja=1.1 cjswa=1.1 + +jsa_sc = -1.6 vba_sc=-7 rs_sc=1.1 jtuna_sc=-0.77 cja_sc=1.1 + .lib 'sm141064.ngspice' dio +.ENDL +* +.LIB diode_ff + .param + +jsa=1.15 rsa=0.9 cja=0.9 cjswa=0.9 + +jsa_sc = 1.6 vba_sc=7 rs_sc=0.9 jtuna_sc=0.77 cja_sc=0.9 + .lib 'sm141064.ngspice' dio +.ENDL +**************************************************** +* +.LIB res_typical +.param ++rsh_nplus_u=60 ++rsh_pplus_u=185 ++rsh_nplus_s=6.3 ++rsh_pplus_s=7 ++rsh_nwell=1000 ++rsh_npolyf_u=310 ++rsh_ppolyf_u=350 ++rsh_npolyf_s=6.8 ++rsh_ppolyf_s=7.3 +* ++rsh_ppolyf_u_1k=1000 ++rsh_ppolyf_u_2k=2000 ++rsh_ppolyf_u_1k_6p0=1000 ++rsh_ppolyf_u_2k_6p0=2000 ++rsh_ppolyf_u_3k=3000 ++rsh_rm1=0.09 ++rsh_rm2=0.09 ++rsh_rm3=0.09 ++rsh_tm6k=60e-3 ++rsh_tm9k=40e-3 ++rsh_tm11k=40e-3 ++rsh_tm30k=9.5e-3 +* +.lib 'sm141064.ngspice' res +.lib 'sm141064.ngspice' efuse +.lib 'sm141064.ngspice' res_statistical_par +.ENDL +* +.LIB res_ss +.param ++rsh_nplus_u=75 ++rsh_pplus_u=225 ++rsh_nplus_s=15 ++rsh_pplus_s=15 ++rsh_nwell=1200 ++rsh_npolyf_u=370 ++rsh_ppolyf_u=420 ++rsh_npolyf_s=15 ++rsh_ppolyf_s=15 +* ++rsh_ppolyf_u_1k='1000+200' ++rsh_ppolyf_u_2k='2000+400' ++rsh_ppolyf_u_1k_6p0='1000+200' ++rsh_ppolyf_u_2k_6p0='2000+400' ++rsh_ppolyf_u_3k='3000+750' ++rsh_rm1='0.09+0.012' ++rsh_rm2='0.09+0.012' ++rsh_rm3='0.09+0.012' ++rsh_tm6k='60e-3 + 10e-3' ++rsh_tm9k='40e-3 + 9e-3' ++rsh_tm11k='40e-3 + 9e-3' ++rsh_tm30k='9.5e-3 + 4.5e-3' +* +.lib 'sm141064.ngspice' res +.lib 'sm141064.ngspice' efuse +.lib 'sm141064.ngspice' res_statistical_par +.ENDL +* +.LIB res_ff +.param ++rsh_nplus_u=45 ++rsh_pplus_u=145 ++rsh_nplus_s=1 ++rsh_pplus_s=1 ++rsh_nwell=800 ++rsh_npolyf_u=250 ++rsh_ppolyf_u=280 ++rsh_npolyf_s=1 ++rsh_ppolyf_s=1 +* ++rsh_ppolyf_u_1k='1000-200' ++rsh_ppolyf_u_2k='2000-400' ++rsh_ppolyf_u_1k_6p0='1000-200' ++rsh_ppolyf_u_2k_6p0='2000-400' ++rsh_ppolyf_u_3k='3000-750' ++rsh_rm1='0.09-0.012' ++rsh_rm2='0.09-0.012' ++rsh_rm3='0.09-0.012' ++rsh_tm6k='60e-3 - 10e-3' ++rsh_tm9k='40e-3 - 9e-3' ++rsh_tm11k='40e-3 - 9e-3' ++rsh_tm30k='9.5e-3 - 3.5e-3' +* +.lib 'sm141064.ngspice' res +.lib 'sm141064.ngspice' efuse +.lib 'sm141064.ngspice' res_statistical_par +.ENDL +**************************************************** +* +.LIB mimcap_typical +.param mim_corner_1p5fF=1 +.param mim_corner_1p0fF=1 +.param mim_corner_2p0fF=1 + +.param mc_c_cox_1p0fF=0 +.param mc_c_cox_1p5fF=0 +.param mc_c_cox_2p0fF=0 + +.lib 'sm141064.ngspice' mim_cap +.ENDL +* +.LIB mimcap_ss +.param mim_corner_1p5fF=1.155 +.param mim_corner_1p0fF=1.1 +.param mim_corner_2p0fF=1.1 +.param mc_c_cox_1p0fF=0 +.param mc_c_cox_1p5fF=0 +.param mc_c_cox_2p0fF=0 + +.lib 'sm141064.ngspice' mim_cap +.ENDL +* +.LIB mimcap_ff +.param mim_corner_1p5fF=0.845 +.param mim_corner_1p0fF=0.9 +.param mim_corner_2p0fF=0.9 + +.param mc_c_cox_1p0fF=0 +.param mc_c_cox_1p5fF=0 +.param mc_c_cox_2p0fF=0 + +.lib 'sm141064.ngspice' mim_cap +.ENDL +**************************************************** +* +.lib moscap_typical +.param + + nmoscap_3p3_corner=1 + + pmoscap_3p3_corner=1 + + nmoscap_6p0_corner=1 + + pmoscap_6p0_corner=1 + + nmoscap_3p3_b_corner=1 + + pmoscap_3p3_b_corner=1 + + nmoscap_6p0_b_corner=1 + + pmoscap_6p0_b_corner=1 + +.lib 'sm141064.ngspice' moscap +.ENDL +* +.lib moscap_ff +.param + + nmoscap_3p3_corner=0.9 + + pmoscap_3p3_corner=0.9 + + nmoscap_6p0_corner=0.9 + + pmoscap_6p0_corner=0.9 + + nmoscap_3p3_b_corner=0.9 + + pmoscap_3p3_b_corner=0.9 + + nmoscap_6p0_b_corner=0.9 + + pmoscap_6p0_b_corner=0.9 + +.lib 'sm141064.ngspice' moscap +.ENDL +* +.lib moscap_ss +.param + + nmoscap_3p3_corner=1.1 + + pmoscap_3p3_corner=1.1 + + nmoscap_6p0_corner=1.1 + + pmoscap_6p0_corner=1.1 + + nmoscap_3p3_b_corner=1.1 + + pmoscap_3p3_b_corner=1.1 + + nmoscap_6p0_b_corner=1.1 + + pmoscap_6p0_b_corner=1.1 + +.lib 'sm141064.ngspice' moscap +.ENDL +**************************************************** +* +.LIB statistical + .param + +* MOSFET statistical parameters + + mc_sig_vth2 = agauss(0, 1, 3) + + mc_toxe2 = agauss(0, 1, 3) + + mc_xl2 = agauss(0, 1, 3) + + mc_xw2 = agauss(0, 1, 3) + + mc_xj2 = agauss(0, 1, 3) + + + mc_sig_vthN2 = agauss(0, 1, 3) + + mc_toxeN2 = agauss(0, 1, 3) + + mc_xlN2 = agauss(0, 1, 3) + + mc_xwN2 = agauss(0, 1, 3) + + mc_xjN2 = agauss(0, 1, 3) + + mc_rdswN2 = agauss(0, 1, 3) + + + mc_sig_vthP2 = agauss(0, 1, 3) + + mc_toxeP2 = agauss(0, 1, 3) + + mc_xlP2 = agauss(0, 1, 3) + + mc_xwP2 = agauss(0, 1, 3) + + mc_xjP2 = agauss(0, 1, 3) + + mc_rdswP2 = agauss(0, 1, 3) + + mc_rsh_nplus_u_temp=agauss(0, 3.85, 3) + + mc_rsh_pplus_u_temp=agauss(0, 10, 3) + + + + mc_sig_vth = mc_sig_vth2 + + mc_toxe = mc_toxe2 + + mc_xl = mc_xl2 + + mc_xw = mc_xw2 + + mc_xj = mc_xj2 + + + mc_sig_vthN = mc_sig_vthN2 + + mc_toxeN = mc_toxeN2 + + mc_xlN = mc_xlN2 + + mc_xwN = mc_xwN2 + + mc_xjN = mc_xjN2 + + mc_rdswN = mc_rdswN2 + + + mc_sig_vthP = mc_sig_vthP2 + + mc_toxeP = mc_toxeP2 + + mc_xlP = mc_xlP2 + + mc_xwP = mc_xwP2 + + mc_xjP = mc_xjP2 + + mc_rdswP = mc_rdswP2 + + mc_rsh_nplus_u=mc_rsh_nplus_u_temp + + mc_rsh_pplus_u=mc_rsh_pplus_u_temp + + + ****** 3.3V devices monte carlo parameters ****** + .param + + nmos_3p3_sig_vth1 = '(5e-3*mc_sig_vth+30e-3*mc_sig_vthN)*sw_stat_global*mc_skew' + + nmos_3p3_sig_vth2 = '(5e-3*mc_sig_vth+25e-3*mc_sig_vthN)*sw_stat_global*mc_skew' + + nmos_3p3_sig_vth3 = '(5e-3*mc_sig_vth+15e-3*mc_sig_vthN)*sw_stat_global*mc_skew' + + nmos_3p3_tox = '8e-009 + (1.6e-10*mc_toxe+0.3e-10*mc_toxeN)*sw_stat_global*mc_skew' + + nmos_3p3_xl = '(7e-9*mc_xl+6e-9*mc_xlN)*sw_stat_global*mc_skew' + + nmos_3p3_xw = '(7e-9*mc_xw+3e-9*mc_xwN)*sw_stat_global*mc_skew' + + nmos_3p3_xj = '1e-7 + (0.3e-9*mc_xj+0.7e-9*mc_xjN)*sw_stat_global*mc_skew' + + nmos_3p3_rdsw = '530 * (1+0.15* mc_rdswN*sw_stat_global*mc_skew)' + + nmos_3p3_vth0_0 = '0.70837662 + nmos_3p3_sig_vth1' + + nmos_3p3_vth0_1 = '0.67781184 + nmos_3p3_sig_vth1' + + nmos_3p3_vth0_2 = '0.66097097 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_3 = '0.66064857 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_4 = '0.72356597 + nmos_3p3_sig_vth1' + + nmos_3p3_vth0_5 = '0.67504024 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_6 = '0.64923469 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_7 = '0.65055971 + nmos_3p3_sig_vth3' + + nmos_3p3_vth0_8 = '0.75419347 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_9 = '0.66260505 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_10 = '0.64815901 + nmos_3p3_sig_vth3' + + nmos_3p3_vth0_11 = '0.64889718 + nmos_3p3_sig_vth3' + + nmos_3p3_vth0_12 = '0.74840818 + nmos_3p3_sig_vth2' + + nmos_3p3_vth0_13 = '0.66297571 + nmos_3p3_sig_vth3' + + nmos_3p3_vth0_14 = '0.64787864 + nmos_3p3_sig_vth3' + + nmos_3p3_vth0_15 = '0.64857 + nmos_3p3_sig_vth3' + + .param + + pmos_3p3_sig_vth1 = '(-5e-3*mc_sig_vth-38e-3*mc_sig_vthP)*sw_stat_global*mc_skew' + + pmos_3p3_sig_vth2 = '(-5e-3*mc_sig_vth-30e-3*mc_sig_vthP)*sw_stat_global*mc_skew' + + pmos_3p3_sig_vth3 = '(-5e-3*mc_sig_vth-18e-3*mc_sig_vthP)*sw_stat_global*mc_skew' + + pmos_3p3_tox = '7.9e-009 + (1.6e-10*mc_toxe+0.3e-10*mc_toxeP)*sw_stat_global*mc_skew' + + pmos_3p3_xl = '(7e-9*mc_xl+4e-9*mc_xlP)*sw_stat_global*mc_skew' + + pmos_3p3_xw = '(7e-9*mc_xw+3e-9*mc_xwP)*sw_stat_global*mc_skew' + + pmos_3p3_xj = '1.0e-7 + (0.3e-9*mc_xj+0.7e-9*mc_xjP)*sw_stat_global*mc_skew' + + pmos_3p3_rdsw = '466 * (1+0.15*mc_rdswP*sw_stat_global*mc_skew)' + + pmos_3p3_vth0_0 = '-0.7506174 + pmos_3p3_sig_vth1' + + pmos_3p3_vth0_1 = '-0.78216327 + pmos_3p3_sig_vth1' + + pmos_3p3_vth0_2 = '-0.76745877 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_3 = '-0.76841429 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_4 = '-0.7710094 + pmos_3p3_sig_vth1' + + pmos_3p3_vth0_5 = '-0.77464237 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_6 = '-0.77376777 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_7 = '-0.77390514 + pmos_3p3_sig_vth3' + + pmos_3p3_vth0_8 = '-0.76226585 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_9 = '-0.76552347 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_10 = '-0.7677531 + pmos_3p3_sig_vth3' + + pmos_3p3_vth0_11 = '-0.7682 + pmos_3p3_sig_vth3' + + pmos_3p3_vth0_12 = '-0.76184364 + pmos_3p3_sig_vth2' + + pmos_3p3_vth0_13 = '-0.76642857 + pmos_3p3_sig_vth3' + + pmos_3p3_vth0_14 = '-0.76779091 + pmos_3p3_sig_vth3' + + pmos_3p3_vth0_15 = '-0.7682 + pmos_3p3_sig_vth3' + + ****** 6.0V devices monte carlo parameters ****** + .param + + nmos_6p0_vsat = '(1-0.063* mc_rdswN*sw_stat_global*mc_skew)' + + nmos_6p0_vth0 = '(8e-3*mc_sig_vth+28e-3*mc_sig_vthN)*sw_stat_global*mc_skew' + + nmos_6p0_xl = '(2e-8*mc_xl+0*mc_xlN)*sw_stat_global*mc_skew' + + nmos_6p0_xw = '(1.5e-8*mc_xw+9e-9*mc_xwN)*sw_stat_global*mc_skew' + + nmos_6p0_tox = '(4e-10*mc_toxe+1.3e-10*mc_toxeN)*sw_stat_global*mc_skew' + + nmos_6p0_cgso = 1 + + nmos_6p0_cgdo = 1 + + .param + + pmos_6p0_vth0 = '-0.8978 + (8e-3*mc_sig_vth+30e-3*mc_sig_vthP)*sw_stat_global*mc_skew' + + pmos_6p0_tox = '156e-010 + (4e-10*mc_toxe+1e-10*mc_toxeP)*sw_stat_global*mc_skew' + + pmos_6p0_xl = '0 + (2e-8*mc_xl+2e-9*mc_xlP)*sw_stat_global*mc_skew' + + pmos_6p0_xw = '0 + (1.5e-8*mc_xw+9e-9*mc_xwP)*sw_stat_global*mc_skew' + + pmos_6p0_xj = '1.5e-7 + (0.3e-9*mc_xj+1e-8*mc_xjP)*sw_stat_global*mc_skew' + + pmos_6p0_rdsw = '1426 * (1+0.2* mc_rdswP*sw_stat_global*mc_skew)' + + .param + + nmos_6p0_nat_vth0 = '-0.039 + (8e-3*mc_sig_vth+60e-3*mc_sig_vthN)*sw_stat_global*mc_skew' + + nmos_6p0_nat_tox = '152e-010 + (4e-10*mc_toxe+6e-10*mc_toxeN)*sw_stat_global*mc_skew' + + nmos_6p0_nat_xl = '0 + (2e-8*mc_xl+8e-8*mc_xlN)*sw_stat_global*mc_skew' + + nmos_6p0_nat_xw = '0 + (1.5e-8*mc_xw+8e-8*mc_xwN)*sw_stat_global*mc_skew' + + nmos_6p0_nat_xj = '1.5e-7 + (0.3e-9*mc_xj+2e-8*mc_xjN)*sw_stat_global*mc_skew' + + nmos_6p0_nat_rdsw = '3480 * (1+0.2* mc_rdswN*sw_stat_global*mc_skew)' + +.param ++ rsh_nplus2_u=60 ++ rsh_pplus2_u=185 + ++ rsh_nplus_u_m = 'rsh_nplus2_u*(1+(mc_rsh_nplus_u/(rsh_nplus2_u))*res_mc_skew*sw_stat_global)' ++ rsh_pplus_u_m = 'rsh_pplus2_u*(1+(mc_rsh_pplus_u/(rsh_pplus2_u))*res_mc_skew*sw_stat_global)' + + .lib 'sm141064.ngspice' fets_mm + .lib 'sm141064.ngspice' nmos_3p3_stat + .lib 'sm141064.ngspice' pmos_3p3_stat + .lib 'sm141064.ngspice' nmos_6p0_t + .lib 'sm141064.ngspice' pmos_6p0_stat + .lib 'sm141064.ngspice' nmos_6p0_nat_stat + .lib 'sm141064.ngspice' noise_corner + +.ENDL +* +* +.LIB noise_corner + .param + +nmos_3p3_noia='(fnoicor==0)*3.2e+041 + (fnoicor==1)*3.5e+042' + +nmos_3p3_noib='(fnoicor==0)*1.2e+020 + (fnoicor==1)*1.2e+020' + +nmos_3p3_noic='(fnoicor==0)*6.0e+008 + (fnoicor==1)*6.0e+008' + + +pmos_3p3_noia='(fnoicor==0)*3.2e+041 + (fnoicor==1)*4.0e+042' + +pmos_3p3_noib='(fnoicor==0)*1.8e+020 + (fnoicor==1)*1.8e+020' + +pmos_3p3_noic='(fnoicor==0)*3.0e+009 + (fnoicor==1)*6.0e+009' + + +nmos_6p0_noia='(fnoicor==0)*1.998e+041 + (fnoicor==1)*8e+041' + +nmos_6p0_noib='(fnoicor==0)*1e+025 + (fnoicor==1)*4e+025' + +nmos_6p0_noic='(fnoicor==0)*5e+008 + (fnoicor==1)*2e+009' + + +pmos_6p0_noia='(fnoicor==0)*6e+040 + (fnoicor==1)*2e+043' + +pmos_6p0_noib='(fnoicor==0)*1.5945e+025 + (fnoicor==1)*1.5945e+025' + +pmos_6p0_noic='(fnoicor==0)*1.0499e+009 + (fnoicor==1)*1.0499e+009' + + +nmos_6p0_nat_noia='(fnoicor==0)*5.5e+040 + (fnoicor==1)*1e+041' + +nmos_6p0_nat_noib='(fnoicor==0)*2.5e+025 + (fnoicor==1)*9.5e+025' + +nmos_6p0_nat_noic='(fnoicor==0)*1e+007 + (fnoicor==1)*2e+007' + +.ENDL +* +* +*************************************************************************************************** +* 3.3V NMOS Models +*************************************************************************************************** +* +.lib nmos_3p3_t + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' + + +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.70837662 ++lvth0 = -3.8715455e-008 ++wvth0 = -1.430587e-008 ++pvth0 = 4.3636364e-016 ++k1 = 0.95938091 ++lk1 = -9.9985454e-008 ++k2 = 0.054714558 ++lk2 = -4.1647636e-008 ++wk2 = -1.9242857e-008 ++pk2 = 5.388e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.1262652 ++lvoff = 3.9354545e-009 ++wvoff = 5.3064935e-009 ++pvoff = -1.4858182e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.023671338 ++lu0 = 4.6525455e-009 ++wu0 = 4.6066597e-009 ++pu0 = -6.5127273e-016 ++ua = -1.1554452e-009 ++lua = 7.0220545e-016 ++wua = 2.7073777e-016 ++pua = -1.4149745e-022 ++ub = 3.3771156e-018 ++lub = -7.9058636e-025 ++wub = -4.093733e-025 ++pub = 9.2644364e-032 ++uc = 2.2660166e-010 ++luc = -6.1360545e-017 ++wuc = -3.2577351e-017 ++puc = 5.4467782e-024 ++eu = 1.67 ++vsat = 92454.546 ++lvsat = -0.0027272727 ++wvsat = -0.00021818182 ++pvsat = 1.3090909e-009 ++a0 = 0.11197377 ++la0 = -3.1454545e-009 ++wa0 = -6.2322078e-009 ++pa0 = 1.7450182e-015 ++ags = 0.32403844 ++lags = -1.5116364e-008 ++wags = 4.7930493e-008 ++pags = -1.2213818e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.14896036 ++lketa = 3.8830182e-008 ++wketa = 8.1643636e-009 ++pketa = -2.4261818e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.3741 ++lpclm = -4.729e-008 ++wpclm = 2.1028364e-008 ++ppclm = 8.5658182e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.652013e-006 ++lalpha0 = -3.0506364e-013 ++walpha0 = 4.8779221e-014 ++palpha0 = -1.3658182e-020 ++alpha1 = 0 ++beta0 = 19.905584 ++lbeta0 = 1.2863636e-007 ++wbeta0 = 1.3848312e-007 ++pbeta0 = 8.7272727e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.45934558 ++lkt1 = 4.2126364e-008 ++wkt1 = 3.2086753e-008 ++pkt1 = -8.6530909e-015 ++kt1l = 0 ++kt2 = -0.024730519 ++lkt2 = 1.2545455e-009 ++wkt2 = 1.0597403e-009 ++pkt2 = -2.9672727e-016 ++ute = -1.5675325 ++lute = 9.0909091e-008 ++wute = 1.0441558e-007 ++pute = -4.3636364e-014 ++ua1 = 1.675e-009 ++ub1 = -4.1945234e-018 ++lub1 = 2.8745455e-025 ++wub1 = 3.3492467e-025 ++pub1 = -5.7490909e-032 ++uc1 = -4.2363636e-011 ++luc1 = -3.8181818e-018 ++wuc1 = -6.5454545e-018 ++puc1 = 1.8327273e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.67781184 ++lvth0 = -2.3433061e-008 ++wvth0 = -1.2304653e-008 ++pvth0 = -5.642449e-016 ++k1 = 0.74639857 ++lk1 = 6.5057143e-009 ++k2 = 0.0237458 ++lk2 = -2.6163257e-008 ++wk2 = -3.01296e-009 ++pk2 = -2.7269486e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11273959 ++lvoff = -2.8273469e-009 ++wvoff = 1.6942041e-009 ++pvoff = 3.2032653e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.029675694 ++lu0 = 1.6503673e-009 ++wu0 = 8.572898e-010 ++pu0 = 1.2234122e-015 ++ua = -1.2961984e-009 ++lua = 7.7258204e-016 ++wua = 4.7264816e-017 ++pua = -2.976098e-023 ++ub = 3.0836898e-018 ++lub = -6.4387347e-025 ++wub = -2.7080816e-026 ++pub = -9.8501878e-032 ++uc = 8.4613959e-011 ++luc = 9.6333061e-018 ++wuc = 2.2398367e-018 ++puc = -1.1961815e-023 ++eu = 1.67 ++vsat = 83571.429 ++lvsat = 0.0017142857 ++wvsat = -0.0017142857 ++pvsat = 2.0571429e-009 ++a0 = 1.0861147 ++la0 = -4.9021592e-007 ++wa0 = -5.1997224e-008 ++pa0 = 2.4627526e-014 ++ags = 0.47870122 ++lags = -9.2447755e-008 ++wags = 4.3304327e-008 ++pags = -9.9007347e-015 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028417143 ++lketa = -2.1441429e-008 ++wketa = -7.4262857e-009 ++pketa = 5.3691429e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.082893878 ++lpclm = 9.8313061e-008 ++wpclm = 4.3902367e-008 ++ppclm = -2.8711837e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.5720816e-006 ++lalpha0 = -2.265098e-012 ++walpha0 = -1.5330612e-014 ++palpha0 = 1.8396735e-020 ++alpha1 = 0 ++beta0 = 22.625306 ++lbeta0 = -1.2312245e-006 ++wbeta0 = -3.5054694e-007 ++pbeta0 = 2.4538775e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33916633 ++lkt1 = -1.7963265e-008 ++wkt1 = -2.4641633e-009 ++pkt1 = 8.6223674e-015 ++kt1l = 0 ++kt2 = -0.020311225 ++lkt2 = -9.5510204e-010 ++wkt2 = -3.9183673e-011 ++pkt2 = 2.5273469e-016 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.804398e-018 ++lub1 = -4.0760816e-025 ++wub1 = 5.6899592e-026 ++pub1 = 8.1521633e-032 ++uc1 = -6.0285714e-011 ++luc1 = 5.1428571e-018 ++wuc1 = 2.0571429e-018 ++puc1 = -2.4685714e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.66097097 ++lvth0 = -3.224026e-009 ++wvth0 = -9.7008312e-009 ++pvth0 = -3.6888312e-015 ++k1 = 0.79593364 ++lk1 = -5.2936364e-008 ++k2 = 0.0056393844 ++lk2 = -4.4355584e-009 ++wk2 = -7.4596769e-009 ++pk2 = 2.6091117e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12631325 ++lvoff = 1.3461039e-008 ++wvoff = 2.0819221e-009 ++pvoff = -1.4493507e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032447266 ++lu0 = -1.6755195e-009 ++wu0 = 6.7095584e-010 ++pu0 = 1.447013e-015 ++ua = -8.1547091e-010 ++lua = 1.9570909e-016 ++wua = 6.0458182e-018 ++pua = 1.9701818e-023 ++ub = 2.7427942e-018 ++lub = -2.347987e-025 ++wub = -1.6048831e-026 ++pub = -1.1174026e-031 ++uc = 9.84685e-011 ++luc = -6.9921429e-018 ++wuc = -8.8975636e-018 ++puc = 1.4030649e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.224418 ++la0 = -6.5617987e-007 ++wa0 = 4.291948e-009 ++pa0 = -4.2919481e-014 ++ags = 0.25784649 ++lags = 1.7257792e-007 ++wags = -2.606026e-009 ++pags = 4.5191688e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019651071 ++lketa = -3.1960714e-008 ++wketa = -6.5992208e-010 ++pketa = -2.7504935e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.18918506 ++lpclm = -2.9236364e-008 ++wpclm = 2.1551688e-009 ++ppclm = 4.7225454e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.5243347e-005 ++lalpha0 = -8.4670617e-011 ++walpha0 = 7.5358442e-012 ++palpha0 = -9.043013e-018 ++alpha1 = 0 ++beta0 = 24.210162 ++lbeta0 = -3.133052e-006 ++wbeta0 = 1.1381299e-007 ++pbeta0 = -3.1184416e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32898149 ++lkt1 = -3.0185065e-008 ++wkt1 = -7.3528831e-009 ++pkt1 = 1.4488831e-014 ++kt1l = 0 ++kt2 = -0.021107143 ++wkt2 = 1.7142857e-010 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5166039e-018 ++lub1 = -7.5296104e-025 ++wub1 = 2.224987e-026 ++pub1 = 1.231013e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.66064857 ++wvth0 = -1.0069714e-008 ++k1 = 0.79064 ++k2 = 0.0051958286 ++wk2 = -7.1987657e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12496714 ++wvoff = 2.0674286e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032279714 ++wu0 = 8.1565714e-010 ++ua = -7.959e-010 ++wua = 8.016e-018 ++ub = 2.7193143e-018 ++wub = -2.7222857e-026 ++uc = 9.7769286e-011 ++wuc = -8.7572571e-018 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1588 ++ags = 0.27510429 ++wags = 1.9131429e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.022847143 ++wketa = -9.3497143e-010 ++dwg = 0 ++dwb = 0 ++pclm = 0.18626143 ++wpclm = 6.8777143e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6776286e-005 ++walpha0 = 6.6315429e-012 ++alpha1 = 0 ++beta0 = 23.896857 ++wbeta0 = 8.2628571e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.332 ++wkt1 = -5.904e-009 ++kt1l = 0 ++kt2 = -0.021107143 ++wkt2 = 1.7142857e-010 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5919e-018 ++wub1 = 3.456e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72356597 ++lvth0 = -4.1979273e-008 ++wvth0 = -2.1596758e-008 ++pvth0 = 2.0029964e-015 ++k1 = 0.95938091 ++lk1 = -9.9985454e-008 ++k2 = 0.041255727 ++lk2 = -3.7879164e-008 ++wk2 = -1.2782618e-008 ++pk2 = 3.5791331e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.079311948 ++lvoff = -9.2114546e-009 ++wvoff = -1.7231065e-008 ++pvoff = 4.8246982e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.033011551 ++lu0 = 4.0251818e-009 ++wu0 = 1.2335751e-010 ++pu0 = -3.5013818e-016 ++ua = -6.3005701e-010 ++lua = 3.9938436e-016 ++wua = 1.8551439e-017 ++pua = 3.8566691e-024 ++ub = 2.2836418e-018 ++lub = -9.0230909e-026 ++wub = 1.1549411e-025 ++pub = -2.4352626e-031 ++uc = 1.5877203e-010 ++luc = -3.4349127e-017 ++wuc = -1.9125195e-020 ++puc = -7.5187026e-024 ++eu = 1.67 ++vsat = 71618.182 ++lvsat = 0.0042909091 ++wvsat = 0.0097832727 ++pvsat = -2.0596364e-009 ++a0 = 0.10680558 ++la0 = -1.6983636e-009 ++wa0 = -3.7514805e-009 ++pa0 = 1.0504145e-015 ++ags = 0.35500309 ++lags = -1.1780546e-008 ++wags = 3.3067462e-008 ++pags = -1.3815011e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12490989 ++lketa = 3.0254945e-008 ++wketa = -3.3798633e-009 ++pketa = 1.6899316e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.45921829 ++lpclm = -8.0088e-008 ++wpclm = -1.9828414e-008 ++ppclm = 2.4308858e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6500109e-006 ++lalpha0 = -2.8170545e-013 ++walpha0 = 4.9740218e-014 ++palpha0 = -2.4870109e-020 ++alpha1 = 0 ++beta0 = 20.982852 ++lbeta0 = -8.9454546e-008 ++wbeta0 = -3.786053e-007 ++pbeta0 = 1.0555636e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37773746 ++lkt1 = 1.6718727e-008 ++wkt1 = -7.0851491e-009 ++pkt1 = 3.5425745e-015 ++kt1l = 0 ++kt2 = -0.014603854 ++lkt2 = -3.3230727e-009 ++wkt2 = -3.8010589e-009 ++pkt2 = 1.9005294e-015 ++ute = -1.4342857 ++wute = 4.0457143e-008 ++ua1 = 1.675e-009 ++ub1 = -3.65896e-018 ++lub1 = 2.4878e-025 ++wub1 = 7.7854254e-026 ++pub1 = -3.8927127e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.67504024 ++lvth0 = -1.7716408e-008 ++wvth0 = -1.0974289e-008 ++pvth0 = -3.3082384e-015 ++k1 = 0.76833212 ++lk1 = -4.4610612e-009 ++wk1 = -1.0528104e-008 ++pk1 = 5.2640522e-015 ++k2 = 0.0082103273 ++lk2 = -2.1356464e-008 ++wk2 = 4.4440669e-009 ++pk2 = -5.0342094e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12049225 ++lvoff = 1.1378694e-008 ++wvoff = 5.4154776e-009 ++pvoff = -6.4985731e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031181163 ++lu0 = 4.9403755e-009 ++wu0 = 1.3466449e-010 ++pu0 = -3.5579167e-016 ++ua = -1.1586455e-009 ++lua = 6.6367861e-016 ++wua = -1.8760555e-017 ++pua = 2.2512666e-023 ++ub = 2.8240225e-018 ++lub = -3.6042122e-025 ++wub = 9.755951e-026 ++pub = -2.3455895e-031 ++uc = 8.1997037e-011 ++luc = 4.0383673e-018 ++wuc = 3.4959595e-018 ++puc = -9.2762449e-024 ++eu = 1.67 ++vsat = 88428.571 ++lvsat = -0.0041142857 ++wvsat = -0.0040457143 ++pvsat = 4.8548571e-009 ++a0 = 0.97533082 ++la0 = -4.3596098e-007 ++wa0 = 1.1790367e-009 ++pa0 = -1.4148441e-015 ++ags = 0.441074 ++lags = -5.4816e-008 ++wags = 6.1365394e-008 ++pags = -2.7963977e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.21719837 ++lpclm = 4.0921959e-008 ++wpclm = -2.0563788e-008 ++ppclm = 2.4676545e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.8164074e-006 ++lalpha0 = -2.3649037e-012 ++walpha0 = -1.3260696e-013 ++palpha0 = 6.6303478e-020 ++alpha1 = 0 ++beta0 = 21.036008 ++lbeta0 = -1.1603265e-007 ++wbeta0 = 4.1231608e-007 ++pbeta0 = -2.8990433e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.4079911 ++lkt1 = 3.1845551e-008 ++wkt1 = 3.0571729e-008 ++pkt1 = -1.5285865e-014 ++kt1l = 0 ++kt2 = -0.031229592 ++lkt2 = 4.9897959e-009 ++wkt2 = 5.2016327e-009 ++pkt2 = -2.6008163e-015 ++ute = -1.4342857 ++wute = 4.0457143e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8098294e-018 ++lub1 = -1.7578531e-025 ++wub1 = 5.9506678e-026 ++pub1 = -2.9753339e-032 ++uc1 = -1.1888774e-010 ++luc1 = 3.1443869e-017 ++wuc1 = 3.0186115e-017 ++puc1 = -1.5093057e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64923469 ++lvth0 = 1.325026e-008 ++wvth0 = -4.067414e-009 ++pvth0 = -1.1596488e-014 ++k1 = 0.79418892 ++lk1 = -3.5489221e-008 ++wk1 = 8.3746286e-010 ++pk1 = -8.3746286e-015 ++k2 = -0.0057236965 ++lk2 = -4.6356351e-009 ++wk2 = -2.005398e-009 ++pk2 = 2.7051485e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036490513 ++lu0 = -1.4308442e-009 ++wu0 = -1.2698026e-009 ++pu0 = 1.3295688e-015 ++ua = -7.881063e-010 ++lua = 2.1903156e-016 ++wua = -7.0891948e-018 ++pua = 8.5070338e-024 ++ub = 3.0594896e-018 ++lub = -6.4298182e-025 ++wub = -1.6806265e-025 ++pub = 8.4187636e-032 ++uc = 9.7557278e-011 ++luc = -1.4633922e-017 ++wuc = -8.460177e-018 ++puc = 5.071119e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.2333595 ++la0 = -7.4559545e-007 ++ags = 0.28370796 ++lags = 1.3402325e-007 ++wags = -1.501953e-008 ++pags = 6.3697932e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22708279 ++lpclm = 2.9060649e-008 ++wpclm = -1.603574e-008 ++ppclm = 1.9242888e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0921047e-005 ++lalpha0 = -1.0329047e-010 ++walpha0 = 1.0548281e-014 ++palpha0 = -1.0548281e-019 ++alpha1 = 0 ++beta0 = 24.039866 ++lbeta0 = -3.7206623e-006 ++wbeta0 = 1.9555512e-007 ++pbeta0 = -2.9791169e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33923366 ++lkt1 = -5.0663377e-008 ++wkt1 = -2.4318421e-009 ++pkt1 = 2.4318421e-014 ++kt1l = 0 ++kt2 = -0.021803571 ++lkt2 = -6.3214286e-009 ++wkt2 = 5.0571429e-010 ++pkt2 = 3.0342857e-015 ++ute = -1.7216234 ++lute = 3.448052e-007 ++wute = 1.7837922e-007 ++pute = -1.6550649e-013 ++ua1 = 1.675e-009 ++ub1 = -3.5465249e-018 ++lub1 = 7.0824935e-025 ++wub1 = 5.1661197e-025 ++pub1 = -5.7827969e-031 ++uc1 = -5.0997566e-011 ++luc1 = -5.0024338e-017 ++wuc1 = -2.4011682e-018 ++puc1 = 2.4011682e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.65055971 ++wvth0 = -5.2270629e-009 ++k1 = 0.79064 ++k2 = -0.00618726 ++wk2 = -1.7348832e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036347429 ++wu0 = -1.1368457e-009 ++ua = -7.6620314e-010 ++wua = -6.2384914e-018 ++ub = 2.9951914e-018 ++wub = -1.5964389e-025 ++uc = 9.6093886e-011 ++wuc = -7.9530651e-018 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1588 ++ags = 0.29711029 ++wags = -8.6497371e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.22998886 ++wpclm = -1.4111451e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6678 ++wbeta0 = 1.92576e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.022435714 ++wkt2 = 8.0914286e-010 ++ute = -1.6871429 ++wute = 1.6182857e-007 ++ua1 = 1.675e-009 ++ub1 = -3.4757e-018 ++wub1 = 4.58784e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.75419347 ++lvth0 = -5.5747725e-008 ++wvth0 = -5.7737207e-008 ++pvth0 = 1.824977e-014 ++k1 = 0.95060511 ++lk1 = -9.5597554e-008 ++wk1 = 1.0355446e-008 ++pk1 = -5.177723e-015 ++k2 = 0.013945175 ++lk2 = -3.0232209e-008 ++wk2 = 1.9443834e-008 ++pk2 = -5.4442735e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12424632 ++lvoff = 6.8691116e-010 ++wvoff = 3.5791497e-008 ++pvoff = -6.8553733e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046898182 ++lu0 = 1.7050207e-010 ++wu0 = -1.6262868e-008 ++pu0 = 4.1983839e-015 ++ua = -6.6207759e-010 ++lua = 2.5458994e-016 ++wua = 5.6335718e-017 ++pua = 1.7471409e-022 ++ub = 3.7962141e-018 ++lub = -3.3240512e-025 ++wub = -1.6693412e-024 ++pub = 4.2239319e-032 ++uc = 2.9436835e-010 ++luc = -6.8059408e-017 ++wuc = -1.6002278e-016 ++puc = 3.2259428e-023 ++eu = 1.67 ++vsat = 85682.645 ++lvsat = -0.00034132231 ++wvsat = -0.0068127934 ++pvsat = 3.4063967e-009 ++a0 = 0.10362636 ++la0 = -8.0818182e-010 ++ags = 0.2705431 ++lags = 3.2753448e-008 ++wags = 1.3273025e-007 ++pags = -6.6365124e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12424077 ++lketa = 2.9920384e-008 ++wketa = -4.1694295e-009 ++pketa = 2.0847148e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.20476889 ++lpclm = -9.798626e-009 ++wpclm = 2.8042187e-007 ++ppclm = -5.8632603e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.5953123e-006 ++lalpha0 = -2.5435614e-013 ++walpha0 = 1.1428461e-013 ++palpha0 = -5.7142305e-020 ++alpha1 = 0 ++beta0 = 21.140586 ++wbeta0 = -5.6473191e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.59809917 ++lnoff = 1.2990496e-006 ++wnoff = 3.065757e-006 ++pnoff = -1.5328785e-012 ++voffcv = 0.22872521 ++lvoffcv = -1.118626e-007 ++wvoffcv = -2.6399574e-007 ++pvoffcv = 1.3199787e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28115299 ++lkt1 = -1.0099496e-008 ++wkt1 = -1.2105482e-007 ++pkt1 = 3.5188078e-014 ++kt1l = 0 ++kt2 = -0.025449687 ++lkt2 = 9.6575269e-010 ++wkt2 = 8.9970236e-009 ++pkt2 = -3.1602845e-015 ++ute = -1.5701136 ++wute = 2.0073409e-007 ++ua1 = 1.675e-009 ++ub1 = -5.3788142e-018 ++lub1 = 4.827456e-025 ++wub1 = 2.1072821e-024 ++pub1 = -3.1500653e-031 ++uc1 = -2.2938539e-010 ++luc1 = 4.973267e-017 ++wuc1 = 2.0459475e-016 ++puc1 = -5.8684551e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.66260505 ++lvth0 = -9.953513e-009 ++wvth0 = 3.6992425e-009 ++pvth0 = -1.2468455e-014 ++k1 = 0.75941 ++k2 = 0.017155231 ++lk2 = -3.1837237e-008 ++wk2 = -6.1109193e-009 ++pk2 = 7.3331031e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10253679 ++lvoff = -1.0167857e-008 ++wvoff = -1.5771964e-008 ++pvoff = 1.8926357e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038465008 ++lu0 = 4.387089e-009 ++wu0 = -8.4602728e-009 ++pu0 = 2.9708645e-016 ++ua = -9.289245e-010 ++lua = 3.880134e-016 ++wua = -2.8983135e-016 ++pua = 3.4779762e-022 ++ub = 3.4725304e-018 ++lub = -1.7056325e-025 ++wub = -6.6767982e-025 ++pub = -4.5859137e-031 ++uc = 1.5722431e-010 ++luc = 5.1261039e-019 ++wuc = -8.5272224e-017 ++puc = -5.1158517e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.57970277 ++la0 = -2.3884638e-007 ++wa0 = 4.6802014e-007 ++pa0 = -2.3401007e-013 ++ags = 0.63340774 ++lags = -1.4867887e-007 ++wags = -1.6558842e-007 ++pags = 8.279421e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.047719 ++lpclm = 6.8726318e-008 ++wpclm = 1.7942187e-007 ++ppclm = -8.1325983e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7040286e-006 ++lalpha0 = -2.3087143e-012 ++alpha1 = 0 ++beta0 = 21.043581 ++lbeta0 = 4.8502597e-008 ++wbeta0 = 4.0337993e-007 ++pbeta0 = -4.8405592e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30297354 ++lkt1 = 8.1077922e-010 ++wkt1 = -9.3348999e-008 ++pkt1 = 2.1335166e-014 ++kt1l = 0 ++kt2 = -0.021799026 ++lkt2 = -8.5957792e-010 ++wkt2 = -5.9264351e-009 ++pkt2 = 4.3014448e-015 ++ute = -1.5701136 ++wute = 2.0073409e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0334126e-018 ++lub1 = -6.899552e-025 ++wub1 = 3.2333483e-025 ++pub1 = 5.7696713e-031 ++uc1 = -1.4511739e-010 ++luc1 = 7.5986727e-018 ++wuc1 = 6.1137104e-017 ++puc1 = 1.3044275e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64815901 ++lvth0 = 7.3817355e-009 ++wvth0 = -2.7981116e-009 ++pvth0 = -4.6716298e-015 ++k1 = 0.79747612 ++lk1 = -4.5679339e-008 ++wk1 = -3.0414256e-009 ++pk1 = 3.6497107e-015 ++k2 = -0.0074231864 ++lk2 = -2.3431364e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040494054 ++lu0 = 1.9522345e-009 ++wu0 = -5.9939808e-009 ++pu0 = -2.662464e-015 ++ua = -8.1072595e-010 ++lua = 2.4617513e-016 ++wua = 1.9601988e-017 ++pua = -2.3522386e-023 ++ub = 3.1895805e-018 ++lub = 1.6897655e-025 ++wub = -3.2156993e-025 ++pub = -8.7392324e-031 ++uc = 1.0432829e-010 ++luc = 6.3987831e-017 ++wuc = -1.6449976e-017 ++puc = -8.7702549e-023 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.175342 ++la0 = -9.536135e-007 ++wa0 = 6.8460666e-008 ++pa0 = 2.454613e-013 ++ags = 0.26729169 ++lags = 2.9066039e-007 ++wags = 4.3516718e-009 ++pags = -1.211339e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23344442 ++lpclm = -1.5414418e-007 ++wpclm = -2.3542459e-008 ++ppclm = 2.3542459e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0929986e-005 ++lalpha0 = -1.0337986e-010 ++alpha1 = 0 ++beta0 = 24.512311 ++lbeta0 = -4.1139731e-006 ++wbeta0 = -3.6192965e-007 ++pbeta0 = 4.3431558e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.128874 ++lnoff = -1.5464876e-007 ++wnoff = -1.5207128e-007 ++pnoff = 1.8248554e-013 ++voffcv = -0.065880682 ++lvoffcv = 8.5056818e-008 ++wvoffcv = 8.3639205e-008 ++pvoffcv = -1.0036705e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31506405 ++lkt1 = 1.5319401e-008 ++wkt1 = -3.095198e-008 ++pkt1 = -5.3541257e-014 ++kt1l = 0 ++kt2 = -0.016812862 ++lkt2 = -6.8429752e-009 ++wkt2 = -5.3833233e-009 ++pkt2 = 3.6497107e-015 ++ute = -1.5472572 ++lute = -2.7427686e-008 ++wute = -2.7372831e-008 ++pute = 2.7372831e-013 ++ua1 = 1.6533492e-009 ++lua1 = 2.5980992e-017 ++wua1 = 2.5547975e-017 ++pua1 = -3.065757e-023 ++ub1 = -2.1483391e-018 ++lub1 = -1.7520434e-024 ++wub1 = -1.1332474e-024 ++pub1 = 2.3248657e-030 ++uc1 = -4.4711114e-011 ++luc1 = -1.1288886e-016 ++wuc1 = -9.8191818e-018 ++puc1 = 9.8191818e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64889718 ++wvth0 = -3.2652745e-009 ++k1 = 0.79290818 ++wk1 = -2.6764545e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040689277 ++wu0 = -6.2602272e-009 ++ua = -7.8610843e-010 ++wua = 1.7249749e-017 ++ub = 3.2064782e-018 ++wub = -4.0896225e-025 ++uc = 1.1072708e-010 ++wuc = -2.5220231e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.0799807 ++wa0 = 9.3006796e-008 ++ags = 0.29635773 ++wags = -7.7617182e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.100914 ++wbeta0 = -3.1849809e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1134091 ++wnoff = -1.3382273e-007 ++voffcv = -0.057375 ++wvoffcv = 7.36025e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31353211 ++wkt1 = -3.6306106e-008 ++kt1l = 0 ++kt2 = -0.017497159 ++wkt2 = -5.0183523e-009 ++ute = -1.55 ++ua1 = 1.6559473e-009 ++wua1 = 2.2482218e-017 ++ub1 = -2.3235434e-018 ++wub1 = -9.0076078e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.74840818 ++lvth0 = -5.3919091e-008 ++k1 = 0.95164273 ++lk1 = -9.6116364e-008 ++k2 = 0.015893454 ++lk2 = -3.0777727e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045268636 ++lu0 = 5.9118182e-010 ++ua = -6.5643273e-010 ++lua = 2.7209636e-016 ++ub = 3.6289455e-018 ++lub = -3.2817273e-025 ++uc = 2.78334e-010 ++luc = -6.4827e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.13211844 ++la0 = -1.5054221e-008 ++wa0 = -2.8435094e-007 ++pa0 = 1.4217547e-013 ++ags = 0.46155061 ++lags = -6.2750307e-008 ++wags = -1.7735247e-006 ++pags = 8.8676235e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12105603 ++lketa = 2.8328017e-008 ++wketa = -3.5953066e-008 ++pketa = 1.7976533e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23286727 ++lpclm = -1.5673636e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6067636e-006 ++lalpha0 = -2.6008182e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.3e-010 ++cgdo = 2.3e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.29090909 ++lnoff = 1.1454545e-006 ++voffcv = 0.20227273 ++lvoffcv = -9.8636364e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29328273 ++lkt1 = -6.5736364e-009 ++kt1l = 0 ++kt2 = -0.024548182 ++lkt2 = 6.4909091e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.1676636e-018 ++lub1 = 4.5118182e-025 ++uc1 = -2.0888491e-010 ++luc1 = 4.3852454e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.66297571 ++lvth0 = -1.1202857e-008 ++k1 = 0.75941 ++k2 = 0.016542914 ++lk2 = -3.1102457e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10411714 ++lvoff = -8.2714286e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.037617286 ++lu0 = 4.4168571e-009 ++ua = -9.5796571e-010 ++lua = 4.2286286e-016 ++ub = 3.4056286e-018 ++lub = -2.1651429e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.62659857 ++la0 = -2.6229429e-007 ++ags = 0.61681571 ++lags = -1.4038286e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.065697143 ++lpclm = 6.7911429e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7040286e-006 ++lalpha0 = -2.3087143e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31232714 ++lkt1 = 2.9485714e-009 ++kt1l = 0 ++kt2 = -0.022392857 ++lkt2 = -4.2857143e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -3.0010143e-018 ++lub1 = -6.3214286e-025 ++uc1 = -1.3899143e-010 ++luc1 = 8.9057143e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64787864 ++lvth0 = 6.9136364e-009 ++k1 = 0.79717136 ++lk1 = -4.5313636e-008 ++k2 = -0.0074231864 ++lk2 = -2.3431364e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.039893455 ++lu0 = 1.6854546e-009 ++ua = -8.0876182e-010 ++lua = 2.4381818e-016 ++ub = 3.1573591e-018 ++lub = 8.1409091e-026 ++uc = 1.0268e-010 ++luc = 5.52e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1822018 ++la0 = -9.2901818e-007 ++ags = 0.26772773 ++lags = 2.7852273e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23108545 ++lpclm = -1.3055455e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0929986e-005 ++lalpha0 = -1.0337986e-010 ++alpha1 = 0 ++beta0 = 24.476046 ++lbeta0 = -4.0704545e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1136364 ++lnoff = -1.3636364e-007 ++voffcv = -0.0575 ++lvoffcv = 7.5e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31816545 ++lkt1 = 9.9545454e-009 ++kt1l = 0 ++kt2 = -0.017352273 ++lkt2 = -6.4772727e-009 ++ute = -1.55 ++ua1 = 1.6559091e-009 ++lua1 = 2.2909091e-017 ++ub1 = -2.2618909e-018 ++lub1 = -1.5190909e-024 ++uc1 = -4.5695e-011 ++luc1 = -1.0305e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8e-009 ++toxp = 8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64857 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.3e-010 ++cgdo = 2.3e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +*resistor + +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + +.endl nmos_3p3_t +* +* +.lib nmos_3p3_f + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.63571386 ++lvth0 = -3.5583899e-008 ++wvth0 = -1.5283991e-008 ++pvth0 = 4.2939034e-016 ++k1 = 0.94866818 ++lk1 = -9.1790218e-008 ++k2 = 0.052196642 ++lk2 = -3.8749265e-008 ++wk2 = -2.0007159e-008 ++pk2 = 5.3018972e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12637972 ++lvoff = 3.7549747e-009 ++wvoff = 5.5172608e-009 ++pvoff = -1.4620741e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.023697233 ++lu0 = 4.3334833e-009 ++wu0 = 4.8629688e-009 ++pu0 = -6.4086508e-016 ++ua = -1.1068315e-009 ++lua = 6.5818091e-016 ++wua = 2.7394695e-016 ++pua = -1.3923626e-022 ++ub = 3.334019e-018 ++lub = -7.3464598e-025 ++wub = -4.2815738e-025 ++pub = 9.1163863e-032 ++uc = 2.2336e-010 ++luc = -5.6852041e-017 ++wuc = -3.4293319e-017 ++puc = 5.3597361e-024 ++eu = 1.67 ++vsat = 99670.454 ++lvsat = -0.0026289205 ++wvsat = -8.3522727e-005 ++pvsat = 1.288171e-009 ++a0 = 0.11226647 ++la0 = -3.0545135e-009 ++wa0 = -6.4797433e-009 ++pa0 = 1.717132e-015 ++ags = 0.31756239 ++lags = -1.270937e-008 ++wags = 4.9972817e-008 ++pags = -1.2018636e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.14562336 ++lketa = 3.5879506e-008 ++wketa = 8.4725454e-009 ++pketa = -2.3874103e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.36674716 ++lpclm = -4.4233047e-008 ++wpclm = 2.3523508e-008 ++ppclm = 8.4289324e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0039772727 ++ldelta = 2.9210227e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6143989e-006 ++lalpha0 = -2.787532e-013 ++walpha0 = 5.071667e-014 ++palpha0 = -1.3439918e-020 ++alpha1 = 0 ++beta0 = 19.904932 ++lbeta0 = 1.1800932e-007 ++wbeta0 = 1.4853682e-007 ++pbeta0 = 8.5878068e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.45807784 ++lkt1 = 3.950099e-008 ++wkt1 = 3.3399235e-008 ++pkt1 = -8.5148105e-015 ++kt1l = 0 ++kt2 = -0.024703182 ++lkt2 = 1.1800932e-009 ++wkt2 = 1.1018318e-009 ++pkt2 = -2.9198543e-016 ++ute = -1.5681818 ++lute = 8.7630682e-008 ++wute = 1.0690909e-007 ++pute = -4.2939034e-014 ++ua1 = 1.675e-009 ++ub1 = -4.197971e-018 ++lub1 = 2.6939132e-025 ++wub1 = 3.5239491e-025 ++pub1 = -5.6572177e-032 ++uc1 = -4.2111364e-011 ++luc1 = -3.6804886e-018 ++wuc1 = -6.8054318e-018 ++puc1 = 1.8034394e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.60850921 ++lvth0 = -2.2389644e-008 ++wvth0 = -1.320417e-008 ++pvth0 = -5.793228e-016 ++k1 = 0.74656121 ++lk1 = 6.2316611e-009 ++k2 = 0.02341267 ++lk2 = -2.4789039e-008 ++wk2 = -3.3025902e-009 ++pk2 = -2.7998188e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11298759 ++lvoff = -2.7402067e-009 ++wvoff = 1.8245588e-009 ++pvoff = 3.2888638e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.029624466 ++lu0 = 1.4587752e-009 ++wu0 = 9.5169113e-010 ++pu0 = 1.2561046e-015 ++ua = -1.2817297e-009 ++lua = 7.4300653e-016 ++wua = 4.9864474e-017 ++pua = -3.055626e-023 ++ub = 3.0706704e-018 ++lub = -6.0692192e-025 ++wub = -3.1666793e-026 ++pub = -1.0113407e-031 ++uc = 8.4652626e-011 ++luc = 1.0421037e-017 ++wuc = 2.0802857e-018 ++puc = -1.2281462e-023 ++eu = 1.67 ++vsat = 91287.5 ++lvsat = 0.0014368125 ++wvsat = -0.001782375 ++pvsat = 2.1121144e-009 ++a0 = 1.0792115 ++la0 = -4.7202287e-007 ++wa0 = -5.5074584e-008 ++pa0 = 2.528563e-014 ++ags = 0.47190495 ++lags = -8.7565511e-008 ++wags = 4.6151516e-008 ++pags = -1.0165305e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028193589 ++lketa = -2.1073934e-008 ++wketa = -7.8161737e-009 ++pketa = 5.5126185e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.080786018 ++lpclm = 9.4458106e-008 ++wpclm = 4.6980911e-008 ++ppclm = -2.9479082e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00138165 ++lpdiblc2= 8.6783475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015357143 ++ldelta = 4.1051786e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.5170032e-006 ++lalpha0 = -2.1715163e-012 ++walpha0 = -1.5939525e-014 ++palpha0 = 1.8888337e-020 ++alpha1 = 0 ++beta0 = 22.630402 ++lbeta0 = -1.2038436e-006 ++wbeta0 = -3.6916688e-007 ++pbeta0 = 2.5194507e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33938118 ++lkt1 = -1.8066891e-008 ++wkt1 = -2.4102225e-009 ++pkt1 = 8.8527765e-015 ++kt1l = 0 ++kt2 = -0.020331679 ++lkt2 = -9.4008589e-010 ++wkt2 = -3.52275e-011 ++pkt2 = 2.5948834e-016 ++ute = -1.3875 ++wute = 1.8375e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8207275e-018 ++lub1 = -3.9857179e-025 ++wub1 = 6.3173775e-026 ++pub1 = 8.3700075e-032 ++uc1 = -6.0365e-011 ++luc1 = 5.172525e-018 ++wuc1 = 2.13885e-018 ++puc1 = -2.5345373e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.59197793 ++lvth0 = -2.8000692e-009 ++wvth0 = -1.0403021e-008 ++pvth0 = -3.8986845e-015 ++k1 = 0.79586747 ++lk1 = -5.2196247e-008 ++k2 = 0.0064105499 ++lk2 = -4.6415264e-009 ++wk2 = -7.9923454e-009 ++pk2 = 2.757541e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12651327 ++lvoff = 1.3287723e-008 ++wvoff = 2.231366e-009 ++pvoff = -1.5318025e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032375092 ++lu0 = -1.8007167e-009 ++wu0 = 7.2111957e-010 ++pu0 = 1.5293319e-015 ++ua = -8.1585861e-010 ++lua = 1.9094925e-016 ++wua = 6.5067587e-018 ++pua = 2.0822632e-023 ++ub = 2.744187e-018 ++lub = -2.2003905e-025 ++wub = -1.7352055e-026 ++pub = -1.1809703e-031 ++uc = 9.9386407e-011 ++luc = -7.0384932e-018 ++wuc = -9.5351961e-018 ++puc = 1.4828837e-024 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.2231563 ++la0 = -6.4259738e-007 ++wa0 = 4.5429264e-009 ++pa0 = -4.536112e-014 ++ags = 0.25832779 ++lags = 1.6552342e-007 ++wags = -2.7327843e-009 ++pags = 4.7762591e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019621922 ++lketa = -3.123136e-008 ++wketa = -7.1103921e-010 ++pketa = -2.9069659e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.18891787 ++lpclm = -3.3678143e-008 ++wpclm = 2.3733463e-009 ++ppclm = 4.9912056e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064234716 ++lpdiblc2= 1.7439086e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027306818 ++ldelta = 2.689142e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.4353703e-005 ++lalpha0 = -8.2558005e-011 ++walpha0 = 8.0653667e-012 ++palpha0 = -9.5574596e-018 ++alpha1 = 0 ++beta0 = 24.194431 ++lbeta0 = -3.0572184e-006 ++wbeta0 = 1.2157547e-007 ++pbeta0 = -3.2958461e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32825519 ++lkt1 = -3.1251192e-008 ++wkt1 = -7.8619588e-009 ++pkt1 = 1.5313084e-014 ++kt1l = 0 ++kt2 = -0.021125 ++wkt2 = 1.8375e-010 ++ute = -1.3875 ++wute = 1.8375e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5198788e-018 ++lub1 = -7.5507747e-025 ++wub1 = 2.4014016e-026 ++pub1 = 1.3010439e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.5916975 ++wvth0 = -1.0793475e-008 ++k1 = 0.79064 ++k2 = 0.0059457 ++wk2 = -7.716177e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.1251825 ++wvoff = 2.216025e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.03219475 ++wu0 = 8.742825e-010 ++ua = -7.96735e-010 ++wua = 8.59215e-018 ++ub = 2.72215e-018 ++wub = -2.91795e-026 ++uc = 9.86815e-011 ++wuc = -9.386685e-018 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.1588 ++ags = 0.274905 ++wags = 2.05065e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.02274975 ++wketa = -1.0021725e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.185545 ++wpclm = 7.37205e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.60855e-005 ++walpha0 = 7.108185e-012 ++alpha1 = 0 ++beta0 = 23.88825 ++wbeta0 = 8.85675e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.331385 ++wkt1 = -6.32835e-009 ++kt1l = 0 ++kt2 = -0.021125 ++wkt2 = 1.8375e-010 ++ute = -1.3875 ++wute = 1.8375e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5955e-018 ++wub1 = 3.7044e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.6494457 ++lvth0 = -3.8570937e-008 ++wvth0 = -2.2012593e-008 ++pvth0 = 1.8930389e-015 ++k1 = 0.94866818 ++lk1 = -9.1790218e-008 ++k2 = 0.037416157 ++lk2 = -3.4832437e-008 ++wk2 = -1.2764722e-008 ++pk2 = 3.3826512e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.080003796 ++lvoff = -8.5346442e-009 ++wvoff = -1.720694e-008 ++pvoff = 4.5598392e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.033441305 ++lu0 = 3.7009358e-009 ++wu0 = 8.8373727e-011 ++pu0 = -3.3091682e-016 ++ua = -5.8760066e-010 ++lua = 3.665866e-016 ++wua = 1.9523816e-017 ++pua = 3.6449515e-024 ++ub = 2.2723958e-018 ++lub = -7.8888061e-026 ++wub = 9.2037981e-026 ++pub = -2.3015752e-031 ++uc = 1.5510632e-010 ++luc = -3.141186e-017 ++wuc = -8.4901632e-019 ++puc = -7.1059521e-024 ++eu = 1.67 ++vsat = 79409.091 ++lvsat = 0.0039725909 ++wvsat = 0.0098445454 ++pvsat = -1.9465696e-009 ++a0 = 0.10668786 ++la0 = -1.5761839e-009 ++wa0 = -3.7462282e-009 ++pa0 = 9.9275047e-016 ++ags = 0.3531832 ++lags = -1.0591044e-008 ++wags = 3.2518616e-008 ++pags = -1.3056615e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12161181 ++lketa = 2.774773e-008 ++wketa = -3.293114e-009 ++pketa = 1.5971603e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.45094152 ++lpclm = -7.3917648e-008 ++wpclm = -1.773173e-008 ++ppclm = 2.2974387e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0039772727 ++ldelta = 2.9210227e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.618997e-006 ++lalpha0 = -2.5821257e-013 ++walpha0 = 4.8463561e-014 ++palpha0 = -2.3504827e-020 ++alpha1 = 0 ++beta0 = 20.979752 ++lbeta0 = -8.3833352e-008 ++wbeta0 = -3.781252e-007 ++pbeta0 = 9.9761689e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37582777 ++lkt1 = 1.529097e-008 ++wkt1 = -6.9032982e-009 ++pkt1 = 3.3480996e-015 ++kt1l = 0 ++kt2 = -0.014896384 ++lkt2 = -3.0815037e-009 ++wkt2 = -3.7034991e-009 ++pkt2 = 1.7961971e-015 ++ute = -1.435 ++wute = 4.165e-008 ++ua1 = 1.675e-009 ++ub1 = -3.6336059e-018 ++lub1 = 2.2901987e-025 ++wub1 = 7.5856009e-026 ++pub1 = -3.6790164e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.60479255 ++lvth0 = -1.6914157e-008 ++wvth0 = -1.1383005e-008 ++pvth0 = -3.2623115e-015 ++k1 = 0.76840415 ++lk1 = -4.3621628e-009 ++wk1 = -1.0703038e-008 ++pk1 = 5.1909737e-015 ++k2 = 0.0076001761 ++lk2 = -2.0371686e-008 ++wk2 = 4.4455318e-009 ++pk2 = -4.9643217e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12030052 ++lvoff = 1.1009268e-008 ++wvoff = 5.4078955e-009 ++pvoff = -6.4083562e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031302452 ++lu0 = 4.7382792e-009 ++wu0 = 1.2947795e-010 ++pu0 = -3.5085237e-016 ++ua = -1.1417323e-009 ++lua = 6.3534043e-016 ++wua = -1.8734289e-017 ++pua = 2.2200133e-023 ++ub = 2.813393e-018 ++lub = -3.412717e-025 ++wub = 9.439913e-026 ++pub = -2.3130267e-031 ++uc = 8.2040368e-011 ++luc = 4.0251276e-018 ++wuc = 3.3602922e-018 ++puc = -9.1474668e-024 ++eu = 1.67 ++vsat = 95895 ++lvsat = -0.004023075 ++wvsat = -0.00404005 ++pvsat = 4.7874593e-009 ++a0 = 0.9644116 ++la0 = -4.175722e-007 ++wa0 = 1.177386e-009 ++pa0 = -1.3952024e-015 ++ags = 0.43863251 ++lags = -5.2033959e-008 ++wags = 6.2455008e-008 ++pags = -2.7575765e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.044144964 ++lketa = -9.8236923e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.21857359 ++lpclm = 3.8780801e-008 ++wpclm = -2.0534997e-008 ++ppclm = 2.4333971e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00138165 ++lpdiblc2= 8.6783475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015357143 ++ldelta = 4.1051786e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7595967e-006 ++lalpha0 = -2.2664034e-012 ++walpha0 = -1.3481034e-013 ++palpha0 = 6.5383015e-020 ++alpha1 = 0 ++beta0 = 21.025956 ++lbeta0 = -1.0624202e-007 ++wbeta0 = 4.170117e-007 ++pbeta0 = -2.8587971e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.40772797 ++lkt1 = 3.0762566e-008 ++wkt1 = 3.1079706e-008 ++pkt1 = -1.5073657e-014 ++kt1l = 0 ++kt2 = -0.031195536 ++lkt2 = 4.8235848e-009 ++wkt2 = 5.2880625e-009 ++pkt2 = -2.5647103e-015 ++ute = -1.435 ++wute = 4.165e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8152615e-018 ++lub1 = -1.6787717e-025 ++wub1 = 6.0495435e-026 ++pub1 = -2.9340286e-032 ++uc1 = -1.1862793e-010 ++luc1 = 3.0374545e-017 ++wuc1 = 3.0687684e-017 ++puc1 = -1.4883527e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.57932332 ++lvth0 = 1.3266882e-008 ++wvth0 = -4.2022626e-009 ++pvth0 = -1.1771491e-014 ++k1 = 0.79412996 ++lk1 = -3.4847247e-008 ++wk1 = 8.5137806e-010 ++pk1 = -8.5010099e-015 ++k2 = -0.0056941447 ++lk2 = -4.6179157e-009 ++wk2 = -2.061045e-009 ++pk2 = 2.7459718e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12195946 ++lvoff = 1.297511e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036511114 ++lu0 = -1.433985e-009 ++wu0 = -1.3055311e-009 ++pu0 = 1.3496333e-015 ++ua = -7.8770753e-010 ++lua = 2.1582113e-016 ++wua = -7.2872686e-018 ++pua = 8.6354133e-024 ++ub = 3.0616512e-018 ++lub = -6.3545771e-025 ++wub = -1.7290955e-025 ++pub = 8.5458111e-032 ++uc = 9.7688241e-011 ++luc = -1.4517602e-017 ++wuc = -8.703095e-018 ++puc = 5.1476471e-024 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.2324275 ++la0 = -7.351711e-007 ++ags = 0.28413926 ++lags = 1.3104055e-007 ++wags = -1.5380403e-008 ++pags = 6.4659197e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021073023 ++lketa = -3.7163943e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22740181 ++lpclm = 2.8319355e-008 ++wpclm = -1.6483783e-008 ++ppclm = 1.9533282e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064234716 ++lpdiblc2= 1.7439086e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027306818 ++ldelta = 2.689142e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.079175e-005 ++lalpha0 = -1.018445e-010 ++walpha0 = 1.072355e-014 ++palpha0 = -1.0707464e-019 ++alpha1 = 0 ++beta0 = 24.031764 ++lbeta0 = -3.6681242e-006 ++wbeta0 = 2.0128262e-007 ++pbeta0 = -3.0240747e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33925459 ++lkt1 = -5.0378387e-008 ++wkt1 = -2.4722493e-009 ++pkt1 = 2.468541e-014 ++kt1l = 0 ++kt2 = -0.021820469 ++lkt2 = -6.2858695e-009 ++wkt2 = 5.2452969e-010 ++pkt2 = 3.0800761e-015 ++ute = -1.7243381 ++lute = 3.4286561e-007 ++wute = 1.8342565e-007 ++pute = -1.6800415e-013 ++ua1 = 1.675e-009 ++ub1 = -3.5547478e-018 ++lub1 = 7.0841414e-025 ++wub1 = 5.3109983e-025 ++pub1 = -5.870065e-031 ++uc1 = -5.1018233e-011 ++luc1 = -4.9742943e-017 ++wuc1 = -2.4410658e-018 ++puc1 = 2.4374042e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.580652 ++wvth0 = -5.38118e-009 ++k1 = 0.79064 ++k2 = -0.00615663 ++wk2 = -1.7860353e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.0363675 ++wu0 = -1.170365e-009 ++ua = -7.66093e-010 ++wua = -6.42243e-018 ++ub = 2.99801e-018 ++wub = -1.643509e-025 ++uc = 9.62343e-011 ++wuc = -8.187557e-018 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.1588 ++ags = 0.297263 ++wags = -8.90477e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.230238 ++wpclm = -1.452752e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6644 ++wbeta0 = 1.98254e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.02245 ++wkt2 = 8.33e-010 ++ute = -1.69 ++wute = 1.666e-007 ++ua1 = 1.675e-009 ++ub1 = -3.4838e-018 ++wub1 = 4.72311e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.67826787 ++lvth0 = -5.1192629e-008 ++wvth0 = -5.631097e-008 ++pvth0 = 1.6912853e-014 ++k1 = 0.94035419 ++lk1 = -8.7757932e-008 ++wk1 = 9.8936502e-009 ++pk1 = -4.7984203e-015 ++k2 = 0.010689994 ++lk2 = -2.7750003e-008 ++wk2 = 1.9039412e-008 ++pk2 = -5.0454443e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12420249 ++lvoff = 6.3595312e-010 ++wvoff = 3.538951e-008 ++pvoff = -6.3531717e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046929878 ++lu0 = 1.5325411e-010 ++wu0 = -1.5963029e-008 ++pu0 = 3.8908244e-015 ++ua = -6.3486383e-010 ++lua = 2.3358646e-016 ++wua = 7.5766988e-017 ++pua = 1.6191512e-022 ++ub = 3.762013e-018 ++lub = -3.051927e-025 ++wub = -1.6806064e-024 ++pub = 3.9145008e-032 ++uc = 2.8720922e-010 ++luc = -6.2506115e-017 ++wuc = -1.5805146e-016 ++puc = 2.9896211e-023 ++eu = 1.67 ++vsat = 93151.55 ++lvsat = -0.00031600155 ++wvsat = -0.0065089804 ++pvsat = 3.1568555e-009 ++a0 = 0.10353977 ++la0 = -7.4193977e-010 ++ags = 0.27394573 ++lags = 3.0120571e-008 ++wags = 1.2681121e-007 ++pags = -6.1503437e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12103166 ++lketa = 2.7466355e-008 ++wketa = -3.983496e-009 ++pketa = 1.9319955e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.20348625 ++lpclm = -8.9497813e-009 ++wpclm = 2.7674005e-007 ++ppclm = -5.4337375e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0039772727 ++ldelta = 2.9210227e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.567968e-006 ++lalpha0 = -2.3346347e-013 ++walpha0 = 1.0918815e-013 ++palpha0 = -5.2956251e-020 ++alpha1 = 0 ++beta0 = 21.141066 ++wbeta0 = -5.7008843e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.46137913 ++lnoff = 1.1937689e-006 ++wnoff = 2.9290412e-006 ++pnoff = -1.420585e-012 ++voffcv = 0.21695209 ++lvoffcv = -1.0279677e-007 ++wvoffcv = -2.5222299e-007 ++pvoffcv = 1.2232815e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28213548 ++lkt1 = -9.299129e-009 ++wkt1 = -1.1839713e-007 ++pkt1 = 3.2610317e-014 ++kt1l = 0 ++kt2 = -0.025353566 ++lkt2 = 8.8905907e-010 ++wkt2 = 8.7405474e-009 ++pkt2 = -2.9287727e-015 ++ute = -1.5702841 ++wute = 2.0263807e-007 ++ua1 = 1.675e-009 ++ub1 = -5.3288522e-018 ++lub1 = 4.4342327e-025 ++wub1 = 2.0931991e-024 ++pub1 = -2.9193021e-031 ++uc1 = -2.2422528e-010 ++luc1 = 4.5702115e-017 ++wuc1 = 2.0018808e-016 ++puc1 = -5.4385517e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.59235333 ++lvth0 = -9.5240796e-009 ++wvth0 = 3.4196621e-009 ++pvth0 = -1.2056503e-014 ++k1 = 0.75941 ++k2 = 0.016364333 ++lk2 = -3.0502058e-008 ++wk2 = -5.9838153e-009 ++pk2 = 7.0908211e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10277799 ++lvoff = -9.7549306e-009 ++wvoff = -1.5443916e-008 ++pvoff = 1.830104e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038581863 ++lu0 = 4.2020412e-009 ++wu0 = -8.5330215e-009 ++pu0 = 2.8727087e-016 ++ua = -9.1898543e-010 ++lua = 3.7138544e-016 ++wua = -2.8380301e-016 ++pua = 3.3630657e-022 ++ub = 3.468843e-018 ++lub = -1.6300526e-025 ++wub = -6.8558634e-025 ++pub = -4.4343974e-031 ++uc = 1.5730964e-010 ++luc = 4.9517784e-019 ++wuc = -8.6210147e-017 ++puc = -4.9468266e-024 ++eu = 1.67 ++vsat = 92500 ++a0 = 0.57333915 ++la0 = -2.2859464e-007 ++wa0 = 4.665536e-007 ++pa0 = -2.262785e-013 ++ags = 0.62982962 ++lags = -1.4248312e-007 ++wags = -1.6506955e-007 ++pags = 8.0058731e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.044144964 ++lketa = -9.8236923e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.049284973 ++lpclm = 6.5837837e-008 ++wpclm = 1.8091845e-007 ++ppclm = -7.8639014e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00138165 ++lpdiblc2= 8.6783475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015357143 ++ldelta = 4.1051786e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6463107e-006 ++lalpha0 = -2.2114597e-012 ++alpha1 = 0 ++beta0 = 21.044461 ++lbeta0 = 4.6853149e-008 ++wbeta0 = 3.9498984e-007 ++pbeta0 = -4.6806296e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30287445 ++lkt1 = 7.5927144e-010 ++wkt1 = -9.3695983e-008 ++pkt1 = 2.0630263e-014 ++kt1l = 0 ++kt2 = -0.021815574 ++lkt2 = -8.2686693e-010 ++wkt2 = -5.8740916e-009 ++pkt2 = 4.1593273e-015 ++ute = -1.5702841 ++wute = 2.0263807e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0509483e-018 ++lub1 = -6.6136013e-025 ++wub1 = 3.4096267e-025 ++pub1 = 5.5790443e-031 ++uc1 = -1.4497962e-010 ++luc1 = 7.2679686e-018 ++wuc1 = 6.2046194e-017 ++puc1 = 1.2613299e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.57817062 ++lvth0 = 7.2824411e-009 ++wvth0 = -2.8305468e-009 ++pvth0 = -4.6500058e-015 ++k1 = 0.79742159 ++lk1 = -4.504374e-008 ++wk1 = -3.0656684e-009 ++pk1 = 3.632817e-015 ++k2 = -0.0074261153 ++lk2 = -2.3103764e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12195946 ++lvoff = 1.297511e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040501587 ++lu0 = 1.9271691e-009 ++wu0 = -6.0541938e-009 ++pu0 = -2.65014e-015 ++ua = -8.1043485e-010 ++lua = 2.4275299e-016 ++wua = 1.9758233e-017 ++pua = -2.3413506e-023 ++ub = 3.1900657e-018 ++lub = 1.6734577e-025 ++wub = -3.2572281e-025 ++pub = -8.6987803e-031 ++uc = 1.0442234e-010 ++luc = 6.3166633e-017 ++wuc = -1.6716674e-017 ++puc = -8.7296592e-023 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.1740916 ++la0 = -9.4048631e-007 ++wa0 = 6.9419757e-008 ++pa0 = 2.4432511e-013 ++ags = 0.26765145 ++lags = 2.8669802e-007 ++wags = 4.2400941e-009 ++pags = -1.205732e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021073023 ++lketa = -3.7163943e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23327148 ++lpclm = -1.5218617e-007 ++wpclm = -2.3468689e-008 ++ppclm = 2.3433486e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064234716 ++lpdiblc2= 1.7439086e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027306818 ++ldelta = 2.689142e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0800762e-005 ++lalpha0 = -1.0193448e-010 ++alpha1 = 0 ++beta0 = 24.507475 ++lbeta0 = -4.0568183e-006 ++wbeta0 = -3.6481453e-007 ++pbeta0 = 4.3230522e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1288096 ++lnoff = -1.5263937e-007 ++wnoff = -1.5328342e-007 ++pnoff = 1.8164085e-013 ++voffcv = -0.065845277 ++lvoffcv = 8.3951653e-008 ++wvoffcv = 8.430588e-008 ++pvoffcv = -9.9902467e-014 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31501857 ++lkt1 = 1.5150046e-008 ++wkt1 = -3.1313123e-008 ++pkt1 = -5.3293425e-014 ++kt1l = 0 ++kt2 = -0.016816848 ++lkt2 = -6.7503577e-009 ++wkt2 = -5.4297792e-009 ++pkt2 = 3.632817e-015 ++ute = -1.5472686 ++lute = -2.7273401e-008 ++wute = -2.7287058e-008 ++pute = 2.7246128e-013 ++ua1 = 1.65336e-009 ++lua1 = 2.5643414e-017 ++wua1 = 2.5751614e-017 ++pua1 = -3.0515663e-023 ++ub1 = -2.1495693e-018 ++lub1 = -1.7294942e-024 ++wub1 = -1.1410626e-024 ++pub1 = 2.3141044e-030 ++uc1 = -4.4843991e-011 ++luc1 = -1.1139275e-016 ++wuc1 = -9.7884135e-018 ++puc1 = 9.7737308e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.57889996 ++wvth0 = -3.2962459e-009 ++k1 = 0.79291046 ++wk1 = -2.7018409e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040694593 ++wu0 = -6.3196059e-009 ++ua = -7.8612308e-010 ++wua = 1.7413365e-017 ++ub = 3.2068255e-018 ++wub = -4.1284129e-025 ++uc = 1.1074849e-010 ++wuc = -2.5459447e-017 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.0799017 ++wa0 = 9.3888972e-008 ++ags = 0.29636432 ++wags = -7.8353386e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.101184 ++wbeta0 = -3.2151907e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1135227 ++wnoff = -1.3509204e-007 ++voffcv = -0.0574375 ++wvoffcv = 7.4300625e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31350128 ++wkt1 = -3.6650472e-008 ++kt1l = 0 ++kt2 = -0.017492898 ++wkt2 = -5.0659517e-009 ++ute = -1.55 ++ua1 = 1.6559282e-009 ++wua1 = 2.2695464e-017 ++ub1 = -2.3227785e-018 ++wub1 = -9.0930456e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.67263114 ++lvth0 = -4.9499651e-008 ++k1 = 0.94134454 ++lk1 = -8.8238255e-008 ++k2 = 0.012595841 ++lk2 = -2.8255053e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045331977 ++lu0 = 5.4272602e-010 ++ua = -6.2727955e-010 ++lua = 2.4979418e-016 ++ub = 3.5937841e-018 ++lub = -3.0127428e-025 ++uc = 2.7138825e-010 ++luc = -5.9513501e-017 ++eu = 1.67 ++vsat = 92500 ++a0 = 0.13050819 ++la0 = -1.3821621e-008 ++wa0 = -2.6941446e-007 ++pa0 = 1.3066601e-013 ++ags = 0.45484419 ++lags = -5.7615181e-008 ++wags = -1.6803644e-006 ++pags = 8.1497672e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.11802055 ++lketa = 2.6005966e-008 ++wketa = -3.4064511e-008 ++pketa = 1.6521288e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23118796 ++lpclm = -1.4388958e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0039772727 ++ldelta = 2.9210227e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.5788977e-006 ++lalpha0 = -2.387644e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.07e-010 ++cgdo = 2.07e-010 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.16818182 ++lnoff = 1.0515682e-006 ++voffcv = 0.19170454 ++lvoffcv = -9.0551705e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29398705 ++lkt1 = -6.034833e-009 ++kt1l = 0 ++kt2 = -0.024478636 ++lkt2 = 5.9588864e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.1193227e-018 ++lub1 = 4.1420102e-025 ++uc1 = -2.0418643e-010 ++luc1 = 4.0258119e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.59269564 ++lvth0 = -1.0730937e-008 ++k1 = 0.75941 ++k2 = 0.015765353 ++lk2 = -2.9792266e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10432393 ++lvoff = -7.9229946e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.037727707 ++lu0 = 4.230797e-009 ++ua = -9.4739414e-010 ++lua = 4.0504976e-016 ++ub = 3.4002157e-018 ++lub = -2.0739362e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 92500 ++a0 = 0.62004121 ++la0 = -2.5124514e-007 ++ags = 0.61330614 ++lags = -1.3446923e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.044144964 ++lketa = -9.8236923e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.067394929 ++lpclm = 6.505066e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00138165 ++lpdiblc2= 8.6783475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015357143 ++ldelta = 4.1051786e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6463107e-006 ++lalpha0 = -2.2114597e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31225343 ++lkt1 = 2.8243629e-009 ++kt1l = 0 ++kt2 = -0.022403571 ++lkt2 = -4.1051786e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -3.0168179e-018 ++lub1 = -6.0551384e-025 ++uc1 = -1.3876879e-010 ++luc1 = 8.5305611e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.57788728 ++lvth0 = 6.8169751e-009 ++k1 = 0.79711472 ++lk1 = -4.4680095e-008 ++k2 = -0.0074261153 ++lk2 = -2.3103764e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12195946 ++lvoff = 1.297511e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.039895561 ++lu0 = 1.6618898e-009 ++ua = -8.0845705e-010 ++lua = 2.404093e-016 ++ub = 3.1574609e-018 ++lub = 8.027089e-026 ++uc = 1.02749e-010 ++luc = 5.4428235e-017 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.1810406 ++la0 = -9.1602935e-007 ++ags = 0.26807588 ++lags = 2.7462863e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021073023 ++lketa = -3.7163943e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23092226 ++lpclm = -1.2872923e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064234716 ++lpdiblc2= 1.7439086e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027306818 ++ldelta = 2.689142e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0800762e-005 ++lalpha0 = -1.0193448e-010 ++alpha1 = 0 ++beta0 = 24.470957 ++lbeta0 = -4.0135445e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 7.7e-011 ++cgdo = 7.7e-011 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1134659 ++lnoff = -1.344571e-007 ++voffcv = -0.05740625 ++lvoffcv = 7.3951406e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31815301 ++lkt1 = 9.8153685e-009 ++kt1l = 0 ++kt2 = -0.017360369 ++lkt2 = -6.3867124e-009 ++ute = -1.55 ++ua1 = 1.6559377e-009 ++lua1 = 2.2588793e-017 ++ub1 = -2.2637898e-018 ++lub1 = -1.4978521e-024 ++uc1 = -4.5823812e-011 ++luc1 = -1.0160923e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.6e-009 ++toxp = 7.6e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.5e-008 ++xw = 1e-008 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.57857 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 92500 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.07e-010 ++cgdo = 2.07e-010 ++cgbo = 1e-013 ++cgdl = 9e-011 ++cgsl = 9e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +*resistor +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + + +.endl nmos_3p3_f +* +* +.lib nmos_3p3_s + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.78102964 ++lvth0 = -4.1963855e-008 ++wvth0 = -1.335093e-008 ++pvth0 = 4.4048385e-016 ++k1 = 0.97009364 ++lk1 = -1.0850207e-007 ++k2 = 0.057112207 ++lk2 = -4.4586066e-008 ++wk2 = -1.8436862e-008 ++pk2 = 5.4388743e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12611751 ++lvoff = 4.1027149e-009 ++wvoff = 5.0842288e-009 ++pvoff = -1.4998475e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.02365998 ++lu0 = 4.9752231e-009 ++wu0 = 4.3500625e-009 ++pu0 = -6.5742214e-016 ++ua = -1.2009004e-009 ++lua = 7.4602352e-016 ++wua = 2.6594489e-016 ++pua = -1.428335e-022 ++ub = 3.4181442e-018 ++lub = -8.4745491e-025 ++wub = -3.9003587e-025 ++pub = 9.3519126e-032 ++uc = 2.2972174e-010 ++luc = -6.5971448e-017 ++wuc = -3.0846577e-017 ++puc = 5.4982075e-024 ++eu = 1.67 ++vsat = 82709.416 ++lvsat = -0.002811599 ++wvsat = -0.00033342533 ++pvsat = 1.3214515e-009 ++a0 = 0.11164211 ++la0 = -3.216124e-009 ++wa0 = -5.9711692e-009 ++pa0 = 1.7614949e-015 ++ags = 0.33078713 ++lags = -1.7784597e-008 ++wags = 4.5802637e-008 ++pags = -1.2329143e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.15224321 ++lketa = 4.1863427e-008 ++wketa = 7.8363649e-009 ++pketa = -2.4490902e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.38126164 ++lpclm = -5.0349819e-008 ++wpclm = 1.8707045e-008 ++ppclm = 8.6466979e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0032954546 ++ldelta = 3.4528409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.689932e-006 ++lalpha0 = -3.3259243e-013 ++walpha0 = 4.6736083e-014 ++palpha0 = -1.3787144e-020 ++alpha1 = 0 ++beta0 = 19.906217 ++lbeta0 = 1.3969208e-007 ++wbeta0 = 1.2873117e-007 ++pbeta0 = 8.809677e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.46042018 ++lkt1 = 4.4736487e-008 ++wkt1 = 3.0709777e-008 ++pkt1 = -8.7347947e-015 ++kt1l = 0 ++kt2 = -0.024751234 ++lkt2 = 1.327864e-009 ++wkt2 = 1.0153526e-009 ++pkt2 = -2.9952902e-016 ++ute = -1.5659091 ++lute = 9.3719968e-008 ++wute = 1.0147727e-007 ++pute = -4.4048385e-014 ++ua1 = 1.675e-009 ++ub1 = -4.1897925e-018 ++lub1 = 3.0544077e-025 ++wub1 = 3.1727957e-025 ++pub1 = -5.8033747e-032 ++uc1 = -4.2656818e-011 ++luc1 = -3.9362386e-018 ++wuc1 = -6.2712955e-018 ++puc1 = 1.8500322e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.7471174 ++lvth0 = -2.4499049e-008 ++wvth0 = -1.1432769e-008 ++pvth0 = -5.4736891e-016 ++k1 = 0.74623593 ++lk1 = 6.7846468e-009 ++k2 = 0.024093133 ++lk2 = -2.7581243e-008 ++wk2 = -2.7392647e-009 ++pk2 = -2.6453883e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11249326 ++lvoff = -2.9137715e-009 ++wvoff = 1.5685135e-009 ++pvoff = 3.1074589e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.02972055 ++lu0 = 1.8540296e-009 ++wu0 = 7.6900741e-010 ++pu0 = 1.1868212e-015 ++ua = -1.310512e-009 ++lua = 8.0247348e-016 ++wua = 4.4658224e-017 ++pua = -2.8870859e-023 ++ub = 3.0972222e-018 ++lub = -6.8218008e-025 ++wub = -2.2900119e-026 ++pub = -9.5555786e-032 ++uc = 8.4637593e-011 ++luc = 8.7468885e-018 ++wuc = 2.3616893e-018 ++puc = -1.160405e-023 ++eu = 1.67 ++vsat = 73344.643 ++lvsat = 0.0020112589 ++wvsat = -0.0016424821 ++pvsat = 1.9956158e-009 ++a0 = 1.0928896 ++la0 = -5.0855857e-007 ++wa0 = -4.894097e-008 ++pa0 = 2.3890942e-014 ++ags = 0.48554907 ++lags = -9.7486997e-008 ++wags = 4.0512289e-008 ++pags = -9.6046138e-015 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028668661 ++lketa = -2.1777465e-008 ++wketa = -7.0328534e-009 ++pketa = 5.2085573e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.085016691 ++lpclm = 1.0221633e-007 ++wpclm = 4.0905118e-008 ++ppclm = -2.7853095e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00133635 ++lpdiblc2= 9.4484475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013214286 ++ldelta = 4.4694643e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6270642e-006 ++lalpha0 = -2.3602156e-012 ++walpha0 = -1.4688483e-014 ++palpha0 = 1.7846507e-020 ++alpha1 = 0 ++beta0 = 22.618932 ++lbeta0 = -1.2573561e-006 ++wbeta0 = -3.3178823e-007 ++pbeta0 = 2.3804846e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33899638 ++lkt1 = -1.7796768e-008 ++wkt1 = -2.4927001e-009 ++pkt1 = 8.3644811e-015 ++kt1l = 0 ++kt2 = -0.020292087 ++lkt2 = -9.6859676e-010 ++wkt2 = -4.2326378e-011 ++pkt2 = 2.4517566e-016 ++ute = -1.3839286 ++wute = 1.5946429e-008 ++ua1 = 1.675e-009 ++ub1 = -2.788493e-018 ++lub1 = -4.1622844e-025 ++wub1 = 5.1032672e-026 ++pub1 = 7.9083403e-032 ++uc1 = -6.0193571e-011 ++luc1 = 5.0951893e-018 ++wuc1 = 1.9709786e-018 ++puc1 = -2.394739e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72996498 ++lvth0 = -3.6588628e-009 ++wvth0 = -9.0195048e-009 ++pvth0 = -3.4794852e-015 ++k1 = 0.79599981 ++lk1 = -5.3678465e-008 ++k2 = 0.0048675395 ++lk2 = -4.2221469e-009 ++wk2 = -6.9420874e-009 ++pk2 = 2.4610412e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12611319 ++lvoff = 1.3634437e-008 ++wvoff = 1.9367898e-009 ++pvoff = -1.3670981e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032519064 ++lu0 = -1.5461646e-009 ++wu0 = 6.2244619e-010 ++pu0 = 1.3648931e-015 ++ua = -8.1508834e-010 ++lua = 2.0053373e-016 ++wua = 5.600962e-018 ++pua = 1.8583714e-023 ++ub = 2.7414305e-018 ++lub = -2.4989307e-025 ++wub = -1.4798829e-026 ++pub = -1.0539885e-031 ++uc = 9.7550228e-011 ++luc = -6.9419625e-018 ++wuc = -8.2782193e-018 ++puc = 1.3234392e-024 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.2256909 ++la0 = -6.6991215e-007 ++wa0 = 4.0423109e-009 ++pa0 = -4.0483744e-014 ++ags = 0.25735343 ++lags = 1.7977071e-007 ++wags = -2.4766942e-009 ++pags = 4.2627001e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019679504 ++lketa = -3.269929e-008 ++wketa = -6.1066685e-010 ++pketa = -2.5943994e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.18943996 ++lpclm = -2.465794e-008 ++wpclm = 1.9498441e-009 ++ppclm = 4.4545348e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00063792557 ++lpdiblc2= 1.7934304e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027238636 ++ldelta = 2.7655057e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.6135347e-005 ++lalpha0 = -8.6812779e-011 ++walpha0 = 7.0204199e-012 ++palpha0 = -8.5298102e-018 ++alpha1 = 0 ++beta0 = 24.225975 ++lbeta0 = -3.2099126e-006 ++wbeta0 = 1.0623239e-007 ++pbeta0 = -2.9414659e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32971157 ++lkt1 = -2.9077811e-008 ++wkt1 = -6.8565602e-009 ++pkt1 = 1.3666571e-014 ++kt1l = 0 ++kt2 = -0.021089286 ++wkt2 = 1.5946429e-010 ++ute = -1.3839286 ++wute = 1.5946429e-008 ++ua1 = 1.675e-009 ++ub1 = -2.513361e-018 ++lub1 = -7.505138e-025 ++wub1 = 2.0553877e-026 ++pub1 = 1.1611514e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72959964 ++wvth0 = -9.3669321e-009 ++k1 = 0.79064 ++k2 = 0.0044459571 ++wk2 = -6.6963519e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12475179 ++wvoff = 1.9231393e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032364679 ++wu0 = 7.5873107e-010 ++ua = -7.95065e-010 ++wua = 7.45655e-018 ++ub = 2.7164786e-018 ++wub = -2.5322929e-026 ++uc = 9.6857071e-011 ++wuc = -8.1460736e-018 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.1588 ++ags = 0.27530357 ++wags = 1.7796214e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.022944536 ++wketa = -8.6971821e-010 ++dwg = 0 ++dwb = 0 ++pclm = 0.18697786 ++wpclm = 6.3977071e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7467071e-005 ++walpha0 = 6.1687164e-012 ++alpha1 = 0 ++beta0 = 23.905464 ++wbeta0 = 7.6861786e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.332615 ++wkt1 = -5.49195e-009 ++kt1l = 0 ++kt2 = -0.021089286 ++wkt2 = 1.5946429e-010 ++ute = -1.3839286 ++wute = 1.5946429e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5883e-018 ++wub1 = 3.2148e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.79767867 ++lvth0 = -4.5516631e-008 ++wvth0 = -2.1175971e-008 ++pvth0 = 2.1102886e-015 ++k1 = 0.97009364 ++lk1 = -1.0850207e-007 ++k2 = 0.045081757 ++lk2 = -4.1037083e-008 ++wk2 = -1.2782551e-008 ++pk2 = 3.7708524e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.078638354 ++lvoff = -9.9036356e-009 ++wvoff = -1.7230974e-008 ++pvoff = 5.0831372e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032583121 ++lu0 = 4.3613327e-009 ++wu0 = 1.5618588e-010 ++pu0 = -3.6889363e-016 ++ua = -6.7252796e-010 ++lua = 4.3347724e-016 ++wua = 1.7609833e-017 ++pua = 4.0632548e-024 ++ub = 2.2958092e-018 ++lub = -1.0258242e-025 ++wub = 1.3746161e-025 ++pub = -2.5657094e-031 ++uc = 1.6246617e-010 ++luc = -3.7418989e-017 ++wuc = 7.6353972e-019 ++puc = -7.9214482e-024 ++eu = 1.67 ++vsat = 61335.065 ++lvsat = 0.0046169416 ++wvsat = 0.0097125195 ++pvsat = -2.1699625e-009 ++a0 = 0.10691933 ++la0 = -1.8229027e-009 ++wa0 = -3.7514606e-009 ++pa0 = 1.1066809e-015 ++ags = 0.35687524 ++lags = -1.304868e-008 ++wags = 3.3541222e-008 ++pags = -1.4555024e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12821436 ++lketa = 3.2864396e-008 ++wketa = -3.4571927e-009 ++pketa = 1.7804543e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.46740308 ++lpclm = -8.6444043e-008 ++wpclm = -2.1779432e-008 ++ppclm = 2.5610983e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0032954546 ++ldelta = 3.4528409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6811189e-006 ++lalpha0 = -3.0617722e-013 ++walpha0 = 5.0878248e-014 ++palpha0 = -2.6202298e-020 ++alpha1 = 0 ++beta0 = 20.985552 ++lbeta0 = -9.5051778e-008 ++wbeta0 = -3.7855616e-007 ++pbeta0 = 1.1121058e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37966054 ++lkt1 = 1.8210678e-008 ++wkt1 = -7.2472535e-009 ++pkt1 = 3.7323356e-015 ++kt1l = 0 ++kt2 = -0.014318515 ++lkt2 = -3.5697146e-009 ++wkt2 = -3.8880251e-009 ++pkt2 = 2.0023329e-015 ++ute = -1.4335714 ++wute = 3.9278571e-008 ++ua1 = 1.675e-009 ++ub1 = -3.6841668e-018 ++lub1 = 2.6922491e-025 ++wub1 = 7.9635518e-026 ++pub1 = -4.1012292e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.74529086 ++lvth0 = -1.8536912e-008 ++wvth0 = -1.0574296e-008 ++pvth0 = -3.3495736e-015 ++k1 = 0.76825545 ++lk1 = -4.5554057e-009 ++wk1 = -1.0349174e-008 ++pk1 = 5.3298247e-015 ++k2 = 0.0088249226 ++lk2 = -2.2364814e-008 ++wk2 = 4.4367941e-009 ++pk2 = -5.0971101e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12067823 ++lvoff = 1.1746901e-008 ++wvoff = 5.4154489e-009 ++pvoff = -6.5797704e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031060188 ++lu0 = 5.1456432e-009 ++wu0 = 1.393772e-010 ++pu0 = -3.6023716e-016 ++ua = -1.1755786e-009 ++lua = 6.9254834e-016 ++wua = -1.8760456e-017 ++pua = 2.2793954e-023 ++ub = 2.834859e-018 ++lub = -3.8019306e-025 ++wub = 1.0041062e-025 ++pub = -2.3748968e-031 ++uc = 8.1961894e-011 ++luc = 4.040715e-018 ++wuc = 3.6192678e-018 ++puc = -9.3921482e-024 ++eu = 1.67 ++vsat = 78457.857 ++lvsat = -0.0042012964 ++wvsat = -0.0040456929 ++pvsat = 4.9155168e-009 ++a0 = 0.98625128 ++la0 = -4.5467886e-007 ++wa0 = 1.1790305e-009 ++pa0 = -1.432522e-015 ++ags = 0.44354017 ++lags = -5.7681118e-008 ++wags = 6.0256471e-008 ++pags = -2.8313377e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043632179 ++lketa = -1.0695428e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.21580136 ++lpclm = 4.3130841e-008 ++wpclm = -2.0563679e-008 ++ppclm = 2.498487e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00133635 ++lpdiblc2= 9.4484475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013214286 ++ldelta = 4.4694643e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.8731595e-006 ++lalpha0 = -2.4650781e-012 ++walpha0 = -1.3035323e-013 ++palpha0 = 6.7131915e-020 ++alpha1 = 0 ++beta0 = 21.046316 ++lbeta0 = -1.2634537e-007 ++wbeta0 = 4.0734123e-007 ++pbeta0 = -2.9352658e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.40824074 ++lkt1 = 3.292948e-008 ++wkt1 = 3.0052147e-008 ++pkt1 = -1.5476856e-014 ++kt1l = 0 ++kt2 = -0.031261352 ++lkt2 = 5.1558463e-009 ++wkt2 = 5.1132283e-009 ++pkt2 = -2.6333126e-015 ++ute = -1.4335714 ++wute = 3.9278571e-008 ++ua1 = 1.675e-009 ++ub1 = -2.804371e-018 ++lub1 = -1.8386993e-025 ++wub1 = 5.8495332e-026 ++pub1 = -3.0125096e-032 ++uc1 = -1.1913423e-010 ++luc1 = 3.2514127e-017 ++wuc1 = 2.9673087e-017 ++puc1 = -1.528164e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71914657 ++lvth0 = 1.3228401e-008 ++wvth0 = -3.9348514e-009 ++pvth0 = -1.1416499e-014 ++k1 = 0.79424825 ++lk1 = -3.6136665e-008 ++wk1 = 8.2322976e-010 ++pk1 = -8.244646e-015 ++k2 = -0.0057533677 ++lk2 = -4.6521909e-009 ++wk2 = -1.950261e-009 ++pk2 = 2.6631619e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12199236 ++lvoff = 1.3343565e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036469853 ++lu0 = -1.4270997e-009 ++wu0 = -1.2344251e-009 ++pu0 = 1.3089326e-015 ++ua = -7.8850544e-010 ++lua = 2.2225441e-016 ++wua = -6.893001e-018 ++pua = 8.3749962e-024 ++ub = 3.0573243e-018 ++lub = -6.5048842e-025 ++wub = -1.6326892e-025 ++pub = 8.2880961e-032 ++uc = 9.7426091e-011 ++luc = -1.4748284e-017 ++wuc = -8.2198748e-018 ++puc = 4.9924102e-024 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.2342915 ++la0 = -7.5604777e-007 ++ags = 0.28327385 ++lags = 1.3704246e-007 ++wags = -1.4659294e-008 ++pags = 6.2709277e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.020978796 ++lketa = -3.8219289e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22676292 ++lpclm = 2.9812546e-008 ++wpclm = -1.559195e-008 ++ppclm = 1.894422e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00063792557 ++lpdiblc2= 1.7934304e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027238636 ++ldelta = 2.7655057e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1050349e-005 ++lalpha0 = -1.0474036e-010 ++walpha0 = 1.0369007e-014 ++palpha0 = -1.0384561e-019 ++alpha1 = 0 ++beta0 = 24.04797 ++lbeta0 = -3.7733547e-006 ++wbeta0 = 1.8989449e-007 ++pbeta0 = -2.932878e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3392138 ++lkt1 = -5.0938244e-008 ++wkt1 = -2.3905117e-009 ++pkt1 = 2.3940975e-014 ++kt1l = 0 ++kt2 = -0.021786808 ++lkt2 = -6.3557247e-009 ++wkt2 = 4.8729978e-010 ++pkt2 = 2.9871906e-015 ++ute = -1.7189014 ++lute = 3.4667589e-007 ++wute = 1.7338365e-007 ++pute = -1.6293767e-013 ++ua1 = 1.675e-009 ++ub1 = -3.5382765e-018 ++lub1 = 7.0782525e-025 ++wub1 = 5.0226415e-025 ++pub1 = -5.6930421e-031 ++uc1 = -5.0977959e-011 ++luc1 = -5.0295738e-017 ++wuc1 = -2.3603592e-018 ++puc1 = 2.3638997e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72046743 ++wvth0 = -5.0747914e-009 ++k1 = 0.79064 ++k2 = -0.00621789 ++wk2 = -1.6843437e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036327357 ++wu0 = -1.1037279e-009 ++ua = -7.6631329e-010 ++wua = -6.0567557e-018 ++ub = 2.9923729e-018 ++wub = -1.5499324e-025 ++uc = 9.5953471e-011 ++wuc = -7.7213816e-018 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.1588 ++ags = 0.29695757 ++wags = -8.3977586e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.22973971 ++wpclm = -1.3700366e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6712 ++wbeta0 = 1.86966e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.022421429 ++wkt2 = 7.8557143e-010 ++ute = -1.6842857 ++wute = 1.5711429e-007 ++ua1 = 1.675e-009 ++ub1 = -3.4676e-018 ++wub1 = 4.45419e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.83011576 ++lvth0 = -6.047942e-008 ++wvth0 = -5.9127366e-008 ++pvth0 = 1.9616751e-014 ++k1 = 0.96085697 ++lk1 = -1.0374519e-007 ++wk1 = 1.0806903e-008 ++pk1 = -5.5655552e-015 ++k2 = 0.017201346 ++lk2 = -3.2812362e-008 ++wk2 = 1.983753e-008 ++pk2 = -5.8520714e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.1242889 ++lvoff = 7.3910414e-010 ++wvoff = 3.618017e-008 ++pvoff = -7.3688683e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046865722 ++lu0 = 1.8889394e-010 ++wu0 = -1.6554457e-008 ++pu0 = 4.5128597e-015 ++ua = -6.8932314e-010 ++lua = 2.7643655e-016 ++wua = 3.7260197e-017 ++pua = 1.8780087e-022 ++ub = 3.8304076e-018 ++lub = -3.6068e-025 ++wub = -1.6580185e-024 ++pub = 4.5403213e-032 ++uc = 3.0152161e-010 ++luc = -7.3826884e-017 ++wuc = -1.6193132e-016 ++puc = 3.4675789e-023 ++eu = 1.67 ++vsat = 75713.12 ++lvsat = -0.00036725671 ++wvsat = -0.0071098048 ++pvsat = 3.6615494e-009 ++a0 = 0.10371296 ++la0 = -8.7702159e-010 ++ags = 0.26715255 ++lags = 3.5482186e-008 ++wags = 1.3851677e-007 ++pags = -7.1336137e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12745025 ++lketa = 3.247088e-008 ++wketa = -4.3512005e-009 ++pketa = 2.2408683e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.2060622 ++lpclm = -1.0687288e-008 ++wpclm = 2.839894e-007 ++ppclm = -6.302442e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0032954546 ++ldelta = 3.4528409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.622667e-006 ++lalpha0 = -2.7607448e-013 ++walpha0 = 1.1926697e-013 ++palpha0 = -6.1422492e-020 ++alpha1 = 0 ++beta0 = 21.140107 ++wbeta0 = -5.5938498e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.73454029 ++lnoff = 1.4082882e-006 ++wnoff = 3.1994121e-006 ++pnoff = -1.6476972e-012 ++voffcv = 0.2404743 ++lvoffcv = -1.2126927e-007 ++wvoffcv = -2.7550493e-007 ++pvoffcv = 1.4188504e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28017689 ++lkt1 = -1.0927331e-008 ++wkt1 = -1.2364312e-007 ++pkt1 = 3.7823806e-014 ++kt1l = 0 ++kt2 = -0.025545233 ++lkt2 = 1.045102e-009 ++wkt2 = 9.247235e-009 ++pkt2 = -3.3970025e-015 ++ute = -1.5699432 ++wute = 1.9883352e-007 ++ua1 = 1.675e-009 ++ub1 = -5.4287188e-018 ++lub1 = 5.2357491e-025 ++wub1 = 2.1207614e-024 ++pub1 = -3.3860178e-031 ++uc1 = -2.3453481e-010 ++luc1 = 5.3914751e-017 ++wuc1 = 2.0888573e-016 ++puc1 = -6.3080258e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.73285729 ++lvth0 = -1.0391311e-008 ++wvth0 = 3.9729778e-009 ++pvth0 = -1.2879926e-014 ++k1 = 0.75941 ++k2 = 0.017945817 ++lk2 = -3.3195765e-008 ++wk2 = -6.2346523e-009 ++pk2 = 7.5751026e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10229638 ++lvoff = -1.0587044e-008 ++wvoff = -1.6091313e-008 ++pvoff = 1.9550945e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038348141 ++lu0 = 4.5754485e-009 ++wu0 = -8.387527e-009 ++pu0 = 3.068906e-016 ++ua = -9.3887833e-010 ++lua = 4.0495747e-016 ++wua = -2.9569982e-016 ++pua = 3.5927528e-022 ++ub = 3.4762372e-018 ++lub = -1.7828226e-025 ++wub = -6.5000193e-025 ++pub = -4.7372533e-031 ++uc = 1.5713919e-010 ++luc = 5.3005815e-019 ++wuc = -8.4338174e-017 ++puc = -5.2846797e-024 ++eu = 1.67 ++vsat = 75000 ++a0 = 0.58607632 ++la0 = -2.4929415e-007 ++wa0 = 4.6938374e-007 ++pa0 = -2.4173263e-013 ++ags = 0.63698234 ++lags = -1.5498016e-007 ++wags = -1.6607087e-007 ++pags = 8.5526499e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043632179 ++lketa = -1.0695428e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.046153372 ++lpclm = 7.1665757e-008 ++wpclm = 1.7792447e-007 ++ppclm = -8.4009819e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00133635 ++lpdiblc2= 9.4484475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013214286 ++ldelta = 4.4694643e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7617464e-006 ++lalpha0 = -2.4077004e-012 ++alpha1 = 0 ++beta0 = 21.042721 ++lbeta0 = 5.0153484e-008 ++wbeta0 = 4.1154752e-007 ++pbeta0 = -5.0003024e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30307353 ++lkt1 = 8.6443502e-010 ++wkt1 = -9.2993492e-008 ++pkt1 = 2.2039247e-014 ++kt1l = 0 ++kt2 = -0.02178266 ++lkt2 = -8.9262312e-010 ++wkt2 = -5.976841e-009 ++pkt2 = 4.4433966e-015 ++ute = -1.5699432 ++wute = 1.9883352e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0159014e-018 ++lub1 = -7.1902608e-025 ++wub1 = 3.0598585e-025 ++pub1 = 5.960076e-031 ++uc1 = -1.4525572e-010 ++luc1 = 7.9360174e-018 ++wuc1 = 6.0235233e-017 ++puc1 = 1.3474748e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71814741 ++lvth0 = 7.4811957e-009 ++wvth0 = -2.7658345e-009 ++pvth0 = -4.6922687e-015 ++k1 = 0.79753063 ++lk1 = -4.6316563e-008 ++wk1 = -3.0171481e-009 ++pk1 = 3.6658349e-015 ++k2 = -0.0074202574 ++lk2 = -2.3759842e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12199236 ++lvoff = 1.3343565e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040486527 ++lu0 = 1.9773099e-009 ++wu0 = -5.9339327e-009 ++pu0 = -2.6742266e-015 ++ua = -8.1101699e-010 ++lua = 2.4960595e-016 ++wua = 1.9445519e-017 ++pua = -2.3626306e-023 ++ub = 3.1890972e-018 ++lub = 1.7059289e-025 ++wub = -3.1744322e-025 ++pub = -8.7778417e-031 ++uc = 1.0423443e-010 ++luc = 6.4809343e-017 ++wuc = -1.6185636e-017 ++puc = -8.8090013e-023 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.1765919 ++la0 = -9.6677061e-007 ++wa0 = 6.7508553e-008 ++pa0 = 2.4654573e-013 ++ags = 0.26693219 ++lags = 2.9463078e-007 ++wags = 4.4604535e-009 ++pags = -1.2166906e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.020978796 ++lketa = -3.8219289e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23361686 ++lpclm = -1.5610238e-007 ++wpclm = -2.3611051e-008 ++ppclm = 2.3646468e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00063792557 ++lpdiblc2= 1.7934304e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027238636 ++ldelta = 2.7655057e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1059211e-005 ++lalpha0 = -1.0482912e-010 ++alpha1 = 0 ++beta0 = 24.517146 ++lbeta0 = -4.1712719e-006 ++wbeta0 = -3.5904062e-007 ++pbeta0 = 4.3623435e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.128938 ++lnoff = -1.5665961e-007 ++wnoff = -1.508574e-007 ++pnoff = 1.8329175e-013 ++voffcv = -0.065915874 ++lvoffcv = 8.6162786e-008 ++wvoffcv = 8.2971572e-008 ++pvoffcv = -1.0081046e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31510943 ++lkt1 = 1.5488057e-008 ++wkt1 = -3.0592631e-008 ++pkt1 = -5.3777798e-014 ++kt1l = 0 ++kt2 = -0.016808883 ++lkt2 = -6.9357625e-009 ++wkt2 = -5.3368725e-009 ++pkt2 = 3.6658349e-015 ++ute = -1.5472465 ++lute = -2.7576491e-008 ++wute = -2.7452583e-008 ++pute = 2.7493762e-013 ++ua1 = 1.6533384e-009 ++lua1 = 2.6318815e-017 ++wua1 = 2.5344044e-017 ++pua1 = -3.0793013e-023 ++ub1 = -2.1471138e-018 ++lub1 = -1.774603e-024 ++wub1 = -1.1253962e-024 ++pub1 = 2.3351368e-030 ++uc1 = -4.4578445e-011 ++luc1 = -1.1438687e-016 ++wuc1 = -9.8477906e-018 ++puc1 = 9.8625623e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71889441 ++wvth0 = -3.2343586e-009 ++k1 = 0.79290591 ++wk1 = -2.6511136e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040683961 ++wu0 = -6.2009548e-009 ++ua = -7.8609378e-010 ++wua = 1.7086427e-017 ++ub = 3.2061309e-018 ++wub = -4.0509016e-025 ++uc = 1.1070566e-010 ++wuc = -2.4981444e-017 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.0800597 ++wa0 = 9.2126199e-008 ++ags = 0.29635114 ++wags = -7.6882295e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.100643 ++wbeta0 = -3.1548252e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1132954 ++wnoff = -1.3255568e-007 ++voffcv = -0.0573125 ++wvoffcv = 7.2905625e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31356294 ++wkt1 = -3.5962356e-008 ++kt1l = 0 ++kt2 = -0.017501421 ++wkt2 = -4.9708381e-009 ++ute = -1.55 ++ua1 = 1.6559664e-009 ++wua1 = 2.2269354e-017 ++ub1 = -2.3243083e-018 ++wub1 = -8.9223229e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.82418523 ++lvth0 = -5.8511842e-008 ++k1 = 0.96194091 ++lk1 = -1.0430342e-007 ++k2 = 0.019191068 ++lk2 = -3.339933e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045205295 ++lu0 = 6.4153784e-010 ++ua = -6.8558591e-010 ++lua = 2.9527314e-016 ++ub = 3.6641068e-018 ++lub = -3.5612601e-025 ++uc = 2.8527975e-010 ++luc = -7.0348871e-017 ++eu = 1.67 ++vsat = 75000 ++a0 = 0.13372839 ++la0 = -1.6334972e-008 ++wa0 = -2.9925391e-007 ++pa0 = 1.5411576e-013 ++ags = 0.46825513 ++lags = -6.8085644e-008 ++wags = -1.866476e-006 ++pags = 9.6123512e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12409156 ++lketa = 3.0741152e-008 ++wketa = -3.7837384e-008 ++pketa = 1.9486253e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23454659 ++lpclm = -1.7008694e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0032954546 ++ldelta = 3.4528409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6346295e-006 ++lalpha0 = -2.8223522e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.53e-010 ++cgdo = 2.53e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.41363636 ++lnoff = 1.2430227e-006 ++voffcv = 0.21284091 ++lvoffcv = -1.0703807e-007 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29257841 ++lkt1 = -7.1335693e-009 ++kt1l = 0 ++kt2 = -0.024617727 ++lkt2 = 7.0437954e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.2160045e-018 ++lub1 = 4.8961284e-025 ++uc1 = -2.1358339e-010 ++luc1 = 4.7587744e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.73325579 ++lvth0 = -1.168318e-008 ++k1 = 0.75941 ++k2 = 0.017320476 ++lk2 = -3.2435975e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10391036 ++lvoff = -8.6260661e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.037506864 ++lu0 = 4.6062299e-009 ++ua = -9.6853729e-010 ++lua = 4.409931e-016 ++ub = 3.4110414e-018 ++lub = -2.2579734e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 75000 ++a0 = 0.63315593 ++la0 = -2.7354015e-007 ++ags = 0.62032529 ++lags = -1.4640177e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043632179 ++lketa = -1.0695428e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.063999357 ++lpclm = 7.0823131e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00133635 ++lpdiblc2= 9.4484475e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013214286 ++ldelta = 4.4694643e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7617464e-006 ++lalpha0 = -2.4077004e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31240086 ++lkt1 = 3.0749914e-009 ++kt1l = 0 ++kt2 = -0.022382143 ++lkt2 = -4.4694643e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -2.9852107e-018 ++lub1 = -6.5924598e-025 ++uc1 = -1.3921407e-010 ++luc1 = 9.2875468e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71786999 ++lvth0 = 7.0105569e-009 ++k1 = 0.79722801 ++lk1 = -4.5948877e-008 ++k2 = -0.0074202574 ++lk2 = -2.3759842e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12199236 ++lvoff = 1.3343565e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.039891348 ++lu0 = 1.7090825e-009 ++ua = -8.0906659e-010 ++lua = 2.4723621e-016 ++ub = 3.1572573e-018 ++lub = 8.2550345e-026 ++uc = 1.02611e-010 ++luc = 5.5973835e-017 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.1833631 ++la0 = -9.4204186e-007 ++ags = 0.26737957 ++lags = 2.8242727e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.020978796 ++lketa = -3.8219289e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23124865 ++lpclm = -1.3238476e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00063792557 ++lpdiblc2= 1.7934304e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027238636 ++ldelta = 2.7655057e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1059211e-005 ++lalpha0 = -1.0482912e-010 ++alpha1 = 0 ++beta0 = 24.481134 ++lbeta0 = -4.1275172e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.23e-010 ++cgdo = 1.23e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1138068 ++lnoff = -1.3827528e-007 ++voffcv = -0.05759375 ++lvoffcv = 7.6051406e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3181779 ++lkt1 = 1.0094096e-008 ++kt1l = 0 ++kt2 = -0.017344176 ++lkt2 = -6.568076e-009 ++ute = -1.55 ++ua1 = 1.6558805e-009 ++lua1 = 2.3230248e-017 ++ub1 = -2.2599921e-018 ++lub1 = -1.5403867e-024 ++uc1 = -4.5566188e-011 ++luc1 = -1.0449463e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.4e-009 ++toxp = 8.4e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.5e-008 ++xw = -1e-008 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71857 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 75000 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.53e-010 ++cgdo = 2.53e-010 ++cgbo = 1e-013 ++cgdl = 1.1e-010 ++cgsl = 1.1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +*resistor + +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + +.endl nmos_3p3_s +* +* +.lib nmos_3p3_fs + + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.64635471 ++lvth0 = -3.6607582e-008 ++wvth0 = -1.4783981e-008 ++pvth0 = 4.2707557e-016 ++k1 = 0.95223909 ++lk1 = -9.4486255e-008 ++k2 = 0.052721915 ++lk2 = -3.9622207e-008 ++wk2 = -1.9530798e-008 ++pk2 = 5.2733156e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12625494 ++lvoff = 3.7921347e-009 ++wvoff = 5.3858974e-009 ++pvoff = -1.4541923e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.023766155 ++lu0 = 4.4287103e-009 ++wu0 = 4.7228328e-009 ++pu0 = -6.3741029e-016 ++ua = -1.1188622e-009 ++lua = 6.7054848e-016 ++wua = 2.6992935e-016 ++pua = -1.3848566e-022 ++ub = 3.341622e-018 ++lub = -7.5166395e-025 ++wub = -4.17125e-025 ++pub = 9.0672414e-032 ++uc = 2.2389524e-010 ++luc = -5.8253799e-017 ++wuc = -3.333668e-017 ++puc = 5.3308427e-024 ++eu = 1.67 ++vsat = 97266.234 ++lvsat = -0.0026417045 ++wvsat = -0.00012912338 ++pvsat = 1.2812267e-009 ++a0 = 0.11206719 ++la0 = -3.0583422e-009 ++wa0 = -6.3254637e-009 ++pa0 = 1.7078752e-015 ++ags = 0.32050776 ++lags = -1.3683815e-008 ++wags = 4.8736973e-008 ++pags = -1.1953845e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.14660298 ++lketa = 3.6813935e-008 ++wketa = 8.2761628e-009 ++pketa = -2.3745402e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.36959505 ++lpclm = -4.5110649e-008 ++wpclm = 2.2412267e-008 ++ppclm = 8.3834934e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0038636364 ++ldelta = 3.0068182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.627733e-006 ++lalpha0 = -2.876129e-013 ++walpha0 = 4.9509131e-014 ++palpha0 = -1.3367465e-020 ++alpha1 = 0 ++beta0 = 19.907557 ++lbeta0 = 1.2151841e-007 ++wbeta0 = 1.4348835e-007 ++pbeta0 = 8.5415114e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.45797555 ++lkt1 = 4.0235308e-008 ++wkt1 = 3.2591386e-008 ++pkt1 = -8.4689085e-015 ++kt1l = 0 ++kt2 = -0.024695 ++lkt2 = 1.20015e-009 ++wkt2 = 1.0755977e-009 ++pkt2 = -2.9041139e-016 ++ute = -1.5663149 ++lute = 8.8056818e-008 ++wute = 1.0491274e-007 ++pute = -4.2707557e-014 ++ua1 = 1.675e-009 ++ub1 = -4.191221e-018 ++lub1 = 2.7447418e-025 ++wub1 = 3.4262081e-025 ++pub1 = -5.6267206e-032 ++uc1 = -4.2302273e-011 ++luc1 = -3.6983864e-018 ++wuc1 = -6.6433977e-018 ++puc1 = 1.7937174e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.61806264 ++lvth0 = -2.274447e-008 ++wvth0 = -1.2753387e-008 ++pvth0 = -5.679156e-016 ++k1 = 0.746507 ++lk1 = 6.32247e-009 ++k2 = 0.023469038 ++lk2 = -2.5288297e-008 ++wk2 = -3.1675243e-009 ++pk2 = -2.7446888e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11287523 ++lvoff = -2.7639238e-009 ++wvoff = 1.7601776e-009 ++pvoff = 3.2241042e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.029657487 ++lu0 = 1.5419574e-009 ++wu0 = 9.0899306e-010 ++pu0 = 1.2313712e-015 ++ua = -1.2857579e-009 ++lua = 7.5232737e-016 ++wua = 4.8437374e-017 ++pua = -2.995459e-023 ++ub = 3.0744545e-018 ++lub = -6.207519e-025 ++wub = -2.974725e-026 ++pub = -9.9142683e-032 ++uc = 8.466824e-011 ++luc = 9.9674311e-018 ++wuc = 2.1132713e-018 ++puc = -1.2039633e-023 ++eu = 1.67 ++vsat = 88687.5 ++lvsat = 0.001561875 ++wvsat = -0.0017399375 ++pvsat = 2.0705256e-009 ++a0 = 1.0806312 ++la0 = -4.7765472e-007 ++wa0 = -5.3427231e-008 ++pa0 = 2.4787741e-014 ++ags = 0.47491359 ++lags = -8.9342671e-008 ++wags = 4.4678399e-008 ++pags = -9.965144e-015 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028392375 ++lketa = -2.1109261e-008 ++wketa = -7.5985556e-009 ++pketa = 5.4040719e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.082248339 ++lpclm = 9.5689239e-008 ++wpclm = 4.5419115e-008 ++ppclm = -2.8898622e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013741 ++lpdiblc2= 8.80481e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015 ++ldelta = 4.165e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.5351125e-006 ++lalpha0 = -2.2022289e-012 ++walpha0 = -1.5560013e-014 ++palpha0 = 1.8516415e-020 ++alpha1 = 0 ++beta0 = 22.62283 ++lbeta0 = -1.2089656e-006 ++wbeta0 = -3.5881772e-007 ++pbeta0 = 2.4698413e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33934486 ++lkt1 = -1.7893733e-008 ++wkt1 = -2.4032443e-009 ++pkt1 = 8.6784603e-015 ++kt1l = 0 ++kt2 = -0.020325321 ++lkt2 = -9.409925e-010 ++wkt2 = -3.6219107e-011 ++pkt2 = 2.5437886e-016 ++ute = -1.3866071 ++wute = 1.7754464e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8142257e-018 ++lub1 = -4.0025352e-025 ++wub1 = 6.0336771e-026 ++pub1 = 8.2051973e-032 ++uc1 = -6.0305e-011 ++luc1 = 5.12295e-018 ++wuc1 = 2.087925e-018 ++puc1 = -2.4846307e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.6014737 ++lvth0 = -3.0036269e-009 ++wvth0 = -1.0050112e-008 ++pvth0 = -3.7848123e-015 ++k1 = 0.79588952 ++lk1 = -5.2442732e-008 ++k2 = 0.0060240997 ++lk2 = -4.5288209e-009 ++wk2 = -7.7235646e-009 ++pk2 = 2.6769992e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12641046 ++lvoff = 1.3342993e-008 ++wvoff = 2.1560739e-009 ++pvoff = -1.4870619e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032410861 ++lu0 = -1.7345577e-009 ++wu0 = 6.9614246e-010 ++pu0 = 1.4846634e-015 ++ua = -8.1562356e-010 ++lua = 1.9286754e-016 ++wua = 6.2785193e-018 ++pua = 2.0214448e-023 ++ub = 2.7434392e-018 ++lub = -2.2684367e-025 ++wub = -1.6717846e-026 ++pub = -1.1464767e-031 ++uc = 9.8926027e-011 ++luc = -6.999336e-018 ++wuc = -9.2137918e-018 ++puc = 1.4395718e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.2236495 ++la0 = -6.4784645e-007 ++wa0 = 4.40803e-009 ++pa0 = -4.4036219e-014 ++ags = 0.25812408 ++lags = 1.6863685e-007 ++wags = -2.659998e-009 ++pags = 4.6367549e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019643215 ++lketa = -3.1520762e-008 ++wketa = -6.8584002e-010 ++pketa = -2.8220597e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.1890464 ++lpclm = -3.1400457e-008 ++wpclm = 2.2728176e-009 ++ppclm = 4.8454232e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064161023 ++lpdiblc2= 1.7521438e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027295455 ++ldelta = 2.7018409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.4780689e-005 ++lalpha0 = -8.3414465e-011 ++walpha0 = 7.7968964e-012 ++palpha0 = -9.2783067e-018 ++alpha1 = 0 ++beta0 = 24.201637 ++lbeta0 = -3.0877458e-006 ++wbeta0 = 1.1760436e-007 ++pbeta0 = -3.1995815e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32862431 ++lkt1 = -3.0651179e-008 ++wkt1 = -7.6027077e-009 ++pkt1 = 1.4865822e-014 ++kt1l = 0 ++kt2 = -0.021116071 ++wkt2 = 1.7754464e-010 ++ute = -1.3866071 ++wute = 1.7754464e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5183956e-018 ++lub1 = -7.5229142e-025 ++wub1 = 2.3149925e-026 ++pub1 = 1.2630432e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.60117304 ++wvth0 = -1.0428972e-008 ++k1 = 0.79064 ++k2 = 0.0055707643 ++wk2 = -7.4555967e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12507482 ++wvoff = 2.1411884e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032237232 ++wu0 = 8.4475741e-010 ++ua = -7.963175e-010 ++wua = 8.3019875e-018 ++ub = 2.7207321e-018 ++wub = -2.8194089e-026 ++uc = 9.8225393e-011 ++wuc = -9.0696905e-018 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1588 ++ags = 0.27500464 ++wags = 1.9813982e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.022798446 ++wketa = -9.6832848e-010 ++dwg = 0 ++dwb = 0 ++pclm = 0.18590321 ++wpclm = 7.1230911e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6430893e-005 ++walpha0 = 6.868137e-012 ++alpha1 = 0 ++beta0 = 23.892554 ++wbeta0 = 8.5576518e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3316925 ++wkt1 = -6.1146375e-009 ++kt1l = 0 ++kt2 = -0.021116071 ++wkt2 = 1.7754464e-010 ++ute = -1.3866071 ++wute = 1.7754464e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5937e-018 ++wub1 = 3.5793e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.66075684 ++lvth0 = -3.9687122e-008 ++wvth0 = -2.1769016e-008 ++pvth0 = 1.9206526e-015 ++k1 = 0.95223909 ++lk1 = -9.4486255e-008 ++k2 = 0.038660657 ++lk2 = -3.5825667e-008 ++wk2 = -1.2711088e-008 ++pk2 = 3.4319939e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.079820841 ++lvoff = -8.7450729e-009 ++wvoff = -1.7134642e-008 ++pvoff = 4.6263534e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.033298195 ++lu0 = 3.8067177e-009 ++wu0 = 9.9793159e-011 ++pu0 = -3.357439e-016 ++ua = -6.0169576e-010 ++lua = 3.7738605e-016 ++wua = 1.9103635e-017 ++pua = 3.6981203e-024 ++ub = 2.2763308e-018 ++lub = -8.3236674e-026 ++wub = 9.954125e-026 ++pub = -2.3351482e-031 ++uc = 1.5632343e-010 ++luc = -3.2397203e-017 ++wuc = -5.6435009e-019 ++puc = -7.2096064e-024 ++eu = 1.67 ++vsat = 76839.61 ++lvsat = 0.0040720909 ++wvsat = 0.009777789 ++pvsat = -1.9749641e-009 ++a0 = 0.10671673 ++la0 = -1.6137164e-009 ++wa0 = -3.7304877e-009 ++pa0 = 1.0072317e-015 ++ags = 0.35387843 ++lags = -1.1017368e-008 ++wags = 3.25522e-008 ++pags = -1.3247072e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12272005 ++lketa = 2.8576826e-008 ++wketa = -3.3070572e-009 ++pketa = 1.620458e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.45365742 ++lpclm = -7.5885948e-008 ++wpclm = -1.8357985e-008 ++ppclm = 2.3309514e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0038636364 ++ldelta = 3.0068182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6294657e-006 ++lalpha0 = -2.6600418e-013 ++walpha0 = 4.8668758e-014 ++palpha0 = -2.3847691e-020 ++alpha1 = 0 ++beta0 = 20.979738 ++lbeta0 = -8.5415114e-008 ++wbeta0 = -3.7651952e-007 ++pbeta0 = 1.0121691e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37648295 ++lkt1 = 1.5769644e-008 ++wkt1 = -6.932527e-009 ++pkt1 = 3.3969382e-015 ++kt1l = 0 ++kt2 = -0.014808861 ++lkt2 = -3.1561582e-009 ++wkt2 = -3.7191798e-009 ++pkt2 = 1.8223981e-015 ++ute = -1.4346429 ++wute = 4.1051786e-008 ++ua1 = 1.675e-009 ++ub1 = -3.6418527e-018 ++lub1 = 2.3542184e-025 ++wub1 = 7.6177186e-026 ++pub1 = -3.7326821e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.61484234 ++lvth0 = -1.7189014e-008 ++wvth0 = -1.1191538e-008 ++pvth0 = -3.2623115e-015 ++k1 = 0.76834994 ++lk1 = -4.3805685e-009 ++wk1 = -1.0593824e-008 ++pk1 = 5.1909737e-015 ++k2 = 0.0078158961 ++lk2 = -2.0711735e-008 ++wk2 = 4.4242495e-009 ++pk2 = -4.9643217e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12034945 ++lvoff = 1.1113945e-008 ++wvoff = 5.3851733e-009 ++pvoff = -6.4083562e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031262366 ++lu0 = 4.804274e-009 ++wu0 = 1.3062678e-010 ++pu0 = -3.5085237e-016 ++ua = -1.1474219e-009 ++lua = 6.4479186e-016 ++wua = -1.8655574e-017 ++pua = 2.2200133e-023 ++ub = 2.8171887e-018 ++lub = -3.4825707e-025 ++wub = 9.5026674e-026 ++pub = -2.3130267e-031 ++uc = 8.2034846e-011 ++luc = 4.0042012e-018 ++wuc = 3.390467e-018 ++puc = -9.1474668e-024 ++eu = 1.67 ++vsat = 93395 ++lvsat = -0.00404005 ++wvsat = -0.004023075 ++pvsat = 4.7874593e-009 ++a0 = 0.9680546 ++la0 = -4.2366927e-007 ++wa0 = 1.172439e-009 ++pa0 = -1.3952024e-015 ++ags = 0.4396228 ++lags = -5.3032112e-008 ++wags = 6.1794432e-008 ++pags = -2.7575765e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0440595 ++lketa = -9.966845e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.2180583 ++lpclm = 3.9557623e-008 ++wpclm = -2.0448715e-008 ++ppclm = 2.4333971e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013741 ++lpdiblc2= 8.80481e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015 ++ldelta = 4.165e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7781531e-006 ++lalpha0 = -2.298861e-012 ++walpha0 = -1.3343472e-013 ++palpha0 = 6.5383015e-020 ++alpha1 = 0 ++beta0 = 21.030477 ++lbeta0 = -1.102773e-007 ++wbeta0 = 4.1347359e-007 ++pbeta0 = -2.8587971e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.40772797 ++lkt1 = 3.1079706e-008 ++wkt1 = 3.0762566e-008 ++pkt1 = -1.5073657e-014 ++kt1l = 0 ++kt2 = -0.031191964 ++lkt2 = 4.8715625e-009 ++wkt2 = 5.2341027e-009 ++pkt2 = -2.5647103e-015 ++ute = -1.4346429 ++wute = 4.1051786e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8132801e-018 ++lub1 = -1.7057876e-025 ++wub1 = 5.9878135e-026 ++pub1 = -2.9340286e-032 ++uc1 = -1.1862793e-010 ++luc1 = 3.0687684e-017 ++wuc1 = 3.0374545e-017 ++puc1 = -1.4883527e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.58928172 ++lvth0 = 1.3228117e-008 ++wvth0 = -4.137003e-009 ++pvth0 = -1.1657208e-014 ++k1 = 0.79415202 ++lk1 = -3.5085045e-008 ++wk1 = 8.4269053e-010 ++pk1 = -8.4184784e-015 ++k2 = -0.0057098764 ++lk2 = -4.6160653e-009 ++wk2 = -2.0325861e-009 ++pk2 = 2.7193127e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12196494 ++lvoff = 1.3036382e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.03650052 ++lu0 = -1.4291291e-009 ++wu0 = -1.287342e-009 ++pu0 = 1.3365305e-015 ++ua = -7.8786125e-010 ++lua = 2.1691469e-016 ++wua = -7.1861991e-018 ++pua = 8.5515769e-024 ++ub = 3.0604368e-018 ++lub = -6.3772226e-025 ++wub = -1.7046166e-025 ++pub = 8.4628446e-032 ++uc = 9.7619729e-011 ++luc = -1.4541809e-017 ++wuc = -8.5802375e-018 ++puc = 5.0976715e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.2327382 ++la0 = -7.3864278e-007 ++ags = 0.28395177 ++lags = 1.3221642e-007 ++wags = -1.5186427e-008 ++pags = 6.4031457e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021057318 ++lketa = -3.7339441e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22724843 ++lpclm = 2.8621373e-008 ++wpclm = -1.6255164e-008 ++ppclm = 1.9343645e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064161023 ++lpdiblc2= 1.7521438e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027295455 ++ldelta = 2.7018409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0834879e-005 ++lalpha0 = -1.0232637e-010 ++walpha0 = 1.0614126e-014 ++palpha0 = -1.0603512e-019 ++alpha1 = 0 ++beta0 = 24.03504 ++lbeta0 = -3.6857066e-006 ++wbeta0 = 1.9840421e-007 ++pbeta0 = -2.9947156e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33925459 ++lkt1 = -5.0403614e-008 ++wkt1 = -2.4470223e-009 ++pkt1 = 2.4445753e-014 ++kt1l = 0 ++kt2 = -0.021813326 ++lkt2 = -6.2890172e-009 ++wkt2 = 5.1571306e-010 ++pkt2 = 3.0501733e-015 ++ute = -1.7229095 ++lute = 3.430373e-007 ++wute = 1.8086111e-007 ++pute = -1.6637309e-013 ++ua1 = 1.675e-009 ++ub1 = -3.550491e-018 ++lub1 = 7.0670219e-025 ++wub1 = 5.237162e-025 ++pub1 = -5.8130758e-031 ++uc1 = -5.1018233e-011 ++luc1 = -4.9767852e-017 ++wuc1 = -2.416157e-018 ++puc1 = 2.4137408e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.59060586 ++wvth0 = -5.3038907e-009 ++k1 = 0.79064 ++k2 = -0.006171945 ++wk2 = -1.7603827e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036357464 ++wu0 = -1.1535552e-009 ++ua = -7.6614807e-010 ++wua = -6.3301854e-018 ++ub = 2.9966007e-018 ++wub = -1.6199035e-025 ++uc = 9.6164093e-011 ++wuc = -8.06996e-018 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1588 ++ags = 0.29718664 ++wags = -8.7768718e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.23011343 ++wpclm = -1.4318863e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6661 ++wbeta0 = 1.954065e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.022442857 ++wkt2 = 8.2103571e-010 ++ute = -1.6885714 ++wute = 1.6420714e-007 ++ua1 = 1.675e-009 ++ub1 = -3.47975e-018 ++wub1 = 4.6552725e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.69023545 ++lvth0 = -5.2688923e-008 ++wvth0 = -5.6701171e-008 ++pvth0 = 1.7327786e-014 ++k1 = 0.94377247 ++lk1 = -9.0337611e-008 ++wk1 = 1.0032944e-008 ++pk1 = -4.9161428e-015 ++k2 = 0.011777641 ++lk2 = -2.8567253e-008 ++wk2 = 1.9145286e-008 ++pk2 = -5.1692271e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12421225 ++lvoff = 6.518816e-010 ++wvoff = 3.5469172e-008 ++pvoff = -6.5090378e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046917138 ++lu0 = 1.5943995e-010 ++wu0 = -1.6038654e-008 ++pu0 = 3.9862803e-015 ++ua = -6.4392181e-010 ++lua = 2.405174e-016 ++wua = 6.9141509e-017 ++pua = 1.6588748e-022 ++ub = 3.7731784e-018 ++lub = -3.1413979e-025 ++wub = -1.6742232e-024 ++pub = 4.0105376e-032 ++uc = 2.8957392e-010 ++luc = -6.4329084e-017 ++wuc = -1.5846619e-016 ++puc = 3.0629672e-023 ++eu = 1.67 ++vsat = 90661.054 ++lvsat = -0.00032391632 ++wvsat = -0.0066006214 ++pvsat = 3.2343045e-009 ++a0 = 0.10356864 ++la0 = -7.6373182e-010 ++ags = 0.27282829 ++lags = 3.0978636e-008 ++wags = 1.2859661e-007 ++pags = -6.3012337e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12210189 ++lketa = 2.8273926e-008 ++wketa = -4.0395803e-009 ++pketa = 1.9793943e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.2039517 ++lpclm = -9.2361767e-009 ++wpclm = 2.775433e-007 ++ppclm = -5.5670466e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0038636364 ++ldelta = 3.0068182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.5770972e-006 ++lalpha0 = -2.4034362e-013 ++walpha0 = 1.1072542e-013 ++palpha0 = -5.4255458e-020 ++alpha1 = 0 ++beta0 = 21.140826 ++wbeta0 = -5.6740897e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.50656508 ++lnoff = 1.2282169e-006 ++wnoff = 2.9702796e-006 ++pnoff = -1.455437e-012 ++voffcv = 0.2208431 ++lvoffcv = -1.0576312e-007 ++wvoffcv = -2.5577408e-007 ++pvoffcv = 1.253293e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28182405 ++lkt1 = -9.558142e-009 ++wkt1 = -1.1910332e-007 ++pkt1 = 3.3410365e-014 ++kt1l = 0 ++kt2 = -0.025384429 ++lkt2 = 9.1390428e-010 ++wkt2 = 8.8128685e-009 ++pkt2 = -3.000626e-015 ++ute = -1.5701989 ++wute = 2.0168565e-007 ++ua1 = 1.675e-009 ++ub1 = -5.3452175e-018 ++lub1 = 4.5632098e-025 ++wub1 = 2.0946644e-024 ++pub1 = -2.9909231e-031 ++uc1 = -2.2591814e-010 ++luc1 = 4.7020919e-017 ++wuc1 = 2.0135299e-016 ++puc1 = -5.5719789e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.60243767 ++lvth0 = -9.668011e-009 ++wvth0 = 3.5079858e-009 ++pvth0 = -1.2174701e-014 ++k1 = 0.75941 ++k2 = 0.016627153 ++lk2 = -3.0943514e-008 ++wk2 = -6.0170898e-009 ++pk2 = 7.1603368e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10269969 ++lvoff = -9.8892719e-009 ++wvoff = -1.5529795e-008 ++pvoff = 1.8480456e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038541716 ++lu0 = 4.2633967e-009 ++wu0 = -8.4954031e-009 ++pu0 = 2.9008716e-016 ++ua = -9.2233701e-010 ++lua = 3.7694084e-016 ++wua = -2.8538117e-016 ++pua = 3.3960359e-022 ++ub = 3.4699744e-018 ++lub = -1.6556982e-025 ++wub = -6.7852432e-025 ++pub = -4.4778706e-031 ++uc = 1.572691e-010 ++luc = 5.0028276e-019 ++wuc = -8.5762118e-017 ++puc = -4.9953234e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.57552494 ++la0 = -2.3202232e-007 ++wa0 = 4.6632009e-007 ++pa0 = -2.2849684e-013 ++ags = 0.63099948 ++lags = -1.4452524e-007 ++wags = -1.6498693e-007 ++pags = 8.0843597e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0440595 ++lketa = -9.966845e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.048788318 ++lpclm = 6.6793883e-008 ++wpclm = 1.8013621e-007 ++ppclm = -7.9409961e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013741 ++lpdiblc2= 8.80481e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015 ++ldelta = 4.165e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.66555e-006 ++lalpha0 = -2.2436855e-012 ++alpha1 = 0 ++beta0 = 21.044222 ++lbeta0 = 4.7336172e-008 ++wbeta0 = 3.9718628e-007 ++pbeta0 = -4.7265167e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30292054 ++lkt1 = 7.7913898e-010 ++wkt1 = -9.343424e-008 ++pkt1 = 2.0832514e-014 ++kt1l = 0 ++kt2 = -0.021810866 ++lkt2 = -8.3714133e-010 ++wkt2 = -5.8824982e-009 ++pkt2 = 4.2001037e-015 ++ute = -1.5701989 ++wute = 2.0168565e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0450532e-018 ++lub1 = -6.7075952e-025 ++wub1 = 3.3452927e-025 ++pub1 = 5.6337391e-031 ++uc1 = -1.450168e-010 ++luc1 = 7.3792611e-018 ++wuc1 = 6.1645354e-017 ++puc1 = 1.2736955e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.58816635 ++lvth0 = 7.3148658e-009 ++wvth0 = -2.8152872e-009 ++pvth0 = -4.6500058e-015 ++k1 = 0.79743934 ++lk1 = -4.5254914e-008 ++wk1 = -3.0527874e-009 ++pk1 = 3.632817e-015 ++k2 = -0.007425139 ++lk2 = -2.3212866e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12196494 ++lvoff = 1.3036382e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040498226 ++lu0 = 1.9351498e-009 ++wu0 = -6.024624e-009 ++pu0 = -2.65014e-015 ++ua = -8.1052911e-010 ++lua = 2.4388945e-016 ++wua = 1.9675215e-017 ++pua = -2.3413506e-023 ++ub = 3.1898582e-018 ++lub = 1.6776843e-025 ++wub = -3.2382603e-025 ++pub = -8.6987803e-031 ++uc = 1.0438863e-010 ++luc = 6.3428033e-017 ++wuc = -1.6601388e-017 ++puc = -8.7296592e-023 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1745182 ++la0 = -9.448243e-007 ++wa0 = 6.8990718e-008 ++pa0 = 2.4432511e-013 ++ags = 0.2675321 ++lags = 2.8800094e-007 ++wags = 4.2708771e-009 ++pags = -1.205732e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021057318 ++lketa = -3.7339441e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23332588 ++lpclm = -1.5280581e-007 ++wpclm = -2.3456943e-008 ++ppclm = 2.3433486e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064161023 ++lpdiblc2= 1.7521438e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027295455 ++ldelta = 2.7018409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0843837e-005 ++lalpha0 = -1.0241585e-010 ++alpha1 = 0 ++beta0 = 24.509036 ++lbeta0 = -4.075793e-006 ++wbeta0 = -3.632817e-007 ++pbeta0 = 4.3230522e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1288096 ++lnoff = -1.5328342e-007 ++wnoff = -1.5263937e-007 ++pnoff = 1.8164085e-013 ++voffcv = -0.065845277 ++lvoffcv = 8.430588e-008 ++wvoffcv = 8.3951653e-008 ++pvoffcv = -9.9902467e-014 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31503813 ++lkt1 = 1.5199068e-008 ++wkt1 = -3.1143535e-008 ++pkt1 = -5.3293425e-014 ++kt1l = 0 ++kt2 = -0.01681628 ++lkt2 = -6.7806996e-009 ++wkt2 = -5.4057867e-009 ++pkt2 = 3.632817e-015 ++ute = -1.5472686 ++lute = -2.7287058e-008 ++wute = -2.7273401e-008 ++pute = 2.7246128e-013 ++ua1 = 1.65336e-009 ++lua1 = 2.5751614e-017 ++wua1 = 2.5643414e-017 ++pua1 = -3.0515663e-023 ++ub1 = -2.1493188e-018 ++lub1 = -1.7366835e-024 ++wub1 = -1.1366728e-024 ++pub1 = 2.3141044e-030 ++uc1 = -4.4801054e-011 ++luc1 = -1.1187747e-016 ++wuc1 = -9.7835144e-018 ++puc1 = 9.7737308e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.58889857 ++wvth0 = -3.2807533e-009 ++k1 = 0.79290932 ++wk1 = -2.689142e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040691935 ++wu0 = -6.2899032e-009 ++ua = -7.8611576e-010 ++wua = 1.733152e-017 ++ub = 3.2066518e-018 ++wub = -4.109009e-025 ++uc = 1.1073779e-010 ++wuc = -2.5339785e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.0799412 ++wa0 = 9.3447686e-008 ++ags = 0.29636102 ++wags = -7.7985119e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.101049 ++wbeta0 = -3.200079e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1134659 ++wnoff = -1.344571e-007 ++voffcv = -0.05740625 ++wvoffcv = 7.3951406e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3135167 ++wkt1 = -3.6478212e-008 ++kt1l = 0 ++kt2 = -0.017495028 ++wkt2 = -5.0421413e-009 ++ute = -1.55 ++ua1 = 1.6559377e-009 ++wua1 = 2.2588793e-017 ++ub1 = -2.323161e-018 ++wub1 = -9.0503075e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.68455682 ++lvth0 = -5.0953541e-008 ++k1 = 0.94477727 ++lk1 = -9.0829964e-008 ++k2 = 0.013695045 ++lk2 = -2.9084952e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045310864 ++lu0 = 5.5866682e-010 ++ua = -6.3699727e-010 ++lua = 2.5713106e-016 ++ub = 3.6055045e-018 ++lub = -3.1012323e-025 ++uc = 2.737035e-010 ++luc = -6.1261515e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.13104451 ++la0 = -1.4226912e-008 ++wa0 = -2.7434664e-007 ++pa0 = 1.3442985e-013 ++ags = 0.45707702 ++lags = -5.9303239e-008 ++wags = -1.7111269e-006 ++pags = 8.3845218e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.11903243 ++lketa = 2.6769891e-008 ++wketa = -3.4688132e-008 ++pketa = 1.6997185e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23174773 ++lpclm = -1.4811586e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0038636364 ++ldelta = 3.0068182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.5881864e-006 ++lalpha0 = -2.4577732e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.185e-010 ++cgdo = 2.185e-010 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.20909091 ++lnoff = 1.0824545e-006 ++voffcv = 0.19522727 ++lvoffcv = -9.3211364e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29375227 ++lkt1 = -6.2120864e-009 ++kt1l = 0 ++kt2 = -0.024501818 ++lkt2 = 6.1339091e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.1354364e-018 ++lub1 = 4.2636682e-025 ++uc1 = -2.0575259e-010 ++luc1 = 4.144057e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.602789 ++lvth0 = -1.088731e-008 ++k1 = 0.75941 ++k2 = 0.01602454 ++lk2 = -3.0226405e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.104255 ++lvoff = -8.03845e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.0376909 ++lu0 = 4.292449e-009 ++ua = -9.50918e-010 ++lua = 4.1095222e-016 ++ub = 3.40202e-018 ++lub = -2.104158e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.622227 ++la0 = -2.5490633e-007 ++ags = 0.614476 ++lags = -1.3642874e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0440595 ++lketa = -9.966845e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.066829 ++lpclm = 6.599859e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013741 ++lpdiblc2= 8.80481e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0015 ++ldelta = 4.165e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.66555e-006 ++lalpha0 = -2.2436855e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.312278 ++lkt1 = 2.86552e-009 ++kt1l = 0 ++kt2 = -0.0224 ++lkt2 = -4.165e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -3.01155e-018 ++lub1 = -6.143375e-025 ++uc1 = -1.38843e-010 ++luc1 = 8.65487e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.5878844 ++lvth0 = 6.8491667e-009 ++k1 = 0.7971336 ++lk1 = -4.4891087e-008 ++k2 = -0.007425139 ++lk2 = -2.3212866e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12196494 ++lvoff = 1.3036382e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.039894859 ++lu0 = 1.6697377e-009 ++ua = -8.0855864e-010 ++lua = 2.4154458e-016 ++ub = 3.1574269e-018 ++lub = 8.0649951e-026 ++uc = 1.02726e-010 ++luc = 5.468526e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1814276 ++la0 = -9.2035509e-007 ++ags = 0.26795983 ++lags = 2.759255e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021057318 ++lketa = -3.7339441e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23097666 ++lpclm = -1.2933712e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064161023 ++lpdiblc2= 1.7521438e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027295455 ++ldelta = 2.7018409e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0843837e-005 ++lalpha0 = -1.0241585e-010 ++alpha1 = 0 ++beta0 = 24.472653 ++lbeta0 = -4.0324976e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 8.85e-011 ++cgdo = 8.85e-011 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1135227 ++lnoff = -1.3509204e-007 ++voffcv = -0.0574375 ++lvoffcv = 7.4300625e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31815716 ++lkt1 = 9.8617193e-009 ++kt1l = 0 ++kt2 = -0.017357671 ++lkt2 = -6.4168722e-009 ++ute = -1.55 ++ua1 = 1.6559282e-009 ++lua1 = 2.2695464e-017 ++ub1 = -2.2631568e-018 ++lub1 = -1.5049254e-024 ++uc1 = -4.5780875e-011 ++luc1 = -1.0208906e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.8e-009 ++toxp = 7.8e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1e-008 ++xw = 5e-009 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.58857 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.185e-010 ++cgdo = 2.185e-010 ++cgbo = 1e-013 ++cgdl = 9.5e-011 ++cgsl = 9.5e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + + +*resistor + +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + + + +.endl nmos_3p3_fs +* +* +.lib nmos_3p3_sf + + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.77039529 ++lvth0 = -4.0876103e-008 ++wvth0 = -1.3833002e-008 ++pvth0 = 4.4478044e-016 ++k1 = 0.96652273 ++lk1 = -1.0562749e-007 ++k2 = 0.056667113 ++lk2 = -4.3701293e-008 ++wk2 = -1.8937677e-008 ++pk2 = 5.4919265e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12626439 ++lvoff = 4.0757735e-009 ++wvoff = 5.2223358e-009 ++pvoff = -1.5144774e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.023581366 ++lu0 = 4.8792474e-009 ++wu0 = 4.4895909e-009 ++pu0 = -6.638348e-016 ++ua = -1.1909754e-009 ++lua = 7.3404439e-016 ++wua = 2.7097128e-016 ++pua = -1.4422673e-022 ++ub = 3.4119198e-018 ++lub = -8.3010051e-025 ++wub = -4.0136608e-025 ++pub = 9.4431335e-032 ++uc = 2.2926756e-010 ++luc = -6.4523339e-017 ++wuc = -3.1807431e-017 ++puc = 5.5518384e-024 ++eu = 1.67 ++vsat = 86133.117 ++lvsat = -0.0028091396 ++wvsat = -0.00030073052 ++pvsat = 1.3343413e-009 ++a0 = 0.11186736 ++la0 = -3.2269331e-009 ++wa0 = -6.1333689e-009 ++pa0 = 1.778677e-015 ++ags = 0.32766 ++lags = -1.6641391e-008 ++wags = 4.7087182e-008 ++pags = -1.2449405e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.1512997 ++lketa = 4.0887819e-008 ++wketa = 8.0445414e-009 ++pketa = -2.4729792e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37854122 ++lpclm = -4.9487196e-008 ++wpclm = 1.9698751e-008 ++ppclm = 8.73104e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0034090909 ++ldelta = 3.3613636e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6763946e-006 ++lalpha0 = -3.2302945e-013 ++walpha0 = 4.8005613e-014 ++palpha0 = -1.3921628e-020 ++alpha1 = 0 ++beta0 = 19.903605 ++lbeta0 = 1.3594315e-007 ++wbeta0 = 1.3355442e-007 ++pbeta0 = 8.8956088e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.46065123 ++lkt1 = 4.4027381e-008 ++wkt1 = 3.1555052e-008 ++pkt1 = -8.8199961e-015 ++kt1l = 0 ++kt2 = -0.024763831 ++lkt2 = 1.309011e-009 ++wkt2 = 1.0429334e-009 ++pkt2 = -3.024507e-016 ++ute = -1.5684253 ++lute = 9.3637987e-008 ++wute = 1.0375203e-007 ++pute = -4.4478044e-014 ++ua1 = 1.675e-009 ++ub1 = -4.197398e-018 ++lub1 = 3.0051191e-025 ++wub1 = 3.271121e-025 ++pub1 = -5.8599823e-032 ++uc1 = -4.2438636e-011 ++luc1 = -3.9327954e-018 ++wuc1 = -6.4416477e-018 ++puc1 = 1.8680778e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.73756201 ++lvth0 = -2.4131129e-008 ++wvth0 = -1.1862994e-008 ++pvth0 = -5.599238e-016 ++k1 = 0.74629014 ++lk1 = 6.6911271e-009 ++k2 = 0.024027296 ++lk2 = -2.7054986e-008 ++wk2 = -2.8631843e-009 ++pk2 = -2.7060651e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11260451 ++lvoff = -2.8907672e-009 ++wvoff = 1.6294911e-009 ++pvoff = 3.1787341e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.029691776 ++lu0 = 1.7629382e-009 ++wu0 = 8.0747734e-010 ++pu0 = 1.2140431e-015 ++ua = -1.3065872e-009 ++lua = 7.930064e-016 ++wua = 4.6081741e-017 ++pua = -2.9533064e-023 ++ub = 3.0930961e-018 ++lub = -6.6750038e-025 ++wub = -2.4544774e-026 ++pub = -9.774753e-032 ++uc = 8.4580446e-011 ++luc = 9.2670883e-018 ++wuc = 2.3534472e-018 ++puc = -1.187021e-023 ++eu = 1.67 ++vsat = 76951.786 ++lvsat = 0.0018733393 ++wvsat = -0.0016870982 ++pvsat = 2.0413888e-009 ++a0 = 1.0915554 ++la0 = -5.0286783e-007 ++wa0 = -5.0565226e-008 ++pa0 = 2.4438924e-014 ++ags = 0.48250605 ++lags = -9.5612876e-008 ++wags = 4.194112e-008 ++pags = -9.8249129e-015 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028451232 ++lketa = -2.1764897e-008 ++wketa = -7.2515451e-009 ++pketa = 5.3280249e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.083544401 ++lpclm = 1.0096118e-007 ++wpclm = 4.2405096e-008 ++ppclm = -2.8491956e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013439 ++lpdiblc2= 9.31821e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013571429 ++ldelta = 4.4078571e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6090188e-006 ++lalpha0 = -2.3286678e-012 ++walpha0 = -1.5087478e-014 ++palpha0 = 1.8255849e-020 ++alpha1 = 0 ++beta0 = 22.627356 ++lbeta0 = -1.2531695e-006 ++wbeta0 = -3.4216904e-007 ++pbeta0 = 2.4350853e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33900277 ++lkt1 = -1.8013338e-008 ++wkt1 = -2.5161865e-009 ++pkt1 = 8.5563355e-015 ++kt1l = 0 ++kt2 = -0.020297566 ++lkt2 = -9.6878403e-010 ++wkt2 = -4.1870281e-011 ++pkt2 = 2.507992e-016 ++ute = -1.3848214 ++wute = 1.6540179e-008 ++ua1 = 1.675e-009 ++ub1 = -2.7947117e-018 ++lub1 = -4.1485807e-025 ++wub1 = 5.3588288e-026 ++pub1 = 8.0897323e-032 ++uc1 = -6.0262143e-011 ++luc1 = 5.1571929e-018 ++wuc1 = 2.0245179e-018 ++puc1 = -2.4496666e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72046857 ++lvth0 = -3.4480652e-009 ++wvth0 = -9.3568204e-009 ++pvth0 = -3.5923941e-015 ++k1 = 0.79597775 ++lk1 = -5.3430878e-008 ++k2 = 0.0052544426 ++lk2 = -4.3398333e-009 ++wk2 = -7.1995204e-009 ++pk2 = 2.5409017e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12621602 ++lvoff = 1.3579168e-008 ++wvoff = 2.008846e-009 ++pvoff = -1.4114603e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032483545 ++lu0 = -1.6151023e-009 ++wu0 = 6.462041e-010 ++pu0 = 1.4091837e-015 ++ua = -8.1531997e-010 ++lua = 1.9857306e-016 ++wua = 5.8174289e-018 ++pua = 1.9186754e-023 ++ub = 2.7421588e-018 ++lub = -2.4286628e-025 ++wub = -1.5394771e-026 ++pub = -1.0881903e-031 ++uc = 9.8010851e-011 ++luc = -6.9837022e-018 ++wuc = -8.5858868e-018 ++puc = 1.3663846e-024 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.2251902 ++la0 = -6.6456596e-007 ++wa0 = 4.1755681e-009 ++pa0 = -4.1797436e-014 ++ags = 0.25756499 ++lags = 1.7656581e-007 ++wags = -2.5507436e-009 ++pags = 4.4010242e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019658689 ++lketa = -3.2403874e-008 ++wketa = -6.345102e-010 ++pketa = -2.6785874e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.18931963 ++lpclm = -2.7026844e-008 ++wpclm = 2.0414302e-009 ++ppclm = 4.5990839e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0006386625 ++lpdiblc2= 1.7851584e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.002725 ++ldelta = 2.75275e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.5706791e-005 ++lalpha0 = -8.5936972e-011 ++walpha0 = 7.2781831e-012 ++palpha0 = -8.8066015e-018 ++alpha1 = 0 ++beta0 = 24.218715 ++lbeta0 = -3.1787135e-006 ++wbeta0 = 1.1006248e-007 ++pbeta0 = -3.0369161e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32933993 ++lkt1 = -2.9705368e-008 ++wkt1 = -7.1060329e-009 ++pkt1 = 1.411005e-014 ++kt1l = 0 ++kt2 = -0.021098214 ++wkt2 = 1.6540179e-010 ++ute = -1.3848214 ++wute = 1.6540179e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5148229e-018 ++lub1 = -7.5352353e-025 ++wub1 = 2.136867e-026 ++pub1 = 1.1988306e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72012411 ++wvth0 = -9.7157009e-009 ++k1 = 0.79064 ++k2 = 0.0048208929 ++wk2 = -6.9456841e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12485946 ++wvoff = 1.9947455e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032322196 ++wu0 = 7.869817e-010 ++ua = -7.954825e-010 ++wua = 7.7341875e-018 ++ub = 2.7178964e-018 ++wub = -2.6265804e-026 ++uc = 9.7313179e-011 ++wuc = -8.4493848e-018 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.1588 ++ags = 0.27520393 ++wags = 1.8458839e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.022895839 ++wketa = -9.0210134e-010 ++dwg = 0 ++dwb = 0 ++pclm = 0.18661964 ++wpclm = 6.6359196e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7121679e-005 ++walpha0 = 6.3984027e-012 ++alpha1 = 0 ++beta0 = 23.901161 ++wbeta0 = 7.9723661e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3323075 ++wkt1 = -5.6964375e-009 ++kt1l = 0 ++kt2 = -0.021098214 ++wkt2 = 1.6540179e-010 ++ute = -1.3848214 ++wute = 1.6540179e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5901e-018 ++wub1 = 3.3345e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.78637258 ++lvth0 = -4.4329423e-008 ++wvth0 = -2.1422215e-008 ++pvth0 = 2.0851079e-015 ++k1 = 0.96652273 ++lk1 = -1.0562749e-007 ++k2 = 0.043846284 ++lk2 = -3.9983252e-008 ++wk2 = -1.2847784e-008 ++pk2 = 3.7258573e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.07880914 ++lvoff = -9.6862495e-009 ++wvoff = -1.7318909e-008 ++pvoff = 5.0224835e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032725347 ++lu0 = 4.2490518e-009 ++wu0 = 1.4619976e-010 ++pu0 = -3.6449187e-016 ++ua = -6.5842313e-010 ++lua = 4.2195702e-016 ++wua = 1.8008954e-017 ++pua = 4.0147707e-024 ++ub = 2.29126e-018 ++lub = -9.7593592e-026 ++wub = 1.3094736e-025 ++pub = -2.5350945e-031 ++uc = 1.6123011e-010 ++luc = -3.6357518e-017 ++wuc = 5.103582e-019 ++puc = -7.8269268e-024 ++eu = 1.67 ++vsat = 64899.351 ++lvsat = 0.0045138312 ++wvsat = 0.0097853084 ++pvsat = -2.1440698e-009 ++a0 = 0.10689312 ++la0 = -1.7844039e-009 ++wa0 = -3.7706055e-009 ++pa0 = 1.0934756e-015 ++ags = 0.35614518 ++lags = -1.2574141e-008 ++wags = 3.3556722e-008 ++pags = -1.4381348e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12710186 ++lketa = 3.1977949e-008 ++wketa = -3.4494299e-009 ++pketa = 1.7592093e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.46474849 ++lpclm = -8.4380551e-008 ++wpclm = -2.1249703e-008 ++ppclm = 2.5305384e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0034090909 ++ldelta = 3.3613636e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6705875e-006 ++lalpha0 = -2.9783362e-013 ++walpha0 = 5.0764006e-014 ++palpha0 = -2.5889643e-020 ++alpha1 = 0 ++beta0 = 20.985833 ++lbeta0 = -9.3517938e-008 ++wbeta0 = -3.8050353e-007 ++pbeta0 = 1.0988358e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37899643 ++lkt1 = 1.7695179e-008 ++wkt1 = -7.2309805e-009 ++pkt1 = 3.6878001e-015 ++kt1l = 0 ++kt2 = -0.014401245 ++lkt2 = -3.492865e-009 ++wkt2 = -3.8792949e-009 ++pkt2 = 1.9784404e-015 ++ute = -1.4339286 ++wute = 3.9866071e-008 ++ua1 = 1.675e-009 ++ub1 = -3.6760182e-018 ++lub1 = 2.6245527e-025 ++wub1 = 7.9456704e-026 ++pub1 = -4.0522919e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.73523913 ++lvth0 = -1.8251362e-008 ++wvth0 = -1.0759625e-008 ++pvth0 = -3.3528129e-015 ++k1 = 0.76831276 ++lk1 = -4.5404077e-009 ++wk1 = -1.0460743e-008 ++pk1 = 5.334979e-015 ++k2 = 0.0086062399 ++lk2 = -2.201083e-008 ++wk2 = 4.4618175e-009 ++pk2 = -5.1020394e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12063313 ++lvoff = 1.1643984e-008 ++wvoff = 5.4430856e-009 ++pvoff = -6.5861336e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031100065 ++lu0 = 5.0779459e-009 ++wu0 = 1.3854029e-010 ++pu0 = -3.6058554e-016 ++ua = -1.1698757e-009 ++lua = 6.8279785e-016 ++wua = -1.8856196e-017 ++pua = 2.2815997e-023 ++ub = 2.8309252e-018 ++lub = -3.7282285e-025 ++wub = 9.9986385e-026 ++pub = -2.3771936e-031 ++uc = 8.1961957e-011 ++luc = 4.0692393e-018 ++wuc = 3.5972295e-018 ++puc = -9.4012312e-024 ++eu = 1.67 ++vsat = 81960.714 ++lvsat = -0.0041874643 ++wvsat = -0.0040663393 ++pvsat = 4.9202705e-009 ++a0 = 0.98260745 ++la0 = -4.4839871e-007 ++wa0 = 1.1850475e-009 ++pa0 = -1.4339074e-015 ++ags = 0.44253343 ++lags = -5.6632149e-008 ++wags = 6.0928114e-008 ++pags = -2.8340758e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043717643 ++lketa = -1.0548002e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.21633117 ++lpclm = 4.231228e-008 ++wpclm = -2.0668622e-008 ++ppclm = 2.5009032e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013439 ++lpdiblc2= 9.31821e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013571429 ++ldelta = 4.4078571e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.854642e-006 ++lalpha0 = -2.4317014e-012 ++walpha0 = -1.3175851e-013 ++palpha0 = 6.7196838e-020 ++alpha1 = 0 ++beta0 = 21.041625 ++lbeta0 = -1.219717e-007 ++wbeta0 = 4.1105337e-007 ++pbeta0 = -2.9381044e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.40824973 ++lkt1 = 3.2614365e-008 ++wkt1 = 3.0376124e-008 ++pkt1 = -1.5491823e-014 ++kt1l = 0 ++kt2 = -0.031266454 ++lkt2 = 5.1083916e-009 ++wkt2 = 5.1683514e-009 ++pkt2 = -2.6358592e-015 ++ute = -1.4339286 ++wute = 3.9866071e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8063699e-018 ++lub1 = -1.8106533e-025 ++wub1 = 5.912594e-026 ++pub1 = -3.0154229e-032 ++uc1 = -1.1914311e-010 ++luc1 = 3.2202986e-017 ++wuc1 = 2.9992977e-017 ++puc1 = -1.5296418e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.70918783 ++lvth0 = 1.3270713e-008 ++wvth0 = -3.9984673e-009 ++pvth0 = -1.1533814e-014 ++k1 = 0.79422595 ++lk1 = -3.5895368e-008 ++wk1 = 8.3210458e-010 ++pk1 = -8.3293668e-015 ++k2 = -0.0057375564 ++lk2 = -4.6548363e-009 ++wk2 = -1.9783209e-009 ++pk2 = 2.6905281e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12198688 ++lvoff = 1.3282019e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036480486 ++lu0 = -1.432364e-009 ++wu0 = -1.2523428e-009 ++pu0 = 1.322383e-015 ++ua = -7.8835147e-010 ++lua = 2.2115348e-016 ++wua = -6.9926086e-018 ++pua = 8.4610564e-024 ++ub = 3.0585412e-018 ++lub = -6.4823822e-025 ++wub = -1.6567642e-025 ++pub = 8.3732633e-032 ++uc = 9.7494752e-011 ++luc = -1.4725443e-017 ++wuc = -8.3407396e-018 ++puc = 5.0437114e-024 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.2339809 ++la0 = -7.5256056e-007 ++ags = 0.28346322 ++lags = 1.3584281e-007 ++wags = -1.4852404e-008 ++pags = 6.3353669e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0209945 ++lketa = -3.8043005e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22691687 ++lpclm = 2.9503581e-008 ++wpclm = -1.5817263e-008 ++ppclm = 1.9138888e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0006386625 ++lpdiblc2= 1.7851584e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.002725 ++ldelta = 2.75275e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1007216e-005 ++lalpha0 = -1.0425632e-010 ++walpha0 = 1.048079e-014 ++palpha0 = -1.0491271e-019 ++alpha1 = 0 ++beta0 = 24.044693 ++lbeta0 = -3.755685e-006 ++wbeta0 = 1.9272256e-007 ++pbeta0 = -2.9630159e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33921309 ++lkt1 = -5.0919976e-008 ++wkt1 = -2.4162826e-009 ++pkt1 = 2.4186989e-014 ++kt1l = 0 ++kt2 = -0.021793862 ++lkt2 = -6.3534453e-009 ++wkt2 = 4.9583426e-010 ++pkt2 = 3.0178865e-015 ++ute = -1.7203348 ++lute = 3.4655156e-007 ++wute = 1.7590904e-007 ++pute = -1.6461199e-013 ++ua1 = 1.675e-009 ++ub1 = -3.5425504e-018 ++lub1 = 7.0971302e-025 ++wub1 = 5.0953922e-025 ++pub1 = -5.751543e-031 ++uc1 = -5.0977253e-011 ++luc1 = -5.0277701e-017 ++wuc1 = -2.385805e-018 ++puc1 = 2.3881908e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.71051357 ++wvth0 = -5.1506964e-009 ++k1 = 0.79064 ++k2 = -0.006202575 ++wk2 = -1.7095369e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036337393 ++wu0 = -1.1202366e-009 ++ua = -7.6625821e-010 ++wua = -6.1473482e-018 ++ub = 2.9937821e-018 ++wub = -1.5731152e-025 ++uc = 9.6023679e-011 ++wuc = -7.8368723e-018 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.1588 ++ags = 0.29703393 ++wags = -8.5233661e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.22986429 ++wpclm = -1.3905286e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6695 ++wbeta0 = 1.897625e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.022428571 ++wkt2 = 7.9732143e-010 ++ute = -1.6857143 ++wute = 1.5946429e-007 ++ua1 = 1.675e-009 ++ub1 = -3.47165e-018 ++wub1 = 4.5208125e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.81815039 ++lvth0 = -5.8885304e-008 ++wvth0 = -5.8761136e-008 ++pvth0 = 1.9188267e-014 ++k1 = 0.95743806 ++lk1 = -1.0099431e-007 ++wk1 = 1.0674487e-008 ++pk1 = -5.4439881e-015 ++k2 = 0.016113039 ++lk2 = -3.1940611e-008 ++wk2 = 1.973878e-008 ++pk2 = -5.7242461e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12427998 ++lvoff = 7.2259769e-010 ++wvoff = 3.6109333e-008 ++pvoff = -7.2079119e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046878971 ++lu0 = 1.8200638e-010 ++wu0 = -1.6484308e-008 ++pu0 = 4.4142864e-015 ++ua = -6.8024396e-010 ++lua = 2.6903445e-016 ++wua = 4.3648431e-017 ++pua = 1.8369878e-022 ++ub = 3.8192473e-018 ++lub = -3.5114332e-025 ++wub = -1.6644377e-024 ++pub = 4.4411482e-032 ++uc = 2.9916081e-010 ++luc = -7.1885433e-017 ++wuc = -1.6155822e-016 ++puc = 3.3918374e-023 ++eu = 1.67 ++vsat = 79204.029 ++lvsat = -0.00035905475 ++wvsat = -0.0070226885 ++pvsat = 3.5815711e-009 ++a0 = 0.10368409 ++la0 = -8.5378636e-010 ++ags = 0.26826194 ++lags = 3.4571911e-008 ++wags = 1.3681953e-007 ++pags = -6.977796e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12637977 ++lketa = 3.1609683e-008 ++wketa = -4.2978854e-009 ++pketa = 2.1919215e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.20558963 ++lpclm = -1.0377847e-008 ++wpclm = 2.8326196e-007 ++ppclm = -6.1647793e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0034090909 ++ldelta = 3.3613636e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6135308e-006 ++lalpha0 = -2.6873472e-013 ++walpha0 = 1.178056e-013 ++palpha0 = -6.0080856e-020 ++alpha1 = 0 ++beta0 = 21.140347 ++wbeta0 = -5.6205724e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.68954029 ++lnoff = 1.3716655e-006 ++wnoff = 3.1602098e-006 ++pnoff = -1.611707e-012 ++voffcv = 0.2365993 ++lvoffcv = -1.1811564e-007 ++wvoffcv = -2.7212918e-007 ++pvoffcv = 1.3878588e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28048406 ++lkt1 = -1.0653613e-008 ++wkt1 = -1.2298302e-007 ++pkt1 = 3.699763e-014 ++kt1l = 0 ++kt2 = -0.025514754 ++lkt2 = 1.0188312e-009 ++wkt2 = 9.1790777e-009 ++pkt2 = -3.3228026e-015 ++ute = -1.5700284 ++wute = 1.9978338e-007 ++ua1 = 1.675e-009 ++ub1 = -5.4123917e-018 ++lub1 = 5.0984495e-025 ++wub1 = 2.1196956e-024 ++pub1 = -3.3120579e-031 ++uc1 = -2.3284907e-010 ++luc1 = 5.2512691e-017 ++wuc1 = 2.0779766e-016 ++puc1 = -6.1702412e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.7227726 ++lvth0 = -1.0242633e-008 ++wvth0 = 3.8885457e-009 ++pvth0 = -1.276307e-014 ++k1 = 0.75941 ++k2 = 0.017683205 ++lk2 = -3.2741396e-008 ++wk2 = -6.2036165e-009 ++pk2 = 7.5063759e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10237415 ++lvoff = -1.0449376e-008 ++wvoff = -1.6011211e-008 ++pvoff = 1.9373565e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038388296 ++lu0 = 4.5122507e-009 ++wu0 = -8.4251315e-009 ++pu0 = 3.0410627e-016 ++ua = -9.355169e-010 ++lua = 3.9922365e-016 ++wua = -2.9422783e-016 ++pua = 3.5601568e-022 ++ub = 3.4750928e-018 ++lub = -1.7562456e-025 ++wub = -6.5691059e-025 ++pub = -4.6942736e-031 ++uc = 1.571796e-010 ++luc = 5.249858e-019 ++wuc = -8.47835e-017 ++puc = -5.2367334e-024 ++eu = 1.67 ++vsat = 78500 ++a0 = 0.58388391 ++la0 = -2.4575569e-007 ++wa0 = 4.6968521e-007 ++pa0 = -2.3953946e-013 ++ags = 0.63581483 ++lags = -1.5288006e-007 ++wags = -1.6617753e-007 ++pags = 8.4750542e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043717643 ++lketa = -1.0548002e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.046649798 ++lpclm = 7.0681467e-008 ++wpclm = 1.7870699e-007 ++ppclm = -8.3247623e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013439 ++lpdiblc2= 9.31821e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013571429 ++ldelta = 4.4078571e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7425071e-006 ++lalpha0 = -2.3745126e-012 ++alpha1 = 0 ++beta0 = 21.042948 ++lbeta0 = 4.9673545e-008 ++wbeta0 = 4.0949885e-007 ++pbeta0 = -4.9549361e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30302683 ++lkt1 = 8.4320304e-010 ++wkt1 = -9.3260785e-008 ++pkt1 = 2.1839292e-014 ++kt1l = 0 ++kt2 = -0.021787246 ++lkt2 = -8.8219755e-010 ++wkt2 = -5.9697177e-009 ++pkt2 = 4.403083e-015 ++ute = -1.5700284 ++wute = 1.9978338e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0217801e-018 ++lub1 = -7.0936697e-025 ++wub1 = 3.1223288e-025 ++pub1 = 5.906002e-031 ++uc1 = -1.4521817e-010 ++luc1 = 7.820931e-018 ++wuc1 = 6.0631174e-017 ++puc1 = 1.3352496e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.70815167 ++lvth0 = 7.4486913e-009 ++wvth0 = -2.7809847e-009 ++pvth0 = -4.6929382e-015 ++k1 = 0.79751289 ++lk1 = -4.6104496e-008 ++wk1 = -3.0300479e-009 ++pk1 = 3.666358e-015 ++k2 = -0.0074212337 ++lk2 = -2.3650252e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12198688 ++lvoff = 1.3282019e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040489883 ++lu0 = 1.9693306e-009 ++wu0 = -5.9633841e-009 ++pu0 = -2.6746082e-015 ++ua = -8.1092276e-010 ++lua = 2.4846474e-016 ++wua = 1.9528659e-017 ++pua = -2.3629677e-023 ++ub = 3.1893035e-018 ++lub = 1.7018056e-025 ++wub = -3.193221e-025 ++pub = -8.7790942e-031 ++uc = 1.0426802e-010 ++luc = 6.4547999e-017 ++wuc = -1.6299327e-017 ++puc = -8.8102583e-023 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.1761657 ++la0 = -9.6241665e-007 ++wa0 = 6.7932842e-008 ++pa0 = 2.4658091e-013 ++ags = 0.26705136 ++lags = 2.9332373e-007 ++wags = 4.4315284e-009 ++pags = -1.2168642e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0209945 ++lketa = -3.8043005e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23356279 ++lpclm = -1.5548326e-007 ++wpclm = -2.3626216e-008 ++ppclm = 2.3649842e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0006386625 ++lpdiblc2= 1.7851584e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.002725 ++ldelta = 2.75275e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1016136e-005 ++lalpha0 = -1.043456e-010 ++alpha1 = 0 ++beta0 = 24.515585 ++lbeta0 = -4.1522184e-006 ++wbeta0 = -3.605757e-007 ++pbeta0 = 4.362966e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1289382 ++lnoff = -1.5601523e-007 ++wnoff = -1.515024e-007 ++pnoff = 1.833179e-013 ++voffcv = -0.065916016 ++lvoffcv = 8.5808379e-008 ++wvoffcv = 8.3326318e-008 ++pvoffcv = -1.0082485e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31508994 ++lkt1 = 1.5439565e-008 ++wkt1 = -3.076098e-008 ++pkt1 = -5.3785472e-014 ++kt1l = 0 ++kt2 = -0.016809446 ++lkt2 = -6.9053359e-009 ++wkt2 = -5.3608541e-009 ++pkt2 = 3.666358e-015 ++ute = -1.5472461 ++lute = -2.7566602e-008 ++wute = -2.7470215e-008 ++pute = 2.7497685e-013 ++ua1 = 1.6533384e-009 ++lua1 = 2.6210559e-017 ++wua1 = 2.5452403e-017 ++pua1 = -3.0797407e-023 ++ub1 = -2.147361e-018 ++lub1 = -1.7674141e-024 ++wub1 = -1.1298083e-024 ++pub1 = 2.3354701e-030 ++uc1 = -4.4621244e-011 ++luc1 = -1.1390135e-016 ++wuc1 = -9.8541155e-018 ++puc1 = 9.8639696e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.7088958 ++wvth0 = -3.2498097e-009 ++k1 = 0.79290705 ++wk1 = -2.6637784e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040686619 ++wu0 = -6.2305777e-009 ++ua = -7.8610111e-010 ++wua = 1.7168052e-017 ++ub = 3.2063045e-018 ++wub = -4.0702534e-025 ++uc = 1.1071637e-010 ++wuc = -2.5100784e-017 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.0800202 ++wa0 = 9.25663e-008 ++ags = 0.29635443 ++wags = -7.7249574e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.100778 ++wbeta0 = -3.1698963e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1133523 ++wnoff = -1.3318892e-007 ++voffcv = -0.05734375 ++wvoffcv = 7.3253906e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31354753 ++wkt1 = -3.6134154e-008 ++kt1l = 0 ++kt2 = -0.01749929 ++wkt2 = -4.9945845e-009 ++ute = -1.55 ++ua1 = 1.6559568e-009 ++wua1 = 2.2375739e-017 ++ub1 = -2.3239259e-018 ++wub1 = -8.9649462e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.81225955 ++lvth0 = -5.6961668e-008 ++k1 = 0.95850818 ++lk1 = -1.0154007e-007 ++k2 = 0.018091864 ++lk2 = -3.2514471e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045226409 ++lu0 = 6.2454136e-010 ++ua = -6.7586818e-010 ++lua = 2.8745037e-016 ++ub = 3.6523864e-018 ++lub = -3.4669104e-025 ++uc = 2.829645e-010 ++luc = -6.8485095e-017 ++eu = 1.67 ++vsat = 78500 ++a0 = 0.13319227 ++la0 = -1.5902956e-008 ++wa0 = -2.9434406e-007 ++pa0 = 1.5011547e-013 ++ags = 0.46602357 ++lags = -6.6286522e-008 ++wags = -1.8358528e-006 ++pags = 9.3628492e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12307965 ++lketa = 2.9926622e-008 ++wketa = -3.7216588e-008 ++pketa = 1.898046e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23398682 ++lpclm = -1.6558077e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0034090909 ++ldelta = 3.3613636e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6253409e-006 ++lalpha0 = -2.7475786e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.415e-010 ++cgdo = 2.415e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.37272727 ++lnoff = 1.2100909e-006 ++voffcv = 0.20931818 ++lvoffcv = -1.0420227e-007 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29281318 ++lkt1 = -6.9445773e-009 ++kt1l = 0 ++kt2 = -0.024594545 ++lkt2 = 6.8571818e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.1998909e-018 ++lub1 = 4.7664136e-025 ++uc1 = -2.1201723e-010 ++luc1 = 4.6326986e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.72316243 ++lvth0 = -1.1522139e-008 ++k1 = 0.75941 ++k2 = 0.017061289 ++lk2 = -3.1988877e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10397929 ++lvoff = -8.5071643e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.037543671 ++lu0 = 4.5427376e-009 ++ua = -9.6501343e-010 ++lua = 4.3491445e-016 ++ub = 3.4092371e-018 ++lub = -2.2268494e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 78500 ++a0 = 0.63097014 ++la0 = -2.6976967e-007 ++ags = 0.61915543 ++lags = -1.4438377e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043717643 ++lketa = -1.0548002e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.064565286 ++lpclm = 6.9846904e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0013439 ++lpdiblc2= 9.31821e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0013571429 ++ldelta = 4.4078571e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7425071e-006 ++lalpha0 = -2.3745126e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31237629 ++lkt1 = 3.0326057e-009 ++kt1l = 0 ++kt2 = -0.022385714 ++lkt2 = -4.4078571e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -2.9904786e-018 ++lub1 = -6.5015893e-025 ++uc1 = -1.3913986e-010 ++luc1 = 9.1595271e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.70787288 ++lvth0 = 6.9782212e-009 ++k1 = 0.79720913 ++lk1 = -4.5736941e-008 ++k2 = -0.0074212337 ++lk2 = -2.3650252e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12198688 ++lvoff = 1.3282019e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.03989205 ++lu0 = 1.7011995e-009 ++ua = -8.08965e-010 ++lua = 2.4609585e-016 ++ub = 3.1572912e-018 ++lub = 8.2169587e-026 ++uc = 1.02634e-010 ++luc = 5.571566e-017 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.182976 ++la0 = -9.3769676e-007 ++ags = 0.26749563 ++lags = 2.8112459e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.0209945 ++lketa = -3.8043005e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23119425 ++lpclm = -1.3177414e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.0006386625 ++lpdiblc2= 1.7851584e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.002725 ++ldelta = 2.75275e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.1016136e-005 ++lalpha0 = -1.043456e-010 ++alpha1 = 0 ++beta0 = 24.479438 ++lbeta0 = -4.1084794e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1.115e-010 ++cgdo = 1.115e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.11375 ++lnoff = -1.376375e-007 ++voffcv = -0.0575625 ++lvoffcv = 7.5700625e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31817375 ++lkt1 = 1.0047538e-008 ++kt1l = 0 ++kt2 = -0.017346875 ++lkt2 = -6.5377812e-009 ++ute = -1.55 ++ua1 = 1.65589e-009 ++lua1 = 2.31231e-017 ++ub1 = -2.260625e-018 ++lub1 = -1.5332818e-024 ++uc1 = -4.5609125e-011 ++luc1 = -1.0401266e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.2e-009 ++toxp = 8.2e-009 ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1e-008 ++xw = -5e-009 ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = 0.70857 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 78500 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 530 ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.415e-010 ++cgdo = 2.415e-010 ++cgbo = 1e-013 ++cgdl = 1.05e-010 ++cgsl = 1.05e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +*resistor + +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + + +.endl nmos_3p3_sf +* +*************************************************************************************************** +* 3.3V PMOS Models +*************************************************************************************************** +* +.lib pmos_3p3_t + + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7506174 ++lvth0 = -7.6827273e-009 ++wvth0 = 4.2938493e-009 ++pvth0 = 2.3570182e-015 ++k1 = 0.86959286 ++lk1 = 4.91e-009 ++wk1 = 6.7137132e-008 ++pk1 = -2.0974909e-014 ++k2 = 0.029351195 ++lk2 = -2.4890454e-008 ++wk2 = -2.1522854e-008 ++pk2 = 3.4158327e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094658091 ++lvoff = -1.6014546e-009 ++wvoff = -1.6655127e-009 ++pvoff = 8.3275636e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0077071688 ++lu0 = 2.4492727e-009 ++wu0 = 6.0892675e-010 ++pu0 = -5.2642909e-016 ++ua = -2.4381818e-012 ++lua = 1.0386891e-015 ++wua = 3.3100364e-018 ++pua = -1.9180342e-022 ++ub = 6.7035533e-019 ++lub = -1.4361909e-025 ++wub = -4.8420779e-027 ++pub = 1.3557818e-033 ++uc = 8.6801065e-011 ++luc = 8.4861818e-018 ++wuc = -1.3364176e-017 ++puc = -4.4743636e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.0272635 ++la0 = -2.0434818e-007 ++wa0 = 1.1112467e-008 ++pa0 = -2.7370909e-015 ++ags = 0.19081247 ++lags = 1.0492091e-007 ++wags = -2.3219283e-008 ++pags = -1.2080073e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.066404636 ++lketa = 8.2658182e-009 ++wketa = -7.3229236e-009 ++pketa = 3.6614618e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.35627558 ++lpclm = 7.0823636e-008 ++wpclm = 2.9266005e-008 ++ppclm = 6.5406545e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1485698e-005 ++lalpha0 = -3.0054064e-012 ++walpha0 = -1.0325417e-013 ++palpha0 = 6.39288e-020 ++alpha1 = 0 ++beta0 = 39.773597 ++lbeta0 = -3.6237273e-006 ++wbeta0 = 2.1005299e-007 ++pbeta0 = 1.1827636e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28373805 ++lkt1 = -1.5974545e-008 ++wkt1 = -1.1172031e-008 ++pkt1 = 1.9400727e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1563636e-009 ++lua1 = 1.7181818e-016 ++wua1 = 1.7869091e-016 ++pua1 = -8.9345454e-023 ++ub1 = -2.100161e-018 ++lub1 = -6.7359091e-025 ++wub1 = -1.4002317e-025 ++pub1 = 1.4950473e-031 ++uc1 = -2.5418182e-010 ++luc1 = 5.8570909e-017 ++wuc1 = 4.0843636e-017 ++puc1 = -1.4057018e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.78216327 ++lvth0 = 8.0902041e-009 ++wvth0 = 5.9668408e-009 ++pvth0 = 1.5205225e-015 ++k1 = 1.011648 ++lk1 = -6.6117551e-008 ++wk1 = -1.7990939e-008 ++pk1 = 2.1589126e-014 ++k2 = -0.018784 ++lk2 = -8.2285714e-010 ++wk2 = -2.5231886e-009 ++pk2 = -6.084e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12364214 ++lvoff = 1.2890571e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010288147 ++lu0 = 1.1587837e-009 ++wu0 = -2.4611069e-010 ++pu0 = -9.8910367e-017 ++ua = 3.7095469e-010 ++lua = 8.5199265e-016 ++wua = -4.3130498e-017 ++pua = -1.6858315e-022 ++ub = 1.0877988e-018 ++lub = -3.5234082e-025 ++wub = -1.9235628e-025 ++pub = 9.5112882e-032 ++uc = -1.3265853e-011 ++luc = 5.8519641e-017 ++wuc = -7.386721e-018 ++puc = -7.4630909e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1510659 ++la0 = -2.6624939e-007 ++wa0 = 3.8929322e-008 ++pa0 = -1.6645518e-014 ++ags = 0.19022326 ++lags = 1.0521551e-007 ++wags = 1.3854074e-008 ++pags = -3.0616751e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0050909592 ++lketa = -2.239102e-008 ++wketa = -2.2043755e-009 ++pketa = 1.1021878e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.25657102 ++lpclm = 1.2067592e-007 ++wpclm = 8.5357469e-008 ++ppclm = -2.1505078e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.5504633e-005 ++lalpha0 = -3.5014873e-011 ++walpha0 = 4.8045453e-012 ++palpha0 = -2.3899709e-018 ++alpha1 = 0 ++beta0 = 42.422959 ++lbeta0 = -4.9484082e-006 ++wbeta0 = 2.7621551e-007 ++pbeta0 = 8.5195102e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30703735 ++lkt1 = -4.324898e-009 ++wkt1 = 2.5044049e-008 ++pkt1 = -1.6167967e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2391388e-018 ++lub1 = -6.0410204e-025 ++wub1 = -3.3103837e-026 ++pub1 = 9.6045061e-032 ++uc1 = -7.5563755e-011 ++luc1 = -3.0738122e-017 ++wuc1 = 6.2211526e-018 ++puc1 = 3.2542237e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76745877 ++lvth0 = -9.5551948e-009 ++wvth0 = 3.6783584e-009 ++pvth0 = 4.2667013e-015 ++k1 = 0.95493474 ++lk1 = 1.9383117e-009 ++wk1 = 3.0592208e-008 ++pk1 = -3.6710649e-014 ++k2 = -0.010993416 ++lk2 = -1.0171558e-008 ++wk2 = -1.5055864e-008 ++pk2 = 8.9552104e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097716396 ++lvoff = -1.8220325e-008 ++wvoff = 9.9120779e-010 ++pvoff = -1.1894494e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087516409 ++lu0 = 3.0025909e-009 ++wu0 = 2.1888218e-010 ++pu0 = -6.5690182e-016 ++ua = 3.9822779e-010 ++lua = 8.1926494e-016 ++wua = -5.2662561e-017 ++pua = -1.5714468e-022 ++ub = 8.5181617e-019 ++lub = -6.9161688e-026 ++wub = -1.0966152e-025 ++pub = -4.1208312e-033 ++uc = -4.4095525e-011 ++luc = 9.5515247e-017 ++wuc = 1.8553586e-018 ++puc = -1.8553586e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2626103 ++la0 = -4.001026e-007 ++wa0 = -3.4170078e-009 ++pa0 = 3.4170078e-014 ++ags = 0.15731682 ++lags = 1.4470325e-007 ++wags = 7.2894545e-010 ++pags = -1.4866597e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.00016272403 ++lketa = -2.8304903e-008 ++wketa = -3.463048e-009 ++pketa = 2.6125948e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32143299 ++lpclm = 4.2841558e-008 ++wpclm = 4.9757922e-009 ++ppclm = 7.4952935e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020588939 ++lalpha0 = -2.415082e-009 ++walpha0 = 2.2256682e-011 ++palpha0 = -2.3332535e-017 ++alpha1 = 0 ++beta0 = 44.45026 ++lbeta0 = -7.3811688e-006 ++wbeta0 = 4.0343221e-007 ++pbeta0 = -6.7464935e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.26850506 ++lkt1 = -5.0563636e-008 ++wkt1 = -1.0340166e-008 ++pkt1 = 2.6293091e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0202519e-018 ++lub1 = 3.3323377e-025 ++wub1 = 1.9133501e-025 ++pub1 = -1.7328156e-031 ++uc1 = -3.5566519e-011 ++luc1 = -7.8734805e-017 ++wuc1 = -1.2279955e-017 ++puc1 = 2.5455553e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76841429 ++wvth0 = 4.1050286e-009 ++k1 = 0.95512857 ++wk1 = 2.6921143e-008 ++k2 = -0.012010571 ++wk2 = -1.4160343e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099538429 ++wvoff = 8.7226286e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090519 ++wu0 = 1.53192e-010 ++ua = 4.8015429e-010 ++wua = -6.8377029e-017 ++ub = 8.449e-019 ++wub = -1.100736e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2226 ++ags = 0.17178714 ++wags = -7.5771429e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0029932143 ++wketa = -3.2017886e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.32571714 ++wpclm = 1.2471086e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018173857 ++walpha0 = 1.9923429e-011 ++alpha1 = 0 ++beta0 = 43.712143 ++wbeta0 = 3.9668571e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.27356143 ++wkt1 = -7.7108571e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.9869286e-018 ++wub1 = 1.7400686e-025 ++uc1 = -4.344e-011 ++wuc1 = -9.7344e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7710094 ++lvth0 = -2.1407273e-009 ++wvth0 = 1.4897689e-008 ++pvth0 = -5.2482182e-016 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = 0.014249873 ++lk2 = -2.0467636e-008 ++wk2 = -1.3670166e-008 ++pk2 = 1.1159673e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0091928468 ++lu0 = 1.8372909e-009 ++wu0 = -1.6362577e-010 ++pu0 = -2.0819854e-016 ++ua = -8.0522078e-011 ++lua = 7.4813818e-016 ++wua = 4.3913662e-017 ++pua = -4.0716945e-023 ++ub = 1.748897e-018 ++lub = -3.0903909e-025 ++wub = -5.6568377e-025 ++pub = 8.7374182e-032 ++uc = 8.6704408e-011 ++luc = 1.2453182e-017 ++wuc = -1.3313914e-017 ++puc = -6.5372036e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.66833429 ++la0 = -1.03128e-007 ++wa0 = 1.9775566e-007 ++pa0 = -5.5371585e-014 ++ags = 0.20459958 ++lags = 6.9689636e-008 ++wags = -3.0388584e-008 ++pags = 6.2401891e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.10490303 ++lketa = 2.2143527e-008 ++wketa = 1.2696239e-008 ++pketa = -3.5549469e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.3781492 ++lpclm = 2.7248545e-008 ++wpclm = 1.7891728e-008 ++ppclm = 2.9199702e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.2079775e-005 ++lalpha0 = -3.0255502e-012 ++walpha0 = -4.121738e-013 ++palpha0 = 7.4403585e-020 ++alpha1 = 0 ++beta0 = 38.238696 ++lbeta0 = -2.7152909e-006 ++wbeta0 = 1.0082017e-006 ++pbeta0 = -3.5411055e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33225761 ++lkt1 = 5.3309091e-010 ++wkt1 = 1.4058139e-008 ++pkt1 = -6.6438982e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 2.0124e-009 ++lua1 = -2.562e-016 ++wua1 = -2.66448e-016 ++pua1 = 1.33224e-022 ++ub1 = -2.8876353e-018 ++lub1 = -2.9730909e-026 ++wub1 = 2.6946346e-025 ++pub1 = -1.8530247e-031 ++uc1 = 6.432e-012 ++luc1 = -3.4608e-017 ++wuc1 = -9.4675549e-017 ++puc1 = 3.4396015e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.77464237 ++lvth0 = -3.242449e-010 ++wvth0 = 2.0559739e-009 ++pvth0 = 5.8960359e-015 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.026847376 ++lk2 = 8.0987755e-011 ++wk2 = 1.6697667e-009 ++pk2 = -6.5539994e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12364214 ++lvoff = 1.2890571e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097471347 ++lu0 = 1.5601469e-009 ++wu0 = 3.5215673e-011 ++pu0 = -3.0761926e-016 ++ua = 2.6778433e-010 ++lua = 5.7398498e-016 ++wua = 1.0518093e-017 ++pua = -2.4019161e-023 ++ub = 1.2732368e-018 ++lub = -7.120898e-026 ++wub = -2.8878406e-025 ++pub = -5.1075673e-032 ++uc = 8.0016841e-012 ++luc = 5.1804544e-017 ++wuc = -1.844584e-017 ++puc = -3.9712404e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.3454526 ++la0 = -4.4168718e-007 ++wa0 = -6.215178e-008 ++pa0 = 7.4582136e-014 ++ags = 0.19226653 ++lags = 7.5856163e-008 ++wags = 1.2791576e-008 ++pags = -1.5349891e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0016565918 ++lketa = -2.947969e-008 ++wketa = -3.9902465e-009 ++pketa = 4.7882958e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.55246506 ++lpclm = -5.9909388e-008 ++wpclm = -6.8507432e-008 ++ppclm = 7.2399282e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.000123026 ++lalpha0 = -5.8498663e-011 ++walpha0 = -1.9906566e-011 ++palpha0 = 9.8215995e-018 ++alpha1 = 0 ++beta0 = 43.366204 ++lbeta0 = -5.2790449e-006 ++wbeta0 = -2.1427184e-007 ++pbeta0 = 2.571262e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28366163 ++lkt1 = -2.3764898e-008 ++wkt1 = 1.2888678e-008 ++pkt1 = -6.0591673e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.1375788e-018 ++lub1 = 9.5240816e-026 ++wub1 = 4.3408496e-025 ++pub1 = -2.6761322e-031 ++uc1 = -9.9154286e-011 ++luc1 = 1.8185143e-017 ++wuc1 = 1.8488229e-017 ++puc1 = -2.2185874e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.77376777 ++lvth0 = -1.3737662e-009 ++wvth0 = 6.9590384e-009 ++pvth0 = 1.2358442e-017 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.027452061 ++lk2 = 8.0661039e-010 ++wk2 = -6.4973683e-009 ++pk2 = 3.2465626e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095810227 ++lvoff = -2.0507727e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097323026 ++lu0 = 1.5779454e-009 ++wu0 = -2.910619e-010 ++pu0 = 8.3913818e-017 ++ua = 4.0315384e-010 ++lua = 4.1154156e-016 ++wua = -5.5224108e-017 ++pua = 5.487148e-023 ++ub = 1.1661759e-018 ++lub = 5.7264156e-026 ++wub = -2.7312856e-025 ++pub = -6.986227e-032 ++uc = 1.1632475e-012 ++luc = 6.0010667e-017 ++wuc = -2.1679203e-017 ++puc = -9.1205299e-026 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1189871 ++la0 = -1.6992857e-007 ++wa0 = 7.1267013e-008 ++pa0 = -8.5520416e-014 ++ags = 0.16561084 ++lags = 1.0784299e-007 ++wags = -3.583948e-009 ++pags = 4.3007377e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.3288581 ++lpclm = 2.0841896e-007 ++wpclm = 1.1147314e-009 ++ppclm = -1.1147314e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.002173683 ++lalpha0 = -2.519287e-009 ++walpha0 = -3.7433637e-011 ++palpha0 = 3.0854085e-017 ++alpha1 = 0 ++beta0 = 44.354662 ++lbeta0 = -6.4651948e-006 ++wbeta0 = 4.5314286e-007 ++pbeta0 = -5.4377143e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33774851 ++lkt1 = 4.1139351e-008 ++wkt1 = 2.5666423e-008 ++pkt1 = -2.1392462e-014 ++kt1l = 0 ++kt2 = -0.016947818 ++lkt2 = 4.6581818e-009 ++wkt2 = 2.0185455e-009 ++pkt2 = -2.4222546e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5969484e-018 ++lub1 = -5.5351558e-025 ++wub1 = -2.878281e-026 ++pub1 = 2.878281e-031 ++uc1 = -4.2545455e-011 ++luc1 = -4.9745455e-017 ++wuc1 = -8.6509091e-018 ++puc1 = 1.0381091e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.77390514 ++wvth0 = 6.9602743e-009 ++k1 = 1.0069 ++k2 = -0.0273714 ++wk2 = -6.172712e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0098900971 ++wu0 = -2.8267051e-010 ++ua = 4.44308e-010 ++wua = -4.973696e-017 ++ub = 1.1719023e-018 ++wub = -2.8011479e-025 ++uc = 7.1643143e-012 ++wuc = -2.1688323e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1019943 ++wa0 = 6.2714971e-008 ++ags = 0.17639514 ++wags = -3.1538743e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0019217543 ++walpha0 = -3.4348229e-011 ++alpha1 = 0 ++beta0 = 43.708143 ++wbeta0 = 3.9876571e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33363457 ++wkt1 = 2.3527177e-008 ++kt1l = 0 ++kt2 = -0.016482 ++wkt2 = 1.77632e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.752e-011 ++wuc1 = -7.6128e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76226585 ++lvth0 = -8.7733719e-009 ++wvth0 = 4.2305517e-009 ++pvth0 = 7.5670046e-015 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = -0.00067810868 ++lk2 = -1.7691446e-008 ++wk2 = 4.5419708e-009 ++pk2 = -2.2709854e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011352976 ++lu0 = 1.7890915e-009 ++wu0 = -2.7989835e-009 ++pu0 = -1.493953e-016 ++ua = 3.4788822e-010 ++lua = 6.3071157e-016 ++wua = -4.7874691e-016 ++pua = 1.0254352e-022 ++ub = 9.2772209e-019 ++lub = 3.2915171e-026 ++wub = 4.3614967e-025 ++pub = -3.2981002e-031 ++uc = 1.3375779e-010 ++luc = -7.439668e-018 ++wuc = -7.0719038e-017 ++puc = 1.7732073e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.8879706 ++la0 = -1.4725376e-007 ++wa0 = -7.0200638e-008 ++pa0 = -1.5381528e-015 ++ags = 0.3341873 ++lags = -2.4436508e-009 ++wags = -1.884856e-007 ++pags = 9.42428e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.088919542 ++lketa = 1.7668152e-008 ++wketa = -6.803611e-009 ++pketa = 1.9050111e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32482036 ++lpclm = 5.0559583e-008 ++wpclm = 8.2952909e-008 ++ppclm = 7.6023645e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.723125e-006 ++lalpha0 = -2.2830898e-012 ++walpha0 = 2.4629388e-012 ++palpha0 = -8.3139811e-019 ++alpha1 = 0 ++beta0 = 37.805966 ++lbeta0 = -2.3737058e-006 ++wbeta0 = 1.5361323e-006 ++pbeta0 = -7.708444e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29596713 ++lkt1 = -8.3979897e-009 ++wkt1 = -3.0216242e-008 ++pkt1 = 4.2520201e-015 ++kt1l = 0 ++kt2 = -0.020842369 ++lkt2 = 2.1773833e-009 ++wkt2 = 9.4871699e-009 ++pkt2 = -2.6564076e-015 ++ute = -1 ++ua1 = 1.8116799e-009 ++lua1 = -1.5583996e-016 ++wua1 = -2.1569499e-017 ++pua1 = 1.078475e-023 ++ub1 = -2.5843988e-018 ++lub1 = -1.2857843e-025 ++wub1 = -1.0048507e-025 ++pub1 = -6.4708497e-032 ++uc1 = -8.5778578e-011 ++luc1 = 8.8928926e-019 ++wuc1 = 1.7821357e-017 ++puc1 = -8.9106783e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76552347 ++lvth0 = -7.1445584e-009 ++wvth0 = -9.069076e-009 ++pvth0 = 1.4216818e-014 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.030551827 ++lk2 = -2.7545864e-009 ++wk2 = 6.1891978e-009 ++pk2 = -3.0945989e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094286796 ++lvoff = -1.787102e-009 ++wvoff = -3.5813523e-008 ++pvoff = 1.7906761e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010127025 ++lu0 = 2.4020669e-009 ++wu0 = -4.282509e-010 ++pu0 = -1.3347616e-015 ++ua = 3.2582253e-010 ++lua = 6.4174442e-016 ++wua = -6.0288518e-017 ++pua = -1.0668567e-022 ++ub = 9.6220002e-019 ++lub = 1.5676208e-026 ++wub = 9.0680837e-026 ++pub = -1.570756e-031 ++uc = -2.7758895e-011 ++luc = 7.3318673e-017 ++wuc = 2.5182066e-017 ++puc = -3.0218479e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1782327 ++la0 = -2.9238479e-007 ++wa0 = 1.4185662e-007 ++pa0 = -1.0756678e-013 ++ags = 0.20788505 ++lags = 6.0707474e-008 ++wags = -6.2630205e-009 ++pags = 3.1315103e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0066799724 ++lketa = -2.3451633e-008 ++wketa = 2.1382778e-009 ++pketa = -2.5659333e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37778426 ++lpclm = 2.407763e-008 ++wpclm = 1.4460314e-007 ++ppclm = -3.006488e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011108151 ++lalpha0 = -5.296228e-011 ++walpha0 = -5.3342836e-012 ++palpha0 = 3.0672131e-018 ++alpha1 = 0 ++beta0 = 43.187318 ++lbeta0 = -5.0643818e-006 ++wbeta0 = 3.968961e-009 ++pbeta0 = -4.7627532e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30269355 ++lkt1 = -5.0347792e-009 ++wkt1 = 3.6107623e-008 ++pkt1 = -2.8909912e-014 ++kt1l = 0 ++kt2 = -0.010621998 ++lkt2 = -2.9328019e-009 ++wkt2 = -2.981682e-009 ++pkt2 = 3.5780184e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4617658e-018 ++lub1 = -1.8989494e-025 ++wub1 = -3.9040685e-025 ++pub1 = 8.0252392e-032 ++uc1 = -3.4810909e-011 ++luc1 = -2.4594545e-017 ++wuc1 = -6.0010691e-017 ++puc1 = 3.0005345e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7677531 ++lvth0 = -4.4690083e-009 ++wvth0 = -3.7885537e-010 ++pvth0 = 3.7885537e-015 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.036023042 ++lk2 = 3.8108709e-009 ++wk2 = 3.9592281e-009 ++pk2 = -4.1863519e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098145312 ++lvoff = 2.8431167e-009 ++wvoff = 2.848803e-009 ++pvoff = -2.848803e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011031559 ++lu0 = 1.3166262e-009 ++wu0 = -1.8761549e-009 ++pu0 = 4.0272326e-016 ++ua = 6.676128e-010 ++lua = 2.315961e-016 ++wua = -3.7786403e-016 ++pua = 2.7440495e-022 ++ub = 9.7526352e-019 ++wub = -4.0215498e-026 ++uc = -1.6606591e-011 ++luc = 5.9935909e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1832393 ++la0 = -2.9839274e-007 ++wa0 = -7.1205867e-009 ++pa0 = 7.1205867e-014 ++ags = 0.16685819 ++lags = 1.0993971e-007 ++wags = -5.1057076e-009 ++pags = 1.7427347e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34313423 ++lpclm = 6.5657665e-008 ++wpclm = -1.6302147e-008 ++ppclm = 1.6302147e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021426891 ++lalpha0 = -2.4908914e-009 ++walpha0 = 3.7885537e-013 ++palpha0 = -3.7885537e-018 ++alpha1 = 0 ++beta0 = 44.161948 ++lbeta0 = -6.233938e-006 ++wbeta0 = 6.8825393e-007 ++pbeta0 = -8.2590471e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29670927 ++lkt1 = -1.2215919e-008 ++wkt1 = -2.4401443e-008 ++pkt1 = 4.3700967e-014 ++kt1l = 0 ++kt2 = -0.012757219 ++lkt2 = -3.7053719e-010 ++wkt2 = -3.0939855e-009 ++pkt2 = 3.7127826e-015 ++ute = -1 ++ua1 = 1.39597e-009 ++lua1 = 1.2483595e-016 ++wua1 = 1.2691655e-016 ++pua1 = -1.5229986e-022 ++ub1 = -2.656703e-018 ++lub1 = 4.4029649e-026 ++wub1 = 4.4117708e-026 ++pub1 = -4.4117708e-031 ++uc1 = -6.6591694e-011 ++luc1 = 1.3542397e-017 ++wuc1 = 2.0685503e-017 ++puc1 = -6.6830088e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7682 ++k1 = 1.0069 ++k2 = -0.035641955 ++wk2 = 3.9173646e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011163222 ++wu0 = -1.8358826e-009 ++ua = 6.9077241e-010 ++wua = -3.5042354e-016 ++ub = 9.7526352e-019 ++wub = -4.0215498e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17785216 ++wags = -4.9314341e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.538555 ++wbeta0 = 6.0566345e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29793086 ++wkt1 = -2.0031346e-008 ++kt1l = 0 ++kt2 = -0.012794273 ++wkt2 = -2.7227073e-009 ++ute = -1 ++ua1 = 1.4084536e-009 ++wua1 = 1.1168656e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5237455e-011 ++wuc1 = 1.4002494e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76184364 ++lvth0 = -8.0181818e-009 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = -0.00022481818 ++lk2 = -1.7918091e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011073636 ++lu0 = 1.7741818e-009 ++ua = 3.0010909e-010 ++lua = 6.4094546e-016 ++ub = 9.7125e-019 ++uc = 1.267e-010 ++luc = -5.67e-018 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.88096455 ++la0 = -1.4740727e-007 ++ags = 0.31537636 ++lags = 6.9618182e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.089598545 ++lketa = 1.7858273e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.33309909 ++lpclm = 5.0635454e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.9689273e-006 ++lalpha0 = -2.3660636e-012 ++alpha1 = 0 ++beta0 = 37.959273 ++lbeta0 = -2.4506364e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29898273 ++lkt1 = -7.9736364e-009 ++kt1l = 0 ++kt2 = -0.019895546 ++lkt2 = 1.9122727e-009 ++ute = -1 ++ua1 = 1.8095273e-009 ++lua1 = -1.5476364e-016 ++ub1 = -2.5944273e-018 ++lub1 = -1.3503636e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76642857 ++lvth0 = -5.7257143e-009 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.029934143 ++lk2 = -3.0634286e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010084286 ++lu0 = 2.2688571e-009 ++ua = 3.1980571e-010 ++lua = 6.3109714e-016 ++ub = 9.7125e-019 ++uc = -2.5245714e-011 ++luc = 7.0302857e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.19239 ++la0 = -3.0312e-007 ++ags = 0.20726 ++lags = 6.102e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0064665714 ++lketa = -2.3707714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39221571 ++lpclm = 2.1077143e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011054914 ++lalpha0 = -5.2656171e-011 ++alpha1 = 0 ++beta0 = 43.187714 ++lbeta0 = -5.0648571e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29909 ++lkt1 = -7.92e-009 ++kt1l = 0 ++kt2 = -0.010919571 ++lkt2 = -2.5757143e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5007286e-018 ++lub1 = -1.8188571e-025 ++uc1 = -4.08e-011 ++luc1 = -2.16e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.76779091 ++lvth0 = -4.0909091e-009 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.035627909 ++lk2 = 3.7690909e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010844318 ++lu0 = 1.3568182e-009 ++ua = 6.2990182e-010 ++lua = 2.5898182e-016 ++ub = 9.7125e-019 ++uc = -1.6606591e-011 ++luc = 5.9935909e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1825286 ++la0 = -2.9128636e-007 ++ags = 0.16634864 ++lags = 1.1011364e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34150727 ++lpclm = 8.1927273e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.002142727 ++lalpha0 = -2.4912696e-009 ++alpha1 = 0 ++beta0 = 44.230636 ++lbeta0 = -6.3163636e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29914454 ++lkt1 = -7.8545455e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4086364e-009 ++lua1 = 1.0963636e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.4527273e-011 ++luc1 = 6.8727273e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.9e-009 ++toxp = 7.9e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 0 ++xw = 0 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7682 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + + + + +.endl pmos_3p3_t +* +* +.lib pmos_3p3_f + + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.67663617 ++lvth0 = -7.3534153e-009 ++wvth0 = 4.7732695e-009 ++pvth0 = 2.3377109e-015 ++k1 = 0.8647782 ++lk1 = 6.1568267e-009 ++wk1 = 6.9370633e-008 ++pk1 = -2.0803095e-014 ++k2 = 0.028918855 ++lk2 = -2.3507638e-008 ++wk2 = -2.2539936e-008 ++pk2 = 3.3878523e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094667623 ++lvoff = -1.5583678e-009 ++wvoff = -1.6924896e-009 ++pvoff = 8.2593493e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0078719299 ++lu0 = 2.3274457e-009 ++wu0 = 5.9859026e-010 ++pu0 = -5.221169e-016 ++ua = 8.7644416e-011 ++lua = 9.8467082e-016 ++wua = -1.3940377e-017 ++pua = -1.9023228e-022 ++ub = 6.5842379e-019 ++lub = -1.3426634e-025 ++wub = -5.017448e-027 ++pub = 1.3446761e-033 ++uc = 8.863003e-011 ++luc = 8.2624703e-018 ++wuc = -1.4595908e-017 ++puc = -4.4377124e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.0088763 ++la0 = -1.9069135e-007 ++wa0 = 1.154901e-008 ++pa0 = -2.7146703e-015 ++ags = 0.20174918 ++lags = 9.8918351e-008 ++wags = -2.5751203e-008 ++pags = -1.198112e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.065134512 ++lketa = 7.447618e-009 ++wketa = -7.4415355e-009 ++pketa = 3.6314694e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.35995623 ++lpclm = 6.5671827e-008 ++wpclm = 3.1666898e-008 ++ppclm = 6.4870775e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1235927e-005 ++lalpha0 = -2.8123501e-012 ++walpha0 = -1.0380713e-013 ++palpha0 = 6.3405134e-020 ++alpha1 = 0 ++beta0 = 39.445349 ++lbeta0 = -3.3940359e-006 ++wbeta0 = 2.3377646e-007 ++pbeta0 = 1.1730752e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28422543 ++lkt1 = -1.5068185e-008 ++wkt1 = -1.1684779e-008 ++pkt1 = 1.9241808e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1573864e-009 ++lua1 = 1.6719545e-016 ++wua1 = 1.8158523e-016 ++pua1 = -8.8613591e-023 ++ub1 = -2.1477044e-018 ++lub1 = -6.4044033e-025 ++wub1 = -1.3505708e-025 ++pub1 = 1.4828008e-031 ++uc1 = -2.5233764e-010 ++luc1 = 5.5767486e-017 ++wuc1 = 4.2084409e-017 ++puc1 = -1.3941872e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70748201 ++lvth0 = 7.6993553e-009 ++wvth0 = 6.367274e-009 ++pvth0 = 1.5598367e-015 ++k1 = 1.0117326 ++lk1 = -6.5556919e-008 ++wk1 = -1.8642534e-008 ++pk1 = 2.214733e-014 ++k2 = -0.018588529 ++lk2 = -3.2403549e-010 ++wk2 = -2.8080536e-009 ++pk2 = -6.2413065e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12338433 ++lvoff = 1.2455386e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010331202 ++lu0 = 1.1273211e-009 ++wu0 = -2.6339567e-010 ++pu0 = -1.0146777e-016 ++ua = 3.9172068e-010 ++lua = 8.3628161e-016 ++wua = -4.9371285e-017 ++pua = -1.72942e-022 ++ub = 1.0960127e-018 ++lub = -3.4780972e-025 ++wub = -2.0220479e-025 ++pub = 9.7572098e-032 ++uc = -1.1491615e-011 ++luc = 5.7121833e-017 ++wuc = -8.0009433e-018 ++puc = -7.6560549e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1426483 ++la0 = -2.5597206e-007 ++wa0 = 4.0977761e-008 ++pa0 = -1.7075901e-014 ++ags = 0.19126654 ++lags = 1.0403388e-007 ++wags = 1.4058737e-008 ++pags = -3.1408371e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0053639133 ++lketa = -2.1720434e-008 ++wketa = -2.3169788e-009 ++pketa = 1.1306857e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.25217946 ++lpclm = 1.1826689e-007 ++wpclm = 9.0167278e-008 ++ppclm = -2.2061108e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00025119377 ++lpdiblc2= 2.3704904e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.4423186e-005 ++lalpha0 = -3.3647732e-011 ++walpha0 = 5.050231e-012 ++palpha0 = -2.4517655e-018 ++alpha1 = 0 ++beta0 = 42.301722 ++lbeta0 = -4.787946e-006 ++wbeta0 = 2.9506668e-007 ++pbeta0 = 8.7397887e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30910467 ++lkt1 = -2.9271156e-009 ++wkt1 = 2.6245925e-008 ++pkt1 = -1.6586003e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2487222e-018 ++lub1 = -5.9114366e-025 ++wub1 = -3.3106883e-026 ++pub1 = 9.852838e-032 ++uc1 = -7.6682222e-011 ++luc1 = -2.9952355e-017 ++wuc1 = 6.6740899e-018 ++puc1 = 3.3383641e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.6927634 ++lvth0 = -9.7863494e-009 ++wvth0 = 3.9098384e-009 ++pvth0 = 4.4792702e-015 ++k1 = 0.95248832 ++lk1 = 4.8252741e-009 ++wk1 = 3.2440732e-008 ++pk1 = -3.853959e-014 ++k2 = -0.0097979054 ++lk2 = -1.0767296e-008 ++wk2 = -1.5975284e-008 ++pk2 = 9.4013629e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097813945 ++lvoff = -1.7922234e-008 ++wvoff = 1.0511012e-009 ++pvoff = -1.2487082e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087371575 ++lu0 = 3.0210454e-009 ++wu0 = 2.316895e-010 ++pu0 = -6.8962895e-016 ++ua = 4.0327941e-010 ++lua = 8.2254984e-016 ++wua = -5.6078614e-017 ++pua = -1.6497369e-022 ++ub = 8.6053432e-019 ++lub = -6.8061407e-026 ++wub = -1.1643187e-025 ++pub = -4.3261328e-033 ++uc = -4.4147189e-011 ++luc = 9.5916655e-017 ++wuc = 1.9501336e-018 ++puc = -1.9477934e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2624812 ++la0 = -3.983336e-007 ++wa0 = -3.5915545e-009 ++pa0 = 3.5872446e-014 ++ags = 0.1574043 ++lags = 1.4426221e-007 ++wags = 7.5813661e-010 ++pags = -1.5607258e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = 8.6249554e-005 ++lketa = -2.8195228e-008 ++wketa = -3.6739399e-009 ++pketa = 2.7427554e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32107112 ++lpclm = 3.6423596e-008 ++wpclm = 5.3623696e-009 ++ppclm = 7.8687123e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.88813e-005 ++lpdiblc2= 4.4175626e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020546973 ++lalpha0 = -2.3862134e-009 ++walpha0 = 2.3605119e-011 ++palpha0 = -2.4494972e-017 ++alpha1 = 0 ++beta0 = 44.410558 ++lbeta0 = -7.2932429e-006 ++wbeta0 = 4.2825183e-007 ++pbeta0 = -7.0826067e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.946 ++lnoff = 5.39352e-007 ++voffcv = 0.0216 ++lvoffcv = -2.157408e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2677292 ++lkt1 = -5.2081178e-008 ++wkt1 = -1.0950226e-008 ++pkt1 = 2.7603024e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0352362e-018 ++lub1 = 3.4323494e-025 ++wub1 = 2.0295616e-025 ++pub1 = -1.8191452e-031 ++uc1 = -3.4663323e-011 ++luc1 = -7.9870808e-017 ++wuc1 = -1.3010587e-017 ++puc1 = 2.672376e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69374321 ++wvth0 = 4.3583036e-009 ++k1 = 0.95297143 ++wk1 = 2.8582143e-008 ++k2 = -0.010875929 ++wk2 = -1.5034018e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099608321 ++wvoff = 9.2608036e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.009039625 ++wu0 = 1.6264375e-010 ++ua = 4.8563321e-010 ++wua = -7.2595804e-017 ++ub = 8.5372e-019 ++wub = -1.16865e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2226 ++ags = 0.17184786 ++wags = -8.0446429e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0027366607 ++wketa = -3.3993348e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.32471786 ++wpclm = 1.3240536e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018157893 ++walpha0 = 2.1152679e-011 ++alpha1 = 0 ++beta0 = 43.680357 ++wbeta0 = 4.2116071e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.27294357 ++wkt1 = -8.1866071e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0008714e-018 ++wub1 = 1.8474286e-025 ++uc1 = -4.266e-011 ++wuc1 = -1.0335e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69642702 ++lvth0 = -1.9920781e-009 ++wvth0 = 1.5262418e-008 ++pvth0 = -5.037978e-016 ++k1 = 0.99566618 ++lk1 = -3.3094297e-008 ++k2 = 0.012709478 ++lk2 = -1.9136714e-008 ++wk2 = -1.3948967e-008 ++pk2 = 1.0712624e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0093531893 ++lu0 = 1.7194104e-009 ++wu0 = -1.8647726e-010 ++pu0 = -1.9985825e-016 ++ua = -1.7033143e-011 ++lua = 6.9948888e-016 ++wua = 4.1538729e-017 ++pua = -3.9085851e-023 ++ub = 1.7312067e-018 ++lub = -2.899821e-025 ++wub = -5.7359242e-025 ++pub = 8.387403e-032 ++uc = 8.7990522e-011 ++luc = 1.1729669e-017 ++wuc = -1.4256968e-017 ++puc = -6.2753276e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.65645235 ++la0 = -9.5523869e-008 ++wa0 = 1.9833372e-007 ++pa0 = -5.3153436e-014 ++ags = 0.21104356 ++lags = 6.5010179e-008 ++wags = -3.0677229e-008 ++pags = 5.9902112e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.10320034 ++lketa = 2.0738198e-008 ++wketa = 1.2733351e-008 ++pketa = -3.4125381e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.38016331 ++lpclm = 2.5024839e-008 ++wpclm = 2.0957146e-008 ++ppclm = 2.8029981e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1826838e-005 ++lalpha0 = -2.8274782e-012 ++walpha0 = -4.1699029e-013 ++palpha0 = 7.1423027e-020 ++alpha1 = 0 ++beta0 = 37.990543 ++lbeta0 = -2.5313328e-006 ++wbeta0 = 1.0048234e-006 ++pbeta0 = -3.3992511e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33242454 ++lkt1 = 5.9583152e-010 ++wkt1 = 1.3860749e-008 ++pkt1 = -6.377748e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.99446e-009 ++lua1 = -2.4129648e-016 ++wua1 = -2.620638e-016 ++pua1 = 1.2788713e-022 ++ub1 = -2.8941809e-018 ++lub1 = -2.5045136e-026 ++wub1 = 2.6057544e-025 ++pub1 = -1.7787938e-031 ++uc1 = 4.9114909e-012 ++luc1 = -3.2836296e-017 ++wuc1 = -9.4257628e-017 ++puc1 = 3.3018133e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69968312 ++lvth0 = -4.0309955e-010 ++wvth0 = 2.2338617e-009 ++pvth0 = 5.8541378e-015 ++k1 = 0.976558 ++lk1 = -2.3769504e-008 ++k2 = -0.02687001 ++lk2 = 1.7807606e-010 ++wk2 = 1.5811316e-009 ++pk2 = -6.5074256e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12338433 ++lvoff = 1.2455386e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097778795 ++lu0 = 1.5121617e-009 ++wu0 = 2.9865002e-011 ++pu0 = -3.0543328e-016 ++ua = 2.791058e-010 ++lua = 5.5497308e-016 ++wua = 1.0314601e-017 ++pua = -2.3848477e-023 ++ub = 1.2763808e-018 ++lub = -6.8027043e-026 ++wub = -2.9779989e-025 ++pub = -5.0712722e-032 ++uc = 9.3297873e-012 ++luc = 5.0116107e-017 ++wuc = -1.9036287e-017 ++puc = -3.9430202e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.3375751 ++la0 = -4.2791177e-007 ++wa0 = -6.2333454e-008 ++pa0 = 7.4052143e-014 ++ags = 0.19358686 ++lags = 7.352905e-008 ++wags = 1.2828966e-008 ++pags = -1.5240812e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0021847972 ++lketa = -2.8557385e-008 ++wketa = -4.0019103e-009 ++pketa = 4.7542695e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.55232393 ++lpclm = -5.8989544e-008 ++wpclm = -6.8909289e-008 ++ppclm = 7.1884801e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00025119377 ++lpdiblc2= 2.3704904e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00012216672 ++lalpha0 = -5.6673338e-011 ++walpha0 = -2.025384e-011 ++palpha0 = 9.7518057e-018 ++alpha1 = 0 ++beta0 = 43.26392 ++lbeta0 = -5.1047406e-006 ++wbeta0 = -2.1489817e-007 ++pbeta0 = 2.5529903e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28433818 ++lkt1 = -2.2870309e-008 ++wkt1 = 1.3119687e-008 ++pkt1 = -6.01611e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.142432e-018 ++lub1 = 9.6101442e-026 ++wub1 = 4.4055934e-025 ++pub1 = -2.6571152e-031 ++uc1 = -9.9075017e-011 ++luc1 = 1.790912e-017 ++wuc1 = 1.8542271e-017 ++puc1 = -2.2028218e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69887884 ++lvth0 = -1.3585892e-009 ++wvth0 = 7.151017e-009 ++pvth0 = 1.255727e-017 ++k1 = 1.0136972 ++lk1 = -6.7890933e-008 ++k2 = -0.027348888 ++lk2 = 7.4698326e-010 ++wk2 = -6.6732628e-009 ++pk2 = 3.2987949e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095830735 ++lvoff = -2.0278287e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097384672 ++lu0 = 1.5589835e-009 ++wu0 = -2.9900464e-010 ++pu0 = 8.5263865e-017 ++ua = 4.0443501e-010 ++lua = 4.0608197e-016 ++wua = -5.6691087e-017 ++pua = 5.575428e-023 ++ub = 1.1705395e-018 ++lub = 5.7712398e-026 ++wub = -2.8073464e-025 ++pub = -7.0986249e-032 ++uc = 1.5649873e-012 ++luc = 5.934069e-017 ++wuc = -2.227732e-017 ++puc = -9.2672655e-026 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1176952 ++la0 = -1.6669444e-007 ++wa0 = 7.3145043e-008 ++pa0 = -8.6896311e-014 ++ags = 0.16577511 ++lags = 1.0656941e-007 ++wags = -3.6783923e-009 ++pags = 4.3699301e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068457125 ++lketa = -2.3020218e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.32904913 ++lpclm = 2.0626092e-007 ++wpclm = 1.1340266e-009 ++ppclm = -1.1326658e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.88813e-005 ++lpdiblc2= 4.4175626e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021717533 ++lalpha0 = -2.4915822e-009 ++walpha0 = -3.8434543e-011 ++palpha0 = 3.1350481e-017 ++alpha1 = 0 ++beta0 = 44.341063 ++lbeta0 = -6.3843867e-006 ++wbeta0 = 4.6508409e-007 ++pbeta0 = -5.5251989e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.946 ++lnoff = 5.39352e-007 ++voffcv = 0.0216 ++lvoffcv = -2.157408e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33811161 ++lkt1 = 4.1012519e-008 ++wkt1 = 2.6352452e-008 ++pkt1 = -2.1736635e-014 ++kt1l = 0 ++kt2 = -0.01697494 ++lkt2 = 4.6438207e-009 ++wkt2 = 2.0717382e-009 ++pkt2 = -2.461225e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5970528e-018 ++lub1 = -5.5180911e-025 ++wub1 = -2.928102e-026 ++pub1 = 2.9245883e-031 ++uc1 = -4.2459e-011 ++luc1 = -4.9350708e-017 ++wuc1 = -8.878878e-018 ++puc1 = 1.0548107e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69901486 ++wvth0 = 7.1522743e-009 ++k1 = 1.0069 ++k2 = -0.0272741 ++wk2 = -6.342987e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0098945529 ++wu0 = -2.9046801e-010 ++ua = 4.45092e-010 ++wua = -5.110896e-017 ++ub = 1.1763177e-018 ++wub = -2.8784179e-025 ++uc = 7.5061857e-012 ++wuc = -2.2286598e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1010057 ++wa0 = 6.4444971e-008 ++ags = 0.17644486 ++wags = -3.2408743e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0019222957 ++walpha0 = -3.5295729e-011 ++alpha1 = 0 ++beta0 = 43.701857 ++wbeta0 = 4.0976571e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33400543 ++wkt1 = 2.4176177e-008 ++kt1l = 0 ++kt2 = -0.01651 ++wkt2 = 1.82532e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.74e-011 ++wuc1 = -7.8228e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.68802184 ++lvth0 = -8.201616e-009 ++wvth0 = 4.9240544e-009 ++pvth0 = 7.1339337e-015 ++k1 = 0.99566618 ++lk1 = -3.3094297e-008 ++k2 = -0.0021980746 ++lk2 = -1.6525108e-008 ++wk2 = 4.3873228e-009 ++pk2 = -2.1410135e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011508627 ++lu0 = 1.6714324e-009 ++wu0 = -2.8376654e-009 ++pu0 = -1.4084519e-016 ++ua = 4.0233366e-010 ++lua = 5.8911437e-016 ++wua = -4.7428243e-016 ++pua = 9.6674803e-023 ++ub = 9.3020973e-019 ++lub = 3.1000449e-026 ++wub = 4.1163392e-025 ++pub = -3.109345e-031 ++uc = 1.3317671e-010 ++luc = -6.9634759e-018 ++wuc = -6.9835979e-017 ++puc = 1.671724e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.87540638 ++la0 = -1.3755908e-007 ++wa0 = -7.0979742e-008 ++pa0 = -1.4501221e-015 ++ags = 0.33412543 ++lags = -2.3548078e-009 ++wags = -1.8206792e-007 ++pags = 8.8849145e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.087399697 ++lketa = 1.6503627e-008 ++wketa = -6.7014347e-009 ++pketa = 1.7959845e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32908612 ++lpclm = 4.7230737e-008 ++wpclm = 8.378208e-008 ++ppclm = 7.1672699e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.5254751e-006 ++lalpha0 = -2.1321619e-012 ++walpha0 = 2.4136865e-012 ++palpha0 = -7.8381597e-019 ++alpha1 = 0 ++beta0 = 37.601303 ++lbeta0 = -2.2168591e-006 ++wbeta0 = 1.4835887e-006 ++pbeta0 = -7.2672783e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29666254 ++lkt1 = -7.8484113e-009 ++wkt1 = -3.0126506e-008 ++pkt1 = 4.0086707e-015 ++kt1l = 0 ++kt2 = -0.02066331 ++lkt2 = 2.0360792e-009 ++wkt2 = 9.344692e-009 ++pkt2 = -2.5043775e-015 ++ute = -1 ++ua1 = 1.7983391e-009 ++lua1 = -1.4558948e-016 ++wua1 = -2.0835087e-017 ++pua1 = 1.0167522e-023 ++ub1 = -2.5953331e-018 ++lub1 = -1.2006485e-025 ++wub1 = -1.0700731e-025 ++pub1 = -6.1005134e-032 ++uc1 = -8.5716307e-011 ++luc1 = 8.3755803e-019 ++wuc1 = 1.7214564e-017 ++puc1 = -8.400707e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69065918 ++lvth0 = -6.9145954e-009 ++wvth0 = -8.8655847e-009 ++pvth0 = 1.3863278e-014 ++k1 = 0.976558 ++lk1 = -2.3769504e-008 ++k2 = -0.030611931 ++lk2 = -2.6591455e-009 ++wk2 = 6.1836949e-009 ++pk2 = -3.0176431e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094293534 ++lvoff = -1.7409232e-009 ++wvoff = -3.578168e-008 ++pvoff = 1.746146e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010175439 ++lu0 = 2.3220281e-009 ++wu0 = -4.5913295e-010 ++pu0 = -1.301569e-015 ++ua = 3.3870848e-010 ++lua = 6.2016345e-016 ++wua = -6.2996698e-017 ++pua = -1.0403264e-022 ++ub = 9.6244193e-019 ++lub = 1.5271135e-026 ++wub = 8.8344941e-026 ++pub = -1.5316948e-031 ++uc = -2.6312627e-011 ++luc = 7.086732e-017 ++wuc = 2.4803882e-017 ++puc = -2.9467012e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1722707 ++la0 = -2.8242886e-007 ++wa0 = 1.4099098e-007 ++pa0 = -1.0489184e-013 ++ags = 0.20910427 ++lags = 5.8655514e-008 ++wags = -6.2574519e-009 ++pags = 3.0536365e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0071507123 ++lketa = -2.2657878e-008 ++wketa = 2.1061652e-009 ++pketa = -2.5021242e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37814802 ++lpclm = 2.3288533e-008 ++wpclm = 1.4532708e-007 ++ppclm = -2.9317233e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00025119377 ++lpdiblc2= 2.3704904e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011002657 ++lalpha0 = -5.1176698e-011 ++walpha0 = -5.3214657e-012 ++palpha0 = 2.9909383e-018 ++alpha1 = 0 ++beta0 = 43.086027 ++lbeta0 = -4.8934045e-006 ++wbeta0 = 3.9093553e-009 ++pbeta0 = -4.6443141e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30282331 ++lkt1 = -4.8419541e-009 ++wkt1 = 3.5856399e-008 ++pkt1 = -2.8190987e-014 ++kt1l = 0 ++kt2 = -0.010678274 ++lkt2 = -2.8366187e-009 ++wkt2 = -2.9369032e-009 ++pkt2 = 3.489041e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4652457e-018 ++lub1 = -1.8354751e-025 ++wub1 = -3.9237991e-025 ++pub1 = 7.8256693e-032 ++uc1 = -3.52542e-011 ++luc1 = -2.378795e-017 ++wuc1 = -5.9957334e-017 ++puc1 = 2.9259179e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69275726 ++lvth0 = -4.4220735e-009 ++wvth0 = -3.7851852e-010 ++pvth0 = 3.780643e-015 ++k1 = 1.0136972 ++lk1 = -6.7890933e-008 ++k2 = -0.036022469 ++lk2 = 3.7685735e-009 ++wk2 = 3.995242e-009 ++pk2 = -4.1776105e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098144776 ++lvoff = 2.8343515e-009 ++wvoff = 2.84627e-009 ++pvoff = -2.8428545e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01103441 ++lu0 = 1.3015701e-009 ++wu0 = -1.8930146e-009 ++pu0 = 4.0188235e-016 ++ua = 6.6815328e-010 ++lua = 2.2878304e-016 ++wua = -3.8106455e-016 ++pua = 2.7383197e-022 ++ub = 9.7529642e-019 ++wub = -4.0585597e-026 ++uc = -1.6546655e-011 ++luc = 5.9265346e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1829466 ++la0 = -2.9511192e-007 ++wa0 = -7.1142556e-009 ++pa0 = 7.1057185e-014 ++ags = 0.1669723 ++lags = 1.087083e-007 ++wags = -5.1509361e-009 ++pags = 1.7390958e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068457125 ++lketa = -2.3020218e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34321309 ++lpclm = 6.4791222e-008 ++wpclm = -1.6287652e-008 ++ppclm = 1.6268107e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.88813e-005 ++lpdiblc2= 4.4175626e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.002140198 ++lalpha0 = -2.4630203e-009 ++walpha0 = 3.7851852e-013 ++palpha0 = -3.780643e-018 ++alpha1 = 0 ++beta0 = 44.155152 ++lbeta0 = -6.1635247e-006 ++wbeta0 = 6.9375436e-007 ++pbeta0 = -8.2418018e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.946 ++lnoff = 5.39352e-007 ++voffcv = 0.0216 ++lvoffcv = -2.157408e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29670156 ++lkt1 = -1.2114597e-008 ++wkt1 = -2.4581904e-008 ++pkt1 = 4.3609717e-014 ++kt1l = 0 ++kt2 = -0.012755062 ++lkt2 = -3.6939483e-010 ++wkt2 = -3.1187122e-009 ++pkt2 = 3.7050301e-015 ++ute = -1 ++ua1 = 1.3959912e-009 ++lua1 = 1.2356248e-016 ++wua1 = 1.2793085e-016 ++pua1 = -1.5198185e-022 ++ub1 = -2.6566947e-018 ++lub1 = 4.3893906e-026 ++wub1 = 4.4078482e-026 ++pub1 = -4.4025588e-031 ++uc1 = -6.6595019e-011 ++luc1 = 1.3444942e-017 ++wuc1 = 2.0808425e-017 ++puc1 = -6.6690543e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.6932 ++k1 = 1.0069 ++k2 = -0.035645159 ++wk2 = 3.9534157e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011164724 ++wu0 = -1.8527781e-009 ++ua = 6.9105907e-010 ++wua = -3.5364845e-016 ++ub = 9.7529642e-019 ++wub = -4.0585597e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17785619 ++wags = -4.9768176e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.538059 ++wbeta0 = 6.1123732e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29791448 ++wkt1 = -2.0215693e-008 ++kt1l = 0 ++kt2 = -0.012792045 ++wkt2 = -2.7477641e-009 ++ute = -1 ++ua1 = 1.4083623e-009 ++wua1 = 1.1271441e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5248909e-011 ++wuc1 = 1.4131358e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.68753091 ++lvth0 = -7.4903564e-009 ++k1 = 0.99566618 ++lk1 = -3.3094297e-008 ++k2 = -0.0017606545 ++lk2 = -1.6738569e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011225709 ++lu0 = 1.65739e-009 ++ua = 3.5504727e-010 ++lua = 5.9875293e-016 ++ub = 9.7125e-019 ++uc = 1.26214e-010 ++luc = -5.296752e-018 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.86832964 ++la0 = -1.3770366e-007 ++ags = 0.31597309 ++lags = 6.5035316e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.088067836 ++lketa = 1.6682688e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.33743927 ++lpclm = 4.7302195e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.7661218e-006 ++lalpha0 = -2.2103091e-012 ++alpha1 = 0 ++beta0 = 37.749218 ++lbeta0 = -2.2893145e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29966618 ++lkt1 = -7.4487433e-009 ++kt1l = 0 ++kt2 = -0.019731636 ++lkt2 = 1.7863906e-009 ++ute = -1 ++ua1 = 1.7962618e-009 ++lua1 = -1.4457577e-016 ++ub1 = -2.6060018e-018 ++lub1 = -1.2614711e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69154309 ++lvth0 = -5.5324142e-009 ++k1 = 0.976558 ++lk1 = -2.3769504e-008 ++k2 = -0.029995411 ++lk2 = -2.9600072e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010129663 ++lu0 = 2.1922605e-009 ++ua = 3.3242766e-010 ++lua = 6.097913e-016 ++ub = 9.7125e-019 ++uc = -2.3839657e-011 ++luc = 6.7929433e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1863276 ++la0 = -2.9288667e-007 ++ags = 0.2084804 ++lags = 5.8959965e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0069407257 ++lketa = -2.2907342e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39263726 ++lpclm = 2.0365578e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00025119377 ++lpdiblc2= 2.3704904e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00010949602 ++lalpha0 = -5.0878499e-011 ++alpha1 = 0 ++beta0 = 43.086417 ++lbeta0 = -4.8938676e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2992484 ++lkt1 = -7.6526208e-009 ++kt1l = 0 ++kt2 = -0.010971086 ++lkt2 = -2.4887582e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5043663e-018 ++lub1 = -1.7574525e-025 ++uc1 = -4.1232e-011 ++luc1 = -2.0870784e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.692795 ++lvth0 = -4.04514e-009 ++k1 = 1.0136972 ++lk1 = -6.7890933e-008 ++k2 = -0.03562414 ++lk2 = 3.7269223e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010845675 ++lu0 = 1.3416381e-009 ++ua = 6.301608e-010 ++lua = 2.5608433e-016 ++ub = 9.7125e-019 ++uc = -1.6546655e-011 ++luc = 5.9265346e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1822374 ++la0 = -2.8802745e-007 ++ags = 0.16645875 ++lags = 1.0888169e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068457125 ++lketa = -2.3020217e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.3415892 ++lpclm = 8.101067e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.88813e-005 ++lpdiblc2= 4.4175626e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021402357 ++lalpha0 = -2.4633972e-009 ++alpha1 = 0 ++beta0 = 44.22432 ++lbeta0 = -6.2456962e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.946 ++lnoff = 5.39352e-007 ++voffcv = 0.0216 ++lvoffcv = -2.157408e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2991524 ++lkt1 = -7.7666688e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.408746e-009 ++lua1 = 1.0840975e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.45204e-011 ++luc1 = 6.7958352e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.5e-009 ++toxp = 7.5e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -1.2e-008 ++xw = 1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.6932 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.116e-010 ++cgdo = 1.116e-010 ++cgbo = 1e-013 ++cgdl = 3.6e-011 ++cgsl = 3.6e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + + + +.endl pmos_3p3_f +* +* +.lib pmos_3p3_s + + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.82463101 ++lvth0 = -8.0025899e-009 ++wvth0 = 3.8459166e-009 ++pvth0 = 2.3657625e-015 ++k1 = 0.87469564 ++lk1 = 3.4485427e-009 ++wk1 = 6.4792254e-008 ++pk1 = -2.1052724e-014 ++k2 = 0.029736614 ++lk2 = -2.6287876e-008 ++wk2 = -2.0504604e-008 ++pk2 = 3.4285051e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094659997 ++lvoff = -1.6389133e-009 ++wvoff = -1.6325113e-009 ++pvoff = 8.358458e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.007549639 ++lu0 = 2.570498e-009 ++wu0 = 6.147434e-010 ++pu0 = -5.2838208e-016 ++ua = -8.9886117e-011 ++lua = 1.092789e-015 ++wua = 1.8563411e-017 ++pua = -1.9251499e-022 ++ub = 6.8226823e-019 ++lub = -1.5325276e-025 ++wub = -4.6603138e-027 ++pub = 1.3608116e-033 ++uc = 8.5033561e-011 ++luc = 8.679411e-018 ++wuc = -1.2200571e-017 ++puc = -4.490963e-024 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.0456883 ++la0 = -2.1845471e-007 ++wa0 = 1.066516e-008 ++pa0 = -2.7472452e-015 ++ags = 0.1800417 ++lags = 1.1100987e-007 ++wags = -2.0850684e-008 ++pags = -1.2124889e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.067725055 ++lketa = 9.1402523e-009 ++wketa = -7.1778231e-009 ++pketa = 3.6750454e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.3525051 ++lpclm = 7.6191219e-008 ++wpclm = 2.6980295e-008 ++ppclm = 6.5649197e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1734592e-005 ++lalpha0 = -3.2039603e-012 ++walpha0 = -1.021993e-013 ++palpha0 = 6.4165969e-020 ++alpha1 = 0 ++beta0 = 40.100221 ++lbeta0 = -3.8596059e-006 ++wbeta0 = 1.8790089e-007 ++pbeta0 = 1.1871516e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28327733 ++lkt1 = -1.6892981e-008 ++wkt1 = -1.0656933e-008 ++pkt1 = 1.9472702e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1565682e-009 ++lua1 = 1.7583709e-016 ++wua1 = 1.7515023e-016 ++pua1 = -8.9676916e-023 ++ub1 = -2.0546713e-018 ++lub1 = -7.0652532e-025 ++wub1 = -1.4365289e-025 ++pub1 = 1.5005937e-031 ++uc1 = -2.5583291e-010 ++luc1 = 6.134421e-017 ++wuc1 = 3.9521569e-017 ++puc1 = -1.4109168e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.85684939 ++lvth0 = 8.4932211e-009 ++wvth0 = 5.5796737e-009 ++pvth0 = 1.4780788e-015 ++k1 = 1.0114941 ++lk1 = -6.6592286e-008 ++wk1 = -1.7315587e-008 ++pk1 = 2.0986491e-014 ++k2 = -0.018959971 ++lk2 = -1.3552238e-009 ++wk2 = -2.2571871e-009 ++pk2 = -5.9141722e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12389995 ++lvoff = 1.3331945e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010245409 ++lu0 = 1.1902635e-009 ++wu0 = -2.2946106e-010 ++pu0 = -9.6149399e-017 ++ua = 3.5072904e-010 ++lua = 8.6719409e-016 ++wua = -3.7369482e-017 ++pua = -1.6387735e-022 ++ub = 1.07928e-018 ++lub = -3.5652279e-025 ++wub = -1.8258434e-025 ++pub = 9.2457915e-032 ++uc = -1.5016171e-011 ++luc = 5.9904874e-017 ++wuc = -6.8025157e-018 ++puc = -7.2547674e-024 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1595369 ++la0 = -2.7674521e-007 ++wa0 = 3.6902724e-008 ++pa0 = -1.6180878e-014 ++ags = 0.18927812 ++lags = 1.0628082e-007 ++wags = 1.3597033e-008 ++pags = -2.976212e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0048215378 ++lketa = -2.3066349e-008 ++wketa = -2.09262e-009 ++pketa = 1.0714215e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.26103151 ++lpclm = 1.230257e-007 ++wpclm = 8.0632068e-008 ++ppclm = -2.0904788e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024138051 ++lpdiblc2= 2.5373158e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.659374e-005 ++lalpha0 = -3.6411844e-011 ++walpha0 = 4.5607375e-012 ++palpha0 = -2.3232577e-018 ++alpha1 = 0 ++beta0 = 42.543923 ++lbeta0 = -5.1107814e-006 ++wbeta0 = 2.5801452e-007 ++pbeta0 = 8.2816979e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3049182 ++lkt1 = -5.8128509e-009 ++wkt1 = 2.3842925e-008 ++pkt1 = -1.5716657e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2298632e-018 ++lub1 = -6.1682707e-025 ++wub1 = -3.2919886e-026 ++pub1 = 9.3364074e-032 ++uc1 = -7.4455718e-011 ++luc1 = -3.1520912e-017 ++wuc1 = 5.7861122e-018 ++puc1 = 3.1633858e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84215481 ++lvth0 = -9.3166113e-009 ++wvth0 = 3.453293e-009 ++pvth0 = 4.0552523e-015 ++k1 = 0.95738704 ++lk1 = -1.0144952e-009 ++wk1 = 2.8788238e-008 ++pk1 = -3.4891345e-014 ++k2 = -0.012190361 ++lk2 = -9.5599917e-009 ++wk2 = -1.4159481e-008 ++pk2 = 8.5114085e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097618657 ++lvoff = -1.8520988e-008 ++wvoff = 9.3275798e-010 ++pvoff = -1.1305027e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087662296 ++lu0 = 2.9830294e-009 ++wu0 = 2.0634563e-010 ++pu0 = -6.2434711e-016 ++ua = 3.9320136e-010 ++lua = 8.1571763e-016 ++wua = -4.9350043e-017 ++pua = -1.4935691e-022 ++ub = 8.4309868e-019 ++lub = -7.0271026e-026 ++wub = -1.0306741e-025 ++pub = -3.9166112e-033 ++uc = -4.4040887e-011 ++luc = 9.508283e-017 ++wuc = 1.7612973e-018 ++puc = -1.7634109e-023 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.2627338 ++la0 = -4.0181986e-007 ++wa0 = -3.2437753e-009 ++pa0 = 3.2476679e-014 ++ags = 0.15723172 ++lags = 1.4512107e-007 ++wags = 6.9911181e-010 ++pags = -1.4129839e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.00041211629 ++lketa = -2.8410567e-008 ++wketa = -3.2573878e-009 ++pketa = 2.48312e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32178284 ++lpclm = 4.939508e-008 ++wpclm = 4.6063177e-009 ++ppclm = 7.1238421e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.7987791e-005 ++lpdiblc2= 4.5176356e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020630943 ++lalpha0 = -2.4440505e-009 ++walpha0 = 2.0941071e-011 ++palpha0 = -2.2176222e-017 ++alpha1 = 0 ++beta0 = 44.489973 ++lbeta0 = -7.4693929e-006 ++wbeta0 = 3.7925089e-007 ++pbeta0 = -6.4121511e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9449091 ++lnoff = 5.5157018e-007 ++voffcv = 0.022036364 ++lvoffcv = -2.2062807e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.26928515 ++lkt1 = -4.9000116e-008 ++wkt1 = -9.743475e-009 ++pkt1 = 2.4990059e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.00524e-018 ++lub1 = 3.2292957e-025 ++wub1 = 1.7999938e-025 ++pub1 = -1.6469408e-031 ++uc1 = -3.6473795e-011 ++luc1 = -7.7555003e-017 ++wuc1 = -1.1565903e-017 ++puc1 = 2.4194028e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84308536 ++wvth0 = 3.8583321e-009 ++k1 = 0.95728571 ++wk1 = 2.5303286e-008 ++k2 = -0.013145214 ++wk2 = -1.3309361e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099468536 ++wvoff = 8.1984321e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.009064175 ++wu0 = 1.4398575e-010 ++ua = 4.7467536e-010 ++wua = -6.4267832e-017 ++ub = 8.3608e-019 ++wub = -1.034586e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.2226 ++ags = 0.17172643 ++wags = -7.1217857e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0032497679 ++wketa = -3.0093734e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.32671643 ++wpclm = 1.1721621e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018189821 ++walpha0 = 1.8726107e-011 ++alpha1 = 0 ++beta0 = 43.743929 ++wbeta0 = 3.7284643e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.27417929 ++wkt1 = -7.2474643e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.9729857e-018 ++wub1 = 1.6354971e-025 ++uc1 = -4.422e-011 ++wuc1 = -9.1494e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84559037 ++lvth0 = -2.2948864e-009 ++wvth0 = 1.4535189e-008 ++pvth0 = -5.4516634e-016 ++k1 = 1.0017393 ++lk1 = -3.7831308e-008 ++k2 = 0.015787252 ++lk2 = -2.1838311e-008 ++wk2 = -1.3390429e-008 ++pk2 = 1.1592273e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090330668 ++lu0 = 1.9585121e-009 ++wu0 = -1.4180477e-010 ++pu0 = -2.1626928e-016 ++ua = -1.4390099e-010 ++lua = 7.9824069e-016 ++wua = 4.6110994e-017 ++pua = -4.2295322e-023 ++ub = 1.7663512e-018 ++lub = -3.2854766e-025 ++wub = -5.5754264e-025 ++pub = 9.0761209e-032 ++uc = 8.5435958e-011 ++luc = 1.3188534e-017 ++wuc = -1.2405794e-017 ++puc = -6.7906158e-024 ++eu = 1.67 ++vsat = 84000 ++a0 = 0.68036585 ++la0 = -1.1106099e-007 ++wa0 = 1.969796e-007 ++pa0 = -5.7518044e-014 ++ags = 0.19813874 ++lags = 7.4525608e-008 ++wags = -3.0080179e-008 ++pags = 6.4820876e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.10659611 ++lketa = 2.3586916e-008 ++wketa = 1.2646415e-008 ++pketa = -3.6927531e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37605618 ++lpclm = 2.9589851e-008 ++wpclm = 1.4969243e-008 ++ppclm = 3.0331617e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.233251e-005 ++lalpha0 = -3.2296894e-012 ++walpha0 = -4.0713741e-013 ++palpha0 = 7.7287812e-020 ++alpha1 = 0 ++beta0 = 38.487806 ++lbeta0 = -2.9055811e-006 ++wbeta0 = 1.0102328e-006 ++pbeta0 = -3.6783751e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33207273 ++lkt1 = 4.5744341e-010 ++wkt1 = 1.4228723e-008 ++pkt1 = -6.9014464e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 2.02998e-009 ++lua1 = -2.7134976e-016 ++wua1 = -2.702898e-016 ++pua1 = 1.3838838e-022 ++ub1 = -2.8805891e-018 ++lub1 = -3.486841e-026 ++wub1 = 2.7756517e-025 ++pub1 = -1.9248565e-031 ++uc1 = 7.8595636e-012 ++luc1 = -3.6378401e-017 ++wuc1 = -9.4961592e-017 ++puc1 = 3.5729363e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84960533 ++lvth0 = -2.3922604e-010 ++wvth0 = 1.8852027e-009 ++pvth0 = 5.9316269e-015 ++k1 = 0.977542 ++lk1 = -2.5442304e-008 ++k2 = -0.026820609 ++lk2 = -2.308677e-011 ++wk2 = 1.7517378e-009 ++pk2 = -6.593562e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12389995 ++lvoff = 1.3331945e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097165838 ++lu0 = 1.6085514e-009 ++wu0 = 4.0239958e-011 ++pu0 = -3.0947618e-016 ++ua = 2.5647799e-010 ++lua = 5.9324665e-016 ++wua = 1.0698549e-017 ++pua = -2.416415e-023 ++ub = 1.270125e-018 ++lub = -7.4479844e-026 ++wub = -2.799153e-025 ++pub = -5.1383988e-032 ++uc = 6.6760848e-012 ++luc = 5.351359e-017 ++wuc = -1.7865566e-017 ++puc = -3.9952125e-024 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.3532832 ++la0 = -4.5559467e-007 ++wa0 = -6.1907875e-008 ++pa0 = 7.5032345e-014 ++ags = 0.19095588 ++lags = 7.8203234e-008 ++wags = 1.2741377e-008 ++pags = -1.5442549e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0011314055 ++lketa = -3.0411013e-008 ++wketa = -3.9745875e-009 ++pketa = 4.8172e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.55256055 ++lpclm = -6.0780385e-008 ++wpclm = -6.8047743e-008 ++ppclm = 7.2836314e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024138051 ++lpdiblc2= 2.5373158e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00012387909 ++lalpha0 = -6.0341539e-011 ++walpha0 = -1.9554792e-011 ++palpha0 = 9.8808868e-018 ++alpha1 = 0 ++beta0 = 43.468326 ++lbeta0 = -5.4556076e-006 ++wbeta0 = -2.1343096e-007 ++pbeta0 = 2.5867832e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28298126 ++lkt1 = -2.4677389e-008 ++wkt1 = 1.2655084e-008 ++pkt1 = -6.095743e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.1325568e-018 ++lub1 = 9.4139058e-026 ++wub1 = 4.2745384e-025 ++pub1 = -2.6922865e-031 ++uc1 = -9.9219566e-011 ++luc1 = 1.8446114e-017 ++wuc1 = 1.8415675e-017 ++puc1 = -2.2319798e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.8486567 ++lvth0 = -1.3889719e-009 ++wvth0 = 6.7692544e-009 ++pvth0 = 1.2156213e-017 ++k1 = 1.0138346 ++lk1 = -6.9428897e-008 ++k2 = -0.027555336 ++lk2 = 8.6740321e-010 ++wk2 = -6.323344e-009 ++pk2 = 3.1934371e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095789719 ++lvoff = -2.073766e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097261353 ++lu0 = 1.5969749e-009 ++wu0 = -2.832063e-010 ++pu0 = 8.2540685e-017 ++ua = 4.0187094e-010 ++lua = 4.1703039e-016 ++wua = -5.3771529e-017 ++pua = 5.3973585e-023 ++ub = 1.1618144e-018 ++lub = 5.6792621e-026 ++wub = -2.6561243e-025 ++pub = -6.8719071e-032 ++uc = 7.6151064e-013 ++luc = 6.0682053e-017 ++wuc = -2.1087925e-017 ++puc = -8.9712851e-026 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1202818 ++la0 = -1.7319698e-007 ++wa0 = 6.940676e-008 ++pa0 = -8.4120993e-014 ++ags = 0.16544644 ++lags = 1.0912068e-007 ++wags = -3.4903977e-009 ++pags = 4.2303621e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0067991511 ++lketa = -2.3541705e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.32866743 ++lpclm = 2.1057807e-007 ++wpclm = 1.0951762e-009 ++ppclm = -1.0964904e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.7987791e-005 ++lpdiblc2= 4.5176356e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021756117 ++lalpha0 = -2.5470415e-009 ++walpha0 = -3.644284e-011 ++palpha0 = 3.0349201e-017 ++alpha1 = 0 ++beta0 = 44.368279 ++lbeta0 = -6.5463501e-006 ++wbeta0 = 4.4131466e-007 ++pbeta0 = -5.3487336e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9449091 ++lnoff = 5.5157018e-007 ++voffcv = 0.022036364 ++lvoffcv = -2.2062807e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33738473 ++lkt1 = 4.1259616e-008 ++wkt1 = 2.4987313e-008 ++pkt1 = -2.1042404e-014 ++kt1l = 0 ++kt2 = -0.01692062 ++lkt2 = 4.6717994e-009 ++wkt2 = 1.9658562e-009 ++pkt2 = -2.3826177e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5968532e-018 ++lub1 = -5.5513372e-025 ++wub1 = -2.8277886e-026 ++pub1 = 2.831182e-031 ++uc1 = -4.2632236e-011 ++luc1 = -5.013773e-017 ++wuc1 = -8.425098e-018 ++puc1 = 1.0211219e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84879543 ++wvth0 = 6.7704686e-009 ++k1 = 1.0069 ++k2 = -0.0274687 ++wk2 = -6.004383e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0098856414 ++wu0 = -2.7496213e-010 ++ua = 4.43524e-010 ++wua = -4.838064e-017 ++ub = 1.1674869e-018 ++wub = -2.724761e-025 ++uc = 6.8224429e-012 ++wuc = -2.1096886e-017 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1029829 ++wa0 = 6.1004743e-008 ++ags = 0.17634543 ++wags = -3.0678686e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0019212129 ++walpha0 = -3.3411557e-011 ++alpha1 = 0 ++beta0 = 43.714429 ++wbeta0 = 3.8789143e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33326371 ++wkt1 = 2.2885594e-008 ++kt1l = 0 ++kt2 = -0.016454 ++wkt2 = 1.72788e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.764e-011 ++wuc1 = -7.4052e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83651091 ++lvth0 = -9.3623482e-009 ++wvth0 = 3.5490455e-009 ++pvth0 = 8.0064625e-015 ++k1 = 1.0017393 ++lk1 = -3.7831308e-008 ++k2 = 0.00084217568 ++lk2 = -1.8894426e-008 ++wk2 = 4.6931134e-009 ++pk2 = -2.4028741e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011197346 ++lu0 = 1.9104148e-009 ++wu0 = -2.7605828e-009 ++pu0 = -1.5807151e-016 ++ua = 2.9342841e-010 ++lua = 6.7361745e-016 ++wua = -4.8305758e-016 ++pua = 1.0849879e-022 ++ub = 9.252807e-019 ++lub = 3.486153e-026 ++wub = 4.6015269e-025 ++pub = -3.4896391e-031 ++uc = 1.3433638e-010 ++luc = -7.929225e-018 ++wuc = -7.1575304e-017 ++puc = 1.8761873e-023 ++eu = 1.67 ++vsat = 84000 ++a0 = 0.90053503 ++la0 = -1.5725154e-007 ++wa0 = -6.9425106e-008 ++pa0 = -1.6274819e-015 ++ags = 0.33423596 ++lags = -2.5272122e-009 ++wags = -1.9475781e-007 ++pags = 9.9716e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.090439654 ++lketa = 1.8869231e-008 ++wketa = -6.902896e-009 ++pketa = 2.0156456e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32055448 ++lpclm = 5.399252e-008 ++wpclm = 8.2126294e-008 ++ppclm = 8.0438758e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.9208915e-006 ++lalpha0 = -2.4388052e-012 ++walpha0 = 2.5109209e-012 ++palpha0 = -8.79682e-019 ++alpha1 = 0 ++beta0 = 38.010737 ++lbeta0 = -2.5355199e-006 ++wbeta0 = 1.5874859e-006 ++pbeta0 = -8.156116e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29527232 ++lkt1 = -8.9643788e-009 ++wkt1 = -3.029977e-008 ++pkt1 = 4.4989585e-015 ++kt1l = 0 ++kt2 = -0.021021054 ++lkt2 = 2.3228759e-009 ++wkt2 = 9.625616e-009 ++pkt2 = -2.8106799e-015 ++ute = -1 ++ua1 = 1.8250192e-009 ++lua1 = -1.6640984e-016 ++wua1 = -2.2287265e-017 ++pua1 = 1.141108e-023 ++ub1 = -2.5734555e-018 ++lub1 = -1.373636e-025 ++wub1 = -9.4066473e-026 ++pub1 = -6.8466478e-032 ++uc1 = -8.58396e-011 ++luc1 = 9.418752e-019 ++wuc1 = 1.8414396e-017 ++puc1 = -9.4281708e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84038823 ++lvth0 = -7.3771601e-009 ++wvth0 = -9.2674868e-009 ++pvth0 = 1.4568527e-014 ++k1 = 0.977542 ++lk1 = -2.5442304e-008 ++k2 = -0.030491622 ++lk2 = -2.8515216e-009 ++wk2 = 6.1936639e-009 ++pk2 = -3.1711559e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094280644 ++lvoff = -1.8331424e-009 ++wvoff = -3.5839366e-008 ++pvoff = 1.8349755e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010078656 ++lu0 = 2.4831844e-009 ++wu0 = -3.9786675e-010 ++pu0 = -1.3677821e-015 ++ua = 3.1294007e-010 ++lua = 6.6362748e-016 ++wua = -5.7620563e-017 ++pua = -1.0932496e-022 ++ub = 9.6196324e-019 ++lub = 1.6080068e-026 ++wub = 9.2960446e-026 ++pub = -1.6096148e-031 ++uc = -2.9204174e-011 ++luc = 7.5803538e-017 ++wuc = 2.5549547e-017 ++puc = -3.0966051e-023 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1841981 ++la0 = -3.0248705e-007 ++wa0 = 1.4268502e-007 ++pa0 = -1.1022787e-013 ++ags = 0.20666573 ++lags = 6.2788747e-008 ++wags = -6.2675398e-009 ++pags = 3.2089804e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0062091486 ++lketa = -2.4256788e-008 ++wketa = 2.1694816e-009 ++pketa = -2.6294117e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37742149 ++lpclm = 2.4876612e-008 ++wpclm = 1.4387051e-007 ++ppclm = -3.0808652e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024138051 ++lpdiblc2= 2.5373158e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011213634 ++lalpha0 = -5.4773114e-011 ++walpha0 = -5.3460607e-012 ++palpha0 = 3.1430926e-018 ++alpha1 = 0 ++beta0 = 43.288609 ++lbeta0 = -5.2377903e-006 ++wbeta0 = 4.02688e-009 ++pbeta0 = -4.8805786e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30256285 ++lkt1 = -5.2316292e-009 ++wkt1 = 3.6348805e-008 ++pkt1 = -2.9625112e-014 ++kt1l = 0 ++kt2 = -0.01056584 ++lkt2 = -3.0301939e-009 ++wkt2 = -3.0251936e-009 ++pkt2 = 3.6665346e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4582886e-018 ++lub1 = -1.9632904e-025 ++wub1 = -3.8841067e-025 ++pub1 = 8.2237749e-032 ++uc1 = -3.43686e-011 ++luc1 = -2.5411277e-017 ++wuc1 = -6.0053994e-017 ++puc1 = 3.0747645e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84274894 ++lvth0 = -4.5159809e-009 ++wvth0 = -3.7912875e-010 ++pvth0 = 3.795837e-015 ++k1 = 1.0138346 ++lk1 = -6.9428897e-008 ++k2 = -0.036023613 ++lk2 = 3.853252e-009 ++wk2 = 3.9232712e-009 ++pk2 = -4.1943999e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098145801 ++lvoff = 2.8514282e-009 ++wvoff = 2.8508586e-009 ++pvoff = -2.8542797e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011028707 ++lu0 = 1.3317214e-009 ++wu0 = -1.8593186e-009 ++pu0 = 4.0349748e-016 ++ua = 6.6707187e-010 ++lua = 2.3441974e-016 ++wua = -3.7466465e-016 ++pua = 2.7493248e-022 ++ub = 9.7523062e-019 ++wub = -3.9846056e-026 ++uc = -1.6666527e-011 ++luc = 6.0607911e-017 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1835318 ++la0 = -3.0167941e-007 ++wa0 = -7.1257249e-009 ++pa0 = 7.1342757e-014 ++ags = 0.16674407 ++lags = 1.111738e-007 ++wags = -5.0605305e-009 ++pags = 1.746085e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0067991511 ++lketa = -2.3541705e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34305511 ++lpclm = 6.6528672e-008 ++wpclm = -1.631391e-008 ++ppclm = 1.6333487e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.7987791e-005 ++lpdiblc2= 4.5176356e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021451803 ++lalpha0 = -2.5188225e-009 ++walpha0 = 3.7912875e-013 ++palpha0 = -3.795837e-018 ++alpha1 = 0 ++beta0 = 44.168746 ++lbeta0 = -6.3045161e-006 ++wbeta0 = 6.8274957e-007 ++pbeta0 = -8.2749248e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9449091 ++lnoff = 5.5157018e-007 ++voffcv = 0.022036364 ++lvoffcv = -2.2062807e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29671705 ++lkt1 = -1.2316734e-008 ++wkt1 = -2.4220578e-008 ++pkt1 = 4.378498e-014 ++kt1l = 0 ++kt2 = -0.012759382 ++lkt2 = -3.7162041e-010 ++wkt2 = -3.0692412e-009 ++pkt2 = 3.7199203e-015 ++ute = -1 ++ua1 = 1.3959491e-009 ++lua1 = 1.2610963e-016 ++wua1 = 1.2590153e-016 ++pua1 = -1.5259265e-022 ++ub1 = -2.6567105e-018 ++lub1 = 4.4158364e-026 ++wub1 = 4.4149543e-026 ++pub1 = -4.4202522e-031 ++uc1 = -6.658826e-011 ++luc1 = 1.3638952e-017 ++wuc1 = 2.0561691e-017 ++puc1 = -6.6958565e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.8432 ++k1 = 1.0069 ++k2 = -0.03563875 ++wk2 = 3.8813775e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01116172 ++wu0 = -1.8190172e-009 ++ua = 6.9048575e-010 ++wua = -3.4720436e-016 ++ub = 9.7523062e-019 ++wub = -3.9846056e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1534 ++ags = 0.17784813 ++wags = -4.8861312e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.53905 ++wbeta0 = 6.000995e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29794725 ++wkt1 = -1.9847327e-008 ++kt1l = 0 ++kt2 = -0.0127965 ++wkt2 = -2.697695e-009 ++ute = -1 ++ua1 = 1.408545e-009 ++wua1 = 1.1066055e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5226e-011 ++wuc1 = 1.387386e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83615636 ++lvth0 = -8.5625018e-009 ++k1 = 1.0017393 ++lk1 = -3.7831308e-008 ++k2 = 0.0013110182 ++lk2 = -1.9134473e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010921564 ++lu0 = 1.8946234e-009 ++ua = 2.4517091e-010 ++lua = 6.844565e-016 ++ub = 9.7125e-019 ++uc = 1.27186e-010 ++luc = -6.054912e-018 ++eu = 1.67 ++vsat = 84000 ++a0 = 0.89359946 ++la0 = -1.5741412e-007 ++ags = 0.31477964 ++lags = 7.4344262e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.091129254 ++lketa = 1.9070594e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.32875891 ++lpclm = 5.4072878e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.0171733e-005 ++lalpha0 = -2.5266856e-012 ++alpha1 = 0 ++beta0 = 38.169327 ++lbeta0 = -2.6169996e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29829927 ++lkt1 = -8.5149324e-009 ++kt1l = 0 ++kt2 = -0.020059454 ++lkt2 = 2.0420887e-009 ++ute = -1 ++ua1 = 1.8227927e-009 ++lua1 = -1.6526988e-016 ++ub1 = -2.5828527e-018 ++lub1 = -1.442034e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84131406 ++lvth0 = -5.9217627e-009 ++k1 = 0.977542 ++lk1 = -2.5442304e-008 ++k2 = -0.029872874 ++lk2 = -3.1683204e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010038909 ++lu0 = 2.3465428e-009 ++ua = 3.0718377e-010 ++lua = 6.5270591e-016 ++ub = 9.7125e-019 ++uc = -2.6651771e-011 ++luc = 7.2710027e-017 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1984524 ++la0 = -3.1349883e-007 ++ags = 0.2060396 ++lags = 6.3109325e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0059924171 ++lketa = -2.4519466e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39179417 ++lpclm = 2.1798824e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024138051 ++lpdiblc2= 2.5373158e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011160227 ++lalpha0 = -5.4459119e-011 ++alpha1 = 0 ++beta0 = 43.289011 ++lbeta0 = -5.2382779e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2989316 ++lkt1 = -8.1911808e-009 ++kt1l = 0 ++kt2 = -0.010868057 ++lkt2 = -2.6639067e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4970909e-018 ++lub1 = -1.8811348e-025 ++uc1 = -4.0368e-011 ++luc1 = -2.2339584e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84278682 ++lvth0 = -4.1367764e-009 ++k1 = 1.0138346 ++lk1 = -6.9428897e-008 ++k2 = -0.035631678 ++lk2 = 3.81135e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010842961 ++lu0 = 1.3720308e-009 ++ua = 6.2964284e-010 ++lua = 2.6188552e-016 ++ub = 9.7125e-019 ++uc = -1.6666527e-011 ++luc = 6.0607911e-017 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1828199 ++la0 = -2.9455227e-007 ++ags = 0.16623852 ++lags = 1.1134823e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0067991511 ++lketa = -2.3541705e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34142534 ++lpclm = 8.2845841e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.7987791e-005 ++lpdiblc2= 4.5176356e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021452182 ++lalpha0 = -2.5192017e-009 ++alpha1 = 0 ++beta0 = 44.236953 ++lbeta0 = -6.3871827e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9449091 ++lnoff = 5.5157018e-007 ++voffcv = 0.022036364 ++lvoffcv = -2.2062807e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29913669 ++lkt1 = -7.9426106e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4085267e-009 ++lua1 = 1.1086561e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.4534145e-011 ++luc1 = 6.9497843e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.3e-009 ++toxp = 8.3e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 1.2e-008 ++xw = -1e-008 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.8432 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 84000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.364e-010 ++cgdo = 1.364e-010 ++cgbo = 1e-013 ++cgdl = 4.4e-011 ++cgsl = 4.4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=225 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + + + +.endl pmos_3p3_s +* +* +.lib pmos_3p3_fs + + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.81501176 ++lvth0 = -7.9299856e-009 ++wvth0 = 4.0333546e-009 ++pvth0 = 2.388645e-015 ++k1 = 0.87205009 ++lk1 = 4.25291e-009 ++wk1 = 6.6268653e-008 ++pk1 = -2.1256353e-014 ++k2 = 0.029903393 ++lk2 = -2.5868222e-008 ++wk2 = -2.1061108e-008 ++pk2 = 3.4616668e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094635213 ++lvoff = -1.6386998e-009 ++wvoff = -1.6612803e-009 ++pvoff = 8.439304e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0075928117 ++lu0 = 2.5375194e-009 ++wu0 = 6.1967943e-010 ++pu0 = -5.3349279e-016 ++ua = -6.122012e-011 ++lua = 1.0774293e-015 ++wua = 1.383858e-017 ++pua = -1.9437706e-022 ++ub = 6.7836503e-019 ++lub = -1.5002929e-025 ++wub = -4.7707426e-027 ++pub = 1.3739739e-033 ++uc = 8.579096e-011 ++luc = 8.6809692e-018 ++wuc = -1.2711987e-017 ++puc = -4.5344012e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.039392 ++la0 = -2.1366429e-007 ++wa0 = 1.0928007e-008 ++pa0 = -2.7738176e-015 ++ags = 0.18391438 ++lags = 1.0913958e-007 ++wags = -2.1847527e-008 ++pags = -1.2242165e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.067178738 ++lketa = 8.7913147e-009 ++wketa = -7.3043146e-009 ++pketa = 3.7105918e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.35338606 ++lpclm = 7.4286569e-008 ++wpclm = 2.8018309e-008 ++ppclm = 6.6284179e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1653153e-005 ++lalpha0 = -3.1380589e-012 ++walpha0 = -1.0367347e-013 ++palpha0 = 6.4786605e-020 ++alpha1 = 0 ++beta0 = 39.988812 ++lbeta0 = -3.7819465e-006 ++wbeta0 = 1.9714501e-007 ++pbeta0 = 1.1986341e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28327726 ++lkt1 = -1.6612629e-008 ++wkt1 = -1.0941603e-008 ++pkt1 = 1.9661049e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1539091e-009 ++lua1 = 1.7581418e-016 ++wua1 = 1.7823682e-016 ++pua1 = -9.0544304e-023 ++ub1 = -2.0676223e-018 ++lub1 = -6.9766226e-025 ++wub1 = -1.440724e-025 ++pub1 = 1.515108e-031 ++uc1 = -2.5586018e-010 ++luc1 = 6.0619732e-017 ++wuc1 = 4.0387143e-017 ++puc1 = -1.4245637e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.84703289 ++lvth0 = 8.3367507e-009 ++wvth0 = 5.7666931e-009 ++pvth0 = 1.508109e-015 ++k1 = 1.0117972 ++lk1 = -6.6738621e-008 ++wk1 = -1.772589e-008 ++pk1 = 2.1412875e-014 ++k2 = -0.018870868 ++lk2 = -1.0908973e-009 ++wk2 = -2.3681999e-009 ++pk2 = -6.0343307e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12381402 ++lvoff = 1.3184133e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010262889 ++lu0 = 1.18112e-009 ++wu0 = -2.3738733e-010 ++pu0 = -9.8102871e-017 ++ua = 3.5795686e-010 ++lua = 8.6448742e-016 ++wua = -3.9646086e-017 ++pua = -1.6720685e-022 ++ub = 1.0847393e-018 ++lub = -3.564674e-025 ++wub = -1.8776762e-025 ++pub = 9.4336388e-032 ++uc = -1.4338071e-011 ++luc = 5.9546517e-017 ++wuc = -7.0667866e-018 ++puc = -7.4021628e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1561845 ++la0 = -2.7299485e-007 ++wa0 = 3.7967e-008 ++pa0 = -1.6509626e-014 ++ags = 0.1893918 ++lags = 1.0635705e-007 ++wags = 1.3830885e-008 ++pags = -3.0366798e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0048813173 ++lketa = -2.2855775e-008 ++wketa = -2.151948e-009 ++pketa = 1.0931896e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.25839327 ++lpclm = 1.2254291e-007 ++wpclm = 8.3053604e-008 ++ppclm = -2.1329512e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024301606 ++lpdiblc2= 2.5091844e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.6165264e-005 ++lalpha0 = -3.5910211e-011 ++walpha0 = 4.6901179e-012 ++palpha0 = -2.3704594e-018 ++alpha1 = 0 ++beta0 = 42.499959 ++lbeta0 = -5.0576089e-006 ++wbeta0 = 2.6675886e-007 ++pbeta0 = 8.4499576e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30596768 ++lkt1 = -5.0858969e-009 ++wkt1 = 2.4495559e-008 ++pkt1 = -1.6035973e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2324617e-018 ++lub1 = -6.1392387e-025 ++wub1 = -3.3344363e-026 ++pub1 = 9.5260957e-032 ++uc1 = -7.4906407e-011 ++luc1 = -3.1304785e-017 ++wuc1 = 5.9908956e-018 ++puc1 = 3.2276564e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83230514 ++lvth0 = -9.4543724e-009 ++wvth0 = 3.5643356e-009 ++pvth0 = 4.1685569e-015 ++k1 = 0.95616008 ++lk1 = 4.7102587e-010 ++wk1 = 2.9690576e-008 ++pk1 = -3.5866216e-014 ++k2 = -0.011590073 ++lk2 = -9.886097e-009 ++wk2 = -1.4606238e-008 ++pk2 = 8.7492189e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097664506 ++lvoff = -1.8404477e-008 ++wvoff = 9.6199433e-010 ++pvoff = -1.1620891e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087584261 ++lu0 = 2.9985114e-009 ++wu0 = 2.1268603e-010 ++pu0 = -6.4179149e-016 ++ua = 3.9557594e-010 ++lua = 8.1904358e-016 ++wua = -5.0968009e-017 ++pua = -1.5352997e-022 ++ub = 8.474689e-019 ++lub = -6.9844795e-026 ++wub = -1.0634177e-025 ++pub = -4.0260421e-033 ++uc = -4.4084373e-011 ++luc = 9.548005e-017 ++wuc = 1.8112319e-018 ++puc = -1.8126809e-023 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.2627392 ++la0 = -4.0171294e-007 ++wa0 = -3.3357398e-009 ++pa0 = 3.3384084e-014 ++ags = 0.15724995 ++lags = 1.451844e-007 ++wags = 7.1650729e-010 ++pags = -1.452463e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.00028266778 ++lketa = -2.8410943e-008 ++wketa = -3.3599854e-009 ++pketa = 2.5524988e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32160177 ++lpclm = 4.6187031e-008 ++wpclm = 4.7768253e-009 ++ppclm = 7.3228837e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8136709e-005 ++lpdiblc2= 4.500927e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020613963 ++lalpha0 = -2.4340693e-009 ++walpha0 = 2.1598538e-011 ++palpha0 = -2.279583e-017 ++alpha1 = 0 ++beta0 = 44.471345 ++lbeta0 = -7.439044e-006 ++wbeta0 = 3.9127265e-007 ++pbeta0 = -6.5913079e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9450909 ++lnoff = 5.4953018e-007 ++voffcv = 0.021963636 ++lvoffcv = -2.1981207e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.26888633 ++lkt1 = -4.9880168e-008 ++wkt1 = -1.0044391e-008 ++pkt1 = 2.5688286e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0128038e-018 ++lub1 = 3.2872945e-025 ++wub1 = 1.8565946e-025 ++pub1 = -1.6929566e-031 ++uc1 = -3.6006695e-011 ++luc1 = -7.8295637e-017 ++wuc1 = -1.1924963e-017 ++puc1 = 2.4870014e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83324982 ++wvth0 = 3.980858e-009 ++k1 = 0.95620714 ++wk1 = 2.6106821e-008 ++k2 = -0.012577893 ++wk2 = -1.3732015e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099503482 ++wvoff = 8.458783e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090580375 ++wu0 = 1.4855819e-010 ++ua = 4.7741482e-010 ++wua = -6.6308733e-017 ++ub = 8.4049e-019 ++wub = -1.0674405e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.2226 ++ags = 0.17175679 ++wags = -7.3479464e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0031214911 ++wketa = -3.1049396e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.32621679 ++wpclm = 1.2093855e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018181839 ++walpha0 = 1.9320777e-011 ++alpha1 = 0 ++beta0 = 43.728036 ++wbeta0 = 3.8468661e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.27387036 ++wkt1 = -7.4776161e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.9799571e-018 ++wub1 = 1.6874343e-025 ++uc1 = -4.383e-011 ++wuc1 = -9.43995e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83576942 ++lvth0 = -2.2414438e-009 ++wvth0 = 1.4723553e-008 ++pvth0 = -5.4095405e-016 ++k1 = 1.0007271 ++lk1 = -3.7021562e-008 ++k2 = 0.015311208 ++lk2 = -2.1380073e-008 ++wk2 = -1.3546134e-008 ++pk2 = 1.1502704e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090866629 ++lu0 = 1.9183067e-009 ++wu0 = -1.4965392e-010 ++pu0 = -2.1459826e-016 ++ua = -1.2290839e-010 ++lua = 7.8149042e-016 ++wua = 4.5608039e-017 ++pua = -4.1968523e-023 ++ub = 1.7620586e-018 ++lub = -3.2223504e-025 ++wub = -5.6287295e-025 ++pub = 9.0059933e-032 ++uc = 8.5890808e-011 ++luc = 1.2960088e-017 ++wuc = -1.2763408e-017 ++puc = -6.7381475e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.67581086 ++la0 = -1.0822777e-007 ++wa0 = 1.9817231e-007 ++pa0 = -5.7073625e-014 ++ags = 0.200375 ++lags = 7.2879057e-008 ++wags = -3.0324746e-008 ++pags = 6.4320031e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.1060667 ++lketa = 2.3111339e-008 ++wketa = 1.2722988e-008 ++pketa = -3.6642206e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37672 ++lpclm = 2.8716008e-008 ++wpclm = 1.6001332e-008 ++ppclm = 3.0097257e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.2249381e-005 ++lalpha0 = -3.1611736e-012 ++walpha0 = -4.1073109e-013 ++palpha0 = 7.669064e-020 ++alpha1 = 0 ++beta0 = 38.401961 ++lbeta0 = -2.8404732e-006 ++wbeta0 = 1.0143734e-006 ++pbeta0 = -3.6499537e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33217428 ++lkt1 = 5.0237373e-010 ++wkt1 = 1.4240363e-008 ++pkt1 = -6.8481216e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 2.02488e-009 ++lua1 = -2.6663904e-016 ++wua1 = -2.703132e-016 ++pua1 = 1.3731911e-022 ++ub1 = -2.8837292e-018 ++lub1 = -3.2595866e-026 ++wub1 = 2.7622264e-025 ++pub1 = -1.9099839e-031 ++uc1 = 7.6479273e-012 ++luc1 = -3.5883051e-017 ++wuc1 = -9.5319534e-017 ++puc1 = 3.5453296e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83962246 ++lvth0 = -2.8410138e-010 ++wvth0 = 1.950321e-009 ++pvth0 = 5.9478478e-015 ++k1 = 0.977378 ++lk1 = -2.5160224e-008 ++k2 = -0.026834606 ++lk2 = 3.0000655e-011 ++wk2 = 1.7331254e-009 ++pk2 = -6.6115932e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12381402 ++lvoff = 1.3184133e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097266426 ++lu0 = 1.593197e-009 ++wu0 = 3.8779626e-011 ++pu0 = -3.103225e-016 ++ua = 2.6021662e-010 ++lua = 5.8686291e-016 ++wua = 1.0690141e-017 ++pua = -2.4230231e-023 ++ub = 1.2719156e-018 ++lub = -7.3242364e-026 ++wub = -2.8416343e-025 ++pub = -5.1524505e-032 ++uc = 7.1659939e-012 ++luc = 5.2952294e-017 ++wuc = -1.814138e-017 ++puc = -4.006138e-024 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.3508441 ++la0 = -4.5114467e-007 ++wa0 = -6.2282725e-008 ++pa0 = 7.5237532e-014 ++ags = 0.19135754 ++lags = 7.7459926e-008 ++wags = 1.2818526e-008 ++pags = -1.5484779e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0012954815 ++lketa = -3.0112442e-008 ++wketa = -3.9986535e-009 ++pketa = 4.8303734e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.55271631 ++lpclm = -6.0690117e-008 ++wpclm = -6.8522762e-008 ++ppclm = 7.3035497e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024301606 ++lpdiblc2= 2.5091844e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00012364806 ++lalpha0 = -5.9751701e-011 ++walpha0 = -1.9763521e-011 ++palpha0 = 9.9079077e-018 ++alpha1 = 0 ++beta0 = 43.434876 ++lbeta0 = -5.3971937e-006 ++wbeta0 = -2.1472328e-007 ++pbeta0 = 2.5938572e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28324255 ++lkt1 = -2.4354946e-008 ++wkt1 = 1.2792118e-008 ++pkt1 = -6.1124128e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.1353993e-018 ++lub1 = 9.525255e-026 ++wub1 = 4.3166852e-025 ++pub1 = -2.699649e-031 ++uc1 = -9.9248709e-011 ++luc1 = 1.842044e-017 ++wuc1 = 1.8527181e-017 ++puc1 = -2.2380835e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.838712 ++lvth0 = -1.3839329e-009 ++wvth0 = 6.8638701e-009 ++pvth0 = 1.2280528e-017 ++k1 = 1.0138117 ++lk1 = -6.9172112e-008 ++k2 = -0.027503825 ++lk2 = 8.3841624e-010 ++wk2 = -6.4106558e-009 ++pk2 = 3.2260946e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095796556 ++lvoff = -2.0660961e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097289562 ++lu0 = 1.5904022e-009 ++wu0 = -2.8713699e-010 ++pu0 = 8.3384782e-017 ++ua = 4.0244395e-010 ++lua = 4.150523e-016 ++wua = -5.4505036e-017 ++pua = 5.4525543e-023 ++ub = 1.1639854e-018 ++lub = 5.7137303e-026 ++wub = -2.6934777e-025 ++pub = -6.9421823e-032 ++uc = 9.5237707e-013 ++luc = 6.0458343e-017 ++wuc = -2.1382694e-017 ++puc = -9.0630294e-026 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1196626 ++la0 = -1.7187734e-007 ++wa0 = 7.0348718e-008 ++pa0 = -8.4981251e-014 ++ags = 0.16551068 ++lags = 1.0868294e-007 ++wags = -3.5377679e-009 ++pags = 4.2736236e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068069114 ++lketa = -2.3454635e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.328728 ++lpclm = 2.0988775e-007 ++wpclm = 1.1068181e-009 ++ppclm = -1.1077036e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8136709e-005 ++lpdiblc2= 4.500927e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021750673 ++lalpha0 = -2.5378662e-009 ++walpha0 = -3.6942045e-011 ++palpha0 = 3.0659565e-017 ++alpha1 = 0 ++beta0 = 44.362547 ++lbeta0 = -6.5178205e-006 ++wbeta0 = 4.4730399e-007 ++pbeta0 = -5.4034322e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9450909 ++lnoff = 5.4953018e-007 ++voffcv = 0.021963636 ++lvoffcv = -2.1981207e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33757353 ++lkt1 = 4.127688e-008 ++wkt1 = 2.5329519e-008 ++pkt1 = -2.1257593e-014 ++kt1l = 0 ++kt2 = -0.016935002 ++lkt2 = 4.6737542e-009 ++wkt2 = 1.9925359e-009 ++pkt2 = -2.4069834e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5968078e-018 ++lub1 = -5.55366e-025 ++wub1 = -2.8578486e-026 ++pub1 = 2.8601349e-031 ++uc1 = -4.2580527e-011 ++luc1 = -5.0034723e-017 ++wuc1 = -8.5394397e-018 ++puc1 = 1.0315643e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83885029 ++wvth0 = 6.8650971e-009 ++k1 = 1.0069 ++k2 = -0.02742005 ++wk2 = -6.0883043e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0098878693 ++wu0 = -2.7880518e-010 ++ua = 4.43916e-010 ++wua = -4.905684e-017 ++ub = 1.1696946e-018 ++wub = -2.762844e-025 ++uc = 6.9933786e-012 ++wuc = -2.139175e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1024886 ++wa0 = 6.1857386e-008 ++ags = 0.17637029 ++wags = -3.1107471e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0019214836 ++walpha0 = -3.3878539e-011 ++alpha1 = 0 ++beta0 = 43.711286 ++wbeta0 = 3.9331286e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33344914 ++wkt1 = 2.3205459e-008 ++kt1l = 0 ++kt2 = -0.016468 ++wkt2 = 1.75203e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.758e-011 ++wuc1 = -7.5087e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.82676296 ++lvth0 = -9.1651899e-009 ++wvth0 = 3.7806977e-009 ++pvth0 = 7.8713975e-015 ++k1 = 1.0007271 ++lk1 = -3.7021562e-008 ++k2 = 0.0003347419 ++lk2 = -1.8489037e-008 ++wk2 = 4.6502732e-009 ++pk2 = -2.3623388e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011249601 ++lu0 = 1.8695879e-009 ++wu0 = -2.7776236e-009 ++pu0 = -1.5540493e-016 ++ua = 3.1164935e-010 ++lua = 6.5915544e-016 ++wua = -4.8237961e-016 ++pua = 1.0666847e-022 ++ub = 9.2602732e-019 ++lub = 3.4256322e-026 ++wub = 4.5290511e-025 ++pub = -3.4307707e-031 ++uc = 1.3415357e-010 ++luc = -7.7670863e-018 ++wuc = -7.1402667e-017 ++puc = 1.8445369e-023 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.89635642 ++la0 = -1.5388505e-007 ++wa0 = -6.9790553e-008 ++pa0 = -1.6000271e-015 ++ags = 0.33424764 ++lags = -2.5134022e-009 ++wags = -1.9298e-007 ++pags = 9.8033842e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.089931978 ++lketa = 1.8464538e-008 ++wketa = -6.8807038e-009 ++pketa = 1.9816427e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32196515 ++lpclm = 5.2836533e-008 ++wpclm = 8.2528472e-008 ++ppclm = 7.9081797e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.8546141e-006 ++lalpha0 = -2.3862494e-012 ++walpha0 = 2.4989109e-012 ++palpha0 = -8.6484221e-019 ++alpha1 = 0 ++beta0 = 37.942253 ++lbeta0 = -2.4809199e-006 ++wbeta0 = 1.5729191e-006 ++pbeta0 = -8.0185264e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29549971 ++lkt1 = -8.7743217e-009 ++wkt1 = -3.0319244e-008 ++pkt1 = 4.4230633e-015 ++kt1l = 0 ++kt2 = -0.020962848 ++lkt2 = 2.2742923e-009 ++wkt2 = 9.5946705e-009 ++pkt2 = -2.7632651e-015 ++ute = -1 ++ua1 = 1.820576e-009 ++lua1 = -1.628526e-016 ++wua1 = -2.208382e-017 ++pua1 = 1.121858e-023 ++ub1 = -2.5770911e-018 ++lub1 = -1.3439579e-025 ++wub1 = -9.6342676e-026 ++pub1 = -6.7311483e-032 ++uc1 = -8.5821897e-011 ++luc1 = 9.2552394e-019 ++wuc1 = 1.8246304e-017 ++puc1 = -9.2691223e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.830432 ++lvth0 = -7.3013165e-009 ++wvth0 = -9.2160872e-009 ++pvth0 = 1.4473764e-014 ++k1 = 0.977378 ++lk1 = -2.5160224e-008 ++k2 = -0.030512551 ++lk2 = -2.818612e-009 ++wk2 = 6.2018282e-009 ++pk2 = -3.1505287e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094277714 ++lvoff = -1.8203092e-009 ++wvoff = -3.5886608e-008 ++pvoff = 1.8230397e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01009483 ++lu0 = 2.4562116e-009 ++wu0 = -4.0856791e-010 ++pu0 = -1.3588852e-015 ++ua = 3.1724186e-010 ++lua = 6.5631445e-016 ++wua = -5.8595534e-017 ++pua = -1.0861384e-022 ++ub = 9.6202895e-019 ++lub = 1.5967497e-026 ++wub = 9.2348847e-026 ++pub = -1.5991449e-031 ++uc = -2.8726012e-011 ++luc = 7.4975743e-017 ++wuc = 2.5467408e-017 ++puc = -3.0764628e-023 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1821897 ++la0 = -2.9908837e-007 ++wa0 = 1.4263238e-007 ++pa0 = -1.0951088e-013 ++ags = 0.20707304 ++lags = 6.2091296e-008 ++wags = -6.2758015e-009 ++pags = 3.1881072e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0063663954 ++lketa = -2.3986778e-008 ++wketa = 2.1625069e-009 ++pketa = -2.6123084e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37752254 ++lpclm = 2.4613381e-008 ++wpclm = 1.4433767e-007 ++ppclm = -3.0608253e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024301606 ++lpdiblc2= 2.5091844e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011178547 ++lalpha0 = -5.4167125e-011 ++walpha0 = -5.3504792e-012 ++palpha0 = 3.122648e-018 ++alpha1 = 0 ++beta0 = 43.254845 ++lbeta0 = -5.1797167e-006 ++wbeta0 = 4.013934e-009 ++pbeta0 = -4.8488322e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3026115 ++lkt1 = -5.1615319e-009 ++wkt1 = 3.6325391e-008 ++pkt1 = -2.9432412e-014 ++kt1l = 0 ++kt2 = -0.010584133 ++lkt2 = -2.9980948e-009 ++wkt2 = -3.0154679e-009 ++pkt2 = 3.6426852e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.459394e-018 ++lub1 = -1.941859e-025 ++wub1 = -3.8967792e-025 ++pub1 = 8.1702823e-032 ++uc1 = -3.4507691e-011 ++luc1 = -2.5142093e-017 ++wuc1 = -6.0133156e-017 ++puc1 = 3.0547643e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83275028 ++lvth0 = -4.5008395e-009 ++wvth0 = -3.7962851e-010 ++pvth0 = 3.7993221e-015 ++k1 = 1.0138117 ++lk1 = -6.9172112e-008 ++k2 = -0.036023963 ++lk2 = 3.8391732e-009 ++wk2 = 3.941312e-009 ++pk2 = -4.1982509e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098146034 ++lvoff = 2.8526213e-009 ++wvoff = 2.8546166e-009 ++pvoff = -2.8569002e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011029914 ++lu0 = 1.32663e-009 ++wu0 = -1.8678007e-009 ++pu0 = 4.0386794e-016 ++ua = 6.6730377e-010 ++lua = 2.3343966e-016 ++wua = -3.7630972e-016 ++pua = 2.751849e-022 ++ub = 9.7524707e-019 ++wub = -4.0030695e-026 ++uc = -1.6646548e-011 ++luc = 6.038375e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1834353 ++la0 = -3.0059299e-007 ++wa0 = -7.1351178e-009 ++pa0 = 7.1408259e-014 ++ags = 0.16678281 ++lags = 1.107619e-007 ++wags = -5.0834017e-009 ++pags = 1.7476882e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068069114 ++lketa = -2.3454635e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34308375 ++lpclm = 6.6215436e-008 ++wpclm = -1.6335415e-008 ++ppclm = 1.6348483e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8136709e-005 ++lpdiblc2= 4.500927e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021443499 ++lalpha0 = -2.509505e-009 ++walpha0 = 3.7962851e-013 ++palpha0 = -3.7993221e-018 ++alpha1 = 0 ++beta0 = 44.166386 ++lbeta0 = -6.2808583e-006 ++wbeta0 = 6.8563925e-007 ++pbeta0 = -8.2825222e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9450909 ++lnoff = 5.4953018e-007 ++voffcv = 0.021963636 ++lvoffcv = -2.1981207e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29671112 ++lkt1 = -1.2289189e-008 ++wkt1 = -2.4318311e-008 ++pkt1 = 4.382518e-014 ++kt1l = 0 ++kt2 = -0.012758239 ++lkt2 = -3.717759e-010 ++wkt2 = -3.0822315e-009 ++pkt2 = 3.7233357e-015 ++ute = -1 ++ua1 = 1.3959388e-009 ++lua1 = 1.2570597e-016 ++wua1 = 1.2643439e-016 ++pua1 = -1.5273275e-022 ++ub1 = -2.6567142e-018 ++lub1 = 4.4176841e-026 ++wub1 = 4.420774e-026 ++pub1 = -4.4243106e-031 ++uc1 = -6.6592244e-011 ++luc1 = 1.3616046e-017 ++wuc1 = 2.0634796e-017 ++puc1 = -6.7020042e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.8332 ++k1 = 1.0069 ++k2 = -0.035640352 ++wk2 = 3.899363e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011162471 ++wu0 = -1.8274461e-009 ++ua = 6.9062908e-010 ++wua = -3.4881323e-016 ++ub = 9.7524707e-019 ++wub = -4.0030695e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1534 ++ags = 0.17785014 ++wags = -4.9087726e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.538802 ++wbeta0 = 6.0288024e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29793906 ++wkt1 = -1.9939296e-008 ++kt1l = 0 ++kt2 = -0.012795386 ++wkt2 = -2.7101956e-009 ++ute = -1 ++ua1 = 1.4084993e-009 ++wua1 = 1.1117333e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5231727e-011 ++wuc1 = 1.3938149e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.82638545 ++lvth0 = -8.3792291e-009 ++k1 = 1.0007271 ++lk1 = -3.7021562e-008 ++k2 = 0.00079907273 ++lk2 = -1.8724917e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010972255 ++lu0 = 1.8540707e-009 ++ua = 2.6348364e-010 ++lua = 6.6980631e-016 ++ub = 9.7125e-019 ++uc = 1.27024e-010 ++luc = -5.925312e-018 ++eu = 1.67 ++vsat = 90000 ++a0 = 0.88938782 ++la0 = -1.5404481e-007 ++ags = 0.31497855 ++lags = 7.2752989e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.090619018 ++lketa = 1.8662405e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.33020564 ++lpclm = 5.2915497e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.0104131e-005 ++lalpha0 = -2.4726041e-012 ++alpha1 = 0 ++beta0 = 38.099309 ++lbeta0 = -2.560985e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29852709 ++lkt1 = -8.3326778e-009 ++kt1l = 0 ++kt2 = -0.020004818 ++lkt2 = 1.9983796e-009 ++ute = -1 ++ua1 = 1.8183709e-009 ++lua1 = -1.6173242e-016 ++ub1 = -2.5867109e-018 ++lub1 = -1.4111686e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83135223 ++lvth0 = -5.8561079e-009 ++k1 = 0.977378 ++lk1 = -2.5160224e-008 ++k2 = -0.029893297 ++lk2 = -3.133193e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010054034 ++lu0 = 2.3205266e-009 ++ua = 3.1139109e-010 ++lua = 6.4546933e-016 ++ub = 9.7125e-019 ++uc = -2.6183086e-011 ++luc = 7.1903887e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1964316 ++la0 = -3.1002305e-007 ++ags = 0.2064464 ++lags = 6.2409629e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0061504686 ++lketa = -2.4247618e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39193469 ++lpclm = 2.155714e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024301606 ++lpdiblc2= 2.5091844e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011125123 ++lalpha0 = -5.3855328e-011 ++alpha1 = 0 ++beta0 = 43.255246 ++lbeta0 = -5.1802008e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2989844 ++lkt1 = -8.1003648e-009 ++kt1l = 0 ++kt2 = -0.010885229 ++lkt2 = -2.6343719e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4983034e-018 ++lub1 = -1.8602786e-025 ++uc1 = -4.0512e-011 ++luc1 = -2.2091904e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.83278818 ++lvth0 = -4.1214764e-009 ++k1 = 1.0138117 ++lk1 = -6.9172112e-008 ++k2 = -0.035630422 ++lk2 = 3.7972536e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010843414 ++lu0 = 1.3669563e-009 ++ua = 6.2972916e-010 ++lua = 2.6091693e-016 ++ub = 9.7125e-019 ++uc = -1.6646548e-011 ++luc = 6.038375e-017 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1827228 ++la0 = -2.9346286e-007 ++ags = 0.16627523 ++lags = 1.109364e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068069114 ++lketa = -2.3454635e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34145265 ++lpclm = 8.2539433e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8136709e-005 ++lpdiblc2= 4.500927e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021443878 ++lalpha0 = -2.5098843e-009 ++alpha1 = 0 ++beta0 = 44.234847 ++lbeta0 = -6.3635595e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9450909 ++lnoff = 5.4953018e-007 ++voffcv = 0.021963636 ++lvoffcv = -2.1981207e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29913931 ++lkt1 = -7.9132346e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4085633e-009 ++lua1 = 1.1045557e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.4531855e-011 ++luc1 = 6.9240803e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 8.1e-009 ++toxp = 8.1e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = 8e-009 ++xw = -5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.8332 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 90000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.302e-010 ++cgdo = 1.302e-010 ++cgbo = 1e-013 ++cgdl = 4.2e-011 ++cgsl = 4.2e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + +.endl pmos_3p3_fs +* +* +.lib pmos_3p3_sf + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.68623384 ++lvth0 = -7.4340753e-009 ++wvth0 = 4.5642665e-009 ++pvth0 = 2.3220935e-015 ++k1 = 0.86723166 ++lk1 = 5.4966687e-009 ++wk1 = 6.795952e-008 ++pk1 = -2.0664117e-014 ++k2 = 0.028783357 ++lk2 = -2.3923245e-008 ++wk2 = -2.1981336e-008 ++pk2 = 3.3652193e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094684782 ++lvoff = -1.5626994e-009 ++wvoff = -1.6675146e-009 ++pvoff = 8.2041716e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0078239364 ++lu0 = 2.3613853e-009 ++wu0 = 5.9658614e-010 ++pu0 = -5.1862883e-016 ++ua = 5.7221977e-011 ++lua = 1.0002135e-015 ++wua = -7.884629e-018 ++pua = -1.8896141e-022 ++ub = 6.6233941e-019 ++lub = -1.3733536e-025 ++wub = -4.9106352e-027 ++pub = 1.3356928e-033 ++uc = 8.7831657e-011 ++luc = 8.2831734e-018 ++wuc = -1.4037289e-017 ++puc = -4.4080656e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.0151475 ++la0 = -1.9522869e-007 ++wa0 = 1.1291855e-008 ++pa0 = -2.6965346e-015 ++ags = 0.19776586 ++lags = 1.0075502e-007 ++wags = -2.4642378e-008 ++pags = -1.1901079e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0656473 ++lketa = 7.7609556e-009 ++wketa = -7.3317252e-009 ++pketa = 3.6072088e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.35913516 ++lpclm = 6.7448817e-008 ++wpclm = 3.0548187e-008 ++ppclm = 6.4437396e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1317951e-005 ++lalpha0 = -2.8752733e-012 ++walpha0 = -1.0265377e-013 ++palpha0 = 6.2981547e-020 ++alpha1 = 0 ++beta0 = 39.557841 ++lbeta0 = -3.4683987e-006 ++wbeta0 = 2.234567e-007 ++pbeta0 = 1.1652383e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28420773 ++lkt1 = -1.5344138e-008 ++wkt1 = -1.1400184e-008 ++pkt1 = 1.9113261e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1592273e-009 ++lua1 = 1.6766018e-016 ++wua1 = 1.7890568e-016 ++pua1 = -8.8021596e-023 ++ub1 = -2.1333843e-018 ++lub1 = -6.4960147e-025 ++wub1 = -1.3550978e-025 ++pub1 = 1.4728947e-031 ++uc1 = -2.5243909e-010 ++luc1 = 5.6525433e-017 ++wuc1 = 4.1267577e-017 ++puc1 = -1.3848731e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.71729526 ++lvth0 = 7.848145e-009 ++wvth0 = 6.1706137e-009 ++pvth0 = 1.5317707e-015 ++k1 = 1.0114756 ++lk1 = -6.5471375e-008 ++wk1 = -1.8245666e-008 ++pk1 = 2.1748834e-014 ++k2 = -0.018690632 ++lk2 = -5.6604249e-010 ++wk2 = -2.6841281e-009 ++pk2 = -6.129007e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12347027 ++lvoff = 1.259976e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01031351 ++lu0 = 1.1365149e-009 ++wu0 = -2.5501298e-010 ++pu0 = -9.9642066e-017 ++ua = 3.8413264e-010 ++lua = 8.3937346e-016 ++wua = -4.6769074e-017 ++pua = -1.6983026e-022 ++ub = 1.0907567e-018 ++lub = -3.4811665e-025 ++wub = -1.9694477e-025 ++pub = 9.5816488e-032 ++uc = -1.2185662e-011 ++luc = 5.7491694e-017 ++wuc = -7.7156746e-018 ++puc = -7.5182999e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1459651 ++la0 = -2.5959096e-007 ++wa0 = 3.9893726e-008 ++pa0 = -1.6768655e-014 ++ags = 0.19108744 ++lags = 1.0404081e-007 ++wags = 1.3857952e-008 ++pags = -3.0843241e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0053017786 ++lketa = -2.1929041e-008 ++wketa = -2.2567913e-009 ++pketa = 1.1103413e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.25477175 ++lpclm = 1.1879561e-007 ++wpclm = 8.7678071e-008 ++ppclm = -2.1664163e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024955823 ++lpdiblc2= 2.3979675e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.4846555e-005 ++lalpha0 = -3.4131346e-011 ++walpha0 = 4.918957e-012 ++palpha0 = -2.407651e-018 ++alpha1 = 0 ++beta0 = 42.345869 ++lbeta0 = -4.8401083e-006 ++wbeta0 = 2.85852e-007 ++pbeta0 = 8.5825341e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30808974 ++lkt1 = -3.5941865e-009 ++wkt1 = 2.5589445e-008 ++pkt1 = -1.6287571e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2459185e-018 ++lub1 = -5.9423465e-025 ++wub1 = -3.2798588e-026 ++pub1 = 9.6755564e-032 ++uc1 = -7.622458e-011 ++luc1 = -3.0172107e-017 ++wuc1 = 6.4565445e-018 ++puc1 = 3.2782971e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70261262 ++lvth0 = -9.6535664e-009 ++wvth0 = 3.7940282e-009 ++pvth0 = 4.3646606e-015 ++k1 = 0.95371136 ++lk1 = 3.3836545e-009 ++wk1 = 3.1504606e-008 ++pk1 = -3.755349e-014 ++k2 = -0.010397236 ++lk2 = -1.045177e-008 ++wk2 = -1.5511159e-008 ++pk2 = 9.1608133e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097768223 ++lvoff = -1.8037078e-008 ++wvoff = 1.0207701e-009 ++pvoff = -1.2167579e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087448909 ++lu0 = 3.0063094e-009 ++wu0 = 2.2513935e-010 ++pu0 = -6.7198364e-016 ++ua = 4.0088804e-010 ++lua = 8.1940101e-016 ++wua = -5.4384592e-017 ++pua = -1.6075256e-022 ++ub = 8.5616366e-019 ++lub = -6.8481784e-026 ++wub = -1.1302537e-025 ++pub = -4.2154414e-033 ++uc = -4.4105686e-011 ++luc = 9.5540362e-017 ++wuc = 1.8994754e-018 ++puc = -1.8979559e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2624795 ++la0 = -3.9847608e-007 ++wa0 = -3.4982576e-009 ++pa0 = 3.495459e-014 ++ags = 0.15738448 ++lags = 1.4421474e-007 ++wags = 7.410721e-010 ++pags = -1.520792e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -4.2919829e-005 ++lketa = -2.8197601e-008 ++wketa = -3.567392e-009 ++pketa = 2.6725774e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32126019 ++lpclm = 3.9541387e-008 ++wpclm = 5.1797956e-009 ++ppclm = 7.6673781e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8732382e-005 ++lpdiblc2= 4.4342116e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020563928 ++lalpha0 = -2.3961345e-009 ++walpha0 = 2.2922796e-011 ++palpha0 = -2.3868227e-017 ++alpha1 = 0 ++beta0 = 44.429178 ++lbeta0 = -7.3234127e-006 ++wbeta0 = 4.1575066e-007 ++pbeta0 = -6.9013864e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9458182 ++lnoff = 5.4138473e-007 ++voffcv = 0.021672727 ++lvoffcv = -2.1655389e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.26812521 ++lkt1 = -5.1231914e-008 ++wkt1 = -1.0639016e-008 ++pkt1 = 2.6896755e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0276908e-018 ++lub1 = 3.3763797e-025 ++wub1 = 1.9708019e-025 ++pub1 = -1.7725993e-031 ++uc1 = -3.5127704e-011 ++luc1 = -7.9159583e-017 ++wuc1 = -1.2638834e-017 ++puc1 = 2.6039988e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70357875 ++wvth0 = 4.2308437e-009 ++k1 = 0.95405 ++wk1 = 2.774625e-008 ++k2 = -0.01144325 ++wk2 = -1.4594344e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099573375 ++wvoff = 8.9899687e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090457625 ++wu0 = 1.5788719e-010 ++ua = 4.8289375e-010 ++wua = -7.0472719e-017 ++ub = 8.4931e-019 ++wub = -1.1344725e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2226 ++ags = 0.1718175 ++wags = -7.809375e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0028649375 ++wketa = -3.2999203e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.3252175 ++wpclm = 1.2853312e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018165875 ++walpha0 = 2.0534062e-011 ++alpha1 = 0 ++beta0 = 43.69625 ++wbeta0 = 4.0884375e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2732525 ++wkt1 = -7.9471875e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.9939e-018 ++wub1 = 1.7934e-025 ++uc1 = -4.305e-011 ++wuc1 = -1.003275e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70624891 ++lvth0 = -2.0423367e-009 ++wvth0 = 1.5072177e-008 ++pvth0 = -5.0856922e-016 ++k1 = 0.99667836 ++lk1 = -3.3863555e-008 ++k2 = 0.013187532 ++lk2 = -1.9573129e-008 ++wk2 = -1.3793528e-008 ++pk2 = 1.0814082e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0092992182 ++lu0 = 1.7578086e-009 ++wu0 = -1.7793682e-010 ++pu0 = -2.0175109e-016 ++ua = -3.8099091e-011 ++lua = 7.1544135e-016 ++wua = 4.2158932e-017 ++pua = -3.9456029e-023 ++ub = 1.7356567e-018 ++lub = -2.9606431e-025 ++wub = -5.6840223e-025 ++pub = 8.4668392e-032 ++uc = 8.7523896e-011 ++luc = 1.1953068e-017 ++wuc = -1.3875714e-017 ++puc = -6.3347605e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.66090759 ++la0 = -9.8161425e-008 ++wa0 = 1.9726782e-007 ++pa0 = -5.3656847e-014 ++ags = 0.20881855 ++lags = 6.6568316e-008 ++wags = -3.0445036e-008 ++pags = 6.0469439e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.10373614 ++lketa = 2.1193464e-008 ++wketa = 1.2664919e-008 ++pketa = -3.4448579e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37955209 ++lpclm = 2.5826511e-008 ++wpclm = 1.9829298e-008 ++ppclm = 2.829545e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1910101e-005 ++lalpha0 = -2.8926407e-012 ++walpha0 = -4.1353238e-013 ++palpha0 = 7.2099467e-020 ++alpha1 = 0 ++beta0 = 38.07575 ++lbeta0 = -2.59284e-006 ++wbeta0 = 1.0015544e-006 ++pbeta0 = -3.4314451e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33233495 ++lkt1 = 5.5962764e-010 ++wkt1 = 1.386661e-008 ++pkt1 = -6.438151e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.9998e-009 ++lua1 = -2.459016e-016 ++wua1 = -2.62395e-016 ++pua1 = 1.2909834e-022 ++ub1 = -2.8913745e-018 ++lub1 = -2.7023324e-026 ++wub1 = 2.6243509e-025 ++pub1 = -1.7956405e-031 ++uc1 = 5.1850909e-012 ++luc1 = -3.3340425e-017 ++wuc1 = -9.3985118e-017 ++puc1 = 3.3330844e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70966351 ++lvth0 = -3.6235097e-010 ++wvth0 = 2.163945e-009 ++pvth0 = 5.8422811e-015 ++k1 = 0.976722 ++lk1 = -2.4045024e-008 ++k2 = -0.026858767 ++lk2 = 1.2965043e-010 ++wk2 = 1.6041428e-009 ++pk2 = -6.4942458e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12347027 ++lvoff = 1.259976e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097676914 ++lu0 = 1.5273198e-009 ++wu0 = 3.1542e-011 ++pu0 = -3.0481466e-016 ++ua = 2.7535709e-010 ++lua = 5.6122091e-016 ++wua = 1.033809e-017 ++pua = -2.3800175e-023 ++ub = 1.2745688e-018 ++lub = -6.9209035e-026 ++wub = -2.9344612e-025 ++pub = -5.0610011e-032 ++uc = 8.8382089e-012 ++luc = 5.0666426e-017 ++wuc = -1.8753207e-017 ++puc = -3.9350342e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.3400455 ++la0 = -4.3229728e-007 ++wa0 = -6.1998457e-008 ++pa0 = 7.3902161e-014 ++ags = 0.19317874 ++lags = 7.4263098e-008 ++wags = 1.276002e-008 ++pags = -1.5209944e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0020187086 ++lketa = -2.8851515e-008 ++wketa = -3.980403e-009 ++pketa = 4.7446404e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.5521986 ++lpclm = -5.9115571e-008 ++wpclm = -6.8471025e-008 ++ppclm = 7.1739209e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024955823 ++lpdiblc2= 2.3979675e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00012240188 ++lalpha0 = -5.7254595e-011 ++walpha0 = -2.0047588e-011 ++palpha0 = 9.7320549e-018 ++alpha1 = 0 ++beta0 = 43.297479 ++lbeta0 = -5.1619305e-006 ++wbeta0 = -2.1374325e-007 ++pbeta0 = 2.5478195e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28407944 ++lkt1 = -2.3182084e-008 ++wkt1 = 1.2984037e-008 ++pkt1 = -6.0039252e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.139702e-018 ++lub1 = 9.5153784e-026 ++wub1 = 4.3643775e-025 ++pub1 = -2.6517336e-031 ++uc1 = -9.90552e-011 ++luc1 = 1.7945798e-017 ++wuc1 = 1.844262e-017 ++puc1 = -2.1983603e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70882353 ++lvth0 = -1.3636128e-009 ++wvth0 = 7.0547555e-009 ++pvth0 = 1.2434931e-017 ++k1 = 1.0137201 ++lk1 = -6.8146803e-008 ++k2 = -0.027400332 ++lk2 = 7.7519526e-010 ++wk2 = -6.5845334e-009 ++pk2 = 3.2666562e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095823899 ++lvoff = -2.0354712e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097356481 ++lu0 = 1.5655154e-009 ++wu0 = -2.950082e-010 ++pu0 = 8.4433178e-017 ++ua = 4.0386316e-010 ++lua = 4.0804167e-016 ++wua = -5.594653e-017 ++pua = 5.5211091e-023 ++ub = 1.1683671e-018 ++lub = 5.7383397e-026 ++wub = -2.7693216e-025 ++pub = -7.0294662e-032 ++uc = 1.3741189e-012 ++luc = 5.9563621e-017 ++wuc = -2.1977422e-017 ++puc = -9.1769787e-026 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1183126 ++la0 = -1.6799168e-007 ++wa0 = 7.2189361e-008 ++pa0 = -8.6049719e-014 ++ags = 0.16571096 ++lags = 1.0700469e-007 ++wags = -3.630332e-009 ++pags = 4.3273558e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068379523 ++lketa = -2.3106977e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.32898832 ++lpclm = 2.0695108e-007 ++wpclm = 1.1225287e-009 ++ppclm = -1.1216307e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8732382e-005 ++lpdiblc2= 4.4342116e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021722983 ++lalpha0 = -2.5007312e-009 ++walpha0 = -3.7927615e-011 ++palpha0 = 3.1045047e-017 ++alpha1 = 0 ++beta0 = 44.346784 ++lbeta0 = -6.4127021e-006 ++wbeta0 = 4.590075e-007 ++pbeta0 = -5.4713694e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9458182 ++lnoff = 5.4138473e-007 ++voffcv = 0.021672727 ++lvoffcv = -2.1655389e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33792326 ++lkt1 = 4.0999742e-008 ++wkt1 = 2.600496e-008 ++pkt1 = -2.1524865e-014 ++kt1l = 0 ++kt2 = -0.016960609 ++lkt2 = 4.642374e-009 ++wkt2 = 2.0446698e-009 ++pkt2 = -2.4372464e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5970921e-018 ++lub1 = -5.516372e-025 ++wub1 = -2.898414e-026 ++pub1 = 2.8960953e-031 ++uc1 = -4.2510491e-011 ++luc1 = -4.9455495e-017 ++wuc1 = -8.7628704e-018 ++puc1 = 1.0445342e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70896 ++wvth0 = 7.056e-009 ++k1 = 1.0069 ++k2 = -0.02732275 ++wk2 = -6.2576062e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.009892325 ++wu0 = -2.8655813e-010 ++ua = 4.447e-010 ++wua = -5.0421e-017 ++ub = 1.17411e-018 ++wub = -2.8396725e-025 ++uc = 7.33525e-012 ++wuc = -2.1986606e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1015 ++wa0 = 6.35775e-008 ++ags = 0.17642 ++wags = -3.19725e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.001922025 ++walpha0 = -3.4820625e-011 ++alpha1 = 0 ++beta0 = 43.705 ++wbeta0 = 4.0425e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33382 ++wkt1 = 2.385075e-008 ++kt1l = 0 ++kt2 = -0.016496 ++wkt2 = 1.80075e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.746e-011 ++wuc1 = -7.7175e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69776909 ++lvth0 = -8.3892994e-009 ++wvth0 = 4.6843987e-009 ++pvth0 = 7.26646e-015 ++k1 = 0.99667836 ++lk1 = -3.3863555e-008 ++k2 = -0.0016908531 ++lk2 = -1.6910112e-008 ++wk2 = 4.4324937e-009 ++pk2 = -2.1807869e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011456358 ++lu0 = 1.7102254e-009 ++wu0 = -2.8204333e-009 ++pu0 = -1.4346165e-016 ++ua = 3.841223e-010 ++lua = 6.0284809e-016 ++wua = -4.7506228e-016 ++pua = 9.847072e-023 ++ub = 9.2943227e-019 ++lub = 3.159209e-026 ++wub = 4.1922273e-025 ++pub = -3.167107e-031 ++uc = 1.3336117e-010 ++luc = -7.1184051e-018 ++wuc = -7.0026382e-017 ++puc = 1.7027795e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.87958485 ++la0 = -1.4075717e-007 ++wa0 = -7.0611818e-008 ++pa0 = -1.4770608e-015 ++ags = 0.33412256 ++lags = -2.3726975e-009 ++wags = -1.8394245e-007 ++pags = 9.0499685e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.087907195 ++lketa = 1.6887989e-008 ++wketa = -6.7255452e-009 ++pketa = 1.8293483e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32767553 ++lpclm = 4.8328885e-008 ++wpclm = 8.3378086e-008 ++ppclm = 7.3004154e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.5916748e-006 ++lalpha0 = -2.1820478e-012 ++walpha0 = 2.4265399e-012 ++palpha0 = -7.9837683e-019 ++alpha1 = 0 ++beta0 = 37.669715 ++lbeta0 = -2.2686901e-006 ++wbeta0 = 1.4989467e-006 ++pbeta0 = -7.4022817e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29643476 ++lkt1 = -8.0291808e-009 ++wkt1 = -3.0111128e-008 ++pkt1 = 4.0831393e-015 ++kt1l = 0 ++kt2 = -0.020721765 ++lkt2 = 2.0823681e-009 ++wkt2 = 9.3783124e-009 ++pkt2 = -2.550901e-015 ++ute = -1 ++ua1 = 1.8027834e-009 ++lua1 = -1.4896941e-016 ++wua1 = -2.10496e-017 ++pua1 = 1.0356403e-023 ++ub1 = -2.5917035e-018 ++lub1 = -1.2288098e-025 ++wub1 = -1.0466188e-025 ++pub1 = -6.213842e-032 ++uc1 = -8.5734843e-011 ++luc1 = 8.5354274e-019 ++wuc1 = 1.7391801e-017 ++puc1 = -8.556766e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7006151 ++lvth0 = -6.989061e-009 ++wvth0 = -8.9203589e-009 ++pvth0 = 1.3960001e-014 ++k1 = 0.976722 ++lk1 = -2.4045024e-008 ++k2 = -0.03059107 ++lk2 = -2.6912057e-009 ++wk2 = 6.1762134e-009 ++pk2 = -3.038697e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094296073 ++lvoff = -1.7539439e-009 ++wvoff = -3.5738389e-008 ++pvoff = 1.7583287e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010159235 ++lu0 = 2.3484099e-009 ++wu0 = -4.4809927e-010 ++pu0 = -1.31065e-015 ++ua = 3.3440437e-010 ++lua = 6.2730931e-016 ++wua = -6.1994828e-017 ++pua = -1.0475847e-022 ++ub = 9.623728e-019 ++lub = 1.538535e-026 ++wub = 8.8993941e-026 ++pub = -1.5423813e-031 ++uc = -2.6791447e-011 ++luc = 7.1676685e-017 ++wuc = 2.4893122e-017 ++puc = -2.9672601e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1742768 ++la0 = -2.8574559e-007 ++wa0 = 1.4106826e-007 ++pa0 = -1.0562366e-013 ++ags = 0.20869703 ++lags = 5.9336662e-008 ++wags = -6.2498812e-009 ++pags = 3.0749415e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0069935214 ++lketa = -2.2921538e-008 ++wketa = 2.1137428e-009 ++pketa = -2.5195814e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37804632 ++lpclm = 2.3546458e-008 ++wpclm = 1.4486552e-007 ++ppclm = -2.9521777e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024955823 ++lpdiblc2= 2.3979675e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011037751 ++lalpha0 = -5.1768678e-011 ++walpha0 = -5.3177339e-012 ++palpha0 = 3.0118059e-018 ++alpha1 = 0 ++beta0 = 43.119792 ++lbeta0 = -4.9501275e-006 ++wbeta0 = 3.9234204e-009 ++pbeta0 = -4.6767172e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3027753 ++lkt1 = -4.9096367e-009 ++wkt1 = 3.5886458e-008 ++pkt1 = -2.8387673e-014 ++kt1l = 0 ++kt2 = -0.010659902 ++lkt2 = -2.8680684e-009 ++wkt2 = -2.9474696e-009 ++pkt2 = 3.5133838e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4641385e-018 ++lub1 = -1.8564299e-025 ++wub1 = -3.9112754e-025 ++pub1 = 7.8802685e-032 ++uc1 = -3.5114455e-011 ++luc1 = -2.4051688e-017 ++wuc1 = -5.9884793e-017 ++puc1 = 2.9463318e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70275593 ++lvth0 = -4.4372015e-009 ++wvth0 = -3.7806056e-010 ++pvth0 = 3.7775811e-015 ++k1 = 1.0137201 ++lk1 = -6.8146803e-008 ++k2 = -0.03602212 ++lk2 = 3.7826066e-009 ++wk2 = 3.9771578e-009 ++pk2 = -4.1742272e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098144574 ++lvoff = 2.8334685e-009 ++wvoff = 2.8428264e-009 ++pvoff = -2.8405521e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011033204 ++lu0 = 1.306639e-009 ++wu0 = -1.8845144e-009 ++pu0 = 4.0155688e-016 ++ua = 6.6792168e-010 ++lua = 2.2975668e-016 ++wua = -3.7941821e-016 ++pua = 2.736102e-022 ++ub = 9.7527997e-019 ++wub = -4.0400465e-026 ++uc = -1.6566634e-011 ++luc = 5.9488707e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1830432 ++la0 = -2.9619524e-007 ++wa0 = -7.1056483e-009 ++pa0 = 7.0999638e-014 ++ags = 0.16693357 ++lags = 1.0911871e-007 ++wags = -5.1280236e-009 ++pags = 1.7376873e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068379523 ++lketa = -2.3106977e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34318463 ++lpclm = 6.510159e-008 ++wpclm = -1.6267946e-008 ++ppclm = 1.6254932e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8732382e-005 ++lpdiblc2= 4.4342116e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021410284 ++lalpha0 = -2.4723045e-009 ++walpha0 = 3.7806056e-013 ++palpha0 = -3.7775811e-018 ++alpha1 = 0 ++beta0 = 44.157511 ++lbeta0 = -6.1870892e-006 ++wbeta0 = 6.9086635e-007 ++pbeta0 = -8.2351269e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9458182 ++lnoff = 5.4138473e-007 ++voffcv = 0.021672727 ++lvoffcv = -2.1655389e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29670745 ++lkt1 = -1.2142514e-008 ++wkt1 = -2.4484407e-008 ++pkt1 = 4.3574398e-014 ++kt1l = 0 ++kt2 = -0.012756202 ++lkt2 = -3.6927975e-010 ++wkt2 = -3.1057295e-009 ++pkt2 = 3.7020295e-015 ++ute = -1 ++ua1 = 1.3960014e-009 ++lua1 = 1.2396634e-016 ++wua1 = 1.2739829e-016 ++pua1 = -1.5185876e-022 ++ub1 = -2.6566915e-018 ++lub1 = 4.3880232e-026 ++wub1 = 4.4025153e-026 ++pub1 = -4.3989932e-031 ++uc1 = -6.6591108e-011 ++luc1 = 1.3468483e-017 ++wuc1 = 2.0735886e-017 ++puc1 = -6.6636531e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7032 ++k1 = 1.0069 ++k2 = -0.035643557 ++wk2 = 3.9353821e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011163973 ++wu0 = -1.8443266e-009 ++ua = 6.9091574e-010 ++wua = -3.5203528e-016 ++ub = 9.7527997e-019 ++wub = -4.0400465e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17785418 ++wags = -4.9541158e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.538307 ++wbeta0 = 6.0844915e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29792267 ++wkt1 = -2.0123479e-008 ++kt1l = 0 ++kt2 = -0.012793159 ++wkt2 = -2.7352301e-009 ++ute = -1 ++ua1 = 1.4084079e-009 ++wua1 = 1.1220026e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5243182e-011 ++wuc1 = 1.4066898e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.69730182 ++lvth0 = -7.6644654e-009 ++k1 = 0.99667836 ++lk1 = -3.3863555e-008 ++k2 = -0.0012487091 ++lk2 = -1.7127647e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011175018 ++lu0 = 1.695915e-009 ++ua = 3.3673455e-010 ++lua = 6.126706e-016 ++ub = 9.7125e-019 ++uc = 1.26376e-010 ++luc = -5.419872e-018 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.87254127 ++la0 = -1.4090451e-007 ++ags = 0.31577418 ++lags = 6.6547025e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.088578073 ++lketa = 1.7070468e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.33599254 ++lpclm = 4.8401708e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.8337236e-006 ++lalpha0 = -2.2616864e-012 ++alpha1 = 0 ++beta0 = 37.819236 ++lbeta0 = -2.3425283e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29943836 ++lkt1 = -7.6218851e-009 ++kt1l = 0 ++kt2 = -0.019786273 ++lkt2 = 1.8279142e-009 ++ute = -1 ++ua1 = 1.8006836e-009 ++lua1 = -1.4793635e-016 ++ub1 = -2.6021436e-018 ++lub1 = -1.2907933e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70150491 ++lvth0 = -5.5965422e-009 ++k1 = 0.976722 ++lk1 = -2.4045024e-008 ++k2 = -0.029974989 ++lk2 = -2.9943176e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010114537 ++lu0 = 2.2176717e-009 ++ua = 3.2822034e-010 ++lua = 6.1685959e-016 ++ub = 9.7125e-019 ++uc = -2.4308343e-011 ++luc = 6.8716825e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1883484 ++la0 = -2.9628161e-007 ++ags = 0.2080736 ++lags = 5.9643389e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0067826743 ++lketa = -2.3172868e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39249674 ++lpclm = 2.0601642e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024955823 ++lpdiblc2= 2.3979675e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00010984706 ++lalpha0 = -5.1468248e-011 ++alpha1 = 0 ++beta0 = 43.120183 ++lbeta0 = -4.950594e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.2991956 ++lkt1 = -7.7413248e-009 ++kt1l = 0 ++kt2 = -0.010953914 ++lkt2 = -2.5176062e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5031537e-018 ++lub1 = -1.7778237e-025 ++uc1 = -4.1088e-011 ++luc1 = -2.1112704e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.70279364 ++lvth0 = -4.0603855e-009 ++k1 = 1.0137201 ++lk1 = -6.8146803e-008 ++k2 = -0.035625396 ++lk2 = 3.7409685e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010845223 ++lu0 = 1.3466945e-009 ++ua = 6.3007447e-010 ++lua = 2.5704947e-016 ++ub = 9.7125e-019 ++uc = -1.6566634e-011 ++luc = 5.9488707e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1823344 ++la0 = -2.8911298e-007 ++ags = 0.16642204 ++lags = 1.0929204e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068379523 ++lketa = -2.3106977e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34156189 ++lpclm = 8.1315986e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8732382e-005 ++lpdiblc2= 4.4342116e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021410661 ++lalpha0 = -2.4726813e-009 ++alpha1 = 0 ++beta0 = 44.226425 ++lbeta0 = -6.2692351e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9458182 ++lnoff = 5.4138473e-007 ++voffcv = 0.021672727 ++lvoffcv = -2.1655389e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29914978 ++lkt1 = -7.7959401e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4087095e-009 ++lua1 = 1.0881833e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.4522691e-011 ++luc1 = 6.8214476e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = 7.7e-009 ++toxp = 7.7e-009 ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = -8e-009 ++xw = 5e-009 ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = -0.7032 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = 1e-007 ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = 466 ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.178e-010 ++cgdo = 1.178e-010 ++cgbo = 1e-013 ++cgdl = 3.8e-011 ++cgsl = 3.8e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=150 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + + + +.endl pmos_3p3_sf +* +* +*************************************************************************************************** +* 6V NMOS Models +*************************************************************************************************** +* +.lib nmos_6p0_t + + +.subckt nmos_6p0_sab d g s b w=10u l=0.6u par=1 s_sab=0.28u d_sab=3.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.01155 ++ par_k=0.0000 ++ par_l=4e-7 ++ par_w=-5e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b nplus_u_m2 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m2 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_6p0 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=0 sb=0 sd=0 ++delvto='mis_vth*sw_stat_mismatch' +.ends + + + + + +.model nmos_6p0.0 nmos level = 54 ++lmin = 7e-007 lmax = 5.0001e-005 wmin = 3e-007 wmax = 0.000100001 ++version = 4.5 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 0 igbmod = 0 geomod = 0 ++diomod = 1 rdsmod = 0 rbodymod= 0 rgeomod = 0 ++rgatemod= 0 permod = 1 acnqsmod= 0 trnqsmod= 0 ++tempmod = 0 wpemod = 0 ++tnom = 25 toxe = '1.52e-008+nmos_6p0_tox' toxp = '1.6e-008+nmos_6p0_tox' toxm = '1.52e-008+nmos_6p0_tox' ++epsrox = 3.9 toxref = 1.52e-008 wint = 1.55e-008 lint = -3e-008 ++ll = 1.93e-014 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = -2.7e-015 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 llc = 0 wlc = 0 ++lwc = 0 wwc = 0 lwlc = 0 wwlc = 0 ++xl = '0+nmos_6p0_xl' xw = '0+nmos_6p0_xw' dlc = 5.4E-8 dwc = 0 ++dlcig = 0 xpart = 0 ++vth0 = '0.67314+nmos_6p0_vth0' k1 = 0.9 k2 = -0.001 k3 = -1.1369995 ++wk3 = -0.047531062 k3b = 0.86 w0 = 1e-009 dvt0 = 5.72 ++dvt1 = 0.299 dvt2 = -0.0793 dvt0w = 10 dvt1w = 976700 ++dvt2w = 0.15 dsub = 0.4 minv = 0 voffl = 0 ++dvtp0 = 0 dvtp1 = 0 lambda = 0 vtl = 200000 ++xn = 3 lpe0 = 1.63e-007 lpeb = 0 vbm = -3 ++xj = 1.5e-007 ngate = 1e+020 ndep = 1.7e+017 nsd = 1e+020 ++phin = 0 cdsc = 0.00024 ud1 = 0 up = 0 ++lp = 1e-008 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.08 nfactor = 0.864 eta0 = 0 etab = -0.43 ++u0 = 0.052500014 lu0 = 0.019999998 wu0 = -8.0300635e-009 pu0 = 0.0018000065 ++ua = 6.8000001e-012 lua = -3.3696895e-019 wua = -8.4912706e-019 pua = 1.4622721e-010 ++ub = 2.8799997e-018 lub = 1.7400001e-018 wub = -1.1655759e-026 pub = -2.3803999e-019 ++uc = 7.9399996e-011 luc = 9.8000018e-011 wuc = 8.0000028e-012 puc = -5.6168065e-012 ++eu = 1.67 vsat = '103999.98*nmos_6p0_vsat' lvsat = '-2649.9871*nmos_6p0_vsat' wvsat = '0.012447116*nmos_6p0_vsat' ++pvsat = '6308.7992*nmos_6p0_vsat' a0 = 0.72499969 la0 = 0.40144032 ags = 0.13699995 ++lags = -0.068999933 wags = -4.2211594e-008 pags = 0.0070910278 a1 = 0 ++a2 = 0.96 b0 = 0 b1 = 0 keta = -0.021200021 ++lketa = 0.04140001 dwg = -6e-010 dwb = 6e-009 pclm = 0.0099999763 ++lpclm = 0.89088024 pdiblc1 = 1.6 pdiblc2 = 0.0022 pdiblcb = 0 ++drout = 0.4 pvag = 1.75 delta = 0.01 pscbe1 = 4.325e+009 ++pscbe2 = 8.8e-006 fprout = 0 pdits = 0 pditsd = 0 ++pditsl = 0 rsh = 7 rdsw = 2175 rsw = 100 ++rdw = 100 rdswmin = 0 rdwmin = 0 rswmin = 0 ++prwg = 1 prwb = 0 wr = 1 alpha0 = -1.88e-007 ++alpha1 = 19 beta0 = 36.6 agidl = 0 bgidl = 2.3e+009 ++cgidl = 0.5 egidl = 0.8 aigbacc = 0.43 bigbacc = 0.054 ++cigbacc = 0.075 nigbacc = 1 aigbinv = 0.35 bigbinv = 0.03 ++cigbinv = 0.006 eigbinv = 1.1 nigbinv = 3 aigc = 0.43 ++bigc = 0.054 cigc = 0.075 aigsd = 0.43 bigsd = 0.054 ++cigsd = 0.075 nigc = 1 poxedge = 1 pigcd = 1 ++ntox = 1 vfbsdoff= 0 ++cgso = '1e-010*nmos_6p0_cgso' cgdo = '1e-010*nmos_6p0_cgdo' cgbo = 1e-013 cgdl = '1.5e-010*nmos_6p0_cgdo' ++cgsl = '1.5e-010*nmos_6p0_cgso' clc = 1e-010 cle = 0.6 ckappas = 0.6 ++ckappad = 0.6 vfbcv = -1 acde = 0.3 moin = 15 ++noff = 1.5 voffcv = 0 ++tvoff = 0 tvfbsdoff= 0 kt1 = -0.412 kt1l = 3.5e-008 ++kt2 = -0.05 ute = -1.5000005 lute = 0.030000222 wute = 0.06000001 ++pute = -0.019999981 ua1 = 1e-009 ub1 = -1e-018 uc1 = -5.5999995e-011 ++luc1 = -1.8816003e-011 prt = 0 at = 109000.03 lat = -75600.021 ++wat = 6479.9797 pat = -6699.9857 ++fnoimod = 1 tnoimod = 0 em = 4.1e+007 ef = 1 ++noia = 'nmos_6p0_noia' noib = 'nmos_6p0_noib' noic = 'nmos_6p0_noic' ntnoi = 1 ++lintnoi = 0 ++jss = 6.88e-007 jsws = 4.88e-013 jswgs = 0 njs = 1.0541 ++ijthsfwd= 0.1 ijthsrev= 0.1 bvs = 11 xjbvs = 1 ++xjbvd = 1 jtss = 0 jtsd = 0 jtssws = 0 ++jtsswd = 0 jtsswgs = 0 jtsswgd = 0 njts = 20 ++njtssw = 20 njtsswg = 20 xtss = 0.02 xtsd = 0.02 ++xtssws = 0.02 xtsswd = 0.02 xtsswgs = 0.02 xtsswgd = 0.02 ++tnjts = 0 tnjtssw = 0 tnjtsswg= 0 vtss = 10 ++vtsd = 10 vtssws = 10 vtsswd = 10 vtsswgs = 10 ++vtsswgd = 10 pbs = 0.606 cjs = 0.00095 mjs = 0.296 ++pbsws = 0.48 cjsws = 1.33e-010 mjsws = 0.01 pbswgs = 0.861 ++cjswgs = 3.573e-010 mjswgs = 0.40313 tpb = 0.00146 tcj = 0.000825 ++tpbsw = 0.00313 tcjsw = 0.0018 tpbswg = 0.0016588 tcjswg = 0.001595 ++xtis = 3 ++dmcg = 0 dmdg = 0 dmcgt = 0 xgw = 0 ++xgl = 0 ++rshg = 0.1 gbmin = 1e-012 rbpb = 50 rbpd = 50 ++rbps = 50 rbdb = 50 rbsb = 50 ngcon = 1 ++xrcrg1 = 12 xrcrg2 = 1 rbps0 = 50 rbpsl = 0 ++rbpsw = 0 rbpsnf = 0 rbpd0 = 50 rbpdl = 0 ++rbpdw = 0 rbpdnf = 0 rbpbx0 = 100 rbpbxl = 0 ++rbpbxw = 0 rbpbxnf = 0 rbpby0 = 100 rbpbyl = 0 ++rbpbyw = 0 rbpbynf = 0 rbsbx0 = 100 rbsby0 = 100 ++rbdbx0 = 100 rbdby0 = 100 rbsdbxl = 0 rbsdbxw = 0 ++rbsdbxnf= 0 rbsdbyl = 0 rbsdbyw = 0 rbsdbynf= 0 ++web = 0 wec = 0 scref = 1e-006 kvth0we = 0 ++k2we = 0 ku0we = 0 saref = 1e-006 sbref = 1e-006 ++wlod = 0 kvth0 = 0 lkvth0 = 0 wkvth0 = 0 ++pkvth0 = 0 llodvth = 0 wlodvth = 0 stk2 = 0 ++lodk2 = 1 lodeta0 = 1 ku0 = 0 lku0 = 0 ++wku0 = 0 pku0 = 0 llodku0 = 0 wlodku0 = 0 ++kvsat = 0 steta0 = 0 tku0 = 0 + +.model nmos_6p0.1 nmos level = 54 ++lmin = 6e-007 lmax = 7e-007 wmin = 3e-007 wmax = 0.000100001 ++version = 4.5 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 0 igbmod = 0 geomod = 0 ++diomod = 1 rdsmod = 0 rbodymod= 0 rgeomod = 0 ++rgatemod= 0 permod = 1 acnqsmod= 0 trnqsmod= 0 ++tempmod = 0 wpemod = 0 ++tnom = 25 toxe = '1.52e-008+nmos_6p0_tox' toxp = '1.6e-008+nmos_6p0_tox' toxm = '1.52e-008+nmos_6p0_tox' ++epsrox = 3.9 toxref = 1.52e-008 wint = 1.55e-008 lint = -3e-008 ++ll = 1.93e-014 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = -2.7e-015 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 llc = 0 wlc = 0 ++lwc = 0 wwc = 0 lwlc = 0 wwlc = 0 ++xl = '0+nmos_6p0_xl' xw = '0+nmos_6p0_xw' dlc = 5.4E-8 dwc = 0 ++dlcig = 0 xpart = 0 ++vth0 = '0.67314+nmos_6p0_vth0' k1 = 0.9 k2 = -0.001 k3 = -1.1369995 ++wk3 = -0.047531062 k3b = 0.86 w0 = 1e-009 dvt0 = 5.72 ++dvt1 = 0.299 dvt2 = -0.0793 dvt0w = 10 dvt1w = 976700 ++dvt2w = 0.15 dsub = 0.4 minv = 0 voffl = 0 ++dvtp0 = 0 dvtp1 = 0 lambda = 0 vtl = 200000 ++xn = 3 lpe0 = 1.63e-007 lpeb = 0 vbm = -3 ++xj = 1.5e-007 ngate = 1e+020 ndep = 1.7e+017 nsd = 1e+020 ++phin = 0 cdsc = 0.00024 ud1 = 0 up = 0 ++lp = 1e-008 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.08 nfactor = 0.864 eta0 = 0 etab = -0.43 ++u0 = 0.052500361 lu0 = 0.019999754 wu0 = -2.8167565e-008 pu0 = 0.0018000207 ++ua = 6.7999991e-012 lua = 3.7339196e-019 wua = 1.3244868e-016 pua = 1.4622711e-010 ++ub = 2.8800011e-018 lub = 1.7399991e-018 wub = 1.8765824e-025 pub = -2.3804013e-019 ++uc = 7.9400388e-011 luc = 9.7999741e-011 wuc = 7.9999428e-012 puc = -5.6167642e-012 ++eu = 1.67 vsat = '64848.09*nmos_6p0_vsat' lvsat = '24946.5*nmos_6p0_vsat' wvsat = '0.14568305*nmos_6p0_vsat' ++pvsat = '6308.7053*nmos_6p0_vsat' a0 = 0.72500081 la0 = 0.40143954 ags = 0.13700019 ++lags = -0.069000099 wags = 5.7853969e-008 pags = 0.0070909573 a1 = 0 ++a2 = 0.96 b0 = 0 b1 = 0 keta = -0.021200265 ++lketa = 0.041400183 dwg = -6e-010 dwb = 6e-009 pclm = 0.0099996572 ++lpclm = 0.89088046 pdiblc1 = 1.6 pdiblc2 = 0.0022 pdiblcb = 0 ++drout = 0.4 pvag = 1.75 delta = 0.01 pscbe1 = 4.325e+009 ++pscbe2 = 8.8e-006 fprout = 0 pdits = 0 pditsd = 0 ++pditsl = 0 rsh = 7 rdsw = 2175 rsw = 100 ++rdw = 100 rdswmin = 0 rdwmin = 0 rswmin = 0 ++prwg = 1 prwb = 0 wr = 1 alpha0 = -1.88e-007 ++alpha1 = 19 beta0 = 36.6 agidl = 0 bgidl = 2.3e+009 ++cgidl = 0.5 egidl = 0.8 aigbacc = 0.43 bigbacc = 0.054 ++cigbacc = 0.075 nigbacc = 1 aigbinv = 0.35 bigbinv = 0.03 ++cigbinv = 0.006 eigbinv = 1.1 nigbinv = 3 aigc = 0.43 ++bigc = 0.054 cigc = 0.075 aigsd = 0.43 bigsd = 0.054 ++cigsd = 0.075 nigc = 1 poxedge = 1 pigcd = 1 ++ntox = 1 vfbsdoff= 0 ++cgso = '1e-010*nmos_6p0_cgso' cgdo = '1e-010*nmos_6p0_cgdo' cgbo = 1e-013 cgdl = '1.5e-010*nmos_6p0_cgdo' ++cgsl = '1.5e-010*nmos_6p0_cgso' clc = 1e-010 cle = 0.6 ckappas = 0.6 ++ckappad = 0.6 vfbcv = -1 acde = 0.3 moin = 15 ++noff = 1.5 voffcv = 0 ++tvoff = 0 tvfbsdoff= 0 kt1 = -0.412 kt1l = 3.5e-008 ++kt2 = -0.05 ute = -1.5000008 lute = 0.030000412 wute = 0.060000189 ++pute = -0.020000108 ua1 = 1e-009 ub1 = -1e-018 uc1 = -5.5999975e-011 ++luc1 = -1.8816017e-011 prt = 0 at = -119957.68 lat = 85782.454 ++wat = -33999.727 pat = 21832.424 ++fnoimod = 1 tnoimod = 0 em = 4.1e+007 ef = 1 ++noia = 'nmos_6p0_noia' noib = 'nmos_6p0_noib' noic = 'nmos_6p0_noic' ntnoi = 1 ++lintnoi = 0 ++jss = 6.88e-007 jsws = 4.88e-013 jswgs = 0 njs = 1.0541 ++ijthsfwd= 0.1 ijthsrev= 0.1 bvs = 11 xjbvs = 1 ++xjbvd = 1 jtss = 0 jtsd = 0 jtssws = 0 ++jtsswd = 0 jtsswgs = 0 jtsswgd = 0 njts = 20 ++njtssw = 20 njtsswg = 20 xtss = 0.02 xtsd = 0.02 ++xtssws = 0.02 xtsswd = 0.02 xtsswgs = 0.02 xtsswgd = 0.02 ++tnjts = 0 tnjtssw = 0 tnjtsswg= 0 vtss = 10 ++vtsd = 10 vtssws = 10 vtsswd = 10 vtsswgs = 10 ++vtsswgd = 10 pbs = 0.606 cjs = 0.00095 mjs = 0.296 ++pbsws = 0.48 cjsws = 1.33e-010 mjsws = 0.01 pbswgs = 0.861 ++cjswgs = 3.573e-010 mjswgs = 0.40313 tpb = 0.00146 tcj = 0.000825 ++tpbsw = 0.00313 tcjsw = 0.0018 tpbswg = 0.0016588 tcjswg = 0.001595 ++xtis = 3 ++dmcg = 0 dmdg = 0 dmcgt = 0 xgw = 0 ++xgl = 0 ++rshg = 0.1 gbmin = 1e-012 rbpb = 50 rbpd = 50 ++rbps = 50 rbdb = 50 rbsb = 50 ngcon = 1 ++xrcrg1 = 12 xrcrg2 = 1 rbps0 = 50 rbpsl = 0 ++rbpsw = 0 rbpsnf = 0 rbpd0 = 50 rbpdl = 0 ++rbpdw = 0 rbpdnf = 0 rbpbx0 = 100 rbpbxl = 0 ++rbpbxw = 0 rbpbxnf = 0 rbpby0 = 100 rbpbyl = 0 ++rbpbyw = 0 rbpbynf = 0 rbsbx0 = 100 rbsby0 = 100 ++rbdbx0 = 100 rbdby0 = 100 rbsdbxl = 0 rbsdbxw = 0 ++rbsdbxnf= 0 rbsdbyl = 0 rbsdbyw = 0 rbsdbynf= 0 ++web = 0 wec = 0 scref = 1e-006 kvth0we = 0 ++k2we = 0 ku0we = 0 saref = 1e-006 sbref = 1e-006 ++wlod = 0 kvth0 = 0 lkvth0 = 0 wkvth0 = 0 ++pkvth0 = 0 llodvth = 0 wlodvth = 0 stk2 = 0 ++lodk2 = 1 lodeta0 = 1 ku0 = 0 lku0 = 0 ++wku0 = 0 pku0 = 0 llodku0 = 0 wlodku0 = 0 ++kvsat = 0 steta0 = 0 tku0 = 0 + + +*resistor +.subckt nplus_u_m2 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m2 + +.endl nmos_6p0_t +* +*************************************************************************************************** +* 6V native NMOS Models +*************************************************************************************************** +* +.lib nmos_6p0_nat_t +.subckt nmos_6p0_nat d g s b w=1e-5 l=1.8e-6 as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 sa=0 sb=0 nf=1 sd=0 m=1 + +m0 d g s b nmos_6p0_nat w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs sa=sa sb=sb nf=nf sd=sd + +.ends nmos_6p0_nat + +.model nmos_6p0_nat.0 nmos ++level = 54 +************************************************************** +* MODEL FLAG PARAMETERS +************************************************************** ++lmin = 1.8e-6 lmax = 50.01e-6 wmin = 0.8e-6 ++wmax = 100.01e-6 version = 4.6 binunit = 1 ++paramchk= 1 mobmod = 0 capmod = 2 ++igcmod = 0 igbmod = 0 geomod = 0 ++diomod = 1 rdsmod = 0 rbodymod= 0 ++rgeomod = 0 rgatemod= 0 permod = 1 ++acnqsmod= 0 trnqsmod= 0 tempmod = 0 ++wpemod = 0 +************************************************************** +* GENERAL MODEL PARAMETERS +************************************************************** ++tnom = 25 toxe = nmos_6p0_nat_tox toxp = 1.6e-008 ++toxm = 1.52e-008 epsrox = 3.9 toxref = 1.52e-008 ++wint = 1e-009 lint = 1e-007 ll = 0 ++wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 ++wwn = 1 lwl = 0 wwl = 0 ++llc = 0 wlc = 0 lwc = 0 ++wwc = 0 lwlc = 0 wwlc = 0 ++xl = nmos_6p0_nat_xl xw = nmos_6p0_nat_xw dlc = 0 ++dwc = 0 dlcig = 0 xpart = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++vth0 = nmos_6p0_nat_vth0 lvth0 = -0.088 k1 = 0.165 ++k2 = -0.001 k3 = -0.6 k3b = -0.6 ++w0 = 1e-010 dvt0 = 2.2 dvt1 = 0.53 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 5300000 ++dvt2w = -0.032 dsub = 0.4 minv = -0.5 ++voffl = 0 dvtp0 = 1e-008 dvtp1 = 0 ++lambda = 0 vtl = 200000 xn = 3 ++lpe0 = 1e-007 lpeb = 0 vbm = -3 ++xj = 1.5e-007 ngate = 1e+020 ndep = 1.7e+017 ++nsd = 1e+020 phin = 0.5 cdsc = 0.00024 ++cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.06 ud1 = 0 up = 0 ++lp = 1e-008 nfactor = 0.40241 lnfactor= 0.45 ++eta0 = 0.06 etab = -0.43 u0 = nmos_6p0_nat_u0 ++lu0 = 0.042 ua = 2.278e-009 ub = 3.97e-019 ++lub = 3.65e-018 uc = 2.625e-012 eu = 1.67 ++vsat = 106700 pvsat = 23500 a0 = 0.88 ++ags = 0.72 a1 = 0 a2 = 0.47 ++b0 = 3.5e-007 b1 = 0 keta = -0.04 ++dwg = 0 dwb = 0 pclm = 3 ++pdiblc1 = 1.41 pdiblc2 = 1e-005 pdiblcb = 0 ++drout = 0.16 pvag = 1 delta = 0.005 ++pscbe1 = 5e+009 pscbe2 = 5e-006 fprout = 65 ++pdits = 0 pditsd = 0 pditsl = 0 ++rsh = 7 rdsw = 3480 rsw = 100 ++rdw = 100 rdswmin = 0 rdwmin = 0 ++rswmin = 0 prwg = 1 prwb = 0 ++wr = 1 alpha0 = 1.36e-008 alpha1 = 1e-005 ++beta0 = 15 agidl = 2e-010 bgidl = 2.3e+009 ++cgidl = 0.5 egidl = 0.8 aigbacc = 0.43 ++bigbacc = 0.054 cigbacc = 0.075 nigbacc = 1 ++aigbinv = 0.35 bigbinv = 0.03 cigbinv = 0.006 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.43 ++bigc = 0.054 cigc = 0.075 aigsd = 0.43 ++bigsd = 0.054 cigsd = 0.075 nigc = 1 ++poxedge = 1 pigcd = 1 ntox = 1 ++vfbsdoff= 0 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cgso = nmos_6p0_nat_cgso cgdo = nmos_6p0_nat_cgdo cgbo = 1e-013 ++cgdl = 1.5e-010 cgsl = 1.5e-010 clc = 1e-010 ++cle = 0.6 ckappas = 0.6 ckappad = 0.6 ++vfbcv = -1 acde = 0.3 moin = 15 ++noff = 1.5 voffcv = 0 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++tvoff = 0 tvfbsdoff= 0 kt1 = -0.412 ++kt1l = 3.5e-008 kt2 = -0.05 ute = -1.5 ++lute = -0.26 ua1 = 1e-009 ub1 = -1e-018 ++uc1 = -5.6e-011 prt = 0 at = 80000 ++lat = -30000 pat = -10000 +************************************************************** +* NOISE PARAMETERS +************************************************************** ++fnoimod = 1 tnoimod = 0 em = 4.1e+007 ++ef = 1 noia = 'nmos_6p0_nat_noia' noib = 'nmos_6p0_nat_noib' ++noic = 'nmos_6p0_nat_noic' ntnoi = 1 lintnoi = 0 +************************************************************** +* DIODE PARAMETERS +************************************************************** ++jss = 6.88e-007 jsws = 4.88e-013 jswgs = 0 ++njs = 1.0541 ijthsfwd= 0.1 ijthsrev= 0.1 ++bvs = 11 xjbvs = 1 xjbvd = 1 ++jtss = 0 jtsd = 0 jtssws = 0 ++jtsswd = 0 jtsswgs = 0 jtsswgd = 0 ++njts = 20 njtssw = 20 njtsswg = 20 ++xtss = 0.02 xtsd = 0.02 xtssws = 0.02 ++xtsswd = 0.02 xtsswgs = 0.02 xtsswgd = 0.02 ++tnjts = 0 tnjtssw = 0 tnjtsswg= 0 ++vtss = 10 vtsd = 10 vtssws = 10 ++vtsswd = 10 vtsswgs = 10 vtsswgd = 10 ++pbs = 0.606 cjs = 0.00095 mjs = 0.296 ++pbsws = 0.48 cjsws = 1.33e-010 mjsws = 0.01 ++pbswgs = 0.861 cjswgs = 3.573e-010 mjswgs = 0.40313 ++tpb = 0.00146 tcj = 0.000825 tpbsw = 0.00313 ++tcjsw = 0.0018 tpbswg = 0.0016588 tcjswg = 0.001595 ++xtis = 3 +************************************************************** +* LAYOUT RELATED PARAMETERS +************************************************************** ++dmcg = 0 dmdg = 0 dmcgt = 0 ++xgw = 0 xgl = 0 +************************************************************** +* RF PARAMETERS +************************************************************** ++rshg = 0.1 gbmin = 1e-012 rbpb = 50 ++rbpd = 50 rbps = 50 rbdb = 50 ++rbsb = 50 ngcon = 1 xrcrg1 = 12 ++xrcrg2 = 1 rbps0 = 50 rbpsl = 0 ++rbpsw = 0 rbpsnf = 0 rbpd0 = 50 ++rbpdl = 0 rbpdw = 0 rbpdnf = 0 ++rbpbx0 = 100 rbpbxl = 0 rbpbxw = 0 ++rbpbxnf = 0 rbpby0 = 100 rbpbyl = 0 ++rbpbyw = 0 rbpbynf = 0 rbsbx0 = 100 ++rbsby0 = 100 rbdbx0 = 100 rbdby0 = 100 ++rbsdbxl = 0 rbsdbxw = 0 rbsdbxnf= 0 ++rbsdbyl = 0 rbsdbyw = 0 rbsdbynf= 0 +************************************************************** +* STRESS PARAMETERS +************************************************************** ++web = 0 wec = 0 scref = 1e-006 ++kvth0we = 0 k2we = 0 ku0we = 0 ++saref = 1e-006 sbref = 1e-006 wlod = 0 ++kvth0 = 0 lkvth0 = 0 wkvth0 = 0 ++pkvth0 = 0 llodvth = 0 wlodvth = 0 ++stk2 = 0 lodk2 = 1 lodeta0 = 1 ++ku0 = 0 lku0 = 0 wku0 = 0 ++pku0 = 0 llodku0 = 0 wlodku0 = 0 ++kvsat = 0 steta0 = 0 tku0 = 0 + +.endl nmos_6p0_nat_t +* +*************************************************************************************************** +* 6V PMOS Models +*************************************************************************************************** +* +.lib pmos_6p0_t + + +.subckt pmos_6p0_sab d g s b w=10u l=0.5u par=1 s_sab=0.28u d_sab=2.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.01051 ++ par_k=0.00517 ++ par_l=3e-7 ++ par_w=-4e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m2 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m2 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_6p0 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=0 sb=0 sd=0 ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_6p0.0 pmos +***** Flag Parameter *** ++level = 54 version = 4.6 binunit = 1 ++paramchk = 1 mobmod = 0 capmod = 2 ++rdsmod = 0 igcmod = 0 igbmod = 0 ++rbodymod = 0 trnqsmod = 0 acnqsmod = 0 ++fnoimod = 1 tnoimod = 0 diomod = 1 ++tempmod = 0 permod = 1 geomod = 1 +***** Geometry Range Parameter *** ++lmin = 0.5e-6 lmax = 50.01e-6 wmin = 0.3e-6 ++wmax = 100.01e-6 +***** Process Parameter *** ++epsrox = 3.9 toxe = '1.56E-8+pmos_6p0_dtox' xj = 1.5E-7 ++ndep = 1.7E17 ngate = 3.6E19 nsd = 6E16 ++rsh = 7 rshg = 0.1 phin = 0 ++lphin = 0.1408 +***** dW and dL Parameter *** ++wint = 4.9E-8 wl = 0 wln = 1 ++ww = -1.37E-14 wwn = 1 wwl = 3.04E-22 ++lint = 6.7E-8 ll = -5.4E-15 lln = 1 ++lw = 0 lwn = 1 lwl = -4.76E-21 ++dwg = -6.6E-9 dwb = -3E-9 xl = '0+pmos_6p0_dxl' ++xw = '0+pmos_6p0_dxw' +***** Vth Related Parameter *** ++vth0 = '-0.8978+pmos_6p0_dvth0' pvth0 = '7.6E-3+8.47e-3*pmos_6p0_dvth0' ++k1 = 0.9588 k2 = 8.936E-3 vfb = -1 ++k3 = -0.75 k3b = 1.2104 w0 = 3.1E-7 ++lpe0 = -4.4E-8 lpeb = -5.96E-8 dvtp0 = 0 ++dvtp1 = 0.3 dvt0 = 1 dvt1 = 1 ++dvt2 = 0 dvt0w = 0 dvt1w = 5.3E6 ++dvt2w = -0.032 +***** Mobility Related Parameter *** ++u0 = 0.0151 ua = 1.78E-9 ub = 4.88E-19 ++uc = -2.7435E-11 luc = 8.691408E-11 puc = -1.501336E-11 ++vsat = 8.55E4 a0 = 0.84 ags = 0.059 ++b0 = 2.625E-8 b1 = 0 keta = -8.6016E-5 ++wketa = 2.772E-3 a1 = 0 a2 = 1 ++rdsw = 1.426E3 wrdsw = 213.9 prdsw = -120 ++rdswmin = 100 prwb = 0.569552 pprwb = -0.052 ++prwg = 0.0432 wr = 1 +***** Subthreshold Related Parameter *** ++voff = -0.1284 voffl = 2.19E-8 minv = 0 ++nfactor = 1 eta0 = 0.08 etab = -0.09408 ++petab = -0.012128 dsub = 0.4824 cit = 0 ++cdsc = 2.4E-4 cdscb = 0 cdscd = 0 +***** Output Resistance Related Parameter *** ++pclm = 0.42 ppclm = 0.071 pdiblc1 = 0.14 ++pdiblc2 = 1E-5 pdiblcb = 0 drout = 0.56 ++pscbe1 = 5.088E8 pscbe2 = 1E-8 pvag = 1.5 ++delta = 0.01 fprout = 0 pdits = 0.01 ++pditsl = 0 pditsd = 0 lambda = 0 ++vtl = 2E5 lc = 0 xn = 3 ++alpha0 = 9.6E-7 alpha1 = 51.5 beta0 = 50.8 ++wbeta0 = 0.22 pbeta0 = 0.14 +***** GIDL Effect Parameters *** ++agidl = 1.1E-15 pagidl = 6.27545E-16 bgidl = 1.578E5 ++egidl = 1.19653E-2 +***** Noise Parameters *** ++ef = 1.1 noia = 'pmos_6p0_noia' ++noib = 'pmos_6p0_noib' noic = 'pmos_6p0_noic' +***** Capacitance Parameter *** ++xpart = 1 cgso = '7.71E-11*pmos_6p0_dcgso' cgdo = '7.71E-11*pmos_6p0_dcgdo' ++cgbo = 1E-13 ckappas = 0.6 ckappad = 0.6 ++dlc = 7.4E-9 noff = 1 voffcv = 0 ++acde = 0.7 moin = 15 cgsl = '5.25E-11*pmos_6p0_dcgso' ++cgdl = '5.25E-11*pmos_6p0_dcgdo' +***** Souce/Drain Junction Diode Model Parameter *** ++ijthsrev = 0.1 ijthdrev = 0.1 ijthsfwd = 0.1 ++ijthdfwd = 0.1 xjbvs = 1 xjbvd = 1 ++bvs = 10.5 bvd = 10.5 jss = 2.0867e-007 ++jsd = 2.0867e-007 jsws = 1.6088e-013 jswd = 1.6088e-013 ++jswgs = 0 jswgd = 0 cjs = 0.000912 ++cjd = 0.000912 mjs = 0.32713 mjd = 0.32713 ++mjsws = 0.056777 mjswd = 0.056777 cjsws = 1.4649e-010 ++cjswd = 1.4649e-010 cjswgs = 3.3229e-010 cjswgd = 3.3229e-010 ++mjswgs = 0.50996 mjswgd =0.50996 pbs = 0.76836 ++pbd = 0.76836 pbsws = 0.5 pbswd = 0.5 ++pbswgs = 1.2295 pbswgd = 1.2295 +***** Temperature coefficient *** ++tnom = 25 ute = -1.2 lute = -0.152467 ++wute = -0.07 kt1 = -0.3828 pkt1 = 2.2E-3 ++kt1l = -3.158E-8 kt2 = -0.09064 ua1 = 1.41E-9 ++lua1 = -6.554813E-10 wua1 = -1.2E-10 pua1 = -3.823641E-10 ++ub1 = -4.31E-18 lub1 = 1.939773E-19 pub1 = 7.291324E-19 ++uc1 = 1.147552E-10 luc1 = -1.067674E-10 puc1 = 1.8536E-11 ++at = -2.18E4 pat = -6.1E3 prt = 454 ++njs = 1 njd = 1 xtis = 3 ++xtid = 3 tpb = 0.0019314 tpbsw = 0.0017642 ++tpbswg = 0.0016588 tcj = 0.001 tcjsw = 0.00071888 ++tcjswg = 0.0009411 + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m2 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m2 + +.endl pmos_6p0_t +* +* +* +.LIB dio + +.model np_3p3 d level = 3 ++tref = 25 ++is = '2.2959e-007 * jsa' ++jsw = '2.1207e-013 * jsa' ++ik = 300000 ++bv = 11.0 ++ibv = 0.001 ++n = 1.01 ++rs = '2e-010 * rsa' ++jtun = 1.1223e-005 ++jtunsw = 6.4125e-012 ++ntun = 10 ++cj = '0.00096797* cja' ++cjp = '1.5663e-010* cjswa' ++pb = 0.70172 ++php = 0.8062 ++mj = 0.32071 ++mjsw = 0.1 ++tlev = 1 ++tlevc = 1 ++trs = 4.5778e-005 ++xti = 3 ++xtitun = -25 ++cta = 0.0009438 ++ctp = 0.00060474 ++eg = 1.17 ++tpb = 0.0018129 ++tphp = 5e-005 +* +.model pn_3p3 d level = 3 ++tref = 25 ++is = '1.653e-007 * jsa' ++jsw = '2.1207e-013 * jsa' ++ik = 500000 ++bv = 10.5 ++ibv = 0.001 ++n = 1 ++rs = '2e-010 * rsa' ++jtun = 5.4028e-005 ++jtunsw = 9.8419e-011 ++ntun = 60 ++cj = '0.00094344* cja' ++cjp = '1.5078e-010* cjswa' ++pb = 0.69939 ++php = 0.8022 ++mj = 0.32084 ++mjsw = 0.05 ++tlev = 1 ++tlevc = 1 ++trs = 3.8628e-005 ++xti = 3 ++xtitun = -40 ++cta = 0.00099187 ++ctp = 0.00063483 ++eg = 1.17 ++tpb = 0.0016906 ++tphp = 0.0052 +* +.model np_6p0 d level = 3 ++tref = 25 ++is = '6.88e-007 * jsa' jsw = '4.88e-013 * jsa' ik = 229000 ++bv = 11 ibv = 0.001 ikr = 1e-030 ++n = 1.0541 rs = '2e-010 * rsa' ++cj = '0.00095 * cja' cjp = '1.33e-010 * cjswa' pb = 0.606 ++php = 0.48 mj = 0.296 mjsw = 0.01 ++tlev = 1 tlevc = 1 trs = 0.0001 ++xti = 5 cta = 0.000825 ctp = 0.0018 ++tpb = 0.00146 tphp = 0.00313 eg = 1.11 + +.model pn_6p0 d level = 3 ++tref = 25 ++is = '2.0867e-007 * jsa' jsw = '1.6088e-013 * jsa' ik = 253800 ++ikr = 0 n = 1.0058 rs = '2.0e-010 * rsa' ++cj = '0.000912 * cja' cjsw = '1.4649e-010 * cjswa' pb = 0.76836 php = 0.5 ++mj = 0.32713 mjsw = 0.056777 ++tlev = 1 tlevc = 1 trs = 0.00168 xti = 3 ++cta = 0.001 ctp = 0.00071888 tpb = 0.0019314 tphp = 0.0017642 ++eg = 1.17 bv=10.5 +* +.model nwp_3p3 d level = 3 ++area = 1.6e-009 ++pj = 0.00016 ++tref = 25 ++is = '1.5654e-006 * jsa' ++jsw = '1.6912e-012 * jsa' ++ik = 300000 ++bv = 0 ++ibv = 0.001 ++n = 1.01 ++rs = '2e-010 * rsa' ++jtun = 0.00037353 ++jtunsw = 3.0737e-011 ++ntun = 22 ++cj = '0.00014917* cja' ++cjp = '5.8113e-010*cjswa' ++pb = 0.5755 ++php = 0.55456 ++mj = 0.33979 ++mjsw = 0.2257 ++tlev = 1 ++tlevc = 1 ++trs = 3.8628e-005 ++xti = 3 ++xtitun = -46 ++cta = 0.0023998 ++ctp = 0.0010977 ++eg = 1.18 ++tpb = 0.0027641 ++tphp = 0.0019629 +* +.model nwp_6p0 d level = 3 ++tref = 25 ++is = '1.6119e-006 * jsa' jsw = '2e-012 * jsa' ik = 100000 ++ikr = 0 n = 1 rs = '2e-010 * rsa' ++cj = '0.00014914 * cja' cjsw = '5.8719e-010 * cjswa' pb = 0.43905 php = 0.48991 ++mj = 0.30525 mjsw = 0.21757 ++tlev = 1 tlevc = 1 trs = 0 xti = 3 ++cta = 0.0028626 ctp = 0.00091707 tpb = 0.0024779 tphp = 0.00125 ++eg = 1.1763 bv=14 +* +.model dnwpw d level = 3 ++tref = 25 ++is = '5.2139e-007* jsa' jsw = '0* jsa' ik = 711930 vb = 14.732 ++ibv = 0.001 ikr = 0 n = 0.98 rs = '2e-010* rsa' ++cj = '0.00032124* cja' cjp = '5.4659e-010* cjswa' pb = 0.63391 php = 0.77752 ++mj = 0.31113 mjsw = 0.39816 ++tlev = 1 tlevc = 1 trs = 0.0002207 xti = 3 ++cta = 0.0012922 ctp = 0.0010772 tpb = 0.0019819 tphp = 0.0016567 ++eg = 1.17 +* +.model dnwps d level = 3 ++tref = 25 ++is = '2e-006* jsa' jsw = '1e-12* jsa' ik = 229050 vb = 30.48 ++ibv = 0.001 ikr = 0 n = 0.99335 rs = '2e-010* rsa' ++cj = '0.00022998* cja' cjp = '7.2369e-010* cjswa' pb = 0.35175 php = 0.37806 ++mj = 0.14716 mjsw = 0.19821 ++tlev = 1 tlevc = 1 trs = 0.0026028 xti = 3 ++cta = 0.0012309 ctp = 0.0012111 tpb = 0.0019414 tphp = 0.0017152 ++eg = 1.17 +* +.model sc_diode d level = 3 ++tref = 25 ++js = '8.16*10**jsa_sc' jsw = 0 ik = 4e+010 vb = '17 + vba_sc' ++ibv = 9.92e-005 ikr = 4e+008 n = 1.0553 rs = '2.768e-009*rs_sc' ++jtun = '1048.7*10**jtuna_sc' jtunsw = 0 ntun = 72.211 ++cj = '0.00176*cja_sc' cjp = 0 pb = 0.14256 php = 0.93627 ++mj = 0.02604 mjsw = 0.1545 ++tlev = 1 tlevc = 1 tcv = -5e-005 trs = 0.0022143 ++xti = 3 xtitun = -12.347 cta = 6.2962e-005 ctp = 0 ++tpb = 0.0002696 tphp = 0 eg = 0.61 +* +.endl diode +* +******************************************************************************************************* +* Resistor Models +* ---------------------- +* +* Temperature : -40, 0, 25, 50, 75, 100 and 125C. +* +* The resistor models were generated from the resistor characterization reports R-EZ-ER-557 Rev.1B or +* refer to resistor_VCR document attached in the lotus notes document. The user is advised to follow +* the instructions on the usage and understand the limitations of the models documented in this report. +* In particular the user should take note of the following : +* +* a. The parameters for each model were extracted from test structures with various dimensions. +* The user should therefore take note of this limitation when extending design & simulation +* beyond the test conditions. +* +* b. The voltage coefficients (r_vc1 and r_vc2) are set to zero by default in each model. +* If the need arise, the user should consult the resistor characterization report for the +* appropriate values to use. +* +* c. The Poly-STI-substrate capacitance parameters are obtained from YI-141-IA001 Rev. 1B. +* +* The models included in this release are as follows : +* +* Model Name Description +* ---------- ----------- +* +* nplus_u Model for 3-terminal unsalicidedn+ diffusion resistor +* pplus_u Model for 3-terminal unsalicidedP+ diffusion resistor +* nplus_s Model for 3-terminal salicided N+ diffusion resistor +* pplus_s Model for 3-terminal salicided P+ diffusion resistor +* nwell Model for 3-terminal nwell resistor under STI +* npolyf_u Model for 3-terminal unsalicidedn+ poly resistor +* ppolyf_u Model for 3-terminal unsalicided p+ poly resistor +* npolyf_s Model for 3-terminal salicided n+ poly resistor +* ppolyf_s Model for 3-terminal salicided p+ poly resistor +* ppolyf_u_1k Model for 3-terminal 1k high-Rs p+ poly resistor on field oxide +* ppolyf_u_2k Model for 3-terminal 2k high-Rs p+ poly resistor on field oxide +* ppolyf_u_1k_6p0 Model for 3-terminal 1k high-Rs p+ poly resistor on field oxide (6.0V area) +* ppolyf_u_2k_6p0 Model for 3-terminal 2k high-Rs p+ poly resistor on field oxide (6.0V area) +* ppolyf_u_3k Model for 3-terminal 3k high-Rs p+ poly resistor on field oxide (3.3V & 6V area) +* rm1 Model for 2-terminal metal 1 resistor +* rm2 Model for 2-terminal metal 2 resistor +* rm3 Model for 2-terminal metal 3 resistor +* tm6k Model for 2-terminal top metal 6k resistor +* tm9k Model for 2-terminal top metal 9k resistor +* tm30k Model for 2-terminal top metal 30k resistor +******************************************************************************************************* +.LIB res +* model for unsalicided n+ diffusion resistor +.subckt nplus_u 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0='rsh_nplus_u*(1+(mc_rsh_nplus_u/(rsh_nplus_u))*res_mc_skew*sw_stat_global)' ++ r_dw='-5E-8*(1+ mc_dw_nplus_u*res_mc_skew*sw_stat_global)' ++ r_dl=2E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* + par_r=0.012608 +* + par_sqrtarea='sqrt(par*(r_l)*(r_w))' +* + var_r='0.7071*par_r*1e-06/par_sqrtarea' +* + mis_r=agauss(0, 0.1, 1) +**** + mis_r=agauss(0, var_r, 1) ++ mis_r = 0 + +* model for terminal resistor +.model nplus_u_t r ++ rsh='18.5+ mc_rt_nplus_u*res_mc_skew*sw_stat_global' ++ tc1=8.5E-4 ++ tc2=1.75E-6 ++ tnom=25 +* model for substrate capacitor +.model np_3p3 d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +rt1 1 11 nplus_u_t l='s*1u' w=r_w dtemp=dtemp +d1 3 1 np_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +* body +rb 11 21 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)*(1+mis_r*sw_stat_mismatch)' +* terminal 2 +rt2 21 2 nplus_u_t l='s*1u' w=r_w dtemp=dtemp +d2 3 2 np_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +*------------------- +.ends nplus_u +******************************************************************************************************* +* model for unsalicided p+ diffusion resistor +.subckt pplus_u 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0='rsh_pplus_u*(1+mc_rsh_pplus_u/(rsh_pplus_u)*res_mc_skew*sw_stat_global)' ++ r_dw='2.75E-8*(1+ mc_dw_pplus_u*res_mc_skew*sw_stat_global)' ++ r_dl=5.0E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* + par_r=0.0126 +* + par_sqrtarea='sqrt(par*(r_l)*(r_w))' +* + var_r='0.7071*par_r*1e-06/par_sqrtarea' +* + mis_r=agauss(0, 0.1, 1) +** + mis_r=agauss(0, var_r, 1) ++ mis_r=0 + +* model for terminal resistor +.model pplus_u_t r ++ rsh='50+mc_rt_pplus_u*res_mc_skew*sw_stat_global' ++ tc1=-1.528E-3 ++ tc2=0.7E-6 ++ tnom=25 +* model for substrate capacitor +.model pn_3p3 d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +rt1 1 11 pplus_u_t l='s*1u' w=r_w dtemp=dtemp +d1 1 3 pn_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +* body +rb 11 21 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)*(1+mis_r*sw_stat_mismatch)' +* terminal 2 +rt2 21 2 pplus_u_t l='s*1u' w=r_w dtemp=dtemp +d2 2 3 pn_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +*------------------- +.ends pplus_u +******************************************************************************************************* +* model for salicided n+ diffusion resistor +.subckt nplus_s 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0='rsh_nplus_s*(1 + mc_rsh_nplus_s/(rsh_nplus_s)*res_mc_skew*sw_stat_global)' ++ r_dw='-1.25E-8*(1+mc_dw_nplus_s*res_mc_skew*sw_stat_global)' ++ r_dl=3.5E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.3E-3 ++ r_tc2=3E-7 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for terminal resistor +.model nplus_s_t r ++ rsh=6 ++ tc1=1.43E-3 ++ tc2=-0.27E-6 ++ tnom=25 +* model for substrate capacitor +.model np_3p3 d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +rt1 1 11 nplus_s_t l='s*1u' w=r_w dtemp=dtemp +d1 3 1 np_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +* body +rb 11 21 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 nplus_s_t l='s*1u' w=r_w dtemp=dtemp +d2 3 2 np_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +*------------------- +.ends nplus_s +******************************************************************************************************* +* model for salicided p+ diffusion resistor +.subckt pplus_s 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0='rsh_pplus_s*(1+ mc_rsh_pplus_s/(rsh_pplus_s)*res_mc_skew*sw_stat_global)' ++ r_dw='-5E-8*(1+mc_dw_pplus_s*res_mc_skew*sw_stat_global)' ++ r_dl=3.5E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.375E-3 ++ r_tc2=0.45E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for terminal resistor +.model pplus_s_t r ++ rsh=6.5 ++ tc1=1.565E-3 ++ tc2=-0.028E-6 ++ tnom=25 +* model for substrate capacitor +.model pn_3p3 d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +rt1 1 11 pplus_s_t l='s*1u' w=r_w dtemp=dtemp +d1 1 3 pn_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +* body +rb 11 21 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 pplus_s_t l='s*1u' w=r_w dtemp=dtemp +d2 2 3 pn_3p3 area='r_w*r_l/2' pj='r_w+2*r_l/2' dtemp=dtemp +*------------------- +.ends pplus_s +******************************************************************************************************* +* model for Nwell resistor under STI +.subckt nwell 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0 = rsh_nwell ++ r_dw = 2.22E-7 ++ r_dl = 1.02E-8 ++ r_vc1 = 0 ++ r_vc2 = 0 ++ r_tc1 = 2.285E-3 ++ r_tc2 = 9.78E-6 ++ r_tnom = 25 ++ r_l = 's*(r_length-2*r_dl)' ++ r_w = 'r_width-2*r_dw' ++ r_n = 'r_l/r_w' ++ r_temp = '1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for terminal resistor +.model nwell_t r ++ rsh = 250 ++ tc1 = 1.72E-3 ++ tc2 = 9.34E-6 ++ tnom = 25 +* model for substrate capacitor +.model nwp d ++ level = 3 ++ cj = 0.00014917 ++ mj = 0.33979 ++ pb = 0.5755 ++ cjsw = 5.8113e-010 ++ mjsw = 0.2257 ++ php = 0.55456 ++ cta = 0.0023998 ++ ctp = 0.0010977 ++ tpb = 0.0027641 ++ tphp = 0.0019629 ++ tlevc = 1 ++ tref = 25 +*------------------- +* terminal 1 +rt1 1 11 nwell_t l='s*1u' w=r_w dtemp=dtemp +d1 3 1 nwp area='r_w*r_l/2' PJ= 'r_w+2*r_l/2' dtemp=dtemp +* body +rb 11 21 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 nwell_t l='s*1u' w=r_w dtemp=dtemp +d2 3 2 nwp area='r_w*r_l/2' PJ= 'r_w+2*r_l/2' dtemp=dtemp +*------------------- +.ends nwell +******************************************************************************************************* +******************************************************************************************************* +* model for n+ poly on field oxide resistor +.subckt npolyf_u 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +* model for body resistor ++ r_rsh0='rsh_npolyf_u*(1+mc_rsh_npolyf_u/(rsh_npolyf_u)*res_mc_skew*sw_stat_global)' ++ r_dw='0.0265e-6*(1+ mc_dw_npolyf_u*res_mc_skew*sw_stat_global)' ++ r_dl=8.48e-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-1.4e-3 ++ r_tc2=2.2E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* + par_r=0.05808 +* + par_sqrtarea='sqrt(par*(r_l)*(r_w))' +* + var_r='0.7071*par_r*1e-06/par_sqrtarea' +* + mis_r=agauss(0, 0.1, 1) +** + mis_r=agauss(0, var_r, 1) ++ mis_r=0 + +.model npolyf_u_body r ++ af=1.684 ++ kf=3.6e-23 ++ noise=1 +* model for terminal resistor +.model npolyf_u_t r ++ rsh='40+ mc_rt_npolyf_u*res_mc_skew*sw_stat_global' ++ tc1=-0.735E-3 ++ tc2=-1.7E-6 ++ tnom=25 ++ af=1.684 ++ kf=3.6e-23 ++ noise=1 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 npolyf_u_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 npolyf_u_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)*(1+mis_r*sw_stat_mismatch)' +* terminal 2 +rt2 21 2 npolyf_u_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends npolyf_u +******************************************************************************************************* +* model for P+ poly on field oxide resistor +.subckt ppolyf_u 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +* model for body resistor ++ r_rsh0='rsh_ppolyf_u*(1+mc_rsh_ppolyf_u/(rsh_ppolyf_u)*res_mc_skew*sw_stat_global)' ++ r_dw='2.55E-8*(1+ mc_dw_ppolyf_u*res_mc_skew*sw_stat_global)' ++ r_dl=2E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-0.9e-4 ++ r_tc2=7E-7 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* + par_r=0.021 +* + par_sqrtarea='sqrt(par*(r_l)*(r_w))' +* + var_r='0.7071*par_r*1e-06/par_sqrtarea' +* + mis_r=agauss(0, 0.1, 1) +** + mis_r=agauss(0, var_r, 1) ++ mis_r = 0 + +.model ppolyf_u_body r ++ af=1.79 ++ kf=2.4E-23 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_t r ++ rsh='60+ mc_rt_ppolyf_u*res_mc_skew*sw_stat_global' ++ tc1=-1.47E-3 ++ tc2=0.82E-6 ++ tnom=25 ++ af=1.79 ++ kf=2.4E-23 ++ noise=1 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85e-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_body l=r_l w=r_w ++r='(r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n))*(1+mis_r*sw_stat_mismatch)' +* terminal 2 +rt2 21 2 ppolyf_u_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u +******************************************************************************************************* +******************************************************************************************************* +* model for salicided n+ poly over field oxide resistor +.subckt npolyf_s 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +* model for body resistor ++ r_rsh0='rsh_npolyf_s*(1+mc_rsh_npolyf_s/(rsh_npolyf_s)*res_mc_skew*sw_stat_global)' ++ r_dw='6.5e-9*(1+mc_dw_npolyf_s*res_mc_skew*sw_stat_global)' ++ r_dl=1.5e-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.26e-3 ++ r_tc2=0.25E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model npolyf_s_body r ++ af=1.684 ++ kf=3.6e-23 ++ noise=1 +* model for terminal resistor +.model npolyf_s_t r ++ rsh=5.5 ++ tc1=1.28E-3 ++ tc2=-0.5E-6 ++ tnom=25 ++ af=1.684 ++ kf=3.6e-23 ++ noise=1 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 npolyf_s_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 npolyf_s_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 npolyf_s_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends npolyf_s +******************************************************************************************************* +******************************************************************************************************* +* model for salicided p+ poly over field oxide resistor +.subckt ppolyf_s 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +* model for body resistor ++ r_rsh0='rsh_ppolyf_s*(1+mc_rsh_ppolyf_s/(rsh_ppolyf_s)*res_mc_skew*sw_stat_global)' ++ r_dw='7.5E-9*(1+mc_dw_ppolyf_s*res_mc_skew*sw_stat_global)' ++ r_dl=1.5E-10 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.245e-3 ++ r_tc2=3.6E-7 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_s_body r ++ af=1.79 ++ kf=2.4E-23 ++ noise=1 +* model for terminal resistor +.model ppolyf_s_t r ++ rsh=5 ++ tc1=1.254E-3 ++ tc2=-0.27E-6 ++ tnom=25 ++ af=1.79 ++ kf=2.4E-23 ++ noise=1 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85e-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_s_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_s_body l=r_l w=r_w ++r='(r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n))' +* terminal 2 +rt2 21 2 ppolyf_s_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_s +******************************************************************************************************* +* model for 1k high-Rs P+ poly on field oxide resistor (LV area) +******************************************************************************************************* +.subckt ppolyf_u_1k 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* model for body resistor +.param ++ r_rsh0='rsh_ppolyf_u_1k*(1+ mc_rsh_ppolyf_u_1k/(rsh_ppolyf_u_1k)*res_mc_skew*sw_stat_global)' ++ r_dw='0.0148E-6*(1+ mc_dw_ppolyf_u_1k*res_mc_skew*sw_stat_global)' ++ r_dl=3.85E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-9.39e-4 ++ r_tc2=2.51E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_u_1k_body r ++ af=1 ++ kf=2.62e-26 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_1k_t r ++ rsh='85.45+mc_rt_ppolyf_u_1k*res_mc_skew*sw_stat_global' ++ tc1=-7.92E-3 ++ tc2=4.25E-5 ++ tnom=25 ++ af=1 ++ kf=2.62e-26 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_1k_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_1k_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 ppolyf_u_1k_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u_1k +******************************************************************************************************* +*** model for 2k high-rs P+ poly on field oxide resistor (LV area) +******************************************************************************************************* +* model for 2k high-Rs P+ poly on field oxide resistor +.subckt ppolyf_u_2k 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* model for body resistor +.param ++ r_rsh0='rsh_ppolyf_u_2k*(1+ mc_rsh_ppolyf_u_2k/(rsh_ppolyf_u_2k)*res_mc_skew*sw_stat_global)' ++ r_dw='0.02256E-6*(1+ mc_dw_ppolyf_u_2k*res_mc_skew*sw_stat_global)' ++ r_dl=-0.0932E-6 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-0.001669823 ++ r_tc2=3.74326E-06 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_u_2k_body r ++ af=1 ++ kf=2.62e-26 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_2k_t r ++ rsh='33.16+mc_rt_ppolyf_u_2k*res_mc_skew*sw_stat_global' ++ tc1=-0.003763316 ++ tc2=9.81166E-06 ++ tnom=25 ++ af=1 ++ kf=2.62e-26 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_2k_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_2k_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 ppolyf_u_2k_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u_2k +******************************************************************************************************* +* model for 1k high-Rs P+ poly on field oxide resistor (MV area) +******************************************************************************************************* +.subckt ppolyf_u_1k_6p0 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* model for body resistor +.param ++ r_rsh0='rsh_ppolyf_u_1k_6p0*(1 + mc_rsh_ppolyf_u_1k_6p0/(rsh_ppolyf_u_1k_6p0)*res_mc_skew*sw_stat_global)' ++ r_dw='0.0148E-6*(1+ mc_dw_ppolyf_u_1k_6p0*res_mc_skew*sw_stat_global)' ++ r_dl=3.85E-11 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-9.39e-4 ++ r_tc2=2.51E-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_u_1k_body r ++ af=1 ++ kf=2.62e-26 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_1k_t r ++ rsh='85.45+mc_rt_ppolyf_u_1k_6p0*res_mc_skew*sw_stat_global' ++ tc1=-7.92E-3 ++ tc2=4.25E-5 ++ tnom=25 ++ af=1 ++ kf=2.62e-26 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_1k_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_1k_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 ppolyf_u_1k_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u_1k_6p0 +******************************************************************************************************* +*** model for 2k high-rs P+ poly on field oxide resistor (MV area) +******************************************************************************************************* +* model for 2k high-Rs P+ poly on field oxide resistor +.subckt ppolyf_u_2k_6p0 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* model for body resistor +.param ++ r_rsh0='rsh_ppolyf_u_2k_6p0+mc_rsh_ppolyf_u_2k_6p0*res_mc_skew*sw_stat_global' ++ r_dw='0.02256E-6*(1+ mc_dw_ppolyf_u_2k_6p0*res_mc_skew*sw_stat_global)' ++ r_dl=-0.0932E-6 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-0.001669823 ++ r_tc2=3.74326E-06 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_u_2k_body r ++ af=1 ++ kf=2.62e-26 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_2k_t r ++ rsh='33.16+mc_rt_ppolyf_u_2k_6p0*res_mc_skew*sw_stat_global' ++ tc1=-0.003763316 ++ tc2=9.81166E-06 ++ tnom=25 ++ af=1 ++ kf=2.62e-26 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_2k_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_2k_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 ppolyf_u_2k_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u_2k_6p0 +******************************************************************************************************* +*** model for 3k high-rs P+ poly on field oxide resistor (LV & MVarea) +******************************************************************************************************* +* model for 3k high-Rs P+ poly on field oxide resistor +.subckt ppolyf_u_3k 1 2 3 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* model for body resistor +.param ++ r_rsh0='rsh_ppolyf_u_3k*(1 + mc_rsh_ppolyf_u_3k/(rsh_ppolyf_u_3k)*res_mc_skew*sw_stat_global)' ++ r_dw='0.02256E-6*(1+ mc_dw_ppolyf_u_3k*res_mc_skew*sw_stat_global)' ++ r_dl=-0.0932E-6 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=-0.001669823 ++ r_tc2=3.74326E-06 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +.model ppolyf_u_3k_body r ++ af=1 ++ kf=2.62e-26 ++ noise=1 +* model for terminal resistor +.model ppolyf_u_3k_t r ++ rsh='33.16+mc_rt_ppolyf_u_3k*res_mc_skew*sw_stat_global' ++ tc1=-0.003763316 ++ tc2=9.81166E-06 ++ tnom=25 ++ af=1 ++ kf=2.62e-26 +* model for substrate capacitor (pF/um2) +.model fox_sub c ++ cox=8.85E-05 +*------------------- +* terminal 1 +rt1 1 11 ppolyf_u_3k_t l='s*1u' w=r_w dtemp=dtemp +c1 1 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +* body +rb 11 21 ppolyf_u_3k_body l=r_l w=r_w ++r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(11,21))/r_n+r_vc2*abs(v(11,21))*abs(v(11,21))/r_n/r_n)' +* terminal 2 +rt2 21 2 ppolyf_u_3k_t l='s*1u' w=r_w dtemp=dtemp +c2 2 3 fox_sub l='r_l/2' w=r_w dtemp=dtemp +*------------------- +.ends ppolyf_u_3k +******************************************************************************************************* +* model for metal 1 resistor +.subckt rm1 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_rm1 ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.33E-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends rm1 +******************************************************************************************************* +* model for metal 2 resistor +.subckt rm2 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_rm2 ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.33E-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends rm2 +******************************************************************************************************* +* model for metal 3 resistor +.subckt rm3 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_rm3 ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.33E-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends rm3 +*************************************************************************************** +* model for top metal 6k resistor +.subckt tm6k 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_tm6k ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.5e-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends tm6k +*************************************************************************************** +* model for top metal 9k resistor +.subckt tm9k 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_tm9k ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.7e-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends tm9k +*************************************************************************************** +* model for top metal 11k resistor +.subckt tm11k 1 2 r_length=l r_width=w dtemp=0 par=1 s=1 +*------------------- +* body resistor parameters ++ r_rsh0=rsh_tm11k ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.7e-3 ++ r_tc2=0 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends tm11k +*************************************************************************************** +* model for top metal 30k resistor +.subckt tm30k 1 2 r_length=l r_width=w par=1 s=1 dtemp=0 +*------------------- +* body resistor parameters ++ r_rsh0='rsh_tm30k' ++ r_dw=0 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=3.86e-3 ++ r_tc2=1.51e-6 ++ r_tnom=25 ++ r_l='s*(r_length-2*r_dl)' ++ r_w='r_width-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +*------------------- +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*rb 1 2 r='r_temp*r_n*r_rsh0' vc1 = 'r_vc1/r_n/r_rsh0' vc2 = 'r_vc2/r_n/r_n/r_rsh0' +*------------------- +.ends tm30k +*************************************************************************************** +* +.ENDL res +* +* ---------------------------------------------------------------------------------------------------- +* MIM Capacitor Scalable DC Model +* +*The models are obtained from YI-141-SM003 Rev. 1E. +* +* ---------------------------------------------------------------------------------------------------- +.LIB mim_cap +*/ ------------------------------------------------------------------------------------- +*/ MIM Capacitor (1.5fF/um2) subcircuit model for GF's 0.18 Analog CMOS process +*/-------------------------------------------------------------------------------------- +.subckt mim_1p5fF 1 2 c_length=l c_width=w dtemp=0 par=1 +.param ++ c_cox='1.47e-3*mim_corner_1p5fF' ++ c_capsw='3.79e-10*mim_corner_1p5fF' ++ c_tnom=25 ++ c_tc1=4.0604E-05 ++ c_tc2=-6.90E-08 ++ c_vcr1=-4.5152E-05 ++ c_vcr2=9.748E-06 ++ c_area='c_length*c_width' ++ c_peri='2*(c_length+c_width)' ++ c_c0='(c_cox*c_area+c_capsw*c_peri)*(1+c_tc1*(temper+dtemp-c_tnom)+c_tc2*(temper+dtemp-c_tnom)*(temper+dtemp-c_tnom))' +*/ +*/ model for capacitance +c_cap 1 2 c='c_c0*(1+ c_vcr1*v(1, 2)+c_vcr2*v(1,2)*v(1,2) )*(1+mc_c_cox_1p5fF)' +** +.ends mim_1p5fF +*/ ------------------------------------------------------------------------------------- +*/ MIM Capacitor (1fF/um2) subcircuit model for GF's 0.18 Analog CMOS process +*/-------------------------------------------------------------------------------------- +.subckt mim_1p0fF 1 2 c_length=l c_width=w dtemp=0 par=1 +.param ++ c_cox='0.987e-3*mim_corner_1p0fF' ++ c_capsw='3.3e-10*mim_corner_1p0fF' ++ c_tnom=25 ++ c_tc1=1.302e-5 ++ c_tc2=-4.93e-9 ++ c_vcr1=6.079e-6 ++ c_vcr2=1.268e-6 ++ c_area='c_length*c_width' ++ c_peri='2*(c_length+c_width)' ++ c_c0='(c_cox*c_area+c_capsw*c_peri)*(1+c_tc1*(temper+dtemp-c_tnom)+c_tc2*(temper+dtemp-c_tnom)*(temper+dtemp-c_tnom))' +*/ +*/ model for capacitance +c_cap 1 2 c='c_c0*(1+ c_vcr1*v(1, 2)+c_vcr2*v(1,2)*v(1,2) )*(1+mc_c_cox_1p0fF)' +** +.ends mim_1p0fF +*/ ------------------------------------------------------------------------------------- +*/ MIM Capacitor (2fF/um2) subcircuit model for GLOBALFOUNDRIES 0.18 Analog CMOS process M2-M3 +*/-------------------------------------------------------------------------------------- +.subckt mim_2p0fF 1 2 c_length=l c_width=w dtemp=0 par=1 +.param gleak='9.51e-10/5*10000' +.param c_cox='1.99e-3*mim_corner_2p0fF' +.param c_capsw='2.383e-10*mim_corner_2p0fF' +.param c_vcr1='0+(c_width>5u||c_length>5u)*8.742e-6+(c_width<=5u||c_length<=5u)*(-81e-6)' +.param c_vcr2='0+(c_width>5u||c_length>5u)*9.188e-6+(c_width<=5u||c_length<=5u)*(16.7e-6)' + +.param c_tnom=25 +.param c_tc1=1.46e-5 +.param c_tc2=-5.55e-8 +.param c_AREA='c_length*c_width' +.param c_PERI='2*(c_length+c_width)' + +.param c_c0='(c_cox*c_AREA+c_capsw*c_PERI)*(1+c_tc1*(temper +dtemp -c_tnom)+c_tc2*(temper+dtemp-c_tnom)*(temper+dtemp-c_tnom))' +* +c_cap 1 2 c='c_c0*(1+c_vcr1*v(1,2)+c_vcr2*v(1,2)*v(1,2))*(1+mc_c_cox_2p0fF)' +r_leak 1 2 r='1/(gleak*c_AREA)' tc1=c_tc1 tc2=c_tc2 dtemp=dtemp +.ends mim_2p0fF +.ENDL mim_cap +* ---------------------------------------------------------------------------------------------------- +* +* +.LIB moscap + +.subckt nmoscap_3p3 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.002003 +.param cvar2=0.00198 +.param cvar3=6.25 +.param cvar4=-3.9375 +c_moscap 1 2 c='nmoscap_3p3_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends nmoscap_3p3 +* +.subckt pmoscap_3p3 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.001998 +.param cvar2=0.00196 +.param cvar3=-6.25 +.param cvar4=-4.9375 +c_moscap 1 2 c='pmoscap_3p3_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends pmoscap_3p3 +* +.subckt nmoscap_6p0 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.001107 +.param cvar2=0.00107 +.param cvar3=6.25 +.param cvar4=-4.1875 +c_moscap 1 2 c='nmoscap_6p0_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends nmoscap_6p0 +* +.subckt pmoscap_6p0 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.001107 +.param cvar2=0.00107 +.param cvar3=-6.25 +.param cvar4=-5.75 +c_moscap 1 2 c='pmoscap_6p0_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends pmoscap_6p0 +* +.subckt nmoscap_3p3_b 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.002458 +.param cvar2=0.001533 +.param cvar3=1.515152 +.param cvar4=0.560606 +c_moscap 1 2 c='nmoscap_3p3_b_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends nmoscap_3p3_b +* +.subckt pmoscap_3p3_b 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.002435 +.param cvar2=0.00154 +.param cvar3=-1.66667 +.param cvar4=0.65 +c_moscap 1 2 c='pmoscap_3p3_b_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends pmoscap_3p3_b +* +.subckt nmoscap_6p0_b 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.001293 +.param cvar2=0.000863 +.param cvar3=1.052632 +.param cvar4=0.736842 +c_moscap 1 2 c='nmoscap_6p0_b_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends nmoscap_6p0_b +* +.subckt pmoscap_6p0_b 1 2 c_length=l c_width=w dtemp=0 +.param cvar1=0.001325 +.param cvar2=0.000865 +.param cvar3=-1.42857 +.param cvar4=0.642857 +c_moscap 1 2 c='pmoscap_6p0_b_corner*c_length*c_width*(cvar1+cvar2*tanh(cvar3*v(1,2)+cvar4))' dtemp=dtemp +.ends pmoscap_6p0_b +* +.ENDL moscap +* +*************************************************************************************************** +* 3.3V NMOS statistical Models +*************************************************************************************************** +* +.lib nmos_3p3_stat + + +.subckt nmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) +xr1 d d1 b nplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b nplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b nmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model nmos_3p3.0 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_0 ++lvth0 = -3.8715455e-008 ++wvth0 = -1.430587e-008 ++pvth0 = 4.3636364e-016 ++k1 = 0.95938091 ++lk1 = -9.9985454e-008 ++k2 = 0.054714558 ++lk2 = -4.1647636e-008 ++wk2 = -1.9242857e-008 ++pk2 = 5.388e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.1262652 ++lvoff = 3.9354545e-009 ++wvoff = 5.3064935e-009 ++pvoff = -1.4858182e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.023671338 ++lu0 = 4.6525455e-009 ++wu0 = 4.6066597e-009 ++pu0 = -6.5127273e-016 ++ua = -1.1554452e-009 ++lua = 7.0220545e-016 ++wua = 2.7073777e-016 ++pua = -1.4149745e-022 ++ub = 3.3771156e-018 ++lub = -7.9058636e-025 ++wub = -4.093733e-025 ++pub = 9.2644364e-032 ++uc = 2.2660166e-010 ++luc = -6.1360545e-017 ++wuc = -3.2577351e-017 ++puc = 5.4467782e-024 ++eu = 1.67 ++vsat = 92454.546 ++lvsat = -0.0027272727 ++wvsat = -0.00021818182 ++pvsat = 1.3090909e-009 ++a0 = 0.11197377 ++la0 = -3.1454545e-009 ++wa0 = -6.2322078e-009 ++pa0 = 1.7450182e-015 ++ags = 0.32403844 ++lags = -1.5116364e-008 ++wags = 4.7930493e-008 ++pags = -1.2213818e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.14896036 ++lketa = 3.8830182e-008 ++wketa = 8.1643636e-009 ++pketa = -2.4261818e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.3741 ++lpclm = -4.729e-008 ++wpclm = 2.1028364e-008 ++ppclm = 8.5658182e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.652013e-006 ++lalpha0 = -3.0506364e-013 ++walpha0 = 4.8779221e-014 ++palpha0 = -1.3658182e-020 ++alpha1 = 0 ++beta0 = 19.905584 ++lbeta0 = 1.2863636e-007 ++wbeta0 = 1.3848312e-007 ++pbeta0 = 8.7272727e-016 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.45934558 ++lkt1 = 4.2126364e-008 ++wkt1 = 3.2086753e-008 ++pkt1 = -8.6530909e-015 ++kt1l = 0 ++kt2 = -0.024730519 ++lkt2 = 1.2545455e-009 ++wkt2 = 1.0597403e-009 ++pkt2 = -2.9672727e-016 ++ute = -1.5675325 ++lute = 9.0909091e-008 ++wute = 1.0441558e-007 ++pute = -4.3636364e-014 ++ua1 = 1.675e-009 ++ub1 = -4.1945234e-018 ++lub1 = 2.8745455e-025 ++wub1 = 3.3492467e-025 ++pub1 = -5.7490909e-032 ++uc1 = -4.2363636e-011 ++luc1 = -3.8181818e-018 ++wuc1 = -6.5454545e-018 ++puc1 = 1.8327273e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.1 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_1 ++lvth0 = -2.3433061e-008 ++wvth0 = -1.2304653e-008 ++pvth0 = -5.642449e-016 ++k1 = 0.74639857 ++lk1 = 6.5057143e-009 ++k2 = 0.0237458 ++lk2 = -2.6163257e-008 ++wk2 = -3.01296e-009 ++pk2 = -2.7269486e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.11273959 ++lvoff = -2.8273469e-009 ++wvoff = 1.6942041e-009 ++pvoff = 3.2032653e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.029675694 ++lu0 = 1.6503673e-009 ++wu0 = 8.572898e-010 ++pu0 = 1.2234122e-015 ++ua = -1.2961984e-009 ++lua = 7.7258204e-016 ++wua = 4.7264816e-017 ++pua = -2.976098e-023 ++ub = 3.0836898e-018 ++lub = -6.4387347e-025 ++wub = -2.7080816e-026 ++pub = -9.8501878e-032 ++uc = 8.4613959e-011 ++luc = 9.6333061e-018 ++wuc = 2.2398367e-018 ++puc = -1.1961815e-023 ++eu = 1.67 ++vsat = 83571.429 ++lvsat = 0.0017142857 ++wvsat = -0.0017142857 ++pvsat = 2.0571429e-009 ++a0 = 1.0861147 ++la0 = -4.9021592e-007 ++wa0 = -5.1997224e-008 ++pa0 = 2.4627526e-014 ++ags = 0.47870122 ++lags = -9.2447755e-008 ++wags = 4.3304327e-008 ++pags = -9.9007347e-015 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.028417143 ++lketa = -2.1441429e-008 ++wketa = -7.4262857e-009 ++pketa = 5.3691429e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.082893878 ++lpclm = 9.8313061e-008 ++wpclm = 4.3902367e-008 ++ppclm = -2.8711837e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.5720816e-006 ++lalpha0 = -2.265098e-012 ++walpha0 = -1.5330612e-014 ++palpha0 = 1.8396735e-020 ++alpha1 = 0 ++beta0 = 22.625306 ++lbeta0 = -1.2312245e-006 ++wbeta0 = -3.5054694e-007 ++pbeta0 = 2.4538775e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33916633 ++lkt1 = -1.7963265e-008 ++wkt1 = -2.4641633e-009 ++pkt1 = 8.6223674e-015 ++kt1l = 0 ++kt2 = -0.020311225 ++lkt2 = -9.5510204e-010 ++wkt2 = -3.9183673e-011 ++pkt2 = 2.5273469e-016 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.804398e-018 ++lub1 = -4.0760816e-025 ++wub1 = 5.6899592e-026 ++pub1 = 8.1521633e-032 ++uc1 = -6.0285714e-011 ++luc1 = 5.1428571e-018 ++wuc1 = 2.0571429e-018 ++puc1 = -2.4685714e-024 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.2 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_2 ++lvth0 = -3.224026e-009 ++wvth0 = -9.7008312e-009 ++pvth0 = -3.6888312e-015 ++k1 = 0.79593364 ++lk1 = -5.2936364e-008 ++k2 = 0.0056393844 ++lk2 = -4.4355584e-009 ++wk2 = -7.4596769e-009 ++pk2 = 2.6091117e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12631325 ++lvoff = 1.3461039e-008 ++wvoff = 2.0819221e-009 ++pvoff = -1.4493507e-016 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032447266 ++lu0 = -1.6755195e-009 ++wu0 = 6.7095584e-010 ++pu0 = 1.447013e-015 ++ua = -8.1547091e-010 ++lua = 1.9570909e-016 ++wua = 6.0458182e-018 ++pua = 1.9701818e-023 ++ub = 2.7427942e-018 ++lub = -2.347987e-025 ++wub = -1.6048831e-026 ++pub = -1.1174026e-031 ++uc = 9.84685e-011 ++luc = -6.9921429e-018 ++wuc = -8.8975636e-018 ++puc = 1.4030649e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.224418 ++la0 = -6.5617987e-007 ++wa0 = 4.291948e-009 ++pa0 = -4.2919481e-014 ++ags = 0.25784649 ++lags = 1.7257792e-007 ++wags = -2.606026e-009 ++pags = 4.5191688e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.019651071 ++lketa = -3.1960714e-008 ++wketa = -6.5992208e-010 ++pketa = -2.7504935e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.18918506 ++lpclm = -2.9236364e-008 ++wpclm = 2.1551688e-009 ++ppclm = 4.7225454e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 7.5243347e-005 ++lalpha0 = -8.4670617e-011 ++walpha0 = 7.5358442e-012 ++palpha0 = -9.043013e-018 ++alpha1 = 0 ++beta0 = 24.210162 ++lbeta0 = -3.133052e-006 ++wbeta0 = 1.1381299e-007 ++pbeta0 = -3.1184416e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.32898149 ++lkt1 = -3.0185065e-008 ++wkt1 = -7.3528831e-009 ++pkt1 = 1.4488831e-014 ++kt1l = 0 ++kt2 = -0.021107143 ++wkt2 = 1.7142857e-010 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5166039e-018 ++lub1 = -7.5296104e-025 ++wub1 = 2.224987e-026 ++pub1 = 1.231013e-031 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.3 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_3 ++wvth0 = -1.0069714e-008 ++k1 = 0.79064 ++k2 = 0.0051958286 ++wk2 = -7.1987657e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12496714 ++wvoff = 2.0674286e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.032279714 ++wu0 = 8.1565714e-010 ++ua = -7.959e-010 ++wua = 8.016e-018 ++ub = 2.7193143e-018 ++wub = -2.7222857e-026 ++uc = 9.7769286e-011 ++wuc = -8.7572571e-018 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1588 ++ags = 0.27510429 ++wags = 1.9131429e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.022847143 ++wketa = -9.3497143e-010 ++dwg = 0 ++dwb = 0 ++pclm = 0.18626143 ++wpclm = 6.8777143e-009 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.6776286e-005 ++walpha0 = 6.6315429e-012 ++alpha1 = 0 ++beta0 = 23.896857 ++wbeta0 = 8.2628571e-008 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.332 ++wkt1 = -5.904e-009 ++kt1l = 0 ++kt2 = -0.021107143 ++wkt2 = 1.7142857e-010 ++ute = -1.3857143 ++wute = 1.7142857e-008 ++ua1 = 1.675e-009 ++ub1 = -2.5919e-018 ++wub1 = 3.456e-026 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.4 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_4 ++lvth0 = -4.1979273e-008 ++wvth0 = -2.1596758e-008 ++pvth0 = 2.0029964e-015 ++k1 = 0.95938091 ++lk1 = -9.9985454e-008 ++k2 = 0.041255727 ++lk2 = -3.7879164e-008 ++wk2 = -1.2782618e-008 ++pk2 = 3.5791331e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.079311948 ++lvoff = -9.2114546e-009 ++wvoff = -1.7231065e-008 ++pvoff = 4.8246982e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.033011551 ++lu0 = 4.0251818e-009 ++wu0 = 1.2335751e-010 ++pu0 = -3.5013818e-016 ++ua = -6.3005701e-010 ++lua = 3.9938436e-016 ++wua = 1.8551439e-017 ++pua = 3.8566691e-024 ++ub = 2.2836418e-018 ++lub = -9.0230909e-026 ++wub = 1.1549411e-025 ++pub = -2.4352626e-031 ++uc = 1.5877203e-010 ++luc = -3.4349127e-017 ++wuc = -1.9125195e-020 ++puc = -7.5187026e-024 ++eu = 1.67 ++vsat = 71618.182 ++lvsat = 0.0042909091 ++wvsat = 0.0097832727 ++pvsat = -2.0596364e-009 ++a0 = 0.10680558 ++la0 = -1.6983636e-009 ++wa0 = -3.7514805e-009 ++pa0 = 1.0504145e-015 ++ags = 0.35500309 ++lags = -1.1780546e-008 ++wags = 3.3067462e-008 ++pags = -1.3815011e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12490989 ++lketa = 3.0254945e-008 ++wketa = -3.3798633e-009 ++pketa = 1.6899316e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.45921829 ++lpclm = -8.0088e-008 ++wpclm = -1.9828414e-008 ++ppclm = 2.4308858e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6500109e-006 ++lalpha0 = -2.8170545e-013 ++walpha0 = 4.9740218e-014 ++palpha0 = -2.4870109e-020 ++alpha1 = 0 ++beta0 = 20.982852 ++lbeta0 = -8.9454546e-008 ++wbeta0 = -3.786053e-007 ++pbeta0 = 1.0555636e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.37773746 ++lkt1 = 1.6718727e-008 ++wkt1 = -7.0851491e-009 ++pkt1 = 3.5425745e-015 ++kt1l = 0 ++kt2 = -0.014603854 ++lkt2 = -3.3230727e-009 ++wkt2 = -3.8010589e-009 ++pkt2 = 1.9005294e-015 ++ute = -1.4342857 ++wute = 4.0457143e-008 ++ua1 = 1.675e-009 ++ub1 = -3.65896e-018 ++lub1 = 2.4878e-025 ++wub1 = 7.7854254e-026 ++pub1 = -3.8927127e-032 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.5 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_5 ++lvth0 = -1.7716408e-008 ++wvth0 = -1.0974289e-008 ++pvth0 = -3.3082384e-015 ++k1 = 0.76833212 ++lk1 = -4.4610612e-009 ++wk1 = -1.0528104e-008 ++pk1 = 5.2640522e-015 ++k2 = 0.0082103273 ++lk2 = -2.1356464e-008 ++wk2 = 4.4440669e-009 ++pk2 = -5.0342094e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12049225 ++lvoff = 1.1378694e-008 ++wvoff = 5.4154776e-009 ++pvoff = -6.4985731e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.031181163 ++lu0 = 4.9403755e-009 ++wu0 = 1.3466449e-010 ++pu0 = -3.5579167e-016 ++ua = -1.1586455e-009 ++lua = 6.6367861e-016 ++wua = -1.8760555e-017 ++pua = 2.2512666e-023 ++ub = 2.8240225e-018 ++lub = -3.6042122e-025 ++wub = 9.755951e-026 ++pub = -2.3455895e-031 ++uc = 8.1997037e-011 ++luc = 4.0383673e-018 ++wuc = 3.4959595e-018 ++puc = -9.2762449e-024 ++eu = 1.67 ++vsat = 88428.571 ++lvsat = -0.0041142857 ++wvsat = -0.0040457143 ++pvsat = 4.8548571e-009 ++a0 = 0.97533082 ++la0 = -4.3596098e-007 ++wa0 = 1.1790367e-009 ++pa0 = -1.4148441e-015 ++ags = 0.441074 ++lags = -5.4816e-008 ++wags = 6.1365394e-008 ++pags = -2.7963977e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.21719837 ++lpclm = 4.0921959e-008 ++wpclm = -2.0563788e-008 ++ppclm = 2.4676545e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.8164074e-006 ++lalpha0 = -2.3649037e-012 ++walpha0 = -1.3260696e-013 ++palpha0 = 6.6303478e-020 ++alpha1 = 0 ++beta0 = 21.036008 ++lbeta0 = -1.1603265e-007 ++wbeta0 = 4.1231608e-007 ++pbeta0 = -2.8990433e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.4079911 ++lkt1 = 3.1845551e-008 ++wkt1 = 3.0571729e-008 ++pkt1 = -1.5285865e-014 ++kt1l = 0 ++kt2 = -0.031229592 ++lkt2 = 4.9897959e-009 ++wkt2 = 5.2016327e-009 ++pkt2 = -2.6008163e-015 ++ute = -1.4342857 ++wute = 4.0457143e-008 ++ua1 = 1.675e-009 ++ub1 = -2.8098294e-018 ++lub1 = -1.7578531e-025 ++wub1 = 5.9506678e-026 ++pub1 = -2.9753339e-032 ++uc1 = -1.1888774e-010 ++luc1 = 3.1443869e-017 ++wuc1 = 3.0186115e-017 ++puc1 = -1.5093057e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.6 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_6 ++lvth0 = 1.325026e-008 ++wvth0 = -4.067414e-009 ++pvth0 = -1.1596488e-014 ++k1 = 0.79418892 ++lk1 = -3.5489221e-008 ++wk1 = 8.3746286e-010 ++pk1 = -8.3746286e-015 ++k2 = -0.0057236965 ++lk2 = -4.6356351e-009 ++wk2 = -2.005398e-009 ++pk2 = 2.7051485e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036490513 ++lu0 = -1.4308442e-009 ++wu0 = -1.2698026e-009 ++pu0 = 1.3295688e-015 ++ua = -7.881063e-010 ++lua = 2.1903156e-016 ++wua = -7.0891948e-018 ++pua = 8.5070338e-024 ++ub = 3.0594896e-018 ++lub = -6.4298182e-025 ++wub = -1.6806265e-025 ++pub = 8.4187636e-032 ++uc = 9.7557278e-011 ++luc = -1.4633922e-017 ++wuc = -8.460177e-018 ++puc = 5.071119e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.2333595 ++la0 = -7.4559545e-007 ++ags = 0.28370796 ++lags = 1.3402325e-007 ++wags = -1.501953e-008 ++pags = 6.3697932e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.22708279 ++lpclm = 2.9060649e-008 ++wpclm = -1.603574e-008 ++ppclm = 1.9242888e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0921047e-005 ++lalpha0 = -1.0329047e-010 ++walpha0 = 1.0548281e-014 ++palpha0 = -1.0548281e-019 ++alpha1 = 0 ++beta0 = 24.039866 ++lbeta0 = -3.7206623e-006 ++wbeta0 = 1.9555512e-007 ++pbeta0 = -2.9791169e-014 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33923366 ++lkt1 = -5.0663377e-008 ++wkt1 = -2.4318421e-009 ++pkt1 = 2.4318421e-014 ++kt1l = 0 ++kt2 = -0.021803571 ++lkt2 = -6.3214286e-009 ++wkt2 = 5.0571429e-010 ++pkt2 = 3.0342857e-015 ++ute = -1.7216234 ++lute = 3.448052e-007 ++wute = 1.7837922e-007 ++pute = -1.6550649e-013 ++ua1 = 1.675e-009 ++ub1 = -3.5465249e-018 ++lub1 = 7.0824935e-025 ++wub1 = 5.1661197e-025 ++pub1 = -5.7827969e-031 ++uc1 = -5.0997566e-011 ++luc1 = -5.0024338e-017 ++wuc1 = -2.4011682e-018 ++puc1 = 2.4011682e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.7 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_7 ++wvth0 = -5.2270629e-009 ++k1 = 0.79064 ++k2 = -0.00618726 ++wk2 = -1.7348832e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.036347429 ++wu0 = -1.1368457e-009 ++ua = -7.6620314e-010 ++wua = -6.2384914e-018 ++ub = 2.9951914e-018 ++wub = -1.5964389e-025 ++uc = 9.6093886e-011 ++wuc = -7.9530651e-018 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1588 ++ags = 0.29711029 ++wags = -8.6497371e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.22998886 ++wpclm = -1.4111451e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 23.6678 ++wbeta0 = 1.92576e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.3443 ++kt1l = 0 ++kt2 = -0.022435714 ++wkt2 = 8.0914286e-010 ++ute = -1.6871429 ++wute = 1.6182857e-007 ++ua1 = 1.675e-009 ++ub1 = -3.4757e-018 ++wub1 = 4.58784e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.8 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_8 ++lvth0 = -5.5747725e-008 ++wvth0 = -5.7737207e-008 ++pvth0 = 1.824977e-014 ++k1 = 0.95060511 ++lk1 = -9.5597554e-008 ++wk1 = 1.0355446e-008 ++pk1 = -5.177723e-015 ++k2 = 0.013945175 ++lk2 = -3.0232209e-008 ++wk2 = 1.9443834e-008 ++pk2 = -5.4442735e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12424632 ++lvoff = 6.8691116e-010 ++wvoff = 3.5791497e-008 ++pvoff = -6.8553733e-015 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.046898182 ++lu0 = 1.7050207e-010 ++wu0 = -1.6262868e-008 ++pu0 = 4.1983839e-015 ++ua = -6.6207759e-010 ++lua = 2.5458994e-016 ++wua = 5.6335718e-017 ++pua = 1.7471409e-022 ++ub = 3.7962141e-018 ++lub = -3.3240512e-025 ++wub = -1.6693412e-024 ++pub = 4.2239319e-032 ++uc = 2.9436835e-010 ++luc = -6.8059408e-017 ++wuc = -1.6002278e-016 ++puc = 3.2259428e-023 ++eu = 1.67 ++vsat = 85682.645 ++lvsat = -0.00034132231 ++wvsat = -0.0068127934 ++pvsat = 3.4063967e-009 ++a0 = 0.10362636 ++la0 = -8.0818182e-010 ++ags = 0.2705431 ++lags = 3.2753448e-008 ++wags = 1.3273025e-007 ++pags = -6.6365124e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12424077 ++lketa = 2.9920384e-008 ++wketa = -4.1694295e-009 ++pketa = 2.0847148e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.20476889 ++lpclm = -9.798626e-009 ++wpclm = 2.8042187e-007 ++ppclm = -5.8632603e-014 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.5953123e-006 ++lalpha0 = -2.5435614e-013 ++walpha0 = 1.1428461e-013 ++palpha0 = -5.7142305e-020 ++alpha1 = 0 ++beta0 = 21.140586 ++wbeta0 = -5.6473191e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.59809917 ++lnoff = 1.2990496e-006 ++wnoff = 3.065757e-006 ++pnoff = -1.5328785e-012 ++voffcv = 0.22872521 ++lvoffcv = -1.118626e-007 ++wvoffcv = -2.6399574e-007 ++pvoffcv = 1.3199787e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28115299 ++lkt1 = -1.0099496e-008 ++wkt1 = -1.2105482e-007 ++pkt1 = 3.5188078e-014 ++kt1l = 0 ++kt2 = -0.025449687 ++lkt2 = 9.6575269e-010 ++wkt2 = 8.9970236e-009 ++pkt2 = -3.1602845e-015 ++ute = -1.5701136 ++wute = 2.0073409e-007 ++ua1 = 1.675e-009 ++ub1 = -5.3788142e-018 ++lub1 = 4.827456e-025 ++wub1 = 2.1072821e-024 ++pub1 = -3.1500653e-031 ++uc1 = -2.2938539e-010 ++luc1 = 4.973267e-017 ++wuc1 = 2.0459475e-016 ++puc1 = -5.8684551e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.9 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_9 ++lvth0 = -9.953513e-009 ++wvth0 = 3.6992425e-009 ++pvth0 = -1.2468455e-014 ++k1 = 0.75941 ++k2 = 0.017155231 ++lk2 = -3.1837237e-008 ++wk2 = -6.1109193e-009 ++pk2 = 7.3331031e-015 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10253679 ++lvoff = -1.0167857e-008 ++wvoff = -1.5771964e-008 ++pvoff = 1.8926357e-014 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.038465008 ++lu0 = 4.387089e-009 ++wu0 = -8.4602728e-009 ++pu0 = 2.9708645e-016 ++ua = -9.289245e-010 ++lua = 3.880134e-016 ++wua = -2.8983135e-016 ++pua = 3.4779762e-022 ++ub = 3.4725304e-018 ++lub = -1.7056325e-025 ++wub = -6.6767982e-025 ++pub = -4.5859137e-031 ++uc = 1.5722431e-010 ++luc = 5.1261039e-019 ++wuc = -8.5272224e-017 ++puc = -5.1158517e-024 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.57970277 ++la0 = -2.3884638e-007 ++wa0 = 4.6802014e-007 ++pa0 = -2.3401007e-013 ++ags = 0.63340774 ++lags = -1.4867887e-007 ++wags = -1.6558842e-007 ++pags = 8.279421e-014 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.047719 ++lpclm = 6.8726318e-008 ++wpclm = 1.7942187e-007 ++ppclm = -8.1325983e-015 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7040286e-006 ++lalpha0 = -2.3087143e-012 ++alpha1 = 0 ++beta0 = 21.043581 ++lbeta0 = 4.8502597e-008 ++wbeta0 = 4.0337993e-007 ++pbeta0 = -4.8405592e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30297354 ++lkt1 = 8.1077922e-010 ++wkt1 = -9.3348999e-008 ++pkt1 = 2.1335166e-014 ++kt1l = 0 ++kt2 = -0.021799026 ++lkt2 = -8.5957792e-010 ++wkt2 = -5.9264351e-009 ++pkt2 = 4.3014448e-015 ++ute = -1.5701136 ++wute = 2.0073409e-007 ++ua1 = 1.675e-009 ++ub1 = -3.0334126e-018 ++lub1 = -6.899552e-025 ++wub1 = 3.2333483e-025 ++pub1 = 5.7696713e-031 ++uc1 = -1.4511739e-010 ++luc1 = 7.5986727e-018 ++wuc1 = 6.1137104e-017 ++puc1 = 1.3044275e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.10 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_10 ++lvth0 = 7.3817355e-009 ++wvth0 = -2.7981116e-009 ++pvth0 = -4.6716298e-015 ++k1 = 0.79747612 ++lk1 = -4.5679339e-008 ++wk1 = -3.0414256e-009 ++pk1 = 3.6497107e-015 ++k2 = -0.0074231864 ++lk2 = -2.3431364e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040494054 ++lu0 = 1.9522345e-009 ++wu0 = -5.9939808e-009 ++pu0 = -2.662464e-015 ++ua = -8.1072595e-010 ++lua = 2.4617513e-016 ++wua = 1.9601988e-017 ++pua = -2.3522386e-023 ++ub = 3.1895805e-018 ++lub = 1.6897655e-025 ++wub = -3.2156993e-025 ++pub = -8.7392324e-031 ++uc = 1.0432829e-010 ++luc = 6.3987831e-017 ++wuc = -1.6449976e-017 ++puc = -8.7702549e-023 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.175342 ++la0 = -9.536135e-007 ++wa0 = 6.8460666e-008 ++pa0 = 2.454613e-013 ++ags = 0.26729169 ++lags = 2.9066039e-007 ++wags = 4.3516718e-009 ++pags = -1.211339e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23344442 ++lpclm = -1.5414418e-007 ++wpclm = -2.3542459e-008 ++ppclm = 2.3542459e-013 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0929986e-005 ++lalpha0 = -1.0337986e-010 ++alpha1 = 0 ++beta0 = 24.512311 ++lbeta0 = -4.1139731e-006 ++wbeta0 = -3.6192965e-007 ++pbeta0 = 4.3431558e-013 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.128874 ++lnoff = -1.5464876e-007 ++wnoff = -1.5207128e-007 ++pnoff = 1.8248554e-013 ++voffcv = -0.065880682 ++lvoffcv = 8.5056818e-008 ++wvoffcv = 8.3639205e-008 ++pvoffcv = -1.0036705e-013 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31506405 ++lkt1 = 1.5319401e-008 ++wkt1 = -3.095198e-008 ++pkt1 = -5.3541257e-014 ++kt1l = 0 ++kt2 = -0.016812862 ++lkt2 = -6.8429752e-009 ++wkt2 = -5.3833233e-009 ++pkt2 = 3.6497107e-015 ++ute = -1.5472572 ++lute = -2.7427686e-008 ++wute = -2.7372831e-008 ++pute = 2.7372831e-013 ++ua1 = 1.6533492e-009 ++lua1 = 2.5980992e-017 ++wua1 = 2.5547975e-017 ++pua1 = -3.065757e-023 ++ub1 = -2.1483391e-018 ++lub1 = -1.7520434e-024 ++wub1 = -1.1332474e-024 ++pub1 = 2.3248657e-030 ++uc1 = -4.4711114e-011 ++luc1 = -1.1288886e-016 ++wuc1 = -9.8191818e-018 ++puc1 = 9.8191818e-023 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.11 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_11 ++wvth0 = -3.2652745e-009 ++k1 = 0.79290818 ++wk1 = -2.6764545e-009 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040689277 ++wu0 = -6.2602272e-009 ++ua = -7.8610843e-010 ++wua = 1.7249749e-017 ++ub = 3.2064782e-018 ++wub = -4.0896225e-025 ++uc = 1.1072708e-010 ++wuc = -2.5220231e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.0799807 ++wa0 = 9.3006796e-008 ++ags = 0.29635773 ++wags = -7.7617182e-009 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.100914 ++wbeta0 = -3.1849809e-007 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1134091 ++wnoff = -1.3382273e-007 ++voffcv = -0.057375 ++wvoffcv = 7.36025e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31353211 ++wkt1 = -3.6306106e-008 ++kt1l = 0 ++kt2 = -0.017497159 ++wkt2 = -5.0183523e-009 ++ute = -1.55 ++ua1 = 1.6559473e-009 ++wua1 = 2.2482218e-017 ++ub1 = -2.3235434e-018 ++wub1 = -9.0076078e-025 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.12 nmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_12 ++lvth0 = -5.3919091e-008 ++k1 = 0.95164273 ++lk1 = -9.6116364e-008 ++k2 = 0.015893454 ++lk2 = -3.0777727e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.045268636 ++lu0 = 5.9118182e-010 ++ua = -6.5643273e-010 ++lua = 2.7209636e-016 ++ub = 3.6289455e-018 ++lub = -3.2817273e-025 ++uc = 2.78334e-010 ++luc = -6.4827e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.13211844 ++la0 = -1.5054221e-008 ++wa0 = -2.8435094e-007 ++pa0 = 1.4217547e-013 ++ags = 0.46155061 ++lags = -6.2750307e-008 ++wags = -1.7735247e-006 ++pags = 8.8676235e-013 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.12105603 ++lketa = 2.8328017e-008 ++wketa = -3.5953066e-008 ++pketa = 1.7976533e-014 ++dwg = 0 ++dwb = 0 ++pclm = 0.23286727 ++lpclm = -1.5673636e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.003171 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0036363636 ++ldelta = 3.1818182e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 2.6067636e-006 ++lalpha0 = -2.6008182e-013 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.3e-010 ++cgdo = 2.3e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = -0.29090909 ++lnoff = 1.1454545e-006 ++voffcv = 0.20227273 ++lvoffcv = -9.8636364e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29328273 ++lkt1 = -6.5736364e-009 ++kt1l = 0 ++kt2 = -0.024548182 ++lkt2 = 6.4909091e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -5.1676636e-018 ++lub1 = 4.5118182e-025 ++uc1 = -2.0888491e-010 ++luc1 = 4.3852454e-017 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.13 nmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_13 ++lvth0 = -1.1202857e-008 ++k1 = 0.75941 ++k2 = 0.016542914 ++lk2 = -3.1102457e-008 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.10411714 ++lvoff = -8.2714286e-009 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.037617286 ++lu0 = 4.4168571e-009 ++ua = -9.5796571e-010 ++lua = 4.2286286e-016 ++ub = 3.4056286e-018 ++lub = -2.1651429e-025 ++uc = 1.4868e-010 ++eu = 1.67 ++vsat = 85000 ++a0 = 0.62659857 ++la0 = -2.6229429e-007 ++ags = 0.61681571 ++lags = -1.4038286e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.043888571 ++lketa = -1.0255714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.065697143 ++lpclm = 6.7911429e-008 ++pdiblc1 = 0.39 ++pdiblc2 = 0.001359 ++lpdiblc2= 9.06e-010 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0014285714 ++ldelta = 4.2857143e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 6.7040286e-006 ++lalpha0 = -2.3087143e-012 ++alpha1 = 0 ++beta0 = 21.084 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2 ++voffcv = 0.005 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31232714 ++lkt1 = 2.9485714e-009 ++kt1l = 0 ++kt2 = -0.022392857 ++lkt2 = -4.2857143e-010 ++ute = -1.55 ++ua1 = 1.675e-009 ++ub1 = -3.0010143e-018 ++lub1 = -6.3214286e-025 ++uc1 = -1.3899143e-010 ++luc1 = 8.9057143e-018 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.14 nmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 0 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_14 ++lvth0 = 6.9136364e-009 ++k1 = 0.79717136 ++lk1 = -4.5313636e-008 ++k2 = -0.0074231864 ++lk2 = -2.3431364e-009 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12197591 ++lvoff = 1.3159091e-008 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.039893455 ++lu0 = 1.6854546e-009 ++ua = -8.0876182e-010 ++lua = 2.4381818e-016 ++ub = 3.1573591e-018 ++lub = 8.1409091e-026 ++uc = 1.0268e-010 ++luc = 5.52e-017 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.1822018 ++la0 = -9.2901818e-007 ++ags = 0.26772773 ++lags = 2.7852273e-007 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.021025909 ++lketa = -3.7690909e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.23108545 ++lpclm = -1.3055455e-007 ++pdiblc1 = 0.39 ++pdiblc2 = 0.00064013636 ++lpdiblc2= 1.7686364e-009 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.0027272727 ++ldelta = 2.7272727e-009 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 9.0929986e-005 ++lalpha0 = -1.0337986e-010 ++alpha1 = 0 ++beta0 = 24.476046 ++lbeta0 = -4.0704545e-006 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 1e-010 ++cgdo = 1e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1136364 ++lnoff = -1.3636364e-007 ++voffcv = -0.0575 ++lvoffcv = 7.5e-008 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31816545 ++lkt1 = 9.9545454e-009 ++kt1l = 0 ++kt2 = -0.017352273 ++lkt2 = -6.4772727e-009 ++ute = -1.55 ++ua1 = 1.6559091e-009 ++lua1 = 2.2909091e-017 ++ub1 = -2.2618909e-018 ++lub1 = -1.5190909e-024 ++uc1 = -4.5695e-011 ++luc1 = -1.0305e-016 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model nmos_3p3.15 nmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = nmos_3p3_tox ++toxp = nmos_3p3_tox ++toxm = 8e-009 ++epsrox = 3.9 ++wint = 1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = nmos_3p3_xl ++xw = nmos_3p3_xw ++dlc = 3e-008 ++dwc = 0 ++xpart = 0 ++toxref = 8e-009 ++dlcig = 1.5e-007 ++vth0 = nmos_3p3_vth0_15 ++k1 = 0.79264 ++k2 = -0.0076575 ++k3 = 0 ++k3b = 0 ++w0 = 5e-007 ++dvt0 = 0 ++dvt1 = 0.53 ++dvt2 = 0 ++dvt0w = 0 ++dvt1w = 0 ++dvt2w = 0 ++dsub = 0.5 ++minv = -0.25 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 1.1e-007 ++lpeb = 0 ++vbm = -3 ++xj = nmos_3p3_xj ++ngate = 6e+019 ++ndep = 3e+017 ++nsd = 1e+020 ++phin = 0.07 ++cdsc = 0 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12066 ++nfactor = 1 ++eta0 = 0.75 ++etab = -0.32 ++u0 = 0.040062 ++ua = -7.8438e-010 ++ub = 3.1655e-018 ++uc = 1.082e-010 ++eu = 1.67 ++vsat = 85000 ++a0 = 1.0893 ++ags = 0.29558 ++a1 = 0 ++a2 = 1 ++b0 = 0 ++b1 = 0 ++keta = -0.024795 ++dwg = 0 ++dwb = 0 ++pclm = 0.21803 ++pdiblc1 = 0.39 ++pdiblc2 = 0.000817 ++pdiblcb = 0.2 ++drout = 0.56 ++pvag = 0 ++delta = 0.003 ++pscbe1 = 6.6469e+008 ++pscbe2 = 1.638e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = nmos_3p3_rdsw ++rdswmin = 50 ++rdwmin = 0 ++rswmin = 0 ++prwg = 0 ++prwb = 0 ++wr = 1 ++alpha0 = 8.0592e-005 ++alpha1 = 0 ++beta0 = 24.069 ++agidl = 1.3268e-010 ++bgidl = 1.8961e+009 ++cgidl = 0.5 ++egidl = 0.8 ++cgso = 2.3e-010 ++cgdo = 2.3e-010 ++cgbo = 1e-013 ++cgdl = 1e-010 ++cgsl = 1e-010 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 0.6 ++moin = 15 ++noff = 2.1 ++voffcv = -0.05 ++tvoff = 0.001 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.31717 ++kt1l = 0 ++kt2 = -0.018 ++ute = -1.55 ++ua1 = 1.6582e-009 ++ub1 = -2.4138e-018 ++uc1 = -5.6e-011 ++prt = 0 ++at = 23000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 0.95 ++noia = nmos_3p3_noia ++noib = nmos_3p3_noib ++noic = nmos_3p3_noic ++ntnoi = 1 ++jss = 2.2959e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1.01 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++pbs = 0.70172 ++cjs = 0.00096797 ++mjs = 0.32071 ++pbsws = 0.8062 ++cjsws = 1.5663e-010 ++mjsws = 0.1 ++pbswgs = 0.74743 ++cjswgs = 5.9903e-010 ++mjswgs = 0.32059 ++tpb = 0.0018129 ++tcj = 0.0009438 ++tpbsw = 5e-005 ++tcjsw = 0.00060474 ++tpbswg = 0.0016872 ++tcjswg = 0.001 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + + +*resistor +.subckt nplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 +*------------------- +* body resistor parameters +*.param rsh_nplus_u_m=60 ++ r_rsh0=rsh_nplus_u_m ++ r_dw=-5E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.36E-3 ++ r_tc2=6.5E-7 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' + +* model for substrate capacitor +.model np_junction d ++ Level=3 ++ Cj=0.00096797 ++ Mj=0.32071 ++ Pb=0.70172 ++ Cjsw=1.5663e-010 ++ Mjsw=0.1 ++ Php=0.8062 ++ Cta=0.0009438 ++ Ctp=0.00060474 ++ Tpb=0.0018129 ++ Tphp=5e-005 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 + +d1 3 1 np_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' + +*------------------- +.ends nplus_u_m1 + +.endl nmos_3p3_stat +* +* +*************************************************************************************************** +* 3.3V PMOS statistical Models +*************************************************************************************************** +* +.lib pmos_3p3_stat + + +.subckt pmos_3p3_sab d g s b w=10u l=0.28u par=1 s_sab=0.48u d_sab=1.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m1 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m1 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_3p3 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=sa sb=sb sd=sd ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_3p3.0 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_0 ++lvth0 = -7.6827273e-009 ++wvth0 = 4.2938493e-009 ++pvth0 = 2.3570182e-015 ++k1 = 0.86959286 ++lk1 = 4.91e-009 ++wk1 = 6.7137132e-008 ++pk1 = -2.0974909e-014 ++k2 = 0.029351195 ++lk2 = -2.4890454e-008 ++wk2 = -2.1522854e-008 ++pk2 = 3.4158327e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094658091 ++lvoff = -1.6014546e-009 ++wvoff = -1.6655127e-009 ++pvoff = 8.3275636e-016 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0077071688 ++lu0 = 2.4492727e-009 ++wu0 = 6.0892675e-010 ++pu0 = -5.2642909e-016 ++ua = -2.4381818e-012 ++lua = 1.0386891e-015 ++wua = 3.3100364e-018 ++pua = -1.9180342e-022 ++ub = 6.7035533e-019 ++lub = -1.4361909e-025 ++wub = -4.8420779e-027 ++pub = 1.3557818e-033 ++uc = 8.6801065e-011 ++luc = 8.4861818e-018 ++wuc = -1.3364176e-017 ++puc = -4.4743636e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.0272635 ++la0 = -2.0434818e-007 ++wa0 = 1.1112467e-008 ++pa0 = -2.7370909e-015 ++ags = 0.19081247 ++lags = 1.0492091e-007 ++wags = -2.3219283e-008 ++pags = -1.2080073e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.066404636 ++lketa = 8.2658182e-009 ++wketa = -7.3229236e-009 ++pketa = 3.6614618e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.35627558 ++lpclm = 7.0823636e-008 ++wpclm = 2.9266005e-008 ++ppclm = 6.5406545e-015 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.1485698e-005 ++lalpha0 = -3.0054064e-012 ++walpha0 = -1.0325417e-013 ++palpha0 = 6.39288e-020 ++alpha1 = 0 ++beta0 = 39.773597 ++lbeta0 = -3.6237273e-006 ++wbeta0 = 2.1005299e-007 ++pbeta0 = 1.1827636e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28373805 ++lkt1 = -1.5974545e-008 ++wkt1 = -1.1172031e-008 ++pkt1 = 1.9400727e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.1563636e-009 ++lua1 = 1.7181818e-016 ++wua1 = 1.7869091e-016 ++pua1 = -8.9345454e-023 ++ub1 = -2.100161e-018 ++lub1 = -6.7359091e-025 ++wub1 = -1.4002317e-025 ++pub1 = 1.4950473e-031 ++uc1 = -2.5418182e-010 ++luc1 = 5.8570909e-017 ++wuc1 = 4.0843636e-017 ++puc1 = -1.4057018e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.1 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_1 ++lvth0 = 8.0902041e-009 ++wvth0 = 5.9668408e-009 ++pvth0 = 1.5205225e-015 ++k1 = 1.011648 ++lk1 = -6.6117551e-008 ++wk1 = -1.7990939e-008 ++pk1 = 2.1589126e-014 ++k2 = -0.018784 ++lk2 = -8.2285714e-010 ++wk2 = -2.5231886e-009 ++pk2 = -6.084e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12364214 ++lvoff = 1.2890571e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010288147 ++lu0 = 1.1587837e-009 ++wu0 = -2.4611069e-010 ++pu0 = -9.8910367e-017 ++ua = 3.7095469e-010 ++lua = 8.5199265e-016 ++wua = -4.3130498e-017 ++pua = -1.6858315e-022 ++ub = 1.0877988e-018 ++lub = -3.5234082e-025 ++wub = -1.9235628e-025 ++pub = 9.5112882e-032 ++uc = -1.3265853e-011 ++luc = 5.8519641e-017 ++wuc = -7.386721e-018 ++puc = -7.4630909e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1510659 ++la0 = -2.6624939e-007 ++wa0 = 3.8929322e-008 ++pa0 = -1.6645518e-014 ++ags = 0.19022326 ++lags = 1.0521551e-007 ++wags = 1.3854074e-008 ++pags = -3.0616751e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0050909592 ++lketa = -2.239102e-008 ++wketa = -2.2043755e-009 ++pketa = 1.1021878e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.25657102 ++lpclm = 1.2067592e-007 ++wpclm = 8.5357469e-008 ++ppclm = -2.1505078e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 7.5504633e-005 ++lalpha0 = -3.5014873e-011 ++walpha0 = 4.8045453e-012 ++palpha0 = -2.3899709e-018 ++alpha1 = 0 ++beta0 = 42.422959 ++lbeta0 = -4.9484082e-006 ++wbeta0 = 2.7621551e-007 ++pbeta0 = 8.5195102e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30703735 ++lkt1 = -4.324898e-009 ++wkt1 = 2.5044049e-008 ++pkt1 = -1.6167967e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.2391388e-018 ++lub1 = -6.0410204e-025 ++wub1 = -3.3103837e-026 ++pub1 = 9.6045061e-032 ++uc1 = -7.5563755e-011 ++luc1 = -3.0738122e-017 ++wuc1 = 6.2211526e-018 ++puc1 = 3.2542237e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.2 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_2 ++lvth0 = -9.5551948e-009 ++wvth0 = 3.6783584e-009 ++pvth0 = 4.2667013e-015 ++k1 = 0.95493474 ++lk1 = 1.9383117e-009 ++wk1 = 3.0592208e-008 ++pk1 = -3.6710649e-014 ++k2 = -0.010993416 ++lk2 = -1.0171558e-008 ++wk2 = -1.5055864e-008 ++pk2 = 8.9552104e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097716396 ++lvoff = -1.8220325e-008 ++wvoff = 9.9120779e-010 ++pvoff = -1.1894494e-015 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0087516409 ++lu0 = 3.0025909e-009 ++wu0 = 2.1888218e-010 ++pu0 = -6.5690182e-016 ++ua = 3.9822779e-010 ++lua = 8.1926494e-016 ++wua = -5.2662561e-017 ++pua = -1.5714468e-022 ++ub = 8.5181617e-019 ++lub = -6.9161688e-026 ++wub = -1.0966152e-025 ++pub = -4.1208312e-033 ++uc = -4.4095525e-011 ++luc = 9.5515247e-017 ++wuc = 1.8553586e-018 ++puc = -1.8553586e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2626103 ++la0 = -4.001026e-007 ++wa0 = -3.4170078e-009 ++pa0 = 3.4170078e-014 ++ags = 0.15731682 ++lags = 1.4470325e-007 ++wags = 7.2894545e-010 ++pags = -1.4866597e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.00016272403 ++lketa = -2.8304903e-008 ++wketa = -3.463048e-009 ++pketa = 2.6125948e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32143299 ++lpclm = 4.2841558e-008 ++wpclm = 4.9757922e-009 ++ppclm = 7.4952935e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0020588939 ++lalpha0 = -2.415082e-009 ++walpha0 = 2.2256682e-011 ++palpha0 = -2.3332535e-017 ++alpha1 = 0 ++beta0 = 44.45026 ++lbeta0 = -7.3811688e-006 ++wbeta0 = 4.0343221e-007 ++pbeta0 = -6.7464935e-014 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.26850506 ++lkt1 = -5.0563636e-008 ++wkt1 = -1.0340166e-008 ++pkt1 = 2.6293091e-014 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.0202519e-018 ++lub1 = 3.3323377e-025 ++wub1 = 1.9133501e-025 ++pub1 = -1.7328156e-031 ++uc1 = -3.5566519e-011 ++luc1 = -7.8734805e-017 ++wuc1 = -1.2279955e-017 ++puc1 = 2.5455553e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.3 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 2.2e-007 ++wmax = 5e-007 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_3 ++wvth0 = 4.1050286e-009 ++k1 = 0.95512857 ++wk1 = 2.6921143e-008 ++k2 = -0.012010571 ++wk2 = -1.4160343e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.099538429 ++wvoff = 8.7226286e-010 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0090519 ++wu0 = 1.53192e-010 ++ua = 4.8015429e-010 ++wua = -6.8377029e-017 ++ub = 8.449e-019 ++wub = -1.100736e-025 ++uc = -3.4544e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.2226 ++ags = 0.17178714 ++wags = -7.5771429e-010 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0029932143 ++wketa = -3.2017886e-009 ++dwg = 0 ++dwb = 0 ++pclm = 0.32571714 ++wpclm = 1.2471086e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018173857 ++walpha0 = 1.9923429e-011 ++alpha1 = 0 ++beta0 = 43.712143 ++wbeta0 = 3.9668571e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.27356143 ++wkt1 = -7.7108571e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.9869286e-018 ++wub1 = 1.7400686e-025 ++uc1 = -4.344e-011 ++wuc1 = -9.7344e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.4 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_4 ++lvth0 = -2.1407273e-009 ++wvth0 = 1.4897689e-008 ++pvth0 = -5.2482182e-016 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = 0.014249873 ++lk2 = -2.0467636e-008 ++wk2 = -1.3670166e-008 ++pk2 = 1.1159673e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0091928468 ++lu0 = 1.8372909e-009 ++wu0 = -1.6362577e-010 ++pu0 = -2.0819854e-016 ++ua = -8.0522078e-011 ++lua = 7.4813818e-016 ++wua = 4.3913662e-017 ++pua = -4.0716945e-023 ++ub = 1.748897e-018 ++lub = -3.0903909e-025 ++wub = -5.6568377e-025 ++pub = 8.7374182e-032 ++uc = 8.6704408e-011 ++luc = 1.2453182e-017 ++wuc = -1.3313914e-017 ++puc = -6.5372036e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.66833429 ++la0 = -1.03128e-007 ++wa0 = 1.9775566e-007 ++pa0 = -5.5371585e-014 ++ags = 0.20459958 ++lags = 6.9689636e-008 ++wags = -3.0388584e-008 ++pags = 6.2401891e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.10490303 ++lketa = 2.2143527e-008 ++wketa = 1.2696239e-008 ++pketa = -3.5549469e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.3781492 ++lpclm = 2.7248545e-008 ++wpclm = 1.7891728e-008 ++ppclm = 2.9199702e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 1.2079775e-005 ++lalpha0 = -3.0255502e-012 ++walpha0 = -4.121738e-013 ++palpha0 = 7.4403585e-020 ++alpha1 = 0 ++beta0 = 38.238696 ++lbeta0 = -2.7152909e-006 ++wbeta0 = 1.0082017e-006 ++pbeta0 = -3.5411055e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33225761 ++lkt1 = 5.3309091e-010 ++wkt1 = 1.4058139e-008 ++pkt1 = -6.6438982e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 2.0124e-009 ++lua1 = -2.562e-016 ++wua1 = -2.66448e-016 ++pua1 = 1.33224e-022 ++ub1 = -2.8876353e-018 ++lub1 = -2.9730909e-026 ++wub1 = 2.6946346e-025 ++pub1 = -1.8530247e-031 ++uc1 = 6.432e-012 ++luc1 = -3.4608e-017 ++wuc1 = -9.4675549e-017 ++puc1 = 3.4396015e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.5 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_5 ++lvth0 = -3.242449e-010 ++wvth0 = 2.0559739e-009 ++pvth0 = 5.8960359e-015 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.026847376 ++lk2 = 8.0987755e-011 ++wk2 = 1.6697667e-009 ++pk2 = -6.5539994e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.12364214 ++lvoff = 1.2890571e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097471347 ++lu0 = 1.5601469e-009 ++wu0 = 3.5215673e-011 ++pu0 = -3.0761926e-016 ++ua = 2.6778433e-010 ++lua = 5.7398498e-016 ++wua = 1.0518093e-017 ++pua = -2.4019161e-023 ++ub = 1.2732368e-018 ++lub = -7.120898e-026 ++wub = -2.8878406e-025 ++pub = -5.1075673e-032 ++uc = 8.0016841e-012 ++luc = 5.1804544e-017 ++wuc = -1.844584e-017 ++puc = -3.9712404e-024 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.3454526 ++la0 = -4.4168718e-007 ++wa0 = -6.215178e-008 ++pa0 = 7.4582136e-014 ++ags = 0.19226653 ++lags = 7.5856163e-008 ++wags = 1.2791576e-008 ++pags = -1.5349891e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0016565918 ++lketa = -2.947969e-008 ++wketa = -3.9902465e-009 ++pketa = 4.7882958e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.55246506 ++lpclm = -5.9909388e-008 ++wpclm = -6.8507432e-008 ++ppclm = 7.2399282e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.000123026 ++lalpha0 = -5.8498663e-011 ++walpha0 = -1.9906566e-011 ++palpha0 = 9.8215995e-018 ++alpha1 = 0 ++beta0 = 43.366204 ++lbeta0 = -5.2790449e-006 ++wbeta0 = -2.1427184e-007 ++pbeta0 = 2.571262e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.28366163 ++lkt1 = -2.3764898e-008 ++wkt1 = 1.2888678e-008 ++pkt1 = -6.0591673e-015 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -3.1375788e-018 ++lub1 = 9.5240816e-026 ++wub1 = 4.3408496e-025 ++pub1 = -2.6761322e-031 ++uc1 = -9.9154286e-011 ++luc1 = 1.8185143e-017 ++wuc1 = 1.8488229e-017 ++puc1 = -2.2185874e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.6 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_6 ++lvth0 = -1.3737662e-009 ++wvth0 = 6.9590384e-009 ++pvth0 = 1.2358442e-017 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.027452061 ++lk2 = 8.0661039e-010 ++wk2 = -6.4973683e-009 ++pk2 = 3.2465626e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.095810227 ++lvoff = -2.0507727e-008 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0097323026 ++lu0 = 1.5779454e-009 ++wu0 = -2.910619e-010 ++pu0 = 8.3913818e-017 ++ua = 4.0315384e-010 ++lua = 4.1154156e-016 ++wua = -5.5224108e-017 ++pua = 5.487148e-023 ++ub = 1.1661759e-018 ++lub = 5.7264156e-026 ++wub = -2.7312856e-025 ++pub = -6.986227e-032 ++uc = 1.1632475e-012 ++luc = 6.0010667e-017 ++wuc = -2.1679203e-017 ++puc = -9.1205299e-026 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1189871 ++la0 = -1.6992857e-007 ++wa0 = 7.1267013e-008 ++pa0 = -8.5520416e-014 ++ags = 0.16561084 ++lags = 1.0784299e-007 ++wags = -3.583948e-009 ++pags = 4.3007377e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.3288581 ++lpclm = 2.0841896e-007 ++wpclm = 1.1147314e-009 ++ppclm = -1.1147314e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.002173683 ++lalpha0 = -2.519287e-009 ++walpha0 = -3.7433637e-011 ++palpha0 = 3.0854085e-017 ++alpha1 = 0 ++beta0 = 44.354662 ++lbeta0 = -6.4651948e-006 ++wbeta0 = 4.5314286e-007 ++pbeta0 = -5.4377143e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33774851 ++lkt1 = 4.1139351e-008 ++wkt1 = 2.5666423e-008 ++pkt1 = -2.1392462e-014 ++kt1l = 0 ++kt2 = -0.016947818 ++lkt2 = 4.6581818e-009 ++wkt2 = 2.0185455e-009 ++pkt2 = -2.4222546e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5969484e-018 ++lub1 = -5.5351558e-025 ++wub1 = -2.878281e-026 ++pub1 = 2.878281e-031 ++uc1 = -4.2545455e-011 ++luc1 = -4.9745455e-017 ++wuc1 = -8.6509091e-018 ++puc1 = 1.0381091e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.7 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 5e-007 ++wmax = 1.2e-006 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_7 ++wvth0 = 6.9602743e-009 ++k1 = 1.0069 ++k2 = -0.0273714 ++wk2 = -6.172712e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.0098900971 ++wu0 = -2.8267051e-010 ++ua = 4.44308e-010 ++wua = -4.973696e-017 ++ub = 1.1719023e-018 ++wub = -2.8011479e-025 ++uc = 7.1643143e-012 ++wuc = -2.1688323e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1019943 ++wa0 = 6.2714971e-008 ++ags = 0.17639514 ++wags = -3.1538743e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0019217543 ++walpha0 = -3.4348229e-011 ++alpha1 = 0 ++beta0 = 43.708143 ++wbeta0 = 3.9876571e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.33363457 ++wkt1 = 2.3527177e-008 ++kt1l = 0 ++kt2 = -0.016482 ++wkt2 = 1.77632e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.6523e-018 ++uc1 = -4.752e-011 ++wuc1 = -7.6128e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.8 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_8 ++lvth0 = -8.7733719e-009 ++wvth0 = 4.2305517e-009 ++pvth0 = 7.5670046e-015 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = -0.00067810868 ++lk2 = -1.7691446e-008 ++wk2 = 4.5419708e-009 ++pk2 = -2.2709854e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011352976 ++lu0 = 1.7890915e-009 ++wu0 = -2.7989835e-009 ++pu0 = -1.493953e-016 ++ua = 3.4788822e-010 ++lua = 6.3071157e-016 ++wua = -4.7874691e-016 ++pua = 1.0254352e-022 ++ub = 9.2772209e-019 ++lub = 3.2915171e-026 ++wub = 4.3614967e-025 ++pub = -3.2981002e-031 ++uc = 1.3375779e-010 ++luc = -7.439668e-018 ++wuc = -7.0719038e-017 ++puc = 1.7732073e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.8879706 ++la0 = -1.4725376e-007 ++wa0 = -7.0200638e-008 ++pa0 = -1.5381528e-015 ++ags = 0.3341873 ++lags = -2.4436508e-009 ++wags = -1.884856e-007 ++pags = 9.42428e-014 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.088919542 ++lketa = 1.7668152e-008 ++wketa = -6.803611e-009 ++pketa = 1.9050111e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.32482036 ++lpclm = 5.0559583e-008 ++wpclm = 8.2952909e-008 ++ppclm = 7.6023645e-016 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.723125e-006 ++lalpha0 = -2.2830898e-012 ++walpha0 = 2.4629388e-012 ++palpha0 = -8.3139811e-019 ++alpha1 = 0 ++beta0 = 37.805966 ++lbeta0 = -2.3737058e-006 ++wbeta0 = 1.5361323e-006 ++pbeta0 = -7.708444e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29596713 ++lkt1 = -8.3979897e-009 ++wkt1 = -3.0216242e-008 ++pkt1 = 4.2520201e-015 ++kt1l = 0 ++kt2 = -0.020842369 ++lkt2 = 2.1773833e-009 ++wkt2 = 9.4871699e-009 ++pkt2 = -2.6564076e-015 ++ute = -1 ++ua1 = 1.8116799e-009 ++lua1 = -1.5583996e-016 ++wua1 = -2.1569499e-017 ++pua1 = 1.078475e-023 ++ub1 = -2.5843988e-018 ++lub1 = -1.2857843e-025 ++wub1 = -1.0048507e-025 ++pub1 = -6.4708497e-032 ++uc1 = -8.5778578e-011 ++luc1 = 8.8928926e-019 ++wuc1 = 1.7821357e-017 ++puc1 = -8.9106783e-024 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.9 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_9 ++lvth0 = -7.1445584e-009 ++wvth0 = -9.069076e-009 ++pvth0 = 1.4216818e-014 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.030551827 ++lk2 = -2.7545864e-009 ++wk2 = 6.1891978e-009 ++pk2 = -3.0945989e-015 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.094286796 ++lvoff = -1.787102e-009 ++wvoff = -3.5813523e-008 ++pvoff = 1.7906761e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010127025 ++lu0 = 2.4020669e-009 ++wu0 = -4.282509e-010 ++pu0 = -1.3347616e-015 ++ua = 3.2582253e-010 ++lua = 6.4174442e-016 ++wua = -6.0288518e-017 ++pua = -1.0668567e-022 ++ub = 9.6220002e-019 ++lub = 1.5676208e-026 ++wub = 9.0680837e-026 ++pub = -1.570756e-031 ++uc = -2.7758895e-011 ++luc = 7.3318673e-017 ++wuc = 2.5182066e-017 ++puc = -3.0218479e-023 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1782327 ++la0 = -2.9238479e-007 ++wa0 = 1.4185662e-007 ++pa0 = -1.0756678e-013 ++ags = 0.20788505 ++lags = 6.0707474e-008 ++wags = -6.2630205e-009 ++pags = 3.1315103e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0066799724 ++lketa = -2.3451633e-008 ++wketa = 2.1382778e-009 ++pketa = -2.5659333e-015 ++dwg = 0 ++dwb = 0 ++pclm = 0.37778426 ++lpclm = 2.407763e-008 ++wpclm = 1.4460314e-007 ++ppclm = -3.006488e-014 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011108151 ++lalpha0 = -5.296228e-011 ++walpha0 = -5.3342836e-012 ++palpha0 = 3.0672131e-018 ++alpha1 = 0 ++beta0 = 43.187318 ++lbeta0 = -5.0643818e-006 ++wbeta0 = 3.968961e-009 ++pbeta0 = -4.7627532e-015 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.30269355 ++lkt1 = -5.0347792e-009 ++wkt1 = 3.6107623e-008 ++pkt1 = -2.8909912e-014 ++kt1l = 0 ++kt2 = -0.010621998 ++lkt2 = -2.9328019e-009 ++wkt2 = -2.981682e-009 ++pkt2 = 3.5780184e-015 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.4617658e-018 ++lub1 = -1.8989494e-025 ++wub1 = -3.9040685e-025 ++pub1 = 8.0252392e-032 ++uc1 = -3.4810909e-011 ++luc1 = -2.4594545e-017 ++wuc1 = -6.0010691e-017 ++puc1 = 3.0005345e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.10 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_10 ++lvth0 = -4.4690083e-009 ++wvth0 = -3.7885537e-010 ++pvth0 = 3.7885537e-015 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.036023042 ++lk2 = 3.8108709e-009 ++wk2 = 3.9592281e-009 ++pk2 = -4.1863519e-016 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.098145312 ++lvoff = 2.8431167e-009 ++wvoff = 2.848803e-009 ++pvoff = -2.848803e-014 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011031559 ++lu0 = 1.3166262e-009 ++wu0 = -1.8761549e-009 ++pu0 = 4.0272326e-016 ++ua = 6.676128e-010 ++lua = 2.315961e-016 ++wua = -3.7786403e-016 ++pua = 2.7440495e-022 ++ub = 9.7526352e-019 ++wub = -4.0215498e-026 ++uc = -1.6606591e-011 ++luc = 5.9935909e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1832393 ++la0 = -2.9839274e-007 ++wa0 = -7.1205867e-009 ++pa0 = 7.1205867e-014 ++ags = 0.16685819 ++lags = 1.0993971e-007 ++wags = -5.1057076e-009 ++pags = 1.7427347e-015 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34313423 ++lpclm = 6.5657665e-008 ++wpclm = -1.6302147e-008 ++ppclm = 1.6302147e-013 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0021426891 ++lalpha0 = -2.4908914e-009 ++walpha0 = 3.7885537e-013 ++palpha0 = -3.7885537e-018 ++alpha1 = 0 ++beta0 = 44.161948 ++lbeta0 = -6.233938e-006 ++wbeta0 = 6.8825393e-007 ++pbeta0 = -8.2590471e-013 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29670927 ++lkt1 = -1.2215919e-008 ++wkt1 = -2.4401443e-008 ++pkt1 = 4.3700967e-014 ++kt1l = 0 ++kt2 = -0.012757219 ++lkt2 = -3.7053719e-010 ++wkt2 = -3.0939855e-009 ++pkt2 = 3.7127826e-015 ++ute = -1 ++ua1 = 1.39597e-009 ++lua1 = 1.2483595e-016 ++wua1 = 1.2691655e-016 ++pua1 = -1.5229986e-022 ++ub1 = -2.656703e-018 ++lub1 = 4.4029649e-026 ++wub1 = 4.4117708e-026 ++pub1 = -4.4117708e-031 ++uc1 = -6.6591694e-011 ++luc1 = 1.3542397e-017 ++wuc1 = 2.0685503e-017 ++puc1 = -6.6830088e-023 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.11 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1.2e-006 ++wmax = 1e-005 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_11 ++k1 = 1.0069 ++k2 = -0.035641955 ++wk2 = 3.9173646e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011163222 ++wu0 = -1.8358826e-009 ++ua = 6.9077241e-010 ++wua = -3.5042354e-016 ++ub = 9.7526352e-019 ++wub = -4.0215498e-026 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17785216 ++wags = -4.9314341e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.538555 ++wbeta0 = 6.0566345e-007 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29793086 ++wkt1 = -2.0031346e-008 ++kt1l = 0 ++kt2 = -0.012794273 ++wkt2 = -2.7227073e-009 ++ute = -1 ++ua1 = 1.4084536e-009 ++wua1 = 1.1168656e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.5237455e-011 ++wuc1 = 1.4002494e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.12 pmos ++level = 54 ++lmin = 2.8e-007 ++lmax = 5e-007 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_12 ++lvth0 = -8.0181818e-009 ++k1 = 0.99870273 ++lk1 = -3.5426364e-008 ++k2 = -0.00022481818 ++lk2 = -1.7918091e-008 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.011073636 ++lu0 = 1.7741818e-009 ++ua = 3.0010909e-010 ++lua = 6.4094546e-016 ++ub = 9.7125e-019 ++uc = 1.267e-010 ++luc = -5.67e-018 ++eu = 1.67 ++vsat = 94000 ++a0 = 0.88096455 ++la0 = -1.4740727e-007 ++ags = 0.31537636 ++lags = 6.9618182e-009 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.089598545 ++lketa = 1.7858273e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.33309909 ++lpclm = 5.0635454e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00073695 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 9.9689273e-006 ++lalpha0 = -2.3660636e-012 ++alpha1 = 0 ++beta0 = 37.959273 ++lbeta0 = -2.4506364e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29898273 ++lkt1 = -7.9736364e-009 ++kt1l = 0 ++kt2 = -0.019895546 ++lkt2 = 1.9122727e-009 ++ute = -1 ++ua1 = 1.8095273e-009 ++lua1 = -1.5476364e-016 ++ub1 = -2.5944273e-018 ++lub1 = -1.3503636e-025 ++uc1 = -8.4e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.13 pmos ++level = 54 ++lmin = 5e-007 ++lmax = 1.2e-006 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_13 ++lvth0 = -5.7257143e-009 ++k1 = 0.97705 ++lk1 = -2.46e-008 ++k2 = -0.029934143 ++lk2 = -3.0634286e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010084286 ++lu0 = 2.2688571e-009 ++ua = 3.1980571e-010 ++lua = 6.3109714e-016 ++ub = 9.7125e-019 ++uc = -2.5245714e-011 ++luc = 7.0302857e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.19239 ++la0 = -3.0312e-007 ++ags = 0.20726 ++lags = 6.102e-008 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0064665714 ++lketa = -2.3707714e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.39221571 ++lpclm = 2.1077143e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00024628714 ++lpdiblc2= 2.4533143e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.00011054914 ++lalpha0 = -5.2656171e-011 ++alpha1 = 0 ++beta0 = 43.187714 ++lbeta0 = -5.0648571e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2.4 ++voffcv = -0.16 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29909 ++lkt1 = -7.92e-009 ++kt1l = 0 ++kt2 = -0.010919571 ++lkt2 = -2.5757143e-009 ++ute = -1 ++ua1 = 1.5e-009 ++ub1 = -2.5007286e-018 ++lub1 = -1.8188571e-025 ++uc1 = -4.08e-011 ++luc1 = -2.16e-017 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.14 pmos ++level = 54 ++lmin = 1.2e-006 ++lmax = 1e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_14 ++lvth0 = -4.0909091e-009 ++k1 = 1.0137659 ++lk1 = -6.8659091e-008 ++k2 = -0.035627909 ++lk2 = 3.7690909e-009 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.010844318 ++lu0 = 1.3568182e-009 ++ua = 6.2990182e-010 ++lua = 2.5898182e-016 ++ub = 9.7125e-019 ++uc = -1.6606591e-011 ++luc = 5.9935909e-017 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1825286 ++la0 = -2.9128636e-007 ++ags = 0.16634864 ++lags = 1.1011364e-007 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0068224318 ++lketa = -2.3280682e-008 ++dwg = 0 ++dwb = 0 ++pclm = 0.34150727 ++lpclm = 8.1927273e-008 ++pdiblc1 = 0.1484 ++pdiblc2 = 7.8434545e-005 ++lpdiblc2= 4.4675455e-010 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.002142727 ++lalpha0 = -2.4912696e-009 ++alpha1 = 0 ++beta0 = 44.230636 ++lbeta0 = -6.3163636e-006 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 1.9454546 ++lnoff = 5.4545454e-007 ++voffcv = 0.021818182 ++lvoffcv = -2.1818182e-007 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29914454 ++lkt1 = -7.8545455e-009 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4086364e-009 ++lua1 = 1.0963636e-016 ++ub1 = -2.6523e-018 ++uc1 = -6.4527273e-011 ++luc1 = 6.8727273e-018 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 +.model pmos_3p3.15 pmos ++level = 54 ++lmin = 1e-005 ++lmax = 5.0001e-005 ++wmin = 1e-005 ++wmax = 0.000100001 ++version = 4.5 ++binunit = 2 ++paramchk= 1 ++mobmod = 0 ++capmod = 2 ++igcmod = 0 ++igbmod = 0 ++geomod = 0 ++diomod = 1 ++rdsmod = 0 ++rbodymod= 0 ++rgatemod= 0 ++permod = 1 ++acnqsmod= 0 ++trnqsmod= 0 ++tnom = 25 ++toxe = pmos_3p3_tox ++toxp = pmos_3p3_tox ++toxm = 7.9e-009 ++epsrox = 3.9 ++wint = -1e-008 ++lint = 0 ++ll = 0 ++wl = 0 ++lln = 1 ++wln = 1 ++lw = 0 ++ww = 0 ++lwn = 1 ++wwn = 1 ++lwl = 0 ++wwl = 0 ++xl = pmos_3p3_xl ++xw = pmos_3p3_xw ++dlc = -8e-009 ++dwc = 0 ++xpart = 0 ++toxref = 7.9e-009 ++dlcig = 1.5e-007 ++vth0 = pmos_3p3_vth0_15 ++k1 = 1.0069 ++k2 = -0.035251 ++k3 = 0 ++k3b = 0 ++w0 = 2.5e-006 ++dvt0 = 2.8985 ++dvt1 = 0.23999 ++dvt2 = -0.016 ++dvt0w = 0 ++dvt1w = 5300000 ++dvt2w = -0.032 ++dsub = 0.3659 ++minv = -0.1 ++voffl = 0 ++dvtp0 = 0 ++dvtp1 = 0 ++lpe0 = 3.2493e-008 ++lpeb = 0 ++vbm = -3 ++xj = pmos_3p3_xj ++ngate = 6e+019 ++ndep = 5.6e+017 ++nsd = 1e+020 ++phin = 0 ++cdsc = 0.00024 ++cdscb = 0 ++cdscd = 0 ++cit = 0 ++voff = -0.097861 ++nfactor = 0.8 ++eta0 = 0.2541 ++etab = -0.15284 ++vfb = 0 ++u0 = 0.01098 ++ua = 6.558e-010 ++ub = 9.7125e-019 ++uc = -1.0613e-011 ++eu = 1.67 ++vsat = 94000 ++a0 = 1.1534 ++ags = 0.17736 ++a1 = 0 ++a2 = 0.99 ++b0 = 0 ++b1 = 0 ++keta = -0.0091505 ++dwg = 0 ++dwb = 0 ++pclm = 0.3497 ++pdiblc1 = 0.1484 ++pdiblc2 = 0.00012311 ++pdiblcb = 0 ++drout = 0.56 ++pvag = 0 ++delta = 0.01 ++pscbe1 = 6.7448e+008 ++pscbe2 = 1e-005 ++fprout = 0 ++pdits = 0 ++pditsd = 0 ++pditsl = 0 ++rsh = 7 ++rdsw = pmos_3p3_rdsw ++rdswmin = 20 ++prwg = 0 ++prwb = 0 ++alpha0 = 0.0018936 ++alpha1 = 0 ++beta0 = 43.599 ++agidl = 1.5908e-011 ++bgidl = 1.3902e+009 ++cgidl = 7.5 ++egidl = 0.1009 ++cgso = 1.24e-010 ++cgdo = 1.24e-010 ++cgbo = 1e-013 ++cgdl = 4e-011 ++cgsl = 4e-011 ++clc = 1e-007 ++cle = 0.6 ++cf = 0 ++ckappas = 0.6 ++ckappad = 0.6 ++vfbcv = -1 ++acde = 1 ++moin = 15 ++noff = 2 ++voffcv = 0 ++tvoff = 0.0032 ++ltvoff = 0 ++wtvoff = 0 ++ptvoff = 0 ++kt1 = -0.29993 ++kt1l = 0 ++kt2 = -0.013066 ++ute = -1 ++ua1 = 1.4196e-009 ++ub1 = -2.6523e-018 ++uc1 = -6.384e-011 ++prt = 0 ++at = 12000 ++fnoimod = 1 ++tnoimod = 0 ++em = 4.1e+007 ++ef = 1.12 ++noia = pmos_3p3_noia ++noib = pmos_3p3_noib ++noic = pmos_3p3_noic ++ntnoi = 1 ++jss = 1.653e-007 ++jsws = 2.1207e-013 ++jswgs = 0 ++njs = 1 ++ijthsfwd= 0.1 ++ijthsrev= 0.1 ++jtss = 1e-011 ++jtssws = 1e-011 ++jtsswgs = 1e-011 ++njts = 20 ++njtssw = 20 ++njtsswg = 20 ++vtss = 10 ++vtssws = 10 ++vtsswgs = 10 ++pbs = 0.69939 ++cjs = 0.00094344 ++mjs = 0.32084 ++pbsws = 0.8022 ++cjsws = 1.5078e-010 ++mjsws = 0.05 ++pbswgs = 0.65 ++cjswgs = 4.794e-010 ++mjswgs = 0.21964 ++tpb = 0.0016906 ++tcj = 0.00099187 ++tpbsw = 0.0052 ++tcjsw = 0.00063483 ++tpbswg = 0.000744 ++tcjswg = 0.000932 ++xtis = 3 ++dmcg = 1.5e-007 ++saref = 4.4e-007 ++sbref = 4.4e-007 ++kvth0 = 0 ++ku0 = 0 ++kvsat = 0 + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m1 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m1 + + +.endl pmos_3p3_stat +* +*************************************************************************************************** +* 6V native NMOS statistical Models +*************************************************************************************************** +* +.lib nmos_6p0_nat_stat + +*.lib nmos_6p0_nat_t +.subckt nmos_6p0_nat d g s b w=1e-5 l=1.8e-6 as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 sa=0 sb=0 nf=1 sd=0 m=1 + +m0 d g s b nmos_6p0_nat w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs sa=sa sb=sb nf=nf sd=sd + +.ends nmos_6p0_nat + +.model nmos_6p0_nat.0 nmos ++level = 54 +************************************************************** +* MODEL FLAG PARAMETERS +************************************************************** ++lmin = 1.8e-6 lmax = 50.01e-6 wmin = 0.8e-6 ++wmax = 100.01e-6 version = 4.6 binunit = 1 ++paramchk= 1 mobmod = 0 capmod = 2 ++igcmod = 0 igbmod = 0 geomod = 0 ++diomod = 1 rdsmod = 0 rbodymod= 0 ++rgeomod = 0 rgatemod= 0 permod = 1 ++acnqsmod= 0 trnqsmod= 0 tempmod = 0 ++wpemod = 0 +************************************************************** +* GENERAL MODEL PARAMETERS +************************************************************** ++tnom = 25 toxe = nmos_6p0_nat_tox toxp = '8e-10+nmos_6p0_nat_tox' ++toxm = 1.52e-008 epsrox = 3.9 toxref = 1.52e-008 ++wint = 1e-009 lint = 1e-007 ll = 0 ++wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 ++wwn = 1 lwl = 0 wwl = 0 ++llc = 0 wlc = 0 lwc = 0 ++wwc = 0 lwlc = 0 wwlc = 0 ++xl = nmos_6p0_nat_xl xw = nmos_6p0_nat_xw dlc = 0 ++dwc = 0 dlcig = 0 xpart = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++vth0 = nmos_6p0_nat_vth0 lvth0 = -0.088 k1 = 0.165 ++k2 = -0.001 k3 = -0.6 k3b = -0.6 ++w0 = 1e-010 dvt0 = 2.2 dvt1 = 0.53 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 5300000 ++dvt2w = -0.032 dsub = 0.4 minv = -0.5 ++voffl = 0 dvtp0 = 1e-008 dvtp1 = 0 ++lambda = 0 vtl = 200000 xn = 3 ++lpe0 = 1e-007 lpeb = 0 vbm = -3 ++xj = nmos_6p0_nat_xj ngate = 1e+020 ndep = 1.7e+017 ++nsd = 1e+020 phin = 0.5 cdsc = 0.00024 ++cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.06 ud1 = 0 up = 0 ++lp = 1e-008 nfactor = 0.40241 lnfactor= 0.45 ++eta0 = 0.06 etab = -0.43 u0 = 0.070102 ++lu0 = 0.042 ua = 2.278e-009 ub = 3.97e-019 ++lub = 3.65e-018 uc = 2.625e-012 eu = 1.67 ++vsat = 106700 pvsat = 23500 a0 = 0.88 ++ags = 0.72 a1 = 0 a2 = 0.47 ++b0 = 3.5e-007 b1 = 0 keta = -0.04 ++dwg = 0 dwb = 0 pclm = 3 ++pdiblc1 = 1.41 pdiblc2 = 1e-005 pdiblcb = 0 ++drout = 0.16 pvag = 1 delta = 0.005 ++pscbe1 = 5e+009 pscbe2 = 5e-006 fprout = 65 ++pdits = 0 pditsd = 0 pditsl = 0 ++rsh = 7 rdsw = nmos_6p0_nat_rdsw rsw = 100 ++rdw = 100 rdswmin = 0 rdwmin = 0 ++rswmin = 0 prwg = 1 prwb = 0 ++wr = 1 alpha0 = 1.36e-008 alpha1 = 1e-005 ++beta0 = 15 agidl = 2e-010 bgidl = 2.3e+009 ++cgidl = 0.5 egidl = 0.8 aigbacc = 0.43 ++bigbacc = 0.054 cigbacc = 0.075 nigbacc = 1 ++aigbinv = 0.35 bigbinv = 0.03 cigbinv = 0.006 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.43 ++bigc = 0.054 cigc = 0.075 aigsd = 0.43 ++bigsd = 0.054 cigsd = 0.075 nigc = 1 ++poxedge = 1 pigcd = 1 ntox = 1 ++vfbsdoff= 0 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cgso = 1e-010 cgdo = 1e-010 cgbo = 1e-013 ++cgdl = 1.5e-010 cgsl = 1.5e-010 clc = 1e-010 ++cle = 0.6 ckappas = 0.6 ckappad = 0.6 ++vfbcv = -1 acde = 0.3 moin = 15 ++noff = 1.5 voffcv = 0 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++tvoff = 0 tvfbsdoff= 0 kt1 = -0.412 ++kt1l = 3.5e-008 kt2 = -0.05 ute = -1.5 ++lute = -0.26 ua1 = 1e-009 ub1 = -1e-018 ++uc1 = -5.6e-011 prt = 0 at = 80000 ++lat = -30000 pat = -10000 +************************************************************** +* NOISE PARAMETERS +************************************************************** ++fnoimod = 1 tnoimod = 0 em = 4.1e+007 ++ef = 1 noia = nmos_6p0_nat_noia noib = nmos_6p0_nat_noib ++noic = nmos_6p0_nat_noic ntnoi = 1 lintnoi = 0 +************************************************************** +* DIODE PARAMETERS +************************************************************** ++jss = 6.88e-007 jsws = 4.88e-013 jswgs = 0 ++njs = 1.0541 ijthsfwd= 0.1 ijthsrev= 0.1 ++bvs = 11 xjbvs = 1 xjbvd = 1 ++jtss = 0 jtsd = 0 jtssws = 0 ++jtsswd = 0 jtsswgs = 0 jtsswgd = 0 ++njts = 20 njtssw = 20 njtsswg = 20 ++xtss = 0.02 xtsd = 0.02 xtssws = 0.02 ++xtsswd = 0.02 xtsswgs = 0.02 xtsswgd = 0.02 ++tnjts = 0 tnjtssw = 0 tnjtsswg= 0 ++vtss = 10 vtsd = 10 vtssws = 10 ++vtsswd = 10 vtsswgs = 10 vtsswgd = 10 ++pbs = 0.606 cjs = 0.00095 mjs = 0.296 ++pbsws = 0.48 cjsws = 1.33e-010 mjsws = 0.01 ++pbswgs = 0.861 cjswgs = 3.573e-010 mjswgs = 0.40313 ++tpb = 0.00146 tcj = 0.000825 tpbsw = 0.00313 ++tcjsw = 0.0018 tpbswg = 0.0016588 tcjswg = 0.001595 ++xtis = 3 +************************************************************** +* LAYOUT RELATED PARAMETERS +************************************************************** ++dmcg = 0 dmdg = 0 dmcgt = 0 ++xgw = 0 xgl = 0 +************************************************************** +* RF PARAMETERS +************************************************************** ++rshg = 0.1 gbmin = 1e-012 rbpb = 50 ++rbpd = 50 rbps = 50 rbdb = 50 ++rbsb = 50 ngcon = 1 xrcrg1 = 12 ++xrcrg2 = 1 rbps0 = 50 rbpsl = 0 ++rbpsw = 0 rbpsnf = 0 rbpd0 = 50 ++rbpdl = 0 rbpdw = 0 rbpdnf = 0 ++rbpbx0 = 100 rbpbxl = 0 rbpbxw = 0 ++rbpbxnf = 0 rbpby0 = 100 rbpbyl = 0 ++rbpbyw = 0 rbpbynf = 0 rbsbx0 = 100 ++rbsby0 = 100 rbdbx0 = 100 rbdby0 = 100 ++rbsdbxl = 0 rbsdbxw = 0 rbsdbxnf= 0 ++rbsdbyl = 0 rbsdbyw = 0 rbsdbynf= 0 +************************************************************** +* STRESS PARAMETERS +************************************************************** ++web = 0 wec = 0 scref = 1e-006 ++kvth0we = 0 k2we = 0 ku0we = 0 ++saref = 1e-006 sbref = 1e-006 wlod = 0 ++kvth0 = 0 lkvth0 = 0 wkvth0 = 0 ++pkvth0 = 0 llodvth = 0 wlodvth = 0 ++stk2 = 0 lodk2 = 1 lodeta0 = 1 ++ku0 = 0 lku0 = 0 wku0 = 0 ++pku0 = 0 llodku0 = 0 wlodku0 = 0 ++kvsat = 0 steta0 = 0 tku0 = 0 + +.endl nmos_6p0_nat_stat +* +*************************************************************************************************** +* 6V PMOS statistical Models +*************************************************************************************************** +* +.lib pmos_6p0_stat + + +.subckt pmos_6p0_sab d g s b w=10u l=0.5u par=1 s_sab=0.28u d_sab=2.78u as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 dtemp=0 nf=1 sa=0 sb=0 sd=0 m=1 + +.param ++ par_vth=0.01051 ++ par_k=0.00517 ++ par_l=3e-7 ++ par_w=-4e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +xr1 d d1 b pplus_u_m2 wr='w' lr='(d_sab==0) ? 1e-15 : d_sab' +xr2 s s1 b pplus_u_m2 wr='w' lr='(s_sab==0) ? 1e-15 : s_sab' +m0 d1 g s1 b pmos_6p0 w='w' l='l' as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs nf=nf sa=0 sb=0 sd=0 ++delvto='mis_vth*sw_stat_mismatch' +.ends + + +.model pmos_6p0.0 pmos +***** Flag Parameter *** ++level = 54 version = 4.6 binunit = 1 ++paramchk = 1 mobmod = 0 capmod = 2 ++rdsmod = 0 igcmod = 0 igbmod = 0 ++rbodymod = 0 trnqsmod = 0 acnqsmod = 0 ++fnoimod = 1 tnoimod = 0 diomod = 1 ++tempmod = 0 permod = 1 geomod = 1 +***** Geometry Range Parameter *** ++lmin = 0.5e-6 lmax = 50.01e-6 wmin = 0.3e-6 ++wmax = 100.01e-6 +***** Process Parameter *** ++epsrox = 3.9 toxe = pmos_6p0_tox xj = pmos_6p0_xj ++ndep = 1.7E17 ngate = 3.6E19 nsd = 6E16 ++rsh = 7 rshg = 0.1 phin = 0 ++lphin = 0.1408 +***** dW and dL Parameter *** ++wint = 4.9E-8 wl = 0 wln = 1 ++ww = -1.37E-14 wwn = 1 wwl = 3.04E-22 ++lint = 6.7E-8 ll = -5.4E-15 lln = 1 ++lw = 0 lwn = 1 lwl = -4.76E-21 ++dwg = -6.6E-9 dwb = -3E-9 xl = pmos_6p0_xl ++xw = pmos_6p0_xw +***** Vth Related Parameter *** ++vth0 = pmos_6p0_vth0 pvth0 = 7.6E-3 ++k1 = 0.9588 k2 = 8.936E-3 vfb = -1 ++k3 = -0.75 k3b = 1.2104 w0 = 3.1E-7 ++lpe0 = -4.4E-8 lpeb = -5.96E-8 dvtp0 = 0 ++dvtp1 = 0.3 dvt0 = 1 dvt1 = 1 ++dvt2 = 0 dvt0w = 0 dvt1w = 5.3E6 ++dvt2w = -0.032 +***** Mobility Related Parameter *** ++u0 = 0.0151 ua = 1.78E-9 ub = 4.88E-19 ++uc = -2.7435E-11 luc = 8.691408E-11 puc = -1.501336E-11 ++vsat = 8.55E4 a0 = 0.84 ags = 0.059 ++b0 = 2.625E-8 b1 = 0 keta = -8.6016E-5 ++wketa = 2.772E-3 a1 = 0 a2 = 1 ++rdsw = pmos_6p0_rdsw wrdsw = 213.9 prdsw = -120 ++rdswmin = 100 prwb = 0.569552 pprwb = -0.052 ++prwg = 0.0432 wr = 1 +***** Subthreshold Related Parameter *** ++voff = -0.1284 voffl = 2.19E-8 minv = 0 ++nfactor = 1 eta0 = 0.08 etab = -0.09408 ++petab = -0.012128 dsub = 0.4824 cit = 0 ++cdsc = 2.4E-4 cdscb = 0 cdscd = 0 +***** Output Resistance Related Parameter *** ++pclm = 0.42 ppclm = 0.071 pdiblc1 = 0.14 ++pdiblc2 = 1E-5 pdiblcb = 0 drout = 0.56 ++pscbe1 = 5.088E8 pscbe2 = 1E-8 pvag = 1.5 ++delta = 0.01 fprout = 0 pdits = 0.01 ++pditsl = 0 pditsd = 0 lambda = 0 ++vtl = 2E5 lc = 0 xn = 3 ++alpha0 = 9.6E-7 alpha1 = 51.5 beta0 = 50.8 ++wbeta0 = 0.22 pbeta0 = 0.14 +***** Noise Parameters *** ++ef = 1.1 noia = pmos_6p0_noia ++noib = pmos_6p0_noib noic = pmos_6p0_noic +***** Capacitance Parameter *** ++xpart = 1 cgso = 7.71E-11 cgdo = 7.71E-11 ++cgbo = 1E-13 ckappas = 0.6 ckappad = 0.6 ++dlc = 7.4E-9 noff = 1 voffcv = 0 ++acde = 0.7 moin = 15 cgsl = 5.25E-11 ++cgdl = 5.25E-11 +***** Souce/Drain Junction Diode Model Parameter *** ++ijthsrev = 0.1 ijthdrev = 0.1 ijthsfwd = 0.1 ++ijthdfwd = 0.1 xjbvs = 1 xjbvd = 1 ++bvs = 10.5 bvd = 10.5 jss = 2.0867e-007 ++jsd = 2.0867e-007 jsws = 1.6088e-013 jswd = 1.6088e-013 ++jswgs = 0 jswgd = 0 cjs = 0.000912 ++cjd = 0.000912 mjs = 0.32713 mjd = 0.32713 ++mjsws = 0.056777 mjswd = 0.056777 cjsws = 1.4649e-010 ++cjswd = 1.4649e-010 cjswgs = 3.3229e-010 cjswgd = 3.3229e-010 ++mjswgs = 0.50996 mjswgd =0.50996 pbs = 0.76836 ++pbd = 0.76836 pbsws = 0.5 pbswd = 0.5 ++pbswgs = 1.2295 pbswgd = 1.2295 +***** Temperature coefficient *** ++tnom = 25 ute = -1.2 lute = -0.152467 ++wute = -0.07 kt1 = -0.3828 pkt1 = 2.2E-3 ++kt1l = -3.158E-8 kt2 = -0.09064 ua1 = 1.41E-9 ++lua1 = -6.554813E-10 wua1 = -1.2E-10 pua1 = -3.823641E-10 ++ub1 = -4.31E-18 lub1 = 1.939773E-19 pub1 = 7.291324E-19 ++uc1 = 1.147552E-10 luc1 = -1.067674E-10 puc1 = 1.8536E-11 ++at = -2.18E4 pat = -6.1E3 prt = 454 ++njs = 1 njd = 1 xtis = 3 ++xtid = 3 tpb = 0.0019314 tpbsw = 0.0017642 ++tpbswg = 0.0016588 tcj = 0.001 tcjsw = 0.00071888 ++tcjswg = 0.0009411 + + + + +* model for unsalicided p+ diffusion resistor +.subckt pplus_u_m2 1 2 3 lr=lr wr=wr dtemp=0 par=1 +*------------------- +* body resistor parameters +*.param rsh_pplus_u_m=185 ++ r_rsh0=rsh_pplus_u_m ++ r_dw=2.75E-8 ++ r_dl=0 ++ r_vc1=0 ++ r_vc2=0 ++ r_tc1=1.375E-3 ++ r_tc2=1E-6 ++ r_tnom=25 ++ r_l='lr-2*r_dl' ++ r_w='wr-2*r_dw' ++ r_n='r_l/r_w' ++ r_temp='1+r_tc1*(temper+dtemp-r_tnom)+r_tc2*(temper+dtemp-r_tnom)*(temper+dtemp-r_tnom)' +* model for substrate capacitor +.model pn_junction d ++ Level=3 ++ Cj=0.00094344 ++ Mj=0.32084 ++ Pb=0.69939 ++ Cjsw=1.5078e-010 ++ Mjsw=0.05 ++ Php=0.8022 ++ Cta=0.00099187 ++ Ctp=0.00063483 ++ Tpb=0.0016906 ++ Tphp=0.0058423 ++ Tlevc=1 ++ Tref=25 +*------------------- +* terminal 1 +d1 1 3 pn_junction area='r_w*r_l' pj='2*(r_w+r_l)' +* body +rb 1 2 r='r_temp*r_n*(r_rsh0+r_vc1*abs(v(1,2))/r_n+r_vc2*abs(v(1,2))*abs(v(1,2))/r_n/r_n)' +*------------------- +.ends pplus_u_m2 + + +.endl pmos_6p0_stat +* + +.LIB efuse +****************************************************************************** +* +* A single resistor is used to simulate the resistance. +* +* Rfuse +* in o--/\/\/\/--o out +* +******************************************************************************* +* +* SYNTAX: +* +* Specify fuse as intact (default, pblow=0) or programmed (pblow=1). +* +* xxx in out efuse (pblow=0) +* +* NOTES: +* +* 1. Model values based on PCELL layout as provided in the design kit. No +* other geometries or layouts are supported. +* +* 2. Resistance toggles between maximum spec value for intact fuse (<200 ohm) +* and minimum end of life value for programmed fuse (> 900 ohm). +* +******************************************************************************* +* +.subckt efuse in out pblow=0 +* +rfuse in out r='200*(1-pblow) + 900*pblow' +* +.ends efuse + +.ENDL efuse + +.lib fets_mm +.subckt nmos_3p3 d g s b w=1e-5 l=2.8e-7 ++ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 ++ sa=0 sb=0 nf=1 sd=0 m=1 + +.param ++ par_vth=0.007148 ++ par_k=0.007008 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +m0 d g s b nmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs ++delvto='mis_vth*sw_stat_mismatch' sa=sa sb=sb nf=nf sd=sd +.ends nmos_3p3 +*------------------------------------------------------------------------ +.subckt pmos_3p3 d g s b w=1e-5 l=2.8e-7 ++ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 ++ sa=0 sb=0 nf=1 sd=0 m=1 + +.param ++ par_vth=0.00666 ++ par_k=0.002833 ++ par_l=1.5e-7 ++ par_w=-1e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +m0 d g s b pmos_3p3 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs ++delvto='mis_vth*sw_stat_mismatch' sa=sa sb=sb nf=nf sd=sd +.ends pmos_3p3 +*------------------------------------------------------------------------ +.subckt nmos_6p0 d g s b w=1e-5 l=7e-7 ++ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 ++ sa=0 sb=0 nf=1 sd=0 m=1 + +.param ++ par_vth=0.01155 ++ par_k=0.0000 ++ par_l=4e-7 ++ par_w=-5e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +m0 d g s b nmos_6p0 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs ++delvto='mis_vth*sw_stat_mismatch' sa=sa sb=sb nf=nf sd=sd +.ends nmos_6p0 +*------------------------------------------------------------------------ +.subckt pmos_6p0 d g s b w=1e-5 l=5e-7 ++ as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0 par=1 dtemp=0 ++ sa=0 sb=0 nf=1 sd=0 m=1 + +.param ++ par_vth=0.01051 ++ par_k=0.00517 ++ par_l=3e-7 ++ par_w=-4e-7 ++ par_leff='l-par_l' ++ par_weff='par*(w-par_w)' ++ p_sqrtarea='sqrt((par_leff)*(par_weff))' + +.param ++ var_k='0.7071*par_k* 1e-06 / p_sqrtarea' ++ mis_k=agauss(0,var_k,1) + +.param ++ var_vth='0.7071*par_vth* 1e-06 / p_sqrtarea' ++ mis_vth=agauss(0,var_vth,1) + +m0 d g s b pmos_6p0 w=w l=l as=as ad=ad ps=ps pd=pd nrd=nrd nrs=nrs ++delvto='mis_vth*sw_stat_mismatch' sa=sa sb=sb nf=nf sd=sd +.ends pmos_6p0 +*------------------------------------------------------------------------ + +.endl fets_mm + +.LIB res_statistical_par +.param ++mc_rsh_nplus_u=0 ++mc_rsh_pplus_u=0 ++mc_rsh_nplus_s=0 ++mc_rsh_pplus_s=0 ++mc_rsh_npolyf_u=0 ++mc_rsh_ppolyf_u=0 ++mc_rsh_npolyf_s=0 ++mc_rsh_ppolyf_s=0 ++mc_rsh_ppolyf_u_1k=0 ++mc_rsh_ppolyf_u_2k=0 ++mc_rsh_ppolyf_u_1k_6p0=0 ++mc_rsh_ppolyf_u_2k_6p0=0 ++mc_rsh_ppolyf_u_3k=0 + ++mc_dw_nplus_u=0 ++mc_dw_pplus_u=0 ++mc_dw_nplus_s=0 ++mc_dw_pplus_s=0 ++mc_dw_npolyf_u=0 ++mc_dw_ppolyf_u=0 ++mc_dw_npolyf_s=0 ++mc_dw_ppolyf_s=0 ++mc_dw_ppolyf_u_1k=0 ++mc_dw_ppolyf_u_2k=0 ++mc_dw_ppolyf_u_1k_6p0=0 ++mc_dw_ppolyf_u_2k_6p0=0 ++mc_dw_ppolyf_u_3k=0 + ++mc_rt_nplus_u=0 ++mc_rt_pplus_u=0 ++mc_rt_npolyf_u=0 ++mc_rt_ppolyf_u=0 ++mc_rt_ppolyf_u_1k=0 ++mc_rt_ppolyf_u_2k=0 ++mc_rt_ppolyf_u_1k_6p0=0 ++mc_rt_ppolyf_u_2k_6p0=0 ++mc_rt_ppolyf_u_3k=0 + +.ENDL res_statistical_par + +.lib res_statistical +.param ++rsh_nplus_u=60 ++rsh_pplus_u=185 ++rsh_nplus_s=6.3 ++rsh_pplus_s=7 ++rsh_nwell=1000 ++rsh_npolyf_u=310 ++rsh_ppolyf_u=350 ++rsh_npolyf_s=6.8 ++rsh_ppolyf_s=7.3 +* ++rsh_ppolyf_u_1k=1000 ++rsh_ppolyf_u_2k=2000 ++rsh_ppolyf_u_1k_6p0=1000 ++rsh_ppolyf_u_2k_6p0=2000 ++rsh_ppolyf_u_3k=3000 ++rsh_rm1=0.09 ++rsh_rm2=0.09 ++rsh_rm3=0.09 ++rsh_tm6k=60e-3 ++rsh_tm9k=40e-3 ++rsh_tm11k=40e-3 ++rsh_tm30k=9.5e-3 + +.param ++ mc_rsh_nplus_u_temp=agauss(0, 3.8, 3) ++ mc_rsh_pplus_u_temp=agauss(0, 10.055, 3) ++ mc_rsh_nplus_s_temp=agauss(0, 1.33, 3) ++ mc_rsh_pplus_s_temp=agauss(0, 1.4917, 3) ++ mc_rsh_npolyf_u_temp=agauss(0, 15.135, 3) ++ mc_rsh_ppolyf_u_temp=agauss(0, 18.116, 3) ++ mc_rsh_npolyf_s_temp=agauss(0, 1.392, 3) ++ mc_rsh_ppolyf_s_temp=agauss(0, 1.5852, 3) ++ mc_rsh_ppolyf_u_1k_temp=agauss(0, 49.754, 3) ++ mc_rsh_ppolyf_u_2k_temp=agauss(0, 101.518, 3) ++ mc_rsh_ppolyf_u_1k_6p0_temp=agauss(0, 51.894, 3) ++ mc_rsh_ppolyf_u_2k_6p0_temp=agauss(0, 99.242, 3) ++ mc_rsh_ppolyf_u_3k_temp=agauss(0, 184.603, 3) + ++ mc_dw_nplus_u_temp=agauss(0, 0.0144, 3) ++ mc_dw_pplus_u_temp=agauss(0, 0.0144, 3) ++ mc_dw_nplus_s_temp=agauss(0, 0.012, 3) ++ mc_dw_pplus_s_temp=agauss(0, 0.018, 3) ++ mc_dw_npolyf_u_temp=agauss(0, 0.0167, 3) ++ mc_dw_ppolyf_u_temp=agauss(0, 0.0167, 3) ++ mc_dw_npolyf_s_temp=agauss(0, 0.006, 3) ++ mc_dw_ppolyf_s_temp=agauss(0, 0.003, 3) ++ mc_dw_ppolyf_u_1k_temp=agauss(0, 0.0167, 3) ++ mc_dw_ppolyf_u_2k_temp=agauss(0, 0.0167, 3) ++ mc_dw_ppolyf_u_1k_6p0_temp=agauss(0, 0.0167, 3) ++ mc_dw_ppolyf_u_2k_6p0_temp=agauss(0, 0.0167, 3) ++ mc_dw_ppolyf_u_3k_temp=agauss(0, 0.0167, 3) + ++ mc_rt_nplus_u_temp=agauss(0, 0.64, 3) ++ mc_rt_pplus_u_temp=agauss(0, 7.2, 3) ++ mc_rt_npolyf_u_temp=agauss(0, 4.8, 3) ++ mc_rt_ppolyf_u_temp=agauss(0, 4.7, 3) ++ mc_rt_ppolyf_u_1k_temp=agauss(0, 6.838, 3) ++ mc_rt_ppolyf_u_2k_temp=agauss(0, 6.838, 3) ++ mc_rt_ppolyf_u_1k_6p0_temp=agauss(0, 6.838, 3) ++ mc_rt_ppolyf_u_2k_6p0_temp=agauss(0, 6.838, 3) ++ mc_rt_ppolyf_u_3k_temp=agauss(0, 6.93, 3) +************************************************************** ++ mc_rsh_nplus_u=mc_rsh_nplus_u_temp ++ mc_rsh_pplus_u=mc_rsh_pplus_u_temp ++ mc_rsh_nplus_s=mc_rsh_nplus_s_temp ++ mc_rsh_pplus_s=mc_rsh_pplus_s_temp ++ mc_rsh_npolyf_u=mc_rsh_npolyf_u_temp ++ mc_rsh_ppolyf_u=mc_rsh_ppolyf_u_temp ++ mc_rsh_npolyf_s=mc_rsh_npolyf_s_temp ++ mc_rsh_ppolyf_s=mc_rsh_ppolyf_s_temp ++ mc_rsh_ppolyf_u_1k=mc_rsh_ppolyf_u_1k_temp ++ mc_rsh_ppolyf_u_2k=mc_rsh_ppolyf_u_2k_temp ++ mc_rsh_ppolyf_u_1k_6p0=mc_rsh_ppolyf_u_1k_6p0_temp ++ mc_rsh_ppolyf_u_2k_6p0=mc_rsh_ppolyf_u_2k_6p0_temp ++ mc_rsh_ppolyf_u_3k=mc_rsh_ppolyf_u_3k_temp + ++ mc_dw_nplus_u=mc_dw_nplus_u_temp ++ mc_dw_pplus_u=mc_dw_pplus_u_temp ++ mc_dw_nplus_s=mc_dw_nplus_s_temp ++ mc_dw_pplus_s=mc_dw_pplus_s_temp ++ mc_dw_npolyf_u=mc_dw_npolyf_u_temp ++ mc_dw_ppolyf_u=mc_dw_ppolyf_u_temp ++ mc_dw_npolyf_s=mc_dw_npolyf_s_temp ++ mc_dw_ppolyf_s=mc_dw_ppolyf_s_temp ++ mc_dw_ppolyf_u_1k=mc_dw_ppolyf_u_1k_temp ++ mc_dw_ppolyf_u_2k=mc_dw_ppolyf_u_2k_temp ++ mc_dw_ppolyf_u_1k_6p0=mc_dw_ppolyf_u_1k_6p0_temp ++ mc_dw_ppolyf_u_2k_6p0=mc_dw_ppolyf_u_2k_6p0_temp ++ mc_dw_ppolyf_u_3k=mc_dw_ppolyf_u_3k_temp + ++ mc_rt_nplus_u=mc_rt_nplus_u_temp ++ mc_rt_pplus_u=mc_rt_pplus_u_temp ++ mc_rt_npolyf_u=mc_rt_npolyf_u_temp ++ mc_rt_ppolyf_u=mc_rt_ppolyf_u_temp ++ mc_rt_ppolyf_u_1k=mc_rt_ppolyf_u_1k_temp ++ mc_rt_ppolyf_u_2k=mc_rt_ppolyf_u_2k_temp ++ mc_rt_ppolyf_u_1k_6p0=mc_rt_ppolyf_u_1k_6p0_temp ++ mc_rt_ppolyf_u_2k_6p0=mc_rt_ppolyf_u_2k_6p0_temp ++ mc_rt_ppolyf_u_3k=mc_rt_ppolyf_u_3k_temp + +* +.lib 'sm141064.ngspice' res +.lib 'sm141064.ngspice' efuse +.endl res_statistical + +*------------------------------------------------------------------------ +.lib bjt_statistical +.param ++isa=1 bfa=1 rba=1 rea=1 ++rca=1 rbma=1 cjea=1 cjca=1 ++is_cor_npn =1 ++bf_cor_npn=1 ++rb_cor_npn=1 ++re_cor_npn=1 ++rc_cor_npn=1 ++rbm_cor_npn=1 ++cjc_cor_npn=1 ++cje_cor_npn=1 + ++ mc_xis_vnpn_temp=agauss(0, 0.7, 3) ++ mc_xbf_vnpn_temp=agauss(0, 0.48, 3) ++ mc_xrb_vnpn_temp=agauss(0, 0.2, 3) ++ mc_xre_vnpn_temp=agauss(0, 0.2, 3) ++ mc_xrc_vnpn_temp=agauss(0, 0.2, 3) ++ mc_xcje_vnpn_temp=agauss(0, 0.15, 3) ++ mc_xcjc_vnpn_temp=agauss(0, 0.15, 3) + ++ mc_xis_vpnp_temp=agauss(0, 0.3, 3) ++ mc_xbf_vpnp_temp=agauss(0, 0.2, 3) ++ mc_xrb_vpnp_temp=agauss(0, 0.2, 3) ++ mc_xre_vpnp_temp=agauss(0, 0.2, 3) ++ mc_xrc_vpnp_temp=agauss(0, 0.2, 3) ++ mc_xcje_vpnp_temp=agauss(0, 0.15, 3) ++ mc_xcjc_vpnp_temp=agauss(0, 0.15, 3) +** ++ mc_xis_vnpn=mc_xis_vnpn_temp ++ mc_xbf_vnpn=mc_xbf_vnpn_temp ++ mc_xrb_vnpn=mc_xrb_vnpn_temp ++ mc_xre_vnpn=mc_xre_vnpn_temp ++ mc_xrc_vnpn=mc_xrc_vnpn_temp ++ mc_xcje_vnpn=mc_xcje_vnpn_temp ++ mc_xcjc_vnpn=mc_xcjc_vnpn_temp ++ mc_xis_vpnp=mc_xis_vpnp_temp ++ mc_xbf_vpnp=mc_xbf_vpnp_temp ++ mc_xrb_vpnp=mc_xrb_vpnp_temp ++ mc_xre_vpnp=mc_xre_vpnp_temp ++ mc_xrc_vpnp=mc_xrc_vpnp_temp ++ mc_xcje_vpnp=mc_xcje_vpnp_temp ++ mc_xcjc_vpnp=mc_xcjc_vpnp_temp +.lib 'sm141064.ngspice' bjt_mc +.endl bjt_statistical + +.lib bjt_mc + +.subckt vpnp_0p42x10 c b e par=1 dtemp=0 + +.param ++mis_is_vpnp_0p42x10=agauss(0,0.0015,1) ++mis_bf_vpnp_0p42x10=agauss(0,0.01088,1) + ++isa_mis_vpnp_0p42x10= 'mis_is_vpnp_0p42x10*sw_stat_mismatch / sqrt(par)' ++bf_mis_vpnp_0p42x10= 'mis_bf_vpnp_0p42x10*sw_stat_mismatch / sqrt(par)' + +q0 c b e vpnp_0p42x10 dtemp=dtemp +.model vpnp_0p42x10 pnp ++tref = 25 level = 1 ++cjc = '2.04e-014*cjca*(1 + mc_xcjc_vpnp*sw_stat_global)' cje = '6.88e-015*cjea*(1 + mc_xcje_vpnp*sw_stat_global)' cjs = 0 fc = 0.5 ++mjc = 0.22711 mje = 0.14469 mjs = 0.5 vjc = 0.43905 ++vje = 0.43905 vjs = 0.75 xcjc = 1 cbcp = 0 ++cbep = 0 ccsp = 0 itf = 0.1 ptf = 0 ++tf = 1e-010 tr = 0 vtf = 10 xtf = 1 ++af = 1 kf = 0 ++is = '9e-019*isa*(1 + mc_xis_vpnp*sw_stat_global)*(1 + isa_mis_vpnp_0p42x10)' rb = '41*rba*(1 + mc_xrb_vpnp*sw_stat_global)' re = '1*rea*(1 + mc_xre_vpnp*sw_stat_global)' irb = 0.1 ++rc = '10*rca*(1 + mc_xrc_vpnp*sw_stat_global)' rbm = '10*rbma' bf = '1.69*bfa*(1 + mc_xbf_vpnp*sw_stat_global)*(1 + bf_mis_vpnp_0p42x10)' nf = 1 ++vaf = 80 ikf = 0.00063375 ise = 2.7e-016 ne = 1.64 ++br = 0.0036 nr = 1 var = 23 ikr = 0.1 ++nkf = 0.4 isc = 1e-018 nc = 2 ++xtb = 0.0001 xti = 3 eg = 1.17 ctc = 0.0028626 ++cte = 0.001 tlevc = 1 tvjc = 0.0024779 tvje = 0.0019314 ++tbf1 = 0.0061 tikf1 = -0.0043 tbf2 = -4.235165e-022 + +.ends vpnp_0p42x10 + +.subckt vpnp_0p42x5 c b e par=1 dtemp=0 + +.param ++mis_is_vpnp_0p42x5=agauss(0,0.0017,1) ++mis_bf_vpnp_0p42x5=agauss(0,0.0119,1) +q0 c b e vpnp_0p42x5 dtemp=dtemp +.model vpnp_0p42x5 pnp ++level = 1 tlevc = 1 tref = 25 ++is = '4.388E-19*isa*(1 + mc_xis_vpnp*sw_stat_global)*(1 + mis_is_vpnp_0p42x5*sw_stat_mismatch / sqrt(par))' bf = '1.681*bfa*(1 + mc_xbf_vpnp*sw_stat_global)*(1 + mis_bf_vpnp_0p42x5*sw_stat_mismatch / sqrt(par))' nf = 1 ++vaf = 180 ikf = 2.4777E-4 nkf = 0.4 ++ise = 1.2124E-16 ne = 1.64 br = 1.9872E-3 ++nr = 1 var = 23 ikr = 0.1 ++isc = 1E-16 nc = 2 ++rb = '41*rba*(1 + mc_xrb_vpnp*sw_stat_global)' irb = 0.1 rbm = '10*rbma' ++re = '1*rea*(1 + mc_xre_vpnp*sw_stat_global)' rc = '10*rca*(1 + mc_xrc_vpnp*sw_stat_global)' ++cje = '3.5E-15*cjea*(1 + mc_xcje_vpnp*sw_stat_global)' vje = 0.43905 mje = 0.15395 ++cjc = '1.17E-14*cjca*(1 + mc_xcjc_vpnp*sw_stat_global)' vjc = 0.43905 mjc = 0.22711 ++cjs = 0 vjs = 0.75 mjs = 0.5 ++tf = 1E-10 xtf = 1 vtf = 10 ++itf = 0.1 xcjc = 1 fc = 0.5 ++tr = 0 ptf = 0 cbcp = 0 ++cbep = 0 ccsp = 0 ++xtb = 1E-4 xti = 3 eg = 1.17 ++tbf1 = 6.1E-3 tbf2 = -4.235165E-22 tikf1 = -4.3E-3 ++cte = 1E-3 ctc = 2.8626E-3 tvje = 1.9314E-3 ++tvjc = 2.4779E-3 ++kf = 0 af = 1 +.ends vpnp_0p42x5 + + +.subckt vpnp_10x10 c b e par=1 dtemp=0 + +.param ++mis_is_vpnp_10x10=agauss(0,0.00077,1) ++mis_bf_vpnp_10x10=agauss(0,0.0013,1) +q0 c b e vpnp_10x10 dtemp=dtemp +.model vpnp_10x10 pnp ++level = 1 tlevc = 1 tref = 25 ++is = '1.249175E-17*isa*(1 + mc_xis_vpnp*sw_stat_global)*(1 + mis_is_vpnp_10x10*sw_stat_mismatch / sqrt(par))' bf = '1.7*bfa*(1 + mc_xbf_vpnp*sw_stat_global)*(1 + mis_bf_vpnp_10x10*sw_stat_mismatch / sqrt(par))' nf = 1 ++vaf = 206.4 ikf = 2.610625E-3 nkf = 0.4 ++ise = 2.7E-16 ne = 1.64 br = 0.017038 ++nr = 1 var = 23 ikr = 0.1 ++isc = 1E-18 nc = 2 ++rb = '27.88*rba*(1 + mc_xrb_vpnp*sw_stat_global)' irb = 0.1 rbm = '10*rbma' ++re = '1*rea*(1 + mc_xre_vpnp*sw_stat_global)' rc = '10*rca*(1 + mc_xrc_vpnp*sw_stat_global)' ++cje = '9.71E-14*cjea*(1 + mc_xcje_vpnp*sw_stat_global)' vje = 0.43905 mje = 0.24192 ++cjc = '4.69E-14*cjca*(1 + mc_xcjc_vpnp*sw_stat_global)' vjc = 0.43905 mjc = 0.24528 ++cjs = 0 vjs = 0.75 mjs = 0.5 ++tf = 1E-10 xtf = 1 vtf = 10 ++itf = 0.1 xcjc = 1 fc = 0.5 ++tr = 0 ptf = 0 cbcp = 0 ++cbep = 0 ccsp = 0 ++xtb = 1E-4 xti = 3 eg = 1.17 ++tbf1 = 4.26E-3 tbf2 = -1.4E-6 tikf1 = -4.3E-3 ++cte = 1E-3 ctc = 2.8626E-3 tvje = 1.9314E-3 ++tvjc = 2.4779E-3 ++kf = 0 af = 1 +.ends vpnp_10x10 + +.subckt vpnp_5x5 c b e par=1 dtemp=0 + +.param ++mis_is_vpnp_5x5=agauss(0,0.00052,1) ++mis_bf_vpnp_5x5=agauss(0,0.0031,1) + +q0 c b e vpnp_5x5 dtemp=dtemp +.model vpnp_5x5 pnp ++level = 1 tlevc = 1 tref = 25 ++is = '3.403E-18*isa*(1 + mc_xis_vpnp*sw_stat_global)*(1 + mis_is_vpnp_5x5*sw_stat_mismatch / sqrt(par))' bf = '1.65*bfa*(1 + mc_xbf_vpnp*sw_stat_global)*(1 +mis_bf_vpnp_5x5*sw_stat_mismatch / sqrt(par))' nf = 1 ++vaf = 208.8 ikf = 1.025275E-3 nkf = 0.4 ++ise = 2.7E-16 ne = 1.64 br = 8.372E-3 ++nr = 1 var = 27.37 ikr = 0.1 ++isc = 1E-18 nc = 2 ++rb = '41*rba*(1 + mc_xrb_vpnp*sw_stat_global)' irb = 0.1 rbm = '10*rbma' ++re = '1*rea*(1 + mc_xre_vpnp*sw_stat_global)' rc = '10*rca*(1 + mc_xrc_vpnp*sw_stat_global)' ++cje = '2.57E-14*cjea*(1 + mc_xcje_vpnp*sw_stat_global)' vje = 0.43905 mje = 0.23266 ++cjc = '2.15E-14*cjca*(1 + mc_xcjc_vpnp*sw_stat_global)' vjc = 0.43905 mjc = 0.22711 ++cjs = 0 vjs = 0.75 mjs = 0.5 ++tf = 1E-10 xtf = 1 vtf = 10 ++itf = 0.1 xcjc = 1 fc = 0.5 ++tr = 0 ptf = 0 cbcp = 0 ++cbep = 0 ccsp = 0 ++xtb = 1E-4 xti = 3 eg = 1.17 ++tbf1 = 4.54E-3 tbf2 = -9E-7 tikf1 = -4.3E-3 ++cte = 1E-3 ctc = 2.8626E-3 tvje = 1.9314E-3 ++tvjc = 2.4779E-3 ++kf = 0 af = 1 +.ends vpnp_5x5 + +.subckt vnpn_10x10 c b e s par=1 dtemp=0 + +q0 c b e s vnpn_10x10 dtemp=dtemp +.model vnpn_10x10 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '7.053E-14*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '1.031E-13*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 1.135E-13 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '1.8108e-017*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '65.442*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '6.9007*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '10.146*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '10.83*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.002 vaf = 95.696 ikf = 0.021028 ise = 2.9626e-016 ++ne = 1.345 br = 0.258 nr = 1.002 var = 29.681 ++ikr = 0.0038951 nkf = 0.584 isc = 1.5816e-016 nc = 1.284 ++iss=6.32E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 5e-005 ++tnr1 = 0.0001584 tne1 = 0.00047174 tbf1 = 0.00484 tbr1 = 0.0003808 ++tikf1 = -0.0053169 tre1 = 0.002 tbf2 = 3.705e-006 + +.ends vnpn_10x10 + +.subckt vnpn_5x5 c b e s par=1 dtemp=0 + +q0 c b e s vnpn_5x5 dtemp=dtemp +.model vnpn_5x5 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '2.972E-14*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '2.733E-14*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 6.618E-14 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '5.1456e-018*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '71.419*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '12.809*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '12.655*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '10.05*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.002 vaf = 77.796 ikf = 0.01158 ise = 2.5923e-016 ++ne = 1.4224 br = 0.16573 nr = 1 var = 28.001 ++ikr = 0.0038951 nkf = 0.584 isc = 1.2536e-016 nc = 1.284 ++iss=3.26E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 6e-005 ++tnr1 = 0.0001071 tne1 = 0.0005 tbf1 = 0.0050844 tbr1 = 0.00045 ++tikf1 = -0.005 tre1 = 0.001 tbf2 = 4.3586e-006 +.ends vnpn_5x5 + +.subckt vnpn_0p54x16 c b e s par=1 dtemp=0 + + +q0 c b e s vnpn_0p54x16 dtemp=dtemp +.model vnpn_0p54x16 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '3.540E-14*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '1.354E-14*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 8.211E-14 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '2.8872e-018*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '137.43*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '14.121*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '12.9*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '8.4987*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.002 vaf = 37.389 ikf = 0.013121 ise = 5.2003e-016 ++ne = 1.4678 br = 0.079582 nr = 1 var = 23.969 ++ikr = 0.0038951 nkf = 0.584 isc = 1.0425e-016 nc = 1.284 ++iss=3.95E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 5.2528e-005 ++tnr1 = 0.0001 tne1 = 0.00034324 tbf1 = 0.0057737 tbr1 = 0.0007104 ++tikf1 = -0.003 tre1 = 0.0035596 tbf2 = 2.2189e-006 +.ends vnpn_0p54x16 + +.subckt vnpn_0p54x8 c b e s par=1 dtemp=0 + +q0 c b e s vnpn_0p54x8 dtemp=dtemp + +.model vnpn_0p54x8 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '2.064E-14*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '6.857E-15*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 5.703E-14 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '1.4309e-018*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '141.94*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '14.573*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '13.434*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '8.4*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.001 vaf = 37.389 ikf = 0.0077487 ise = 2.6232e-016 ++ne = 1.4685 br = 0.069974 nr = 0.996 var = 25.201 ++ikr = 0.0038951 nkf = 0.584 isc = 7.3712e-017 nc = 1.284 ++iss=2.62E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 4.56e-005 ++tnr1 = 0.0001 tne1 = 0.00065 tbf1 = 0.0050727 tbr1 = 0.00085272 ++tikf1 = -0.003 tre1 = 0.00336 tbf2 = 7.3496e-006 +.ends vnpn_0p54x8 + +.subckt vnpn_0p54x4 c b e s par=1 dtemp=0 + + +q0 c b e s vnpn_0p54x4 dtemp=dtemp +.model vnpn_0p54x4 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '1.326E-14*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '3.513E-15*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 4.449E-14 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '7.6696e-019*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '167*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '17.058*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '14.542*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '8.39*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.001 vaf = 37.389 ikf = 0.0048817 ise = 1.3419e-016 ++ne = 1.4801 br = 0.057751 nr = 0.998 var = 25.201 ++ikr = 0.0038951 nkf = 0.584 isc = 6.2655e-017 nc = 1.284 ++iss=1.95E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 5e-005 ++tnr1 = 0.0001 tne1 = 0.0004 tbf1 = 0.0058206 tbr1 = 0.0009 ++tbf2 = -6.2e-007 +.ends vnpn_0p54x4 +.subckt vnpn_0p54x2 c b e s par=1 dtemp=0 + + +q0 c b e s vnpn_0p54x2 dtemp=dtemp +.model vnpn_0p54x2 npn level = 1 +************************************************************** +* GENERAL PARAMETERS +************************************************************** ++tref = 25 +************************************************************** +* CAPACITANCE PARAMETERS +************************************************************** ++cjc = '9.569E-15*cjc_cor_npn*(1 + mc_xcjc_vnpn*sw_stat_global)' cje = '1.841E-15*cje_cor_npn*(1 + mc_xcje_vnpn*sw_stat_global)' cjs = 3.822E-14 ++mjc = 0.31113 mje = 0.32071 mjs = 0.14716 vjc = 0.63391 vje = 0.70172 ++vjs = 0.35175 xcjc = 1 +************************************************************** +* Noise PARAMETERS +************************************************************** ++af = 1 kf = 0 +************************************************************** +* DC PARAMETERS +************************************************************** ++is = '4.5765e-019*is_cor_npn*(1 + mc_xis_vnpn*sw_stat_global)' subs = 1 rb = '231.74*rb_cor_npn*(1 + mc_xrb_vnpn*sw_stat_global)' re = '25.055*re_cor_npn*(1 + mc_xre_vnpn*sw_stat_global)' ++irb = 0.00045303 rc = '17.312*rc_cor_npn*(1 + mc_xrc_vnpn*sw_stat_global)' rbm = '1*rbm_cor_npn' bf = '8.25*bf_cor_npn*(1 + mc_xbf_vnpn*sw_stat_global)' ++nf = 1.004 vaf = 37.389 ikf = 0.0039054 ise = 8e-017 ++ne = 1.49 br = 0.043698 nr = 1.0005 var = 25.201 ++ikr = 0.0038951 nkf = 0.584 isc = 6.2655e-017 nc = 1.284 ++iss=1.61E-16 +************************************************************** +* TEMPERATURE PARAMETERS +************************************************************** ++xtb = 0 xti = 3 eg = 1.17 tnf1 = 5e-005 ++tnr1 = 0.0001 tne1 = 0.0005 tbf1 = 0.005536 tbr1 = 0.001 ++tbf2 = -1.5876e-006 +.ends vnpn_0p54x2 +.endl bjt_mc + +.lib mimcap_statistical +.param mim_corner_1p5fF=1 +.param mim_corner_1p0fF=1 +.param mim_corner_2p0fF=1 + +.param ++ mc_c_cox_1p0fF2=agauss(0, 0.025, 3) ++ mc_c_cox_1p5fF2=agauss(0, 0.03875, 3) ++ mc_c_cox_2p0fF2=agauss(0, 0.025, 3) ++ mc_c_cox_1p0fF='mc_c_cox_1p0fF2*sw_stat_global*cap_mc_skew' ++ mc_c_cox_1p5fF='mc_c_cox_1p5fF2*sw_stat_global*cap_mc_skew' ++ mc_c_cox_2p0fF='mc_c_cox_2p0fF2*sw_stat_global*cap_mc_skew' + +.lib 'sm141064.ngspice' mim_cap +.endl mimcap_statistical + + +* +************************end of file************************* +* + diff --git a/Tech.GF180MCU/template.lef b/Tech.GF180MCU/template.lef new file mode 100755 index 00000000..6aea0f8d --- /dev/null +++ b/Tech.GF180MCU/template.lef @@ -0,0 +1,177 @@ +# LEF file generated by lefgen from LibreSilicon version 0.1 +# + +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +USEMINSPACING OBS ON ; +USEMINSPACING PIN OFF ; +CLEARANCEMEASURE EUCLIDEAN ; + + +MANUFACTURINGGRID 0.005 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER nactive + TYPE MASTERSLICE ; +END nactive + +LAYER pactive + TYPE MASTERSLICE ; +END pactive + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER cc + TYPE CUT ; + SPACING 0.9 ; +END cc + +LAYER metal1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 3.2e-05 ; +END metal1 + +LAYER via + TYPE CUT ; + SPACING 0.9 ; +END via + +LAYER metal2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 2.4 ; + OFFSET 1.2 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 1.6e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.9 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 1.5 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.05 ; + CAPACITANCE CPERSQDIST 1e-05 ; +END metal3 + +SPACING + SAMENET cc via 0.150 ; + SAMENET via via2 0.150 ; +END SPACING + +VIA M2_M1 DEFAULT + LAYER metal1 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; +END M2_M1 + +VIA M3_M2 DEFAULT + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via2 ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal3 ; + RECT -0.900 -0.900 0.900 0.900 ; +END M3_M2 + + +VIARULE viagen21 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER via ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 1.5 BY 1.5 ; +END viagen21 + +VIARULE viagen32 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + WIDTH 1.8 TO 180 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER via2 ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 2.1 BY 2.1 ; +END viagen32 + +VIARULE TURN1 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + LAYER metal1 ; + DIRECTION VERTICAL ; +END TURN1 + +VIARULE TURN2 GENERATE + LAYER metal2 ; + DIRECTION HORIZONTAL ; + LAYER metal2 ; + DIRECTION VERTICAL ; +END TURN2 + +VIARULE TURN3 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + LAYER metal3 ; + DIRECTION VERTICAL ; +END TURN3 + +SITE corner + CLASS PAD ; + SYMMETRY R90 Y ; + SIZE 300.000 BY 300.000 ; +END corner + +SITE IO + CLASS PAD ; + SYMMETRY Y ; + SIZE 90.000 BY 300.000 ; +END IO + +SITE core + CLASS CORE ; + SYMMETRY Y ; + SIZE 2.400 BY 30.000 ; +END core + diff --git a/Tech.GF180MCU/tracks.txt b/Tech.GF180MCU/tracks.txt new file mode 100644 index 00000000..f4b4ed07 --- /dev/null +++ b/Tech.GF180MCU/tracks.txt @@ -0,0 +1,14 @@ +1 Track: 0.56 um + +Tracks per Cell 7 +Cell Height (um) 3.92 + +Tracks per Cell 9 +Cell Height (um) 5.04 + +Tracks per Cell 11 +Cell Height (um) 6.16 + +Tracks per Cell 13 +Cell Height (um) 7.28 + diff --git a/Tech.LS1UM/.gitignore b/Tech.LS1UM/.gitignore new file mode 100644 index 00000000..c18dd8d8 --- /dev/null +++ b/Tech.LS1UM/.gitignore @@ -0,0 +1 @@ +__pycache__/ diff --git a/Tech.LS1UM/SpiceParameterFiles.zip b/Tech.LS1UM/SpiceParameterFiles.zip new file mode 100644 index 00000000..718fdc95 Binary files /dev/null and b/Tech.LS1UM/SpiceParameterFiles.zip differ diff --git a/Tech.LS1UM/bad/libresilicon.m1 b/Tech.LS1UM/bad/libresilicon.m1 new file mode 100755 index 00000000..7acae4da --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m1 @@ -0,0 +1,164 @@ +# This is a template file for characterization, it needs to be adapted to our real values + +.model NMOS_VTL nmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.75e-09 toxp = 1.1e-09 toxm = 1.75e-09 toxref = 1.75e-09 ++dtox = 6.5e-10 lint = 3.75e-09 ++vth0 = 0.471 k1 = 0.53 u0 = 0.04359 vsat = 147390 ++rdsw = 155 ndep = 3.3e+18 xj = 1.4e-08 + +* secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = 0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 etab = 0 ++vfb = -0.55 ua = 6e-010 ub = 1.2e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 ++cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + + + +.model PMOS_VTL pmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.85e-09 toxp = 1.1e-09 toxm = 1.85e-09 toxref = 1.85e-09 ++dtox = 7.5e-10 lint = 3.75e-09 ++vth0 = -0.423 k1 = 0.491 u0 = 0.00432 vsat = 70000 ++rdsw = 155 ndep = 2.54e+18 xj = 1.4e-08 + +*secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.126 etab = 0 ++vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 ++cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + diff --git a/Tech.LS1UM/bad/libresilicon.m10 b/Tech.LS1UM/bad/libresilicon.m10 new file mode 100644 index 00000000..c6702fb4 --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m10 @@ -0,0 +1,7 @@ +.MODEL NMOS_VTL NMOS LEVEL = 39 ++ TOX = 2.000000E-02 TEMP = 2.500000E+01 ++ VDD = 5.000000E+00 VGG = 5.000000E+00 VBB =-5.000000E+00 ++ DL = 0.000000E+00 DW = 0.000000E+00 ++ VGHIGH = 1.270000E-01 LVGHIGH= 0.000000E+00 WVGHIGH= 0.000000E+00 ++ VGLOW =-7.820000E-02 LVGLOW = 0.000000E+00 WVGLOW= 0.000000E+00 + diff --git a/Tech.LS1UM/bad/libresilicon.m11 b/Tech.LS1UM/bad/libresilicon.m11 new file mode 100755 index 00000000..e9e8c63b --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m11 @@ -0,0 +1,164 @@ +# This is a template file for characterization, it needs to be adapted to our real values + +.model NMOS_VTL nmos level = 54 ++ VDD = 5.000000E+00 VGG = 5.000000E+00 VBB =-5.000000E+00 ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.75e-09 toxp = 1.1e-09 toxm = 1.75e-09 toxref = 1.75e-09 ++dtox = 6.5e-10 lint = 3.75e-09 ++vth0 = 0.471 k1 = 0.53 u0 = 0.04359 vsat = 147390 ++rdsw = 155 ndep = 3.3e+18 xj = 1.4e-08 + +* secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = 0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.13 etab = 0 ++vfb = -0.55 ua = 6e-010 ub = 1.2e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 ++cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + + + +.model PMOS_VTL pmos level = 54 ++ VDD = 5.000000E+00 VGG = 5.000000E+00 VBB =-5.000000E+00 ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.85e-09 toxp = 1.1e-09 toxm = 1.85e-09 toxref = 1.85e-09 ++dtox = 7.5e-10 lint = 3.75e-09 ++vth0 = -0.423 k1 = 0.491 u0 = 0.00432 vsat = 70000 ++rdsw = 155 ndep = 2.54e+18 xj = 1.4e-08 + +*secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.126 etab = 0 ++vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 ++cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + diff --git a/Tech.LS1UM/bad/libresilicon.m2 b/Tech.LS1UM/bad/libresilicon.m2 new file mode 100644 index 00000000..02b68d7b --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m2 @@ -0,0 +1,62 @@ +.SUBCKT NMOS4 D G S B ++ PARAMS: ++ W=15E-7 ++ L=10E-7 ++ PD=25E-7 ++ PS=25E-7 + +M1 D G S B NMOS W={W} L={L} PD={PD} PS={PS} + +.MODEL NMOS NMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 1160.761537104032 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 10E-7 ++ Wmax = 20E-7 ++ ) + +* NGATE has to be measured! + +.ENDS NMOS4 +.SUBCKT PMOS4 D G S B ++ PARAMS: ++ W=30E-7 ++ L=10E-7 ++ PD=30E-7 ++ PS=30E-7 + +M1 D G S B PMOS W={W} L={L} PD={PD} PS={PS} + +.MODEL PMOS PMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 439.9319659030368 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 25E-7 ++ Wmax = 35E-7 ++ ) + +* PGATE has to be measured! + +.ENDS PMOS4 diff --git a/Tech.LS1UM/bad/libresilicon.m3 b/Tech.LS1UM/bad/libresilicon.m3 new file mode 100644 index 00000000..750f37c8 --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m3 @@ -0,0 +1,39 @@ +.MODEL NMOS NMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 1160.761537104032 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 10E-7 ++ Wmax = 20E-7 ++ ) + +.MODEL PMOS PMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 439.9319659030368 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 25E-7 ++ Wmax = 35E-7 ++ ) + + diff --git a/Tech.LS1UM/bad/libresilicon.m5 b/Tech.LS1UM/bad/libresilicon.m5 new file mode 100644 index 00000000..b86e6088 --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m5 @@ -0,0 +1,39 @@ +.MODEL NMOS_VTL NMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 1160.761537104032 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 10E-7 ++ Wmax = 20E-7 ++ ) + +.MODEL PMOS_VTL PMOS ( ++ LEVEL = 8 ++ VERSION = 3.3.1 ++ TNOM = 27 ++ U0 = 439.9319659030368 ++ TOX = 40E-9 ++ XT = 2E-6 ++ XJ = 100E-9 ++ NCH = 1.7E17 ++ NSUB = 1.7E17 ++ VTH0 = -0.7 ++ W0 = 1.280703E-8 ++ NLX = 0 ++ Lmin = 5E-7 ++ Lmax = 15E-7 ++ Wmin = 25E-7 ++ Wmax = 35E-7 ++ ) + + diff --git a/Tech.LS1UM/bad/libresilicon.m6 b/Tech.LS1UM/bad/libresilicon.m6 new file mode 100644 index 00000000..cc2d560c --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m6 @@ -0,0 +1,59 @@ +# *nmos model + +.MODEL NMOS_VTL NMOS LEVEL=13 VFB0= ++ -8.27348E-01, 1.42207E-01, 3.48523E-02 ++ 7.87811E-01, 0.00000E+00, 0.00000E+00 ++ 9.01356E-01,-1.96192E-01, 1.89222E-02 ++ 4.83095E-02,-4.10812E-02,-2.21153E-02 ++ 2.11768E-03, 3.04656E-04,-1.14155E-03 ++ 4.93528E+02, 5.39503E-02, 4.54432E-01 ++ 5.81155E-02, 4.95498E-02,-1.96838E-02 ++ -5.88405E-02, 6.06713E-01, 4.88790E-03 ++ 9.22649E+00,-8.66150E+00, 9.55036E+00 ++ -7.95688E-04, 2.67366E-03, 3.88974E-03 ++ 2.14262E-03,-7.19261E-04,-3.56119E-03 ++ 2.05529E-03,-3.66841E-03, 1.86866E-03 + ++ -1.64733E-02,-3.63561E-03, 3.59209E-02 ++ 4.84793E+02, 3.14763E+02,-3.91874E+01 ++ -4.21265E+00,-7.97847E+00, 3.50692E+01 ++ -5.83990E+00, 6.64867E+01,-1.99620E+00 ++ -1.44106E-02, 8.14508E-02, 7.56591E-04 ++ 2.30000E-02, 2.30000E+01, 5.00000E+00 ++ 5.04000E-10, 5.04000E-10, 1.91000E-09 ++ 1.00000E+00, 0.00000E+00, 0.00000E+00 ++ 2.00000E+02, 0.00000E+00, 0.00000E+00 ++ 0.00000E+00, 0.00000E+00, 0.00000E+00 ++ 0.00000E+00, 0.00000E+00, 0.00000E+00 +*n+ diffusion layer ++ 80.0,7.000E-004,4.20E-010,1.00E-008,0.700E000 ++ 0.8000e000,0.5,0.33,0,0 + +.MODEL PMOS_VTL PMOS LEVEL=13 VFB0= ++ -5.63441E-01,-1.06809E-01, 1.32967E-01 ++ 7.46390E-01, 0.00000E+00, 0.00000E+00 ++ 6.57533E-01, 1.94464E-01,-1.60925E-01 ++ -2.55036E-03, 1.14752E-01,-8.78447E-02 ++ -5.59772E-03, 2.50199E-02,-5.66587E-04 ++ 1.73854E+02, 2.72457E-01, 6.57818E-01 ++ 1.26943E-01, 4.25293E-02,-4.31672E-02 ++ -1.00718E-02, 1.50900E-01,-1.00228E-02 ++ 1.03128E+01,-3.94500E+00, 1.87986E+00 ++ 1.55874E-03, 4.80364E-03,-1.45355E-03 ++ 4.20214E-04,-2.05447E-03,-7.44369E-04 ++ 1.00044E-02,-4.43607E-03, 1.05796E-03 ++ -5.64102E-04, 1.97407E-03, 6.65336E-04 ++ 1.77550E+02, 1.02937E+02,-2.94207E+01 ++ 8.73183E+00, 1.51499E+00, 9.06178E-01 ++ 1.11851E+00, 9.75265E+00,-1.88238E+00 ++ -4.70098E-05, 9.43069E-04,-9.19946E-05 ++ 2.30000E-02, 2.30000E+01, 5.00000E+00 ++ 1.00000E-09, 1.00000E-09, 1.91000E-09 ++ 1.00000E+00, 0.00000E+00, 0.00000E+00 ++ 2.00000E+02, 0.00000E+00, 0.00000E+00 ++ 0.00000E+00, 0.00000E+00, 0.00000E+00 ++ 0.00000E+00, 0.00000E+00, 0.00000E+00 +*p+ diffusion layer ++140.0,4.0E-004,2.4E-010,1.00E-008,0.700E000 ++0.8000e000,0.5,0.33,0,0 + diff --git a/Tech.LS1UM/bad/libresilicon.m7 b/Tech.LS1UM/bad/libresilicon.m7 new file mode 100644 index 00000000..74e83b64 --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m7 @@ -0,0 +1,13 @@ +.MODEL NMOS_VTL NMOS LEVEL=27 SOSLEV=2 ++VTO=0.814 TOX=0.34E-7 THETA=0.55E-1 ++FB=0.15 EC=0.3E7 A=0.1E-6 ++UO=370 CGSO=0.46E-9 CGDO=0.46E-9 ++RSH=25 LD=0.3E-6 +* + +.MODEL PMOS_VTL PMOS LEVEL=27 SOSLEV=2 ++VTO=-0.7212 TOX=0.34E-7 THETA=0.75E-1 ++FB=0.0 EC=0.75E7 A=0.1E-6 ++UO=215 CGSO=0.36E-9 CGDO=0.36E-9 ++RSH=80 LD=0.2E-6i +* diff --git a/Tech.LS1UM/bad/libresilicon.m8 b/Tech.LS1UM/bad/libresilicon.m8 new file mode 100755 index 00000000..f5045920 --- /dev/null +++ b/Tech.LS1UM/bad/libresilicon.m8 @@ -0,0 +1,159 @@ +.model NMOS_VTL nmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.75e-09 toxp = 1.1e-09 toxm = 1.75e-09 toxref = 1.75e-09 ++dtox = 6.5e-10 lint = 3.75e-09 ++vth0 = 0.771 k1 = 0.53 u0 = 0.04359 vsat = 147390 ++rdsw = 155 ndep = 3.3e+18 xj = 1.4e-08 + +* secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = 0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1.0e-009 ++dvtp1 = 0.1 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.23 etab = 0 ++vfb = -0.55 ua = 6e-010 ub = 1.2e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1.0 b0 = 0 b1 = 0 ++keta = 0.04 dwg = 0 dwb = 0 pclm = 0.04 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = -0.005 drout = 0.5 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 1e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 0 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.012 bigc = 0.0028 ++cigc = 0.002 aigsd = 0.012 bigsd = 0.0028 cigsd = 0.002 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + +.model PMOS_VTL pmos level = 54 + ++version = 4.0 binunit = 1 paramchk= 1 mobmod = 0 ++capmod = 2 igcmod = 1 igbmod = 1 geomod = 1 ++diomod = 1 rdsmod = 0 rbodymod= 1 rgatemod= 1 ++permod = 1 acnqsmod= 0 trnqsmod= 0 + +* parameters related to the technology node ++tnom = 27 epsrox = 3.9 ++eta0 = 0.0049 nfactor = 2.1 wint = 5e-09 ++cgso = 1.1e-10 cgdo = 1.1e-10 xl = -2e-08 + +* parameters customized by the user ++toxe = 1.85e-09 toxp = 1.1e-09 toxm = 1.85e-09 toxref = 1.85e-09 ++dtox = 7.5e-10 lint = 3.75e-09 ++vth0 = -0.723 k1 = 0.491 u0 = 0.00432 vsat = 70000 ++rdsw = 155 ndep = 2.54e+18 xj = 1.4e-08 + +*secondary parameters ++ll = 0 wl = 0 lln = 1 wln = 1 ++lw = 0 ww = 0 lwn = 1 wwn = 1 ++lwl = 0 wwl = 0 xpart = 0 ++k2 = -0.01 k3 = 0 ++k3b = 0 w0 = 2.5e-006 dvt0 = 1 dvt1 = 2 ++dvt2 = -0.032 dvt0w = 0 dvt1w = 0 dvt2w = 0 ++dsub = 0.1 minv = 0.05 voffl = 0 dvtp0 = 1e-009 ++dvtp1 = 0.05 lpe0 = 0 lpeb = 0 ++ngate = 2e+020 nsd = 2e+020 phin = 0 ++cdsc = 0.000 cdscb = 0 cdscd = 0 cit = 0 ++voff = -0.226 etab = 0 ++vfb = 0.55 ua = 2.0e-009 ub = 0.5e-018 ++uc = 0 a0 = 1.0 ags = 1e-020 ++a1 = 0 a2 = 1 b0 = -1e-020 b1 = 0 ++keta = -0.047 dwg = 0 dwb = 0 pclm = 0.12 ++pdiblc1 = 0.001 pdiblc2 = 0.001 pdiblcb = 3.4e-008 drout = 0.56 ++pvag = 1e-020 delta = 0.01 pscbe1 = 8.14e+008 pscbe2 = 9.58e-007 ++fprout = 0.2 pdits = 0.08 pditsd = 0.23 pditsl = 2.3e+006 ++rsh = 5 rsw = 85 rdw = 85 ++rdswmin = 0 rdwmin = 0 rswmin = 0 prwg = 3.22e-008 ++prwb = 6.8e-011 wr = 1 alpha0 = 0.074 alpha1 = 0.005 ++beta0 = 30 agidl = 0.0002 bgidl = 2.1e+009 cgidl = 0.0002 ++egidl = 0.8 + ++aigbacc = 0.012 bigbacc = 0.0028 cigbacc = 0.002 ++nigbacc = 1 aigbinv = 0.014 bigbinv = 0.004 cigbinv = 0.004 ++eigbinv = 1.1 nigbinv = 3 aigc = 0.69 bigc = 0.0012 ++cigc = 0.0008 aigsd = 0.0087 bigsd = 0.0012 cigsd = 0.0008 ++nigc = 1 poxedge = 1 pigcd = 1 ntox = 1 + ++xrcrg1 = 12 xrcrg2 = 5 ++cgbo = 2.56e-011 cgdl = 2.653e-10 ++cgsl = 2.653e-10 ckappas = 0.03 ckappad = 0.03 acde = 1 ++moin = 15 noff = 0.9 voffcv = 0.02 + ++kt1 = -0.11 kt1l = 0 kt2 = 0.022 ute = -1.5 ++ua1 = 4.31e-009 ub1 = 7.61e-018 uc1 = -5.6e-011 prt = 0 ++at = 33000 + ++fnoimod = 1 tnoimod = 0 + ++jss = 0.0001 jsws = 1e-011 jswgs = 1e-010 njs = 1 ++ijthsfwd= 0.01 ijthsrev= 0.001 bvs = 10 xjbvs = 1 ++jsd = 0.0001 jswd = 1e-011 jswgd = 1e-010 njd = 1 ++ijthdfwd= 0.01 ijthdrev= 0.001 bvd = 10 xjbvd = 1 ++pbs = 1 cjs = 0.0005 mjs = 0.5 pbsws = 1 ++cjsws = 5e-010 mjsws = 0.33 pbswgs = 1 cjswgs = 3e-010 ++mjswgs = 0.33 pbd = 1 cjd = 0.0005 mjd = 0.5 ++pbswd = 1 cjswd = 5e-010 mjswd = 0.33 pbswgd = 1 ++cjswgd = 5e-010 mjswgd = 0.33 tpb = 0.005 tcj = 0.001 ++tpbsw = 0.005 tcjsw = 0.001 tpbswg = 0.005 tcjswg = 0.001 ++xtis = 3 xtid = 3 + ++dmcg = 0e-006 dmci = 0e-006 dmdg = 0e-006 dmcgt = 0e-007 ++dwj = 0.0e-008 xgw = 0e-007 xgl = 0e-008 + ++rshg = 0.4 gbmin = 1e-010 rbpb = 5 rbpd = 15 ++rbps = 15 rbdb = 15 rbsb = 15 ngcon = 1 + + + diff --git a/Tech.LS1UM/drc.lydrc b/Tech.LS1UM/drc.lydrc new file mode 100644 index 00000000..fdb6f87b --- /dev/null +++ b/Tech.LS1UM/drc.lydrc @@ -0,0 +1,103 @@ + + + + + drc + + + + false + false + + true + drc_scripts + tools_menu.drc.end + dsl + drc-dsl-xml + # Read about DRC scripts in the User Manual under "Design Rule Check (DRC)" +# These are the design rules for the Libresilicon.com 1um Process node: + +report("Libresilicon DRC Rules") + +active = input(1) +nwell = input(2) +pwell = input(2,7) +poly = input(3) +polycontact = input(4) +diffcontact = input(5) +contact = polycontact | diffcontact +metal1 = input(6) +via1 = input(7) +metal2 = input(8) +via2 = input(89) # TODO: CORRECT THE LAYER NUMBER WHEN THE LAYER EXISTS +metal3 = input(99) # TODO: CORRECT THE LAYER NUMBER WHEN THE LAYER EXISTS +abutment = input(200) +gate = poly & active +polyoveractive = poly & active +polyoverother = poly - active + +l=0.5.micron + +# Chapter 3: +pwell.width(10*l).output("pwell_min_width", "PWELL width violations") +nwell.width(10*l).output("nwell_min_width", "NWELL width violations") +# THE DOCUMENTATION SAYS ACTIVE.WIDTH >= 3*l but I think 2*l is better for now. +active.width(2*l).output("active_min_width", "ACTIVE width violations") +poly.width(2*l).output("poly_min_width", "POLY width violations") +polycontact.width(2*l).output("polycontact_min_width", "POLY CONTACT width violations") +diffcontact.width(2*l).output("diffcontact_min_width", "DIFF CONTACT width violations") +metal1.width(4*l).output("metal1_min_width", "METAL1 width violations") +via1.width(2*l).output("via1_min_width", "VIA1 width violations") +metal2.width(4*l).output("metal2_min_width", "METAL2 width violations") +via2.width(2*l).output("via2_min_width", "VIA2 width violations") +metal3.width(6*l).output("metal3_min_width", "METAL3 width violations") + +pwell.space(10*l).output("pwell_min_space", "PWELL space violations") +nwell.space(10*l).output("nwell_min_space", "NWELL space violations") +active.space(3*l).output("active_min_space", "ACTIVE space violations") +poly.space(2*l).output("poly_min_space", "POLY space violations") +polycontact.space(2*l).output("polycontact_min_space", "POLY CONTACT space violations") +diffcontact.space(2*l).output("diffcontact_min_space", "DIFF CONTACT space violations") +metal1.space(4*l).output("metal1_min_space", "METAL1 space violations") +via1.space(3*l).output("via1_min_space", "VIA1 space violations") +metal2.space(4*l).output("metal2_min_space", "METAL2 space violations") +via2.space(3*l).output("via2_min_space", "VIA2 space violations") +metal3.space(4*l).output("metal3_min_space", "METAL3 space violations") + +# Chapter 4.1 PWELL rules +# Can we detect the potential and define DRC rules based on same or different potential? + +pwell.separation(nwell,12*l).output("pwell_nwell_separation", "PWELL<->NWELL separation violations") + +# Chapter 4.5 ACTIVE rules +# TODO: The PDF says 6*l, but 2*l is more reasonable. +pwell.enclosing(active,2*l).output("pwell_active_enclosing", "Minimum ACTIVE surround by PWELL") +nwell.enclosing(active,2*l).output("nwell_active_enclosing", "Minimum ACTIVE surround by NWELL") + +# Chapter 4.6 POLY rules +polyoveractive.space(2*l).output("poly_active_separation","Minimum Spacing to POLY over ACTIVE") +poly.overlap(active,2*l).output("poly_active_overlap","Minimum Gate extension beyond ACTIVE") +active.overlap(poly,3*l).output("active_poly_overlap","Minimum ACTIVE extension beyond POLY") +poly.separation(active,1*l).output("poly_active_separation","Minimum Spacing of POLY to ACTIVE") +nwell.enclosing(poly,1*l).output("nwell_poly_enclosing","Minimum POLY surround by NWELL") +pwell.enclosing(poly,1*l).output("pwell_poly_enclosing","Minimum POLY surround by PWELL") + +# Chapter 4.8 CONTACT Rules +contact.overlap(poly|active,1*l).output("contact_polyactive_overlap","Minimum Overlap by POLY or ACTIVE") +contact.separation(gate,2*l).output("contact_gate_separation","Minimum Spacing to Gate") +polycontact.separation(poly,4*l).output("polycontact_poly_separation","Minimum Spacing of POLY CONTACT other POLY") +(active&contact).separation((poly&contact),4*l).output("activecontact_polycontact_separation","Minimum Spacing of POLY CONTACT to other POLY") + +# Chapter 4.9 METAL1 Rules +metal1.overlap(contact|via1,1*l).output("metal1_contact_overlap") +# I dont have an idea how put 2.7.4 into a Klayout design rule + +# Chapter 4.10 +via1.separation(contact,2*l).output("via1_contact_separation","Minimum Spacing to CONTACT") +via1.separation(poly|active,2*l).output("via1_polyactive_separation","Minimum Spacing to POLY or ACTIVE") + +# Chapter 4.11 +metal2.overlap(via1,1*l).output("metal2_via1_overlap","Minimum Overlap to VIA1") + + + diff --git a/Tech.LS1UM/dummy_tech.py b/Tech.LS1UM/dummy_tech.py new file mode 100644 index 00000000..237cb985 --- /dev/null +++ b/Tech.LS1UM/dummy_tech.py @@ -0,0 +1,198 @@ +from lclayout.layout.layers import * + +# Physical size of one data base unit in meters. +db_unit = 1e-9 + +# Scale transistor width. +transistor_channel_width_sizing = 0.7 + +# GDS2 layer numbers for final output. +my_active = (1, 0) +my_nwell = (2, 0) +my_nwell2 = (2, 1) +my_pwell = (2, 7) +my_poly = (3, 0) +my_poly_contact = (4, 0) +my_diff_contact = (5, 0) +my_metal1 = (6, 0) +my_metal1_label = (6, 1) +my_metal1_pin = (6, 2) +my_via1 = (7, 0) +my_metal2 = (8, 0) +my_metal2_label = (8, 1) +my_metal2_pin = (8, 2) +my_abutment_box = (200, 0) + +# lclayout internally uses its own layer numbering scheme. +# For the final output the layers can be remapped with a mapping +# defined in this dictioinary. +output_map = { + l_active: my_active, + l_nwell: [my_nwell, my_nwell2], # Map l_nwell to two output layers. + l_pwell: [my_pwell], # Output layer for pwell. Uncomment this if needed. For instance for twin-well processes. + l_poly: my_poly, + l_poly_contact: my_poly_contact, + l_diff_contact: my_diff_contact, + l_metal1: my_metal1, + l_metal1_label: my_metal1_label, + l_metal1_pin: my_metal1_pin, + l_via1: my_via1, + l_metal2: my_metal2, + l_metal2_label: my_metal2_label, + l_metal2_pin: my_metal2_pin, + l_abutment_box: my_abutment_box +} + +# Define how layers can be used for routing. +# Example for a layer that can be used for horizontal and vertical tracks: {'MyLayer1' : 'hv'} +# Example for a layer that can be contacted but not used for routing: {'MyLayer2' : ''} +routing_layers = { + l_active: '', + l_poly: 'hv', + l_metal1: 'hv', + l_metal2: 'hv', +} + +# Minimum spacing rules for layer pairs. +min_spacing = { + (l_active, l_active): 50, + (l_active, l_poly_contact): 10, + (l_nwell, l_nwell): 50, + (l_nwell, l_pwell): 0, # This might be used when n-well and p-well layers are used for a twin-well process. + (l_pwell, l_pwell): 50, + (l_poly, l_nwell): 50, + (l_poly, l_active): 50, + (l_poly, l_poly): 50, + (l_poly, l_diff_contact): 10, + (l_metal1, l_metal1): 50, + (l_metal2, l_metal2): 100, +} + +# Layer for the pins. +pin_layer = l_metal2 + +# Power stripe layer +power_layer = l_metal1 + +# Layers that can be connected/merged without changing the schematic. +# This can be used to resolve spacing/notch violations by just filling the space. +connectable_layers = {l_nwell} + +# Standard cell dimensions. +# A 'unit cell' corresponds to the dimensions of the smallest possible cell. Usually an inverter. +# `unit_cell_width` also corresponds to the pitch of the gates because gates are spaced on a regular grid. +unit_cell_width = 400 +unit_cell_height = 2400 + +# Width of the gate polysilicon stripe. +gate_length = 50 + +# Minimum length a polysilicon gate must overlap the silicon. +gate_extension = 100 + +# Routing pitch +routing_grid_pitch_x = unit_cell_width // 2 +routing_grid_pitch_y = unit_cell_height // 8 + +# Translate routing grid such that the bottom left grid point is at (grid_offset_x, grid_offset_y) +grid_offset_x = routing_grid_pitch_x +grid_offset_y = routing_grid_pitch_y // 2 + +# Width of power rail. +power_rail_width = 360 + +# Minimum width of polysilicon gate stripes. +minimum_gate_width_nfet = 200 +minimum_gate_width_pfet = 200 + +# Minimum width for pins. +minimum_pin_width = 50 + +# Width of routing wires. +wire_width = { + l_poly: 100, + l_metal1: 100, + l_metal2: 100 +} + +# Width of horizontal routing wires (overwrites `wire_width`). +wire_width_horizontal = { + l_poly: 100, + l_metal1: 100, + l_metal2: 100 +} + +# Side lengths of vias (square shaped). +via_size = { + l_poly_contact: 80, + l_diff_contact: 80, + l_via1: 100 +} + +# Minimum width rules. +minimum_width = { + l_poly: gate_length, + l_metal1: 100, + l_metal2: 100 +} + +# Minimum enclosure rules. +# Syntax: {(outer layer, inner layer): minimum enclosure, ...} +minimum_enclosure = { + # Via enclosure + (l_active, l_diff_contact): 10, + (l_poly, l_poly_contact): 10, + (l_metal1, l_diff_contact): 10, + (l_metal1, l_poly_contact): 10, + (l_metal1, l_via1): 20, + (l_metal2, l_via1): 20, + + # l_nwell must overlap l_active + (l_nwell, l_active): 100 +} + +# Minimum notch rules. +minimum_notch = { + l_active: 50, + l_poly: 50, + l_metal1: 50, + l_metal2: 50, + l_nwell: 50 +} + +# Minimum area rules. +min_area = { + l_metal1: 100 * 100, + l_metal2: 100 * 100, +} + +# ROUTING # + +# Cost for changing routing direction (horizontal/vertical). +# This will avoid creating zig-zag routings. +orientation_change_penalty = 100 + +# Routing edge weights per data base unit. +weights_horizontal = { + l_poly: 2, + l_metal1: 1, + l_metal2: 1, +} +weights_vertical = { + l_poly: 2, + l_metal1: 1, + l_metal2: 2, +} + +# Via weights. +via_weights = { + (l_metal1, l_active): 500, + (l_metal1, l_poly): 500, + (l_metal1, l_metal2): 400 +} + +# Enable double vias between layers. +multi_via = { + (l_metal1, l_poly): 1, + (l_metal1, l_metal2): 1, +} diff --git a/Tech.LS1UM/good/libresilicon.m b/Tech.LS1UM/good/libresilicon.m new file mode 100644 index 00000000..9f3fb7ed --- /dev/null +++ b/Tech.LS1UM/good/libresilicon.m @@ -0,0 +1,6 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos level = 54 + +.model PMOS_VTL pmos level = 54 + diff --git a/Tech.LS1UM/good/libresilicon.m13 b/Tech.LS1UM/good/libresilicon.m13 new file mode 100644 index 00000000..0ed9a895 --- /dev/null +++ b/Tech.LS1UM/good/libresilicon.m13 @@ -0,0 +1,72 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos LEVEL=49 ++ Tnom=27.0 ++ nch=1.024685E+17 tox=1.00000E-08 xj=1.00000E-07 ++ lint=3.75860E-08 wint=-2.02101528644562E-07 ++ vth0=.6094574 k1=.5341038 k2=1.703463E-03 k3=-17.24589 ++ dvt0=.1767506 dvt1=.5109418 dvt2=-0.05 ++ nlx=9.979638E-08 w0=1e-6 ++ k3b=4.139039 ++ vsat=97662.05 ua=-1.748481E-09 ub=3.178541E-18 uc=1.3623e-10 ++ rdsw=298.873 u0=307.2991 prwb=-2.24e-4 ++ a0=.4976366 ++ keta=-2.195445E-02 a1=.0332883 a2=.9 ++ voff=-9.623903E-02 nFactor=.8408191 cit=3.994609E-04 ++ cdsc=1.130797E-04 ++ cdscb=2.4e-5 ++ eta0=.0145072 etab=-3.870303E-03 ++ dsub=.4116711 ++ pclm=1.813153 pdiblc1=2.003703E-02 pdiblc2=.00129051 ++ pdiblcb=-1.034e-3 ++ drout=.4380235 pscbe1=5.752058E+08 pscbe2=7.510319E-05 ++ pvag=.6370527 prt=68.7 ngate=1.e20 alpha0=1.e-7 beta0=28.4 ++ prwg=-0.001 ags=1.2 ++ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032 ++ kt1=-.3 kt2=-.03 ++ at=33000 ++ ute=-1.5 ++ ua1=4.31E-09 ub1=7.61E-18 uc1=-2.378e-10 ++ kt1l=1e-8 ++ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015 ++ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0 ++ cgdo=0.4e-9 cgso=0.4e-9 ++ clc=0.1e-6 ++ cle=0.6 ++ ckappa=0.6 + +.model PMOS_VTL PMOS LEVEL=49 ++ Tnom=27.0 ++ nch=5.73068E+16 tox=1.00000E-08 xj=1.00000E-07 ++ lint=8.195860E-08 wint=-1.821562E-07 ++ vth0=-.86094574 k1=.341038 k2=2.703463E-02 k3=12.24589 ++ dvt0=.767506 dvt1=.65109418 dvt2=-0.145 ++ nlx=1.979638E-07 w0=1.1e-6 ++ k3b=-2.4139039 ++ vsat=60362.05 ua=1.348481E-09 ub=3.178541E-19 uc=1.1623e-10 ++ rdsw=498.873 u0=137.2991 prwb=-1.2e-5 ++ a0=.3276366 ++ keta=-1.8195445E-02 a1=.0232883 a2=.9 ++ voff=-6.623903E-02 nFactor=1.0408191 cit=4.994609E-04 ++ cdsc=1.030797E-3 ++ cdscb=2.84e-4 ++ eta0=.0245072 etab=-1.570303E-03 ++ dsub=.24116711 ++ pclm=2.6813153 pdiblc1=4.003703E-02 pdiblc2=.00329051 ++ pdiblcb=-2.e-4 ++ drout=.1380235 pscbe1=0 pscbe2=1.e-28 ++ pvag=-.16370527 ++ prwg=-0.001 ags=1.2 ++ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032 ++ kt1=-.3 kt2=-.03 prt=76.4 ++ at=33000 ++ ute=-1.5 ++ ua1=4.31E-09 ub1=7.61E-18 uc1=-2.378e-10 ++ kt1l=0 ++ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015 ++ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0 ++ cgdo=0.4e-9 cgso=0.4e-9 ++ clc=0.1e-6 ++ cle=0.6 ++ ckappa=0.6 + diff --git a/Tech.LS1UM/good/libresilicon.m4 b/Tech.LS1UM/good/libresilicon.m4 new file mode 100644 index 00000000..ac4b0ef3 --- /dev/null +++ b/Tech.LS1UM/good/libresilicon.m4 @@ -0,0 +1,28 @@ +.model NMOS_VTL NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) + +.model PMOS_VTL PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 ++ MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) + + diff --git a/Tech.LS1UM/good/libresilicon.m9 b/Tech.LS1UM/good/libresilicon.m9 new file mode 100644 index 00000000..2415a38e --- /dev/null +++ b/Tech.LS1UM/good/libresilicon.m9 @@ -0,0 +1,24 @@ +* Long channel models from CMOS Circuit Design, Layout, and Simulation, +* Level=3 models VDD=5V, see CMOSedu.com +* +.MODEL NMOS_VTL NMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 ++ PHI = 0.7 VTO = 0.8 DELTA = 3.0 ++ UO = 650 ETA = 3.0E-6 THETA = 0.1 ++ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 ++ RSH = 0 NFS = 1E12 TPG = 1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 +* +.MODEL PMOS_VTL PMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 ++ PHI = 0.7 VTO = -0.9 DELTA = 0.1 ++ UO = 250 ETA = 0 THETA = 0.1 ++ KP = 40E-6 VMAX = 5E4 KAPPA = 1 ++ RSH = 0 NFS = 1E12 TPG = -1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 diff --git a/Tech.LS1UM/librecell_tech.py b/Tech.LS1UM/librecell_tech.py new file mode 100644 index 00000000..ed8bee5d --- /dev/null +++ b/Tech.LS1UM/librecell_tech.py @@ -0,0 +1,279 @@ +from lclayout.layout.layers import * +from lclayout.writer.magic_writer import MagWriter +from lclayout.writer.lef_writer import LefWriter +from lclayout.writer.gds_writer import GdsWriter + +# Physical size of one data base unit in meters. +# Libresilicon: We wanted to choose 100nm, so 1 lambda is 5 units of 1e-7, so every lambda value has to be multiplied by 5 +# BUT GDS2 requires the database units to be in nanometers, and lclayout cannot convert to nanometers automatically yet +db_unit = 1e-9 + +# Lambda - how many db_units is 1 lambda? +l = 500 +um = 1000 + +# Scale transistor width. +transistor_channel_width_sizing = 1 + +# GDS2 layer numbers for final output. +my_ndiffusion = (1, 0) +my_pdiffusion = (1, 7) +my_nwell = (2, 0) +#my_nwell2 = (2, 1) # a copy of the nwell layer due to limitations of other tools we don't need +my_pwell = (2, 7) +my_poly = (3, 0) # poly silicium for gates -> poly + ntransistor + ptransistor +my_poly_contact = (4, 0) # Both poly_contact and diff_contact are the same in Libresilicon and they are both just one layer called "CONTACT" +my_diff_contact = (5, 0) # Both poly_contact and diff_contact are the same in Libresilicon and they are both just one layer called "CONTACT" +my_metal1 = (6, 0) +my_metal1_label = (6, 1) +my_metal1_pin = (6, 2) +my_via1 = (7, 0) +my_metal2 = (8, 0) +my_metal2_label = (8, 1) +my_metal2_pin = (8, 2) +my_abutment_box = (200, 0) + +# lclayout internally uses its own layer numbering scheme. +# For the final output the layers can be remapped with a mapping +# defined in this dictioinary. +output_map = { + l_ndiffusion: my_ndiffusion, + l_pdiffusion: my_pdiffusion, + l_nwell: my_nwell, # [my_nwell, my_nwell2], # Map l_nwell to two output layers. + l_pwell: my_pwell, # Output layer for pwell. Uncomment this if needed. For instance for twin-well processes. + l_poly: my_poly, + l_poly_contact: my_poly_contact, + l_diff_contact: my_diff_contact, + l_metal1: my_metal1, + l_metal1_label: my_metal1_label, + l_metal1_pin: my_metal1_pin, + l_via1: my_via1, + l_metal2: my_metal2, + l_metal2_label: my_metal2_label, + l_metal2_pin: my_metal2_pin, + l_abutment_box: my_abutment_box +} + +# Define a list of output writers. +output_writers = [ + MagWriter( + tech_name='scmos', + scale_factor=0.002, # Scale all coordinates by this factor (rounded down to next integer). + output_map={ + l_via1: 'm2contact', + l_poly: 'polysilicon', + l_abutment_box: ['fence'], + l_metal1: 'metal1', + l_metal2: 'metal2', + l_metal1_label: 'metal1', + l_metal2_label: 'metal2', + l_ndiffusion: 'ndiffusion', + l_pdiffusion: 'pdiffusion', + l_metal2_pin: 'metal2', + l_poly_contact: 'polycontact', + l_diff_contact: 'pdcontact' + } + ), + + LefWriter( + db_unit=db_unit, + output_map=output_map + ), + + GdsWriter( + db_unit=db_unit, + output_map=output_map + ) +] + +# Define how layers can be used for routing. +# Example for a layer that can be used for horizontal and vertical tracks: {'MyLayer1' : 'hv'} +# Example for a layer that can be contacted but not used for routing: {'MyLayer2' : ''} +routing_layers = { + l_ndiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_pdiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_poly: '', + l_metal1: 'hv', + l_metal2: 'hv', +} + +# Minimum spacing rules for layer pairs. +min_spacing = { + (l_ndiffusion, l_ndiffusion): 3*l, # 3 -> 3l + (l_pdiffusion, l_ndiffusion): 3*l, # 3 -> 3l + (l_pdiffusion, l_pdiffusion): 3*l, # 3 -> 3l + (l_ndiffusion, l_poly_contact): 4*l, # 2.6.6 -> 4l + (l_pdiffusion, l_poly_contact): 4*l, # 2.6.6 -> 4l + (l_nwell, l_nwell): 10*l, # 3 -> 10l + (l_nwell, l_pwell): 12*l, # 2.2.4->12l + (l_pwell, l_pwell): 10*l, # 3 -> 10l + #(l_poly, l_nwell): 10, # No rule? + (l_poly, l_ndiffusion): 1*l, # 2.4.6 -> 1l + (l_poly, l_pdiffusion): 1*l, # 2.4.6 -> 1l + (l_poly, l_poly): 1*l, # 3 POLY -> 2l XXX: TODO: THIS NEEDS TO BE INCREASED TO 2l BUT AT THE MOMENT IT WOULD BREAK THE ROUTING + (l_poly, l_diff_contact): 2*l, # The maximum "minimum spacing" from poly to anything else is 2l + (l_diff_contact, l_diff_contact): 2*l, # 3 -> 2l + (l_metal1, l_metal1): 4*l, # 3 METAL1 -> 4l # !!!! WARNING: Spacing to BigMetal (>=10um) needs to be 6l ! + (l_metal2, l_metal2): 4*l, # 3 METAL2 -> 4l + (l_via1, l_via1): 3*l, # 3 VIA1 -> 3l + (l_via1, l_diff_contact): 2*l, # 2.8.3 -> 2l + (l_via1, l_ndiffusion): 2*l, # 2.8.4 -> 2l + (l_via1, l_pdiffusion): 2*l, # 2.8.4 -> 2l + (l_poly_contact, l_diff_contact): 4*l, +} + +# Layer for the pins. +pin_layer = l_metal2 + +# Power stripe layer +power_layer = l_metal1 # Was recommended by leviathanch due to lesser resistance + +# Layers that can be connected/merged without changing the schematic. +# This can be used to resolve spacing/notch violations by just filling the space. +connectable_layers = {l_nwell, l_pwell} +# Width of the gate polysilicon stripe. +# is reused as the minimum_width for the l_poly layer +gate_length = 2*l # 2.4.1 -> 2l + +# Minimum length a polysilicon gate must overlap the silicon. +gate_extension = 2*l # 2.4.4 -> 2l + +# Minimum distance of active area to upper or lower boundary of the cell. Basically determines the y-offset of the transistors. +transistor_offset_y = 12*l + +# Standard cell dimensions. +# A 'unit cell' corresponds to the dimensions of the smallest possible cell. Usually an inverter. +# `unit_cell_width` also corresponds to the pitch of the gates because gates are spaced on a regular grid. +unit_cell_width = 16 * l +unit_cell_height = 64 * l # minimum 16um due to pwell width + nwell-pwell spacing +assert unit_cell_height >= 16*um, "minimum 16um due to pwell width + nwell-pwell spacing" +# due to nwell size and spacing requirements routing_grid_pitch_y * 8 # * 8 + +# Routing pitch +routing_grid_pitch_x = unit_cell_width // 2 // 1 +routing_grid_pitch_y = 2*l # unit_cell_height // 8 // 2 + +# Translate routing grid such that the bottom left grid point is at (grid_offset_x, grid_offset_y) +grid_offset_x = routing_grid_pitch_x +grid_offset_y = (routing_grid_pitch_y // 2 ) -0 + +# Width of power rail. +power_rail_width = 6*l +# Between 2 and 3 um + +# Minimum width of polysilicon gate stripes. +# I think this should be (extension over active) + (minimum width of active) + (extension over active) +# No, it seems to be something else. +# It increases w and l from the spice netlist, so it must be width from the spice netlist +minimum_gate_width_nfet = 2*l +minimum_gate_width_pfet = 2*l + +# Minimum width for pins. +minimum_pin_width = 2*l # 2l said leviathanch + +# Width of routing wires. +wire_width = { + l_ndiffusion: 2*l, + l_pdiffusion: 2*l, + l_poly: 2*l, # 2.4.1 -> 2l + l_metal1: 4*l, # 2.7.1 -> 4l + l_metal2: 4*l, # 2.9.1 -> 4l +} + +# Width of horizontal routing wires (overwrites `wire_width`). +wire_width_horizontal = { + l_ndiffusion: 2*l, + l_pdiffusion: 2*l, + l_poly: 2*l, # 2.4.1 -> 2l + l_metal1: 4*l, # 2.7.1 -> 4l + l_metal2: 4*l, # 2.9.1 -> 4l +} + +# Side lengths of vias (square shaped). +via_size = { + l_poly_contact: 2*l, # 2.6.1 -> 2l + l_diff_contact: 2*l, # 2.6.1 -> 2l + l_via1: 2*l # 2.8.1 -> 2l +# l_via2: 10 # 2.10.1 -> 2l librecell only goes to metal2, via2 would go to metal3 +} + +# Minimum width rules. +minimum_width = { + l_ndiffusion: 2*l, # 4 l + l_pdiffusion: 2*l, # 4 l + l_poly: gate_length, # 2.4.1-> 2l + l_metal1: 4*l, # 2.7.1 -> 4l + l_metal2: 4*l, # 2.9.1 -> 4l +} + +# Minimum enclosure rules. +# Syntax: {(outer layer, inner layer): minimum enclosure, ...} +minimum_enclosure = { + # Via enclosure + (l_ndiffusion, l_diff_contact): 1*l, # 2.3.3 -> 6l Source/Drain are DIFF's + (l_pdiffusion, l_diff_contact): 1*l, # 2.3.3 -> 6l Source/Drain are DIFF's + (l_poly, l_poly_contact): 1*l, # 2.6.2 -> 1l ?!?!? PLEASE VERIFY WHETHER THIS IS CORRECT + (l_metal1, l_diff_contact): 1*l, # 2.7.3 -> 1l + (l_metal1, l_poly_contact): 1*l, # 2.7.3 -> 1l + (l_metal1, l_via1): 1*l,# 2.7.3 -> 1l + (l_metal2, l_via1): 1*l,# 2.9.3 -> 1l + + # l_*well must overlap l_*diffusion + (l_nwell, l_pdiffusion): 2*l, # 2.3.3 -> 2l + (l_pwell, l_ndiffusion): 2*l, # 2.3.3 -> 2l + (l_abutment_box, l_nwell): 0, # The nwell and pwell should not go beyond the abutment + (l_abutment_box, l_pwell): 0, +} + +# Minimum notch rules. +minimum_notch = { + l_ndiffusion: 1*l, + l_pdiffusion: 1*l, + l_poly: 1*l, + l_metal1: 1*l, + l_metal2: 1*l, + l_nwell: 1*l, + l_pwell: 1*l, +} + +# Minimum area rules. +min_area = { +# l_metal1: 100 * 100, +# l_metal2: 100 * 100, +} + +# ROUTING # + +# Cost for changing routing direction (horizontal/vertical). +# This will avoid creating zig-zag routings. +orientation_change_penalty = 100 + +# Routing edge weights per data base unit. +weights_horizontal = { + l_ndiffusion: 10000, + l_pdiffusion: 10000, + l_poly: 10, + l_metal1: 1, + l_metal2: 2, +} +weights_vertical = { + l_ndiffusion: 10000, + l_pdiffusion: 10000, + l_poly: 10, + l_metal1: 1, + l_metal2: 2, +} + +# Via weights. +via_weights = { + (l_metal1, l_ndiffusion): 500, + (l_metal1, l_pdiffusion): 500, + (l_metal1, l_poly): 500, + (l_metal1, l_metal2): 400 +} + +# Enable double vias between layers. +multi_via = { + (l_metal1, l_poly): 1, + (l_metal1, l_metal2): 1, +} diff --git a/Tech.LS1UM/libresilicon.m b/Tech.LS1UM/libresilicon.m new file mode 100644 index 00000000..473e6e0a --- /dev/null +++ b/Tech.LS1UM/libresilicon.m @@ -0,0 +1,14 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos level = 54 + +.model PMOS_VTL pmos level = 54 + +.model nmos nmos level = 54 + +.model pmos pmos level = 54 + +.model nfet nmos level = 54 + +.model pfet pmos level = 54 + diff --git a/Tech.LS1UM/libresilicon.m13 b/Tech.LS1UM/libresilicon.m13 new file mode 100644 index 00000000..0ed9a895 --- /dev/null +++ b/Tech.LS1UM/libresilicon.m13 @@ -0,0 +1,72 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos LEVEL=49 ++ Tnom=27.0 ++ nch=1.024685E+17 tox=1.00000E-08 xj=1.00000E-07 ++ lint=3.75860E-08 wint=-2.02101528644562E-07 ++ vth0=.6094574 k1=.5341038 k2=1.703463E-03 k3=-17.24589 ++ dvt0=.1767506 dvt1=.5109418 dvt2=-0.05 ++ nlx=9.979638E-08 w0=1e-6 ++ k3b=4.139039 ++ vsat=97662.05 ua=-1.748481E-09 ub=3.178541E-18 uc=1.3623e-10 ++ rdsw=298.873 u0=307.2991 prwb=-2.24e-4 ++ a0=.4976366 ++ keta=-2.195445E-02 a1=.0332883 a2=.9 ++ voff=-9.623903E-02 nFactor=.8408191 cit=3.994609E-04 ++ cdsc=1.130797E-04 ++ cdscb=2.4e-5 ++ eta0=.0145072 etab=-3.870303E-03 ++ dsub=.4116711 ++ pclm=1.813153 pdiblc1=2.003703E-02 pdiblc2=.00129051 ++ pdiblcb=-1.034e-3 ++ drout=.4380235 pscbe1=5.752058E+08 pscbe2=7.510319E-05 ++ pvag=.6370527 prt=68.7 ngate=1.e20 alpha0=1.e-7 beta0=28.4 ++ prwg=-0.001 ags=1.2 ++ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032 ++ kt1=-.3 kt2=-.03 ++ at=33000 ++ ute=-1.5 ++ ua1=4.31E-09 ub1=7.61E-18 uc1=-2.378e-10 ++ kt1l=1e-8 ++ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015 ++ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0 ++ cgdo=0.4e-9 cgso=0.4e-9 ++ clc=0.1e-6 ++ cle=0.6 ++ ckappa=0.6 + +.model PMOS_VTL PMOS LEVEL=49 ++ Tnom=27.0 ++ nch=5.73068E+16 tox=1.00000E-08 xj=1.00000E-07 ++ lint=8.195860E-08 wint=-1.821562E-07 ++ vth0=-.86094574 k1=.341038 k2=2.703463E-02 k3=12.24589 ++ dvt0=.767506 dvt1=.65109418 dvt2=-0.145 ++ nlx=1.979638E-07 w0=1.1e-6 ++ k3b=-2.4139039 ++ vsat=60362.05 ua=1.348481E-09 ub=3.178541E-19 uc=1.1623e-10 ++ rdsw=498.873 u0=137.2991 prwb=-1.2e-5 ++ a0=.3276366 ++ keta=-1.8195445E-02 a1=.0232883 a2=.9 ++ voff=-6.623903E-02 nFactor=1.0408191 cit=4.994609E-04 ++ cdsc=1.030797E-3 ++ cdscb=2.84e-4 ++ eta0=.0245072 etab=-1.570303E-03 ++ dsub=.24116711 ++ pclm=2.6813153 pdiblc1=4.003703E-02 pdiblc2=.00329051 ++ pdiblcb=-2.e-4 ++ drout=.1380235 pscbe1=0 pscbe2=1.e-28 ++ pvag=-.16370527 ++ prwg=-0.001 ags=1.2 ++ dvt0w=0.58 dvt1w=5.3e6 dvt2w=-0.0032 ++ kt1=-.3 kt2=-.03 prt=76.4 ++ at=33000 ++ ute=-1.5 ++ ua1=4.31E-09 ub1=7.61E-18 uc1=-2.378e-10 ++ kt1l=0 ++ wr=1 b0=1e-7 b1=1e-7 dwg=5e-8 dwb=2e-8 delta=0.015 ++ cgdl=1e-10 cgsl=1e-10 cgbo=1e-10 xpart=0.0 ++ cgdo=0.4e-9 cgso=0.4e-9 ++ clc=0.1e-6 ++ cle=0.6 ++ ckappa=0.6 + diff --git a/Tech.LS1UM/libresilicon.m4 b/Tech.LS1UM/libresilicon.m4 new file mode 100644 index 00000000..ac4b0ef3 --- /dev/null +++ b/Tech.LS1UM/libresilicon.m4 @@ -0,0 +1,28 @@ +.model NMOS_VTL NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) + +.model PMOS_VTL PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 ++ MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) + + diff --git a/Tech.LS1UM/libresilicon.m9 b/Tech.LS1UM/libresilicon.m9 new file mode 100644 index 00000000..2415a38e --- /dev/null +++ b/Tech.LS1UM/libresilicon.m9 @@ -0,0 +1,24 @@ +* Long channel models from CMOS Circuit Design, Layout, and Simulation, +* Level=3 models VDD=5V, see CMOSedu.com +* +.MODEL NMOS_VTL NMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 ++ PHI = 0.7 VTO = 0.8 DELTA = 3.0 ++ UO = 650 ETA = 3.0E-6 THETA = 0.1 ++ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 ++ RSH = 0 NFS = 1E12 TPG = 1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 +* +.MODEL PMOS_VTL PMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 ++ PHI = 0.7 VTO = -0.9 DELTA = 0.1 ++ UO = 250 ETA = 0 THETA = 0.1 ++ KP = 40E-6 VMAX = 5E4 KAPPA = 1 ++ RSH = 0 NFS = 1E12 TPG = -1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 diff --git a/Tech.LS1UM/libresilicon.tech b/Tech.LS1UM/libresilicon.tech new file mode 100644 index 00000000..62f426fb --- /dev/null +++ b/Tech.LS1UM/libresilicon.tech @@ -0,0 +1,2242 @@ +# 1 "scmos.tech.out" +# 1 "" +# 1 "" +# 1 "/usr/include/stdc-predef.h" 1 3 4 +# 1 "" 2 +# 1 "scmos.tech.out" +# 351 "scmos.tech.out" +tech + format 33 + scmos +end + + + +version + version 0.1 + description "LibreSilicon process (1um)" +# 382 "scmos.tech.out" +end + +planes + well,w + implant,i + active,a + metal1,m1 + metal2,m2 + + + + metal3,m3 + metal4,m4 + oxide,ox +end + +types + + + well pwell,pw + well nwell,nw + well capwell,cwell,cw + well highvoltnwell,hvnwell,hnwell,hnw + well highvoltpwell,hvpwell,hpwell,hpw + active polysilicon,red,poly,p + active pbasepolysilicon,pbpoly,pbp + active nbasepolysilicon,nbpoly,nbp + active electrode,poly2,el,p2 + active capacitor,polycap,pcap,cap + active wellcapacitor,wellcap,wcap + active ndiffusion,ndiff,green + active pdiffusion,pdiff,brown + active highvoltndiffusion,hvndiff,hndiff + active highvoltpdiffusion,hvpdiff,hpdiff + metal1 metal1,m1,blue + metal2 metal2,m2,purple + metal3 metal3,m3,cyan + metal4 metcap,mcap + + + + active sonosntransistor,snfet + active sonosptransistor,spfet + active pbsonostransistor,pbsfet + active nbsonostransistor,nbsfet + active ntransistor,nfet + active ptransistor,pfet + active entransistor,enfet + active eptransistor,epfet + active doublentransistor,nfloating-gate,nfloatg,nfg,nffet + active doubleptransistor,pfloating-gate,pfloatg,pfg,pffet + active highvoltntransistor,hvnfet,hnfet + active highvoltptransistor,hvpfet,hpfet + active rntransistor,rnfet + active rptransistor,rpfet + + + + + active collector,coll,col,co,cl + active emitter,emit,em + + + well pbase,pb + well nbase,nb + well pnbase,pnb + well nwpbase,nwpb + well nwpnbase,nwpnb + + active pbasecontact,pbcontact,pbc + active pbasendiffusion,pbndiff,pbnd + active pbasepdiffusion,pbpdiff,pbpd + active pbasendiffcontact,pbndcontact,pbnc + active pbasepdiffcontact,pbpdcontact,pbpc + + active nbasecontact,nbcontact,nbc + active nbasendiffusion,nbndiff,nbnd + active nbasepdiffusion,nbpdiff,nbpd + active nbasendiffcontact,nbndcontact,nbnc + active nbasepdiffcontact,nbpdcontact,nbpc + + + + implant bccdiffusion,bd + active nbccdiffusion,nbd + + + active rndiffusion,rndiff,rnd + active rpdiffusion,rpdiff,rpd + active rpoly,rp,resistor,res + active polycontact,pcontact,polycut,pc + active pdpolycontact,pdpcontact,pdpolycut,pdpc + active ndpolycontact,ndpcontact,ndpolycut,ndpc + active ndcontact,ndiffcut,ndc + active pdcontact,pdiffcut,pdc + active highvoltndcontact,hndiffcut,hndc + active highvoltpdcontact,hpdiffcut,hpdc + active capcontact,ccontact,capc,cc + active electrodecontact,econtact,ec,poly2contact,p2c + active collectorcontact,colcontact,colc,coc,clc + active emittercontact,emitcontact,emc + active nbccdiffcontact,nbdc + metal1 m2contact,m2cut,m2c,via,v + + + + metal2 m3contact,m3cut,m3c,via2,v2 + + + + + + + active psubstratepcontact,ppcontact,ppc,pwcontact,pwc,psc + active nsubstratencontact,nncontact,nnc,nwcontact,nwc,nsc + active psubstratepdiff,ppdiff,pohmic,ppd,psd + active nsubstratendiff,nndiff,nohmic,nnd,nsd + + active highvoltpsubcontact,hpwcontact,hpsc + active highvoltnsubcontact,hnwcontact,hnsc + active highvoltpsubdiff,hpohmic,hpsd + active highvoltnsubdiff,hnohmic,hnsd + + + active nplusdoping,ndoping,ndop + active pplusdoping,pdoping,pdop + metal1 genericcontact,gcontact,gc + + + oxide substrateopen,subopen,open + oxide pdiffusionstop,pdiffstop,pstop + + + metal2 pad + oxide glass + metal3 silk + + active polyndiff,plndiff + active polypdiff,plpdiff + +end + +contact + + ec poly2 metal1 + cc cap metal1 + pc poly metal1 + + ndc ndiff metal1 + pdc pdiff metal1 + nsc nsd metal1 + psc psd metal1 + hndc hndiff metal1 + hpdc hpdiff metal1 + hnsc hnsd metal1 + hpsc hpsd metal1 + + clc col metal1 + emc emit metal1 + + + + + + + + nbdc nbd metal1 + + m2c metal1 metal2 + + + + m3c metal2 metal3 + + + + # MAGIC: stackable! + stackable +end + +styles + styletype mos + + + cwell 10 + nwell 12 + pwell 13 + hnwell 18 + hpwell 11 + + poly 1 + poly2 14 + + ndiff 2 + pdiff 4 + psd 5 + nsd 3 + hndiff 2 + hndiff 11 + hpdiff 4 + hpdiff 18 + hpsd 5 + hpsd 11 + hnsd 3 + hnsd 18 + ndop 2 + ndop 38 + pdop 4 + pdop 38 + + rnfet 6 + rpfet 6 + snfet 6 + spfet 6 + nbsfet 6 + pbsfet 6 + nfet 6 + nfet 7 + rnfet 6 + rnfet 7 + pfet 8 + pfet 9 + rpfet 8 + rpfet 9 + + enfet 6 + enfet 30 + + epfet 8 + epfet 31 + + + nffet 6 + nffet 7 + + nffet 30 + pffet 8 + pffet 9 + + pffet 31 + + hnfet 6 + hnfet 7 + hnfet 30 + + hpfet 8 + hpfet 9 + hpfet 31 + + + pbase pdop_stripes + pbc 15 + pbc 20 + pbc 32 + pbnd 2 + pbpd 4 + pbnc 2 + pbpc 4 + pbnc 32 + pbpc 32 + + + nbase ndop_stripes + nbc 20 + nbc 32 + nbnd 2 + nbpd 4 + nbnc 2 + nbpc 4 + nbnc 32 + nbpc 32 + + + pnbase ndop_stripes + nwpnbase ndop_stripes + + nwpbase pdop_stripes + + + emit 16 + emc 16 + emc 20 + emc 32 + + col 3 + clc 3 + clc 20 + clc 32 + + cap 1 + cap 14 + wcap 6 + wcap 10 + cc 1 + cc 14 + cc 20 + cc 32 + + metal1 20 + metal2 21 + metal3 22 + metcap 23 + + gc 19 + + pcontact 26 + pcontact 32 + ec 14 + ec 20 + ec 32 + + ndpc 32 + pdpc 32 + ndc 2 + ndc 20 + ndc 32 + pdc 4 + pdc 20 + pdc 32 + psc 5 + psc 20 + psc 32 + nsc 3 + nsc 20 + nsc 32 + + hndc 2 + hndc 20 + hndc 32 + hndc 11 + hpdc 4 + hpdc 20 + hpdc 32 + hpdc 18 + hpsc 5 + hpsc 20 + hpsc 32 + hpsc 11 + hnsc 3 + hnsc 20 + hnsc 32 + hnsc 18 + + m2contact 20 + m2contact 21 + m2contact 33 + m3contact 21 + m3contact 22 + m3contact 37 + + pad 20 + pad 21 + pad 33 + pad 34 + glass 34 + + bd 17 + nbd 17 + nbd 3 + nbdc 3 + nbdc 17 + nbdc 20 + nbdc 32 + + open 2 + open 20 + pstop 8 + + error_p 42 + error_s 42 + error_ps 42 + res poly_resist poly_resist_stripes + + rnd ntransistor_stripes + rpd ptransistor_stripes + + rnfet polysilicon poly_resist_stripes + rpfet polysilicon ptransistor_stripes + + plpdiff polysilicon ptransistor_stripes + plndiff polysilicon ntransistor_stripes + pbpoly polysilicon ptransistor_stripes + nbpoly polysilicon ntransistor_stripes + silk 47 +end +compose + + compose nfet poly hndiff + compose pfet poly hpdiff + compose nfet poly ndiff + compose pfet poly pdiff + compose hnfet poly2 hndiff + compose hpfet poly2 hpdiff + compose enfet poly2 ndiff + compose epfet poly2 pdiff + compose nffet nfet poly2 + compose pffet pfet poly2 + compose nffet enfet poly + compose pffet epfet poly + compose cap poly poly2 + + + + + + paint clc col clc + paint emc emit emc + + paint emc pbase emc + paint pbnd pbase pbnd + paint pbpd pbase pbpd + paint snfet pbase pbsfet + paint spfet pbase pbsfet + paint pbsfet pbase pbsfet + paint poly pbase pbpoly + paint pbpoly pbase pbpoly + paint ndiff pbase pbnd + paint pdiff pbase pbpd + paint ndc pbase pbnc + paint pdc pbase pbpc + paint pbpc pbase pbpc + paint pbnc pbase pbnc + paint ppc pbase pbpc + paint nnc pbase pbnc + + paint nbnd pbase nbnd + paint nbpd pbase nbpd + paint nbnc pbase nbnc + paint nbpc pbase nbpc + paint nbpoly pbase nbpoly + + paint emc nwpbase emc + paint pbnd nwpbase pbnd + paint pbpd nwpbase pbpd + paint snfet nwpbase pbsfet + paint spfet nwpbase pbsfet + paint pbsfet nwpbase pbsfet + paint poly nwpbase pbpoly + paint pbpoly nwpbase pbpoly + paint ndiff nwpbase pbnd + paint pdiff nwpbase pbpd + paint ndc nwpbase pbnc + paint pdc nwpbase pbpc + paint pbpc nwpbase pbpc + paint pbnc nwpbase pbnc + paint ppc nwpbase pbpc + paint nnc nwpbase pbnc + + paint nbnd nwpbase nbnd + paint nbpd nwpbase nbpd + paint nbnc nwpbase nbnc + paint nbpc nwpbase nbpc + paint nbpoly nwpbase nbpoly + + + paint nbnd nbase nbnd + paint nbpd nbase nbpd + paint snfet nbase nbsfet + paint spfet nbase nbsfet + paint nbsfet nbase nbsfet + paint poly nbase nbpoly + paint nbpoly nbase nbpoly + paint ndiff nbase nbnd + paint pdiff nbase nbpd + paint ndc nbase nbnc + paint pdc nbase nbpc + paint nbpc nbase nbpc + paint nbnc nbase nbnc + paint ppc nbase nbpc + paint nnc nbase nbnc + + + paint nwpbase nbase nwpnbase + paint nbnd nbase nbnd + paint pbase nbase pnbase + + paint nwpbase nwell nwpbase + paint pnbase nwell nwpnbase + paint nwpnbase nwell nwpnbase + + paint nwell pbase nwpbase + paint nbase pbase pnbase + paint nwpbase pbase nwpbase + + paint nwpnbase nwpbase nwpnbase + + + paint pbase nwell nwpbase + + + paint poly2 poly cap + paint poly poly2 cap + paint poly cap cap + paint poly2 cap cap + paint cap poly cap + paint cap poly2 cap + + + paint ec poly cc + + + + paint pdc pwell ndc + paint pfet pwell nfet + paint epfet pwell enfet + paint pffet pwell nffet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + paint ndc nwell pdc + paint nfet nwell pfet + paint enfet nwell epfet + paint nffet nwell pffet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + + paint pdc hpwell hndc + paint epfet hpwell hnfet + paint pffet hpwell hnfet + paint pdiff hpwell hndiff + paint nsd hpwell hpsd + paint nsc hpwell hpsc + paint ndc hnwell hpdc + paint enfet hnwell hpfet + paint nffet hnwell hpfet + paint ndiff hnwell hpdiff + paint psd hnwell hnsd + paint psc hnwell hnsc +# 919 "scmos.tech.out" + paint nfet cwell wcap + paint poly wcap wcap + paint ndiff wcap wcap + paint wcap poly wcap + paint wcap ndiff wcap + erase wcap poly ndiff + erase wcap ndiff poly + erase wcap cwell nfet + paint cwell nfet wcap active + erase wcap nfet cwell well + + + paint gc m1 gc + + + paint pad m1 pad + paint pad m2 pad + paint pad m3 pad + paint pad m2c pad + + + + + paint hpdc hpwell hndc + paint hpfet hpwell hnfet + paint hpdiff hpwell hndiff + paint hnsd hpwell hpsd + paint hnsc hpwell hpsc + paint hndc hnwell hpdc + paint hnfet hnwell hpfet + paint hndiff hnwell hpdiff + paint hpsd hnwell hnsd + paint hpsc hnwell hnsc + + paint hpdc pwell ndc + paint hpfet pwell enfet + paint hpdiff pwell ndiff + paint hnsd pwell psd + paint hnsc pwell psc + paint hndc nwell pdc + paint hnfet nwell epfet + paint hndiff nwell pdiff + paint hpsd nwell nsd + paint hpsc nwell nsc + +end + +connect + + + + + + + + nwell,nsc,nsd nwell,nsc,nsd + pwell,psc,psd pwell,psc,psd + + hnwell,hnsc,hnsd hnwell,hnsc,hnsd + hpwell,hpsc,hpsd hpwell,hpsc,hpsd + + ndiff,ndc/a cwell + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc + m2,m2c/m2,m3c/m2,pad m2,m2c/m2,m3c/m2,pad + m3,m3c/m3 m3,m3c/m3 + + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly + poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet + + + + ndiff,ndc/a,ndop psd,psc/a,pdop,pstop + pdiff,pdc/a,pdop,pstop nsd,nsc/a,ndop + hndiff,hndc/a,ndop hpsd,hpsc/a,pdop,pstop + hpdiff,hpdc/a,pdop,pstop hnsd,hnsc/a,ndop + ndiff ndc + pdiff pdc + hndiff hndc + hpdiff hpdc + + nbd nbdc + + pbase pbc + collector clc,nwell + emitter emc + + gc ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a,nsd,nsc/a,psd,psc/a,hndiff,hndc/a,hpdiff,hpdc/a,metal1 + gc poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly + gc poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet + + pad pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc + pad m2,m2c/m2,m3c/m2,pad + pad m3,m3c/m3 + +end +# 1024 "scmos.tech.out" +cifoutput + + + + + + +# 1 "cif_template/objs/LSACIFout" 1 + + + style lambda=0.5(gen)(libresilicon) + scalefactor 50 5 + + templayer poly_parts polysilicon,polycontact,nfet,pfet,rpoly,polypdiff,polyndiff,ndpolycontact,pdpolycontact,nbsfet,pbsfet,spfet,snfet,pbpoly,nbpoly,hnfet,hpfet,rnfet,rpfet + + templayer silicide_stop rpoly,rnfet,rpfet,rpdiffusion,rndiffusion + grow 100 + + templayer nimplant ndiff,nfet,ndc,nnd,nnc,pbnc,pbnd,nbnc,nbnd,snfet,pbsfet,hnfet,hndc,hndiff,rndiff,rpdiff,rpfet,rnfet + + templayer nimplant_only rnd,plndiff,ndpc + grow 100 + + templayer pimplant pdiff,pfet,pdc,ppd,ppc,pbpc,pbpd,nbpc,nbpd,spfet,nbsfet,hpfet,hpdc,hpdiff + + templayer pimplant_only rpd,plpdiff,pdpc + grow 100 + + templayer contacts pc,pdc,ndc,ppc,nnc,pbc,ndpc,pdpc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,pc,pdc,ndc,ppc,nnc,pbc,hpdc,hndc + + templayer first_metal m1,contacts,m2c + + templayer first_via m2c + shrink 50 + + templayer second_metal m2,m2c,m3c + + templayer second_via m3c + shrink 50 + + templayer third_metal m3,m3c,pad,silk + + templayer pbase_parts pb,pbnc,pbpc,pbnd,pbpd,pbpoly,pbsfet,nwpnbase,nwpbase,pnbase,pbase + + templayer nbase_parts nb,nbnc,nbpc,nbnd,nbpd,nbpoly,nbsfet,nwpnbase,pnbase,nbase + + templayer sonos_parts snfet,spfet,nbsfet,pbsfet + + templayer nwell_parts nwell,pnbase,nwpnbase,nwpbase + + templayer pwell_parts pwell + + templayer implant_stop_parts rpoly + grow 100 + + templayer fox_selects nimplant,pimplant + + templayer fox_nimplant nimplant + grow 100 + + templayer fox_pimplant pimplant + grow 100 + + templayer sti_wells nwell_parts,pwell_parts + shrink 50 + + templayer sti_contacts psc,nsc + grow 50 + + layer CWN nwell_parts + calma 2 0 + + layer CWP pwell_parts + calma 3 0 + + layer CWP pbase_parts + calma 4 0 + + layer CWP nbase_parts + calma 5 0 + + layer STI sti_wells,sti_contacts + calma 6 0 + + layer FOX fox_selects + calma 7 0 + + layer CPG sonos_parts + grow 50 + calma 8 0 + + layer CPG poly_parts + calma 9 0 + + layer CPG implant_stop_parts + calma 10 0 + + layer CSN fox_nimplant,nimplant_only + calma 11 0 + + layer CSP fox_pimplant,pimplant_only + calma 12 0 + + layer CRG silicide_stop + calma 13 0 + + layer CCA contacts + shrink 50 + calma 14 0 + + layer CMF first_metal + calma 15 0 + + layer CVA first_via + calma 16 0 + + layer CMS second_metal + calma 17 0 + + layer CVS second_via + calma 18 0 + + layer CMT third_metal + calma 19 0 + + layer COG glass + calma 20 0 +# 1032 "scmos.tech.out" 2 +# 1050 "scmos.tech.out" + style plot + scalefactor 100 50 + layer CM2 m2,m2c/m2,pad/m2 + labels m2 + layer CM1 pad + grow 100 + or m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1 + labels m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1,pad/m1 + layer CP poly,pc/active,nfet,pfet + labels poly,nfet,pfet + layer CND ndiff,ndc,nfet,pwc,psd + labels ndiff + layer CPD pdiff,pdc,pfet,nwc,nsd + labels pdiff + layer CNP + bloat-or nsd,nwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 + layer CPP + bloat-or psd,pwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 + layer CV m2c + squares 100 200 300 + layer CC ndc,pdc,pc,pwc,nwc + squares 200 + layer CNW nwell + grow 400 + shrink 400 + layer CG pad + shrink 600 + or glass + labels glass + + +end +# 1093 "scmos.tech.out" +cifinput +# The following section is defined to be able to import GDS2 cells generated by librecell +# 1097 "scmos.tech.out" + style generic + scalefactor 100 + + templayer poly_parts polysilicon,polycontact,nfet,pfet,rpoly,polypdiff,polyndiff,ndpolycontact,pdpolycontact,rpdiffusion,rndiffusion,nbsfet,pbsfet,spfet,snfet,pbpoly,nbpoly,hnfet,hpfet + templayer silicide_stop rpoly,rpdiffusion,rndiffusion + templayer nimplant ndiff,nfet,ndc,nnd,nnc,pbnc,pbnd,nbnc,nbnd,snfet,pbsfet,hnfet,hndc,hndiff + templayer nimplant_only rnd,plndiff,ndpc + grow 100 + templayer pimplant pdiff,pfet,pdc,ppd,ppc,pbpc,pbpd,nbpc,nbpd,spfet,nbsfet,hpfet,hpdc,hpdiff + templayer pimplant_only rpd,plpdiff,pdpc + grow 100 + templayer contacts pc,pdc,ndc,ppc,nnc,pbc,ndpc,pdpc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,pc,pdc,ndc,ppc,nnc,pbc,hpdc,hndc + templayer first_metal m1,contacts,m2c + templayer first_via m2c + shrink 50 + templayer second_metal m2,m2c,m3c + templayer second_via m3c + shrink 50 + templayer third_metal m3,m3c,pad,silk + templayer pbase_parts pb,pbnc,pbpc,pbnd,pbpd,pbpoly,pbsfet,nwpnbase,nwpbase,pnbase,pbase + templayer nbase_parts nb,nbnc,nbpc,nbnd,nbpd,nbpoly,nbsfet,nwpnbase,pnbase,nbase + templayer sonos_parts snfet,spfet,nbsfet,pbsfet + templayer nwell_parts nwell,pnbase,nwpnbase,nwpbase + templayer pwell_parts pwell + templayer implant_stop_parts rpoly + grow 100 + templayer fox_selects nimplant,pimplant + templayer fox_nimplant nimplant + templayer fox_pimplant pimplant + templayer sti_wells nwell_parts,pwell_parts + templayer sti_contacts psc,nsc + + + layer pdiffusion pdiffusion + calma pdiffusion 1 0 + + layer nwell nwell_parts + calma nwell 2 0 + + layer pwell pwell_parts + calma pwell 2 7 + + layer poly poly + calma poly 3 0 + + layer polycontact polycontact + calma polycontact 4 0 + + layer ndcontact ndcontact + calma ndcontact 5 0 + + layer metal1 metal1 + calma metal1 6 0 + calma metal1 6 1 + labels metal1 + + + layer m2contact m2contact + calma m2contact 7 0 + labels metal2 + + layer metal2 metal2 + calma metal2 8 0 + calma metal2 8 1 + calma metal2 8 2 + labels metal2 + + layer pdcontact pdcontact + calma pdcontact 5 0 + + templayer abutment + calma abutment 200 0 + boundary + + +# 1111 "scmos.tech.out" +end + +mzrouter + style irouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + layer poly 128 128 512 1 + contact m2contact metal1 metal2 1024 + contact pcontact metal1 poly 2056 + notactive poly pcontact + style garouter + layer m2 32 64 256 1 + layer m1 64 32 256 1 + contact m2contact metal1 metal2 1024 +end + + + +drc +# 1143 "scmos.tech.out" + edge4way (~nwell)/w nwell 10 nwell nwell 10\ + "N-Well width must be at least 10 (MOSIS rule #1.1)" + edge4way (~pwell)/w pwell 10 pwell pwell 10\ + "P-Well width must be at least 10 (MOSIS rule #1.1)" +# 1163 "scmos.tech.out" + edge4way nwell (~nwell)/w 9 (~nwell)/w (~nwell)/w 9\ + "N-Well spacing must be at least 9 (MOSIS rule #1.2)" + edge4way pwell (~pwell)/w 9 (~pwell)/w (~pwell)/w 9\ + "P-Well spacing must be at least 9 (MOSIS rule #1.2)" +# 1202 "scmos.tech.out" + width ndiff,ndc/a,nfet,enfet,nffet,wcap 2 \ + "N-type Diffusion width must be at least 2" + width pdiff,pdc/a,pfet,epfet,pffet 2 \ + "P-type Diffusion width must be at least 2" + width nsd,nsc/a,psd,psc/a 2 \ + "Ohmic diffusion width must be at least 2" +# 1218 "scmos.tech.out" + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap ndiff,ndc/a,nfet,enfet,nffet,wcap 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing pdiff,pdc/a,pfet,epfet,pffet pdiff,pdc/a,pfet,epfet,pffet 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing nsd,nsc/a nsd,nsc/a 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + spacing psd,psc/a psd,psc/a 3 touching_ok \ + "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" + + + + + + + spacing ndiff,ndc/a pdiff,pdc/a 10 touching_illegal \ + "P-type diffusion must be 10 away from N-type diffusion (MOSIS rule #2.3a)" +# 1243 "scmos.tech.out" + spacing ndiff,ndc/a nsd,nsc/a 8 touching_illegal \ + "N-type diffusion must be 8 away from N-substrate contact (MOSIS rule #2.3a,4a)" + spacing pdiff,pdc/a psd,psc/a 8 touching_illegal \ + "P-type diffusion must be 8 away from P-substrate contact (MOSIS rule #2.3a,4a)" + + + + spacing nsd,nsc/a psd,psc/a 6 touching_illegal \ + "Opposite well contacts must be separated by 6 (MOSIS rule #2.4)" +# 1260 "scmos.tech.out" + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap nwell 5 touching_illegal \ + "N-diffusion and N-well must be separated by 5 (MOSIS rule #2.3a)" + spacing pdiff,pdc/a,pfet,epfet,pffet pwell 5 touching_illegal \ + "P-diffusion and P-well must be separated by 5 (MOSIS rule #2.3a)" + + + + spacing nsd,nsc/a pwell 3 touching_illegal \ + "N-substrate diffusion and P-well must be separated by 3 (MOSIS rule #2.4)" + spacing psd,psc/a nwell 3 touching_illegal \ + "P-substrate diffusion and N-well must be separated by 3 (MOSIS rule #2.4)" + + + + + spacing ndiff,ndc/a,nfet,enfet,nffet,wcap psd,psc/a 4 touching_ok \ + "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" + spacing pdiff,pdc/a,pfet,epfet,pffet nsd,nsc/a 4 touching_ok \ + "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" + + + + + + + width poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 2 \ + "Polysilicon width must be at least 2 (MOSIS rule #3.1)" + + + + + + + spacing poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 2 touching_ok \ + "Polysilicon spacing must be at least 2 (MOSIS rule #3.2a)" + + + + edge4way nfet,pfet poly,pc/act 2 poly,pc/act 0 0 \ + "Poly must overhang transistor by at least 2 (MOSIS rule #3.3)" + + + edge4way nfet,enfet ndiff,ndc/a 3 ndiff,ndc/a,nfet,enfet,nffet,wcap ndiff,ndc/a 3 \ + "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" + edge4way pfet,epfet pdiff,pdc/a 3 pdiff,pdc/a,pfet,epfet,pffet ndiff,ndc/a 3 \ + "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" + + + edge4way nfet,pfet space 1 poly 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way enfet,epfet space 1 poly2 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way nffet,pffet space 1 poly 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + edge4way nffet,pffet space 1 poly2 0 0 \ + "Transistor overhang is missing (MOSIS rule #3.3,4)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a poly,pc 1 space/a 0 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge4way poly,pc ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a 1 space/a 0 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge poly,pc space/a 1 space/a space/a 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" + edge nsd,nsc/a,psd,psc/a,ndiff,ndc/a,pdiff,pdc/a space/a 1 space/a space/a 1 \ + "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" +# 1349 "scmos.tech.out" + spacing pfet,epfet,pffet nsd,nsc/a 3 touching_illegal \ + "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.a)" + spacing nfet,enfet,nffet psd,psc/a 3 touching_illegal \ + "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.b)" + + edge4way psd,psc/a space/act 3 ~(nfet,enfet,nffet)/act psd,psc/a,ndiff,ndc/a 3 \ + "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.c)" + + edge4way nsd,nsc/a space/act 3 ~(pfet,epfet,pffet)/act nsd,nsc/a,pdiff,pdc/a 3 \ + "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.d)" + + edge4way psd,psc/a ~(ndiff,ndc,psc,psd)/act 4 ~(nfet,enfet)/act ~(ndiff,ndc,psc,psd)/act 4 \ + "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.e)" + + edge4way nsd,nsc/a ~(pdiff,pdc,nsc,nsd)/act 4 ~(pfet,epfet)/act ~(pdiff,pdc,nsc,nsd)/act 4 \ + "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.f)" + + + + edge4way ~(pdiff,pdc/a,pfet,epfet,pffet)/act pdiff,pdc,pfet 4 ~(nsd,nsc/a)/act pdiff,pdc/a,pfet,epfet,pffet 2 \ + "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.a)" + edge4way ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/act ndiff,ndc,nfet 4 ~(psd,psc/a)/act ndiff,ndc/a,nfet,enfet,nffet,wcap 2 \ + "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.b)" +# 1383 "scmos.tech.out" + width pc 2 \ + "Poly contact width must be at least 2 (MOSIS rule #5B.1,2,3)" + + + + + + + + edge4way poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet ~(poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet)/act 3 ~pc/act ~(poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet)/act 3 \ + "Poly contact must be at least 3 from other poly (MOSIS rule #5B.4,5)" + + + + + + spacing pc ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a 1 touching_illegal \ + "Poly contact must be 1 unit from diffusion (MOSIS rule #5B.6)" +# 1409 "scmos.tech.out" + width ndc,pdc 2 \ + "Diffusion contact width must be at least 2 (MOSIS rule #6B.1,2,3)" + width nsc,psc 4 \ + "Substrate contact width must be at least 4 (MOSIS rule #6B.1,2,3)" +# 1433 "scmos.tech.out" + edge4way ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a ~(ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a)/act 4 ~(ndc,pdc,nsc,psc)/act \ + ~(ndiff,ndc/a,nfet,enfet,nffet,wcap,pdiff,pdc/a,pfet,epfet,pffet,nsd,nsc/a,psd,psc/a)/act 4 \ + "Diffusion contacts must be 4 from other diffusions (MOSIS rule #6B.4,5)" + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc nfet,enfet,nffet,pfet,epfet,pffet 1 touching_illegal \ + "Diffusion contacts cannot touch transistors (MOSIS rule #6B.6)" + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc poly 1 touching_illegal \ + "Diffusion contact to field poly must be at least 1 (MOSIS rule #6B.7)" + + + + + spacing pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc pc/act 2 touching_illegal \ + "Poly contacts must be 2 away from diffusion contacts (MOSIS rule #6B.9)" +# 1458 "scmos.tech.out" + edge4way m3c/m3 ~m3c/m3 1 ~m3c/m3 (~m3c,m3c)/m3 1 \ + "Metal3 contacts must be rectangular (Magic rules)" + edge4way m2c/m2 ~m2c/m2 1 ~m2c/m2 (~m2c,m2c)/m2 1 \ + "Metal2 contacts must be rectangular (Magic rules)" + + edge4way ndc/m1 ~ndc/m1 1 ~ndc/m1 (~ndc,ndc)/m1 1 \ + "N-diffusion contacts must be rectangular (Magic rules)" + edge4way pdc/m1 ~pdc/m1 1 ~pdc/m1 (~pdc,pdc)/m1 1 \ + "P-diffusion contacts must be rectangular (Magic rules)" + edge4way psc/m1 ~psc/m1 1 ~psc/m1 (~psc,psc)/m1 1 \ + "P-substrate contacts must be rectangular (Magic rules)" + edge4way nsc/m1 ~nsc/m1 1 ~nsc/m1 (~nsc,nsc)/m1 1 \ + "N-substrate contacts must be rectangular (Magic rules)" + + edge4way pc/m1 ~pc/m1 1 ~pc/m1 (~pc,pc)/m1 1 \ + "Polysilicon contacts must be rectangular (Magic rules)" + edge4way ec/m1 ~ec/m1 1 ~ec/m1 (~ec,ec)/m1 1 \ + "Electrode contacts must be rectangular (Magic rules)" + edge4way cc/m1 ~cc/m1 1 ~cc/m1 (~cc,cc)/m1 1 \ + "Capacitor contacts must be rectangular (Magic rules)" + + edge4way emc/m1 ~emc/m1 1 ~emc/m1 (~emc,emc)/m1 1 \ + "Emitter contacts must be rectangular (Magic rules)" + edge4way clc/m1 ~clc/m1 1 ~clc/m1 (~clc,clc)/m1 1 \ + "Collector contacts must be rectangular (Magic rules)" + edge4way pbpc/m1 ~pbpc/m1 1 ~pbpc/m1 (~pbpc,pbpc)/m1 1 \ + "P-base Contacts must be rectangular (Magic rules)" + edge4way nbdc/m1 ~nbdc/m1 1 ~nbdc/m1 (~nbdc,nbdc)/m1 1 \ + "CCD-diffusion Contacts must be rectangular (Magic rules)" + + + + + + width pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 3 \ + "First-level metal width must be at least 3 (MOSIS rule #7.1)" + + + + + spacing pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc,pad/m1 3 touching_ok \ + "First-level metal spacing must be at least 3 (MOSIS rule #7.2)" +# 1511 "scmos.tech.out" + width m2c 2 \ + "Contact width must be at least 2 (MOSIS rule #8.1,2,3)" +# 1540 "scmos.tech.out" + width m2,m2c/m2,m3c/m2,pad 3 \ + "Second-level metal width must be at least 3 (MOSIS rule #9.1)" +# 1552 "scmos.tech.out" + spacing m2,m2c/m2,m3c/m2,pad m2,m2c/m2,m3c/m2,pad 4 touching_ok \ + "Second-level metal spacing must be at least 4 (MOSIS rule #9.2a)" +# 1610 "scmos.tech.out" + width cap,capc/a 2 \ + "Electrode capacitor width must be at least 3 (MOSIS rule #11.1)" + + + spacing poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet 3 touching_ok \ + "Second-level poly spacing must be at least 3 (MOSIS rule #11.2,12.2)" + + + edge4way cap,cc space 1 0 0 0 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + edge4way cap,cc poly 2 poly poly 2 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + edge4way cap,cc poly2 2 poly2 poly2 2 \ + "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" + + + edge4way nw,pw,cw ~(nw,pw,cw)/w 2 ~(cap,cc)/a ~(nw,pw,cw)/w 2 \ + "Cap must be on a flat surface (MOSIS rule #11.4)" active + edge4way ~(nw,pw,cw)/w nw,pw,cw 2 ~(cap,cc)/a nw,pw,cw 2 \ + "Cap must be on a flat surface (MOSIS rule #11.4)" active + edge4way cap ~(cap)/a 2 nfet,enfet,nffet,pfet,epfet,pffet,poly,poly2,space/a,cc/a \ + ndiff,ndc/a,pdiff,pdc/a,poly 2 "Cap must be on a flat surface (MOSIS rule #11.4)" active +# 1641 "scmos.tech.out" + width poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet 2 \ + "Electrode width must be at least 2 (MOSIS rule #12.1)" + + + + + + edge4way enfet,epfet poly2,ec/a 2 poly2,ec/a 0 0 \ + "Poly2 must overhang transistor by at least 2 (MOSIS rule #12.3)" + edge4way nffet,pffet cap 2 cap 0 0 \ + "Cap must overhang transistor by at least 2 (MOSIS rule #12.3)" + edge4way nffet ~(cap,nffet,enfet,nfet)/a 2 cap 0 0 \ + "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" + edge4way pffet ~(cap,pffet,epfet,pfet)/a 2 cap 0 0 \ + "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a el 1 space/a 0 1 \ + "Poly2 and diffusion must be separated by at least 1 (MOSIS rule #12.4)" + + + + + spacing poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet pc,ndc,pdc 2 touching_illegal \ + "Poly2 spacing to poly or diffusion contact must be at least 3 (MOSIS rule #12.6)" +# 1682 "scmos.tech.out" + width ec,capc 4 \ + "Electrode contact width must be at least 4 (MOSIS rule #13.1)" + + + + + + edge4way ec/a space 1 poly2 poly2 1 \ + "Electrode contact must be overlaped by poly2 (MOSIS rule #13.4)" + edge4way ec/a poly2 1 poly2 poly2 1 \ + "Electrode contact must be overlaped by poly2 by 1 (MOSIS rule #13.4)" + + + edge4way ndiff,ndc/a,pdiff,pdc/a,nsd,nsc/a,psd,psc/a ec 2 space/a 0 2 \ + "Poly2 and diffusion contact must be separated by at least 2 (MOSIS rule #13.5)" + + + + + + + + width m3c 4 \ + "Third-level metal contact width must be at least 4 (MOSIS rule #14.1,2,3)" +# 1717 "scmos.tech.out" + width m3,m3c/m3 4 \ + "Third-level metal width must be at least 4" +# 1734 "scmos.tech.out" + spacing m3,m3c/m3 m3,m3c/m3 4 touching_ok \ + "Third-level metal spacing must be at least 4 from other third-level metal (MOSIS rule #15.2a)" + + + + edge4way m3c/m3 ~m3c/m3 1 m3 m3 1 \ + "Mimimum metal3 overlap of via must be at least 1 (MOSIS rule #15.3)" +# 1749 "scmos.tech.out" + width clc,pbc,emc 4 \ + "Transistor contact width must be at least 4 (MOSIS rule #16.1)" +# 1760 "scmos.tech.out" +# edge4way emc/a,emit pbase 4 pbase pbase 4 \ +# "Pbase overlap of emitter must be at least 4 (MOSIS rule #16.3)" + + + + spacing pbc emc/a,emit 7 touching_illegal \ + "Base must be 7 (4+2+1) away from emitter (MOSIS rule #16.3,4,11)" + + + + + + # edge4way pbc (~pbc)/a 3 pb,pbc/a pb,pbc/a 3 \ +# "Pbase overlap of base contact must be at least 3 (MOSIS rule #16.5)" +# 1782 "scmos.tech.out" + width col,clc/a 6 \ + "Collector width must be at least 6 (MOSIS rule #16.6)" + + + +# edge4way pbase space/a 6 nwell space/a 6 \ +# "Nwell overlap of Pbase must be at least 6 (MOSIS rule #16.7)" well + + +# edge4way pbase (~pbase)/a 4 ~(col,clc)/a ~(col,clc)/a 4 \ +# "Pbase must be at least 4 away from collector (MOSIS rule #16.8)" + + + edge4way clc (~clc)/a 1 col col 1 \ + "Collector overlap of contact must be at least 1 (MOSIS rule #16.9)" + + + + + + + edge4way nw ~(nw)/w 3 ~(col,clc)/a ~(nw)/w 3 \ + "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active + edge4way ~(nw)/w nw 3 ~(col,clc)/a nw 3 \ + "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active + + + width em,emc/a 4 \ + "Emitter width must be at least 4 (Magic Bipolar Transistor rule)" + + + + spacing em,emc/a em,emc/a 7 touching_ok \ + "Unrelated emitter must be at least 7 apart (Magic Bipolar transistor rule)" + + + + + +# width pbase,pbc/a 2 \ +# "Pbase width must be at least 2 (MOSIS extension rule)" + +# spacing pbase,pbc/a pbase,pbc/a 2 surround_ok \ +# "Pbase spacing must be at least 2 (MOSIS extension rule)" +# 1835 "scmos.tech.out" + width cwell 10 \ + "Cap-well width must be at least 10 (MOSIS rule #17.1)" + + + spacing cwell cwell 9 touching_ok \ + "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" + spacing cwell nwell 9 touching_illegal \ + "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" + + + edge4way cwell space 5 ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/a ~(ndiff,ndc/a,nfet,enfet,nffet,wcap)/w 5 \ + "Cap-well spacing to external active must be at least 5 (MOSIS rule #17.3)" active + edge4way cwell space 3 ~(psd,psc/a)/a ~(psd,psc/a)/w 3 \ + "P-substrate diffusion and Cap-well must be separated by 3 (MOSIS rule #17.3)" active + + + + + + edge4way space cwell 3 (space,poly,pc)/a 0 0 \ + "Cap-well overlap of diffusion must be at least 3 (MOSIS rule #17.4)" active +# 1865 "scmos.tech.out" + width wcap 3 \ + "Well-capacitor must be at least 3 (MOSIS rule #18.1)" + + + + + + edge4way wcap space 1 poly poly 1 \ + "Well-capacitor overhang is missing (MOSIS rule #18.3)" + + + edge4way wcap ndiff 3 ndiff ndiff 3 \ + "N-diffusion overlap of well-capacitor must be at least 3 (MOSIS rule #18.4)" + + + + spacing wcap pc 2 touching_illegal \ + "Well-capacitor spacing to poly contact must be at least 2 (MOSIS rule #18.5)" + + + + + spacing wcap ndc 4 touching_illegal \ + "Well-capacitor spacing to diffusion contact must be at least 4 (MOSIS rule #18.6)" + + + + + + + + width nbd,nbdc,bd/a 4 \ + "CCD channel width must be at least 4 (MOSIS rule #19.1)" + width nbdc 4 \ + "CCD contact width must be at least 4 (MOSIS rule #19.1)" +# 1910 "scmos.tech.out" + edge4way nbd,nbdc ~(bd,nbd,nbdc)/a 4 (bd,space)/i 0 0 \ + "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" implant + edge4way nbd,nbdc ~(poly,nbd,nbdc)/a 4 ~(poly,nbd,nbdc)/a ~(poly,nbd,nbdc)/a 4 \ + "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" active + + + + + + + edge4way bd space 2 nbd,poly,cap,el 0 0 \ + "CCD channel overhang is missing (MOSIS rule #19.6)" active + + + + + spacing nbdc poly,el 1 touching_illegal \ + "CCD-diffusion contact spacing to poly must be at least 1 (MOSIS CCD rule)" + edge4way nbd poly,el 1 bd 0 0 \ + "Missing Buried CCD Difussion layer (MOSIS CCD rule)" implant +# 1942 "scmos.tech.out" + edge (~hnwell)/w hnwell 10 hnwell hnwell 10\ + "High-Voltage N-Well width must be at least 10 (MOSIS rule #1.1)" + edge (~hpwell)/w hpwell 10 hpwell hpwell 10\ + "High-Voltage P-Well width must be at least 10 (MOSIS rule #1.1)" + + edge hnwell space,pw,hpw 9 space,pw,hpw space,pw,hpw 9\ + "High-Voltage N-Well spacing to N-Well must be at least 9 (MOSIS rule #1.2)" + edge hpwell space,nw,hnw 9 space,nw,hnw space,nw,hnw 9\ + "High-Voltage P-Well spacing to P-Well must be at least 9 (MOSIS rule #1.2)" + edge hnwell space,pw,hpw,nw 12 space,pw,hpw,nw space,pw,hpw,nw 12\ + "High-Voltage N-Well spacing must be at least 12 (MOSIS rule #20.1)" + edge hpwell space,nw,hnw,pw 12 space,nw,hnw,pw space,nw,hnw,pw 12\ + "High-Voltage P-Well spacing must be at least 12 (MOSIS rule #20.1)" + + + + + + + edge4way ~(hndiff,hndc/a,hpdiff,hpdc/a)/a hndiff,hndc/a,hpdiff,hpdc/a 3 hndiff,hndc/a,hpdiff,hpdc/a hndiff,hndc/a,hpdiff,hpdc/a 3\ + "High-Voltage Diffusion width must be at least 3 (MOSIS rule #2.1)" + spacing hndiff,hndc/a,hnfet hndiff,hndc/a,hnfet 5 touching_ok \ + "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" + spacing hpdiff,hpdc/a,hpfet hpdiff,hpdc/a,hpfet 5 touching_ok \ + "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" + + + + + + spacing hndiff,hndc/a hpdiff,hpdc/a 14 touching_illegal \ + "P-type diffusion must be 14 away from N-type diffusion (MOSIS rule #20.3)" + spacing hndiff,hndc/a pdiff,pdc/a 12 touching_illegal \ + "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" + spacing hpdiff,hpdc/a ndiff,ndc/a 12 touching_illegal \ + "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" + + + spacing hndiff,hnfet,hndc/a hnwell 7 touching_illegal \ + "HVN-diffusion and HVN-well must be separated by 7 (MOSIS rule #20.3)" + spacing hpdiff,hpfet,hpdc/a hpwell 7 touching_illegal \ + "HVP-diffusion and HVP-well must be separated by 7 (MOSIS rule #20.3)" + spacing nsd,nsc/a hpwell 3 touching_illegal \ + "N-substrate diffusion and HVP-well must be separated by 3 (MOSIS rule #2.4+20.3)" + spacing psd,psc/a hnwell 3 touching_illegal \ + "P-substrate diffusion and HVN-well must be separated by 3 (MOSIS rule #2.4+20.3)" +# 1996 "scmos.tech.out" + edge (~hndc)/a hndc/a 6 hndc/a hndc/a 6\ + "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" + edge (~hpdc)/a hpdc/a 6 hpdc/a hpdc/a 6\ + "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" + + + + edge hpdiff,hpdc/a hpfet 4 hpfet 0 0 \ + "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" + edge hndiff,hndc/a hnfet 4 hnfet 0 0 \ + "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" + + + + + + exact_overlap m3c,m2c,ndc,pdc,pc,psc,nsc,ec,capc,clc,emc,pbc,hndc,hpdc,hnsc,hpsc + no_overlap pfet,nfet pfet,nfet + no_overlap epfet,enfet epfet,enfet + no_overlap pffet,nffet pffet,nffet + no_overlap hpfet,hnfet hpfet,hnfet + +end + + +extract + + + + + +# 1 "./extract_template/scmosExt.tech.in" 1 +# 98 "./extract_template/scmosExt.tech.in" +# 1 "./extract_template/LibreSiliconExt1um.tech.in" 1 + + + + + + style lambda=lambda_v(libresilicon) + + + + + step 100 + sidehalo 6 + + + + + + + areacap nwell 35 + perimc nwell ~(nwell) 47 + + + areacap ndiff,nsd,ndc/a,nsc/a 0 + areacap pdiff,psd,pdc/a,psc/a 0 + + perimc ndiff,nsd,ndc/a,nsc/a space,pwell 0 + perimc pdiff,psd,pdc/a,psc/a space,nwell 0 +# 39 "./extract_template/LibreSiliconExt1um.tech.in" + areacap (poly,pc)/a 28 + overlap (poly,pc)/a nwell,pwell 28 + + perimc (poly,pc)/a ~(poly,pc)/a 38 + sideoverlap (poly,pc)/a ~(poly,pc)/a nwell,pwell 38 + sideoverlap (poly,pc)/a ~(poly,pc)/a (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 34 + sideoverlap (poly,pc)/a ~(poly,pc)/a (m2,m2c,m3c,pad)/m2 27 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + + sidewall (poly,pc)/a ~(poly,pc)/a ~(poly,pc)/a (poly,pc)/a 15 + + + + areacap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 18 + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 nwell,pwell 18 (poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 46 + overlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (poly,pc)/a 46 + + perimc (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 nwell,pwell 33 ((poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a) + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (poly,pc)/a 33 + sideoverlap (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (m2,m2c,m3c,pad)/m2 28 + + sidewall (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 ~(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 27 + + + + + areacap (m2,m2c,m3c,pad)/m2 9 + overlap (m2,m2c,m3c,pad)/m2 nwell,pwell 9 (poly,pc)/a,(m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a + overlap (m2,m2c,m3c,pad)/m2 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 12 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + overlap (m2,m2c,m3c,pad)/m2 (poly,pc)/a 14 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + overlap (m2,m2c,m3c,pad)/m2 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 30 + + perimc (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 22 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 nwell,pwell 22 ((m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1,(poly,pc)/a,(ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a) + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (ndiff,pdiff,em,col,ppd,nnd,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc)/a 20 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (poly,pc)/a 22 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 + sideoverlap (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (m1,ndc,pdc,nwc,pwc,nbdc,capc,ec,clc,emc,pbc,pc,via)/m1 28 + + sidewall (m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 ~(m2,m2c,m3c,pad)/m2 (m2,m2c,m3c,pad)/m2 33 + + + + + + fet pfet pdiff,pdc 2 pfet Vdd! nwell 270 623 + fet nfet ndiff,ndc 2 nfet Gnd! pwell 90 623 + fet wcap ndiff,ndc 1 wcap Gnd! pwell 300 0 + + + fetresis nfet linear 9700 + fetresis pfet linear 35700 + + + + contact pc 4 16210 + contact ndc,nsc, 4 77000 + contact pdc,psc, 4 44260 + contact m2c 4 150 + + + resist ndiff,nsd,ndc/a,nsc/a 99630 + resist pdiff,psd,pdc/a,psc/a 120000 + resist (poly,pc/act,pfet,nfet) 25000 + resist (metal1,m2c/metal1) 60 + resist (metal2,via/m2,pad) 40 + resist nwell 1500000 + + + + planeorder implant 0 + planeorder well 1 + planeorder active 2 + planeorder metal1 3 + planeorder metal2 4 + planeorder metal3 5 + planeorder metal4 6 + planeorder oxide 7 + +# 99 "./extract_template/scmosExt.tech.in" 2 + + +# 1 "./extract_template/scmosExtDiag.tech.in" 1 + + + + + + + style check_nwell + + lambda 100 + step 100 + + resist nwell 2000000 + areacap nw,nwc,nsd 100 + + + noplaneordering + + style check_pwell + + lambda 100 + step 100 + + resist pwell 2000000 + areacap pw,pwc,psd 100 + + noplaneordering + + style check_psubstr + + + + + + lambda 50 + step 200 + + areacap psd,psc 1000 + + noplaneordering + + style check_nsubstr + + + + + + lambda 50 + step 200 + + areacap nsd,nsc 1000 + + noplaneordering +# 101 "./extract_template/scmosExt.tech.in" 2 +# 2028 "scmos.tech.out" 2 +# 2833 "scmos.tech.out" +end + + +wiring + contact pdcontact 4 pdiff 0 metal1 0 + contact ndcontact 4 ndiff 0 metal1 0 + contact pcontact 4 poly 0 metal1 0 + contact ec 6 poly2 0 metal1 0 + contact m2contact 4 metal1 0 metal2 0 + contact m3contact 5 metal2 0 metal3 0 +end + +router + layer1 metal1 3 pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc 3 + layer2 metal2 3 m2,m2c/m2,m3c/m2,pad 4 poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet,ndiff,ndc/a,pdiff,pdc/a 1 + contacts m2contact 4 + gridspacing 8 +end + +plowing + fixed nfet,enfet,nffet,pfet,epfet,pffet,glass,pad + covered nfet,enfet,nffet,pfet,epfet,pffet + drag nfet,enfet,nffet,pfet,epfet,pffet +end + +plot + + style colorversatec + + ndiff,ndc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + ndiff,ndc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + + nsd,nsc,col,clc yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + + nsd,nsc,col,clc cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + + + pdiff,pdc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + pdiff,pdc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + pdiff,pdc magenta \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + + + psd,psc yellow \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 \ + 1515 2A2A 5151 A2A2 + + psd,psc cyan \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 \ + 0000 1515 0000 5151 + + psd,psc magenta \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 \ + 2A2A 0000 A2A2 0000 + + + poly,pc/a magenta \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + + poly2,ec/a yellow \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF \ + FFFF FFFF FFFF FFFF + + + nfet yellow \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 + + nfet cyan \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 \ + 0000 0505 0000 1414 \ + 0000 5050 0000 4141 + + nfet magenta \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A \ + 5050 2828 4141 A0A0 \ + 0505 8282 1414 0A0A + + + enfet yellow \ + BABA 7575 EAEA D5D5 \ + ABAB 5757 AEAE 5D5D \ + BABA 7575 EAEA D5D5 \ + ABAB 5757 AEAE 5D5D + + enfet cyan \ + 4141 0A0A 0505 2828 \ + 1414 A0A0 5050 8282 \ + 4141 0A0A 0505 2828 \ + 1414 A0A0 5050 8282 + + + nffet yellow \ + 8E8E 0707 8B8B D5D5 \ + E8E8 7070 B8B8 5D5D \ + 8E8E 0707 8B8B D5D5 \ + E8E8 7070 B8B8 5D5D + + nffet cyan \ + 0101 0808 1414 2828 \ + 1010 8080 4141 8282 \ + 0101 0808 1414 2828 \ + 1010 8080 4141 8282 + + nffet magenta \ + 5050 A0A0 4040 0202 \ + 0505 0A0A 0404 2020 \ + 5050 A0A0 4040 0202 \ + 0505 0A0A 0404 2020 + + + pfet yellow \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 \ + 6363 A0A0 5050 2828 \ + 3636 0A0A 0505 8282 + + pfet cyan \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 \ + 0000 5151 0000 5454 \ + 0000 1515 0000 1515 + + pfet magenta \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 \ + 9494 0A0A 2525 8282 \ + 4949 A0A0 5252 2828 + + + epfet yellow \ + BCBC 4F4F 2F2F D3D3 \ + CBCB F4F4 F2F2 3D3D \ + BCBC 4F4F 2F2F D3D3 \ + CBCB F4F4 F2F2 3D3D + + epfet cyan \ + 0000 A0A0 0000 2828 \ + 0000 0A0A 0000 8282 \ + 0000 A0A0 0000 2828 \ + 0000 0A0A 0000 8282 + + epfet magenta \ + 4141 0000 5050 0000 \ + 1414 0000 0505 0000 \ + 4141 0000 5050 0000 \ + 1414 0000 0505 0000 + + + pffet yellow \ + 7B7B F0F0 F0F0 E9E9 \ + B7B7 0F0F 0F0F 9E9E \ + 7B7B F0F0 F0F0 E9E9 \ + B7B7 0F0F 0F0F 9E9E + + pffet cyan \ + 0000 0101 0000 1414 \ + 0000 1010 0000 4141 \ + 0000 0101 0000 1414 \ + 0000 1010 0000 4141 + + pffet magenta \ + 8484 0A0A 2525 8282 \ + 4848 A0A0 5252 2828 \ + 8484 0A0A 2525 8282 \ + 4848 A0A0 5252 2828 + + + cap,cc/a yellow \ + 3E3E 7777 E3E3 C1C1 \ + E3E3 7777 3E3E 1C1C \ + 3E3E 7777 E3E3 C1C1 \ + E3E3 7777 3E3E 1C1C + + cap,cc/a magenta \ + 4141 8888 1414 2A2A \ + 1414 8888 4141 A2A2 \ + 4141 8888 1414 2A2A \ + 1414 8888 4141 A2A2 + + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc cyan \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 \ + AAAA 0000 AAAA 0000 + + + m2,m2c/m2,m3c/m2,pad cyan \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 \ + 0000 1111 0000 4444 + + m2,m2c/m2,m3c/m2,pad magenta \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 \ + 0000 4444 0000 1111 + + + m2c/m1 black \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 \ + 0000 6666 6666 0000 \ + 0000 9999 9999 0000 + + + pad,glass black \ + 0300 0700 0E00 1C00 \ + 3800 7000 E000 C000 \ + 00C0 00E0 0070 0038 \ + 001C 000E 0007 0003 + + + nwell yellow \ + 0800 1000 2000 4000 \ + 8000 0001 0002 0004 \ + 0008 0010 0020 0040 \ + 0080 0010 0200 0400 + + nwell cyan \ + 1000 2000 4000 8000 \ + 0001 0002 0004 0008 \ + 0010 0020 0040 0080 \ + 0100 0200 0400 0800 + + + pwell yellow \ + 1000 0400 0400 0100 \ + 0100 0040 0040 0010 \ + 0010 0004 0004 0001 \ + 0001 4000 4000 1000 + + pwell cyan \ + 0000 0800 0000 0200 \ + 0000 0080 0000 0020 \ + 0000 0008 0000 0002 \ + 0000 8000 0000 2000 + + pwell magenta \ + 0800 0000 0200 0000 \ + 0080 0000 0020 0000 \ + 0008 0000 0002 0000 \ + 8000 0000 2000 0000 + + + bd yellow \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 + + bd cyan \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 + + bd magenta \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 + + + nbd,nbdc yellow \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA \ + 5555 AAAA 5555 AAAA + + nbd,nbdc cyan \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 \ + 0000 5555 0000 5555 + + nbd,nbdc magenta \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 \ + 8888 0000 8888 0000 + + + em,emc yellow \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 \ + 4444 8888 4444 8888 + + em,emc cyan \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 \ + 0000 4444 0000 4444 + + + pbase,pbc yellow \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 \ + 5555 AAAA 0000 0000 + + pbase,pbc cyan \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 \ + 0000 5555 0000 0000 + + pbase,pbc magenta \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 \ + AAAA 0000 0000 0000 + + + m3,m3c/m3 black \ + 0100 0000 0000 0000 \ + 1010 0000 0000 0000 \ + 0001 0000 0000 0000 \ + 1010 0000 0000 0000 + + m3,m3c/m3 cyan \ + 0280 0000 0820 0000 \ + 2008 0000 8002 0000 \ + 8002 0000 2008 0000 \ + 0820 0000 0280 0000 + + m3,m3c/m3 magenta \ + 0100 06C0 0440 1830 \ + 1010 600C 4004 8003 \ + 0001 C006 4004 3018 \ + 1010 0C60 0440 0380 + + + m3c/m2 black \ + 0820 0820 0820 0FE0 \ + E00F 2008 2008 2008 \ + 2008 2008 2008 E00F \ + 0000 0FE0 0820 0820 + + + error_p,error_s,error_ps black \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 \ + 0000 3C3C 4646 4A4A \ + 5252 6262 3C3C 0000 + + + magnet yellow \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 \ + AAAA 0000 5555 0000 + + + fence magenta \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 \ + FFFF 0000 0000 0000 \ + 0000 0000 0000 0000 + + + rotate cyan \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 \ + 0000 E0E0 E0E0 E0E0 \ + 0000 0000 0000 0000 + + + pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,nbdc,clc,emc,pbc X + + + style versatec + + pfet \ + 07c0 0f80 1f00 3e00 \ + 7c00 f800 f001 e003 \ + c007 800f 001f 003e \ + 00c7 00f8 01f0 03e0 + + + nfet \ + 1f00 0f80 07c0 03e0 \ + 01f0 00f8 007c 003e \ + 001f 800f c007 e003 \ + f001 f800 7c00 3e00 + + + m2c \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 \ + c3c3 c3c3 0000 0000 \ + 0000 0000 c3c3 c3c3 + + + pwell \ + 2020 2020 2020 2020 \ + 2020 2020 2020 2020 \ + 0000 0000 0000 0000 \ + 0000 0000 0000 0000 + + + nwell \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 \ + 0808 0404 0202 0101 \ + 0000 0000 0000 0000 + + + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet \ + 0808 0400 0202 0101 \ + 8080 4000 2020 1010 \ + 0808 0004 0202 0101 \ + 8080 0040 2020 1010 + + + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 \ + 8080 0000 0000 0000 \ + 0808 0000 0000 0000 + + + pad,glass \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 \ + 0000 0000 1c1c 3e3e \ + 3636 3e3e 1c1c 0000 + + + nsd,nsc,col,clc \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 \ + 0808 1414 2222 4141 \ + 8080 4040 2020 1010 + + + m2,m2c/m2,m3c/m2,pad \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 \ + 0000 1111 0000 0000 + + + pdiff,pdc,pfet \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 \ + 0000 0808 5555 8080 \ + 0000 8080 5555 0808 + + + psd,psc \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 \ + 1414 2222 0000 2222 \ + 4141 2222 0000 2222 + + + ndiff,nfet,ndc \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 \ + 0808 1010 2020 4040 \ + 8080 4141 2222 1414 + + + poly2,ec/a,enfet,epfet,cap,capc/a,nffet,pffet,hnfet,hpfet \ + 0000 2020 5050 2020 \ + 0000 0202 0505 0202 \ + 0000 2020 5050 2020 \ + 0000 0202 0505 0202 + + + pdc,ndc,psc,nsc,pbnc,pbpc,nbnc,nbpc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,nbdc,clc,emc,pbc X + + + style gremlin + pfet 9 + nfet 10 + m2c 11 + pwell 15 + nwell 16 + poly,pc/a,nfet,pfet,wcap,snfet,spfet,pbpoly,nbpoly,cap,capc/a,nffet,pffet 19 + pdc/m1,ndc/m1,psc/m1,nsc/m1,hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1,pc/m1,ec/m1,capc/m1,clc/m1,emc/m1,nbdc/m1,m1,m2c/m1,gc 22 + pad,glass 23 + nsd,nsc 24 + m2,m2c/m2,m3c/m2,pad 28 + pdiff,pdc,pfet 29 + psd,psc 30 + ndiff,nfet,ndc 31 + m2c/m1,pc/m1,ndc/m1,pdc/m1,psc/m1,nsc/m1,pad/m1 X + + style postscript + + + + + 1 C0C0C0C0 C0C0C0C0 00000000 00000000 0C0C0C0C 0C0C0C0C 00000000 00000000 + 2 A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A + 3 00030003 000C000C 00300030 00C000C0 03000300 0C000C00 30003000 C000C000 + 4 00000000 00000000 C0C0C0C0 00000000 00000000 00000000 0C0C0C0C 00000000 + 5 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF + 6 07070707 0E0E0E0E 1C1C1C1C 38383838 70707070 E0E0E0E0 C1C1C1C1 83838383 + 7 18181818 30303030 60606060 C0C0C0C0 81818181 03030303 06060606 0C0C0C0C + 8 18181818 0C0C0C0C 06060606 03030303 81818181 C0C0C0C0 60606060 30303030 + 9 18181818 3C3C3C3C 3C3C3C3C 18181818 81818181 C3C3C3C3 C3C3C3C3 81818181 + 10 F0F0F0F0 60606060 06060606 0F0F0F0F 0F0F0F0F 06060606 60606060 F0F0F0F0 + 11 01000080 02000040 0C000030 F000000F 000FF000 00300C00 00400200 00800100 + 12 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 + 13 00000000 00000000 33333333 33333333 00000000 00000000 CCCCCCCC CCCCCCCC + + + + + 1 47 95 111 0 + 2 223 31 223 0 + 3 0 0 0 192 + 4 31 111 31 0 + 5 31 111 255 0 + 6 63 95 191 0 + 7 255 63 255 0 + 8 0 0 0 127 + 9 223 47 223 0 + 10 0 255 255 0 + 11 0 0 255 0 + 12 191 127 0 0 + 13 95 223 63 0 + 14 0 0 0 255 + 15 191 127 63 0 + 16 111 151 244 0 + 17 23 175 183 0 + + + + + cc,pc,ndc,pdc,psc,nsc 14 X + m2c,pad,glass 14 B + pad,glass 14 11 + m2c 14 13 + m2,m2c,pad 13 10 + pdc,ndc,psc,nsc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,clc,emc,pbnd,pbpd,pbc,nbdc,m1,m2c,gc 12 9 + cap,cc,poly2 11 7 + nsd,nsc 7 1 + psd,psc 6 1 + nfet,nffet 9 8 + pfet,wcap,pffet 1 7 + poly,pc,cap,cc 10 5 + nfet 16 5 + pfet,wcap 17 5 + pdiff,pdc,pffet 1 5 + ndiff,ndc,nffet 9 5 + pwell 1 4 + nwell 2 4 + + silk 10 5 + + + + + style pnm + draw metal1 + draw metal2 + + draw metal3 + draw pwell + draw nwell + draw silk + map silk metal2 + + draw polysilicon + draw ndiffusion + draw pdiffusion + draw ntransistor + draw ptransistor + map psubstratepdiff pdiffusion + map nsubstratendiff ndiffusion + map polycontact polysilicon metal1 + map m2contact metal1 metal2 + map m3contact metal2 metal3 + map ndcontact ndiffusion metal1 + map pdcontact pdiffusion metal1 + map nsubstratencontact ndiffusion metal1 + map psubstratepcontact pdiffusion metal1 +end diff --git a/Tech.LS1UM/nmos.sp b/Tech.LS1UM/nmos.sp new file mode 100644 index 00000000..9e0758e0 --- /dev/null +++ b/Tech.LS1UM/nmos.sp @@ -0,0 +1 @@ +w=1.0u l=1.0u diff --git a/Tech.LS1UM/pmos.sp b/Tech.LS1UM/pmos.sp new file mode 100644 index 00000000..0c7b022b --- /dev/null +++ b/Tech.LS1UM/pmos.sp @@ -0,0 +1 @@ +w=2.7u l=1.0u diff --git a/Tech.LS1UM/template.lef b/Tech.LS1UM/template.lef new file mode 100755 index 00000000..d0c6b4fc --- /dev/null +++ b/Tech.LS1UM/template.lef @@ -0,0 +1,177 @@ +# LEF file generated by lefgen from LibreSilicon version 0.1 +# + +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +USEMINSPACING OBS ON ; +USEMINSPACING PIN OFF ; +CLEARANCEMEASURE EUCLIDEAN ; + + +MANUFACTURINGGRID 0.15 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER nactive + TYPE MASTERSLICE ; +END nactive + +LAYER pactive + TYPE MASTERSLICE ; +END pactive + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER cc + TYPE CUT ; + SPACING 0.9 ; +END cc + +LAYER metal1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 3.2e-05 ; +END metal1 + +LAYER via + TYPE CUT ; + SPACING 0.9 ; +END via + +LAYER metal2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 2.4 ; + OFFSET 1.2 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 1.6e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.9 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 1.5 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.05 ; + CAPACITANCE CPERSQDIST 1e-05 ; +END metal3 + +SPACING + SAMENET cc via 0.150 ; + SAMENET via via2 0.150 ; +END SPACING + +VIA M2_M1 DEFAULT + LAYER metal1 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; +END M2_M1 + +VIA M3_M2 DEFAULT + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via2 ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal3 ; + RECT -0.900 -0.900 0.900 0.900 ; +END M3_M2 + + +VIARULE viagen21 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER via ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 1.5 BY 1.5 ; +END viagen21 + +VIARULE viagen32 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + WIDTH 1.8 TO 180 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER via2 ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 2.1 BY 2.1 ; +END viagen32 + +VIARULE TURN1 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + LAYER metal1 ; + DIRECTION VERTICAL ; +END TURN1 + +VIARULE TURN2 GENERATE + LAYER metal2 ; + DIRECTION HORIZONTAL ; + LAYER metal2 ; + DIRECTION VERTICAL ; +END TURN2 + +VIARULE TURN3 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + LAYER metal3 ; + DIRECTION VERTICAL ; +END TURN3 + +SITE corner + CLASS PAD ; + SYMMETRY R90 Y ; + SIZE 300.000 BY 300.000 ; +END corner + +SITE IO + CLASS PAD ; + SYMMETRY Y ; + SIZE 90.000 BY 300.000 ; +END IO + +SITE core + CLASS CORE ; + SYMMETRY Y ; + SIZE 2.400 BY 30.000 ; +END core + diff --git a/Tech.SKY130/.gitignore b/Tech.SKY130/.gitignore new file mode 100644 index 00000000..c18dd8d8 --- /dev/null +++ b/Tech.SKY130/.gitignore @@ -0,0 +1 @@ +__pycache__/ diff --git a/Tech.SKY130/caravel-env.sh b/Tech.SKY130/caravel-env.sh new file mode 100644 index 00000000..2cfa5267 --- /dev/null +++ b/Tech.SKY130/caravel-env.sh @@ -0,0 +1,10 @@ +export STDCELLLIB="../" +#e#xport OPENLANE_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1/dependencies/openlane_src" +#e#xport CARAVEL="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1" +#e#xport CARAVEL_ROOT="/home/philipp/libresilicon/StdCellLib/Catalog/sky130_stdcelllib_1/caravel" +export PDK_ROOT=/home/philipp/.volare +export PDK="sky130A" +export STD_CELL_LIBRARY="sky130_fd_sc_lp" +export STD_CELL_LIBRARY_OPT="sky130_fd_sc_lp" +export CARAVEL_BRANCH="skympw-8d" +export KLAYOUT_HOME=/home/philipp/.volare/sky130A/libs.tech/klayout diff --git a/Tech.SKY130/librecell_tech.py b/Tech.SKY130/librecell_tech.py new file mode 100644 index 00000000..8170a651 --- /dev/null +++ b/Tech.SKY130/librecell_tech.py @@ -0,0 +1,432 @@ +from lclayout.layout.layers import * +from lclayout.writer.magic_writer import MagWriter +from lclayout.writer.lef_writer import LefWriter +from lclayout.writer.gds_writer import GdsWriter +from lclayout.writer.oasis_writer import OasisWriter + +# Physical size of one data base unit in meters. +# BUT GDS2 requires the database units to be in nanometers, and lclayout cannot convert to nanometers automatically yet +db_unit = 1e-9 + +# Lambda - how many db_units is 1 lambda? +l = 55 # unused +grid = 5 # grid basis +um = 1000 +nm = 1 + +# Scale transistor width. +transistor_channel_width_sizing = 1 + +# GDS2 layer numbers for final output. +my_diffusion = (65, 20) # = ndiffusion+pdiffusion +my_diffusion_label = (65, 6) +my_diffusion_pin = (65, 16) +#my_pdiffusion = (1, 7) -> my_diffusion + +my_nwell = (64, 20) +my_nwell_label = (64, 5) +my_nwell_pin = (64, 16) # (64, 0) !!! both GDS definitions were found in the Skywater documentation, please check which are correct. + +my_pwell = (64, 13) # This layer is only used for resistors, which we dont need here + +my_poly = (66, 20) # poly silicium for gates -> poly + ntransistor + ptransistor +my_poly_gate = (66, 9) # poly gates? Why do we have a second layer for gates? +my_poly_label = (66, 5) + +my_licon1 = (66, 44) # licon1 is used to contact both polysilicon and diffusion in SKY130. +my_li1 = (67, 20) # "Local Interconnect" (like the first metal layer) +my_li1_label = (67, 5) +my_li1_pin = (67, 16) + +my_mcon = (67, 44) # connecting li1 to metal1 +my_metal1 = (68, 20) +my_metal1_label = (68, 5) +my_metal1_pin = (68, 16) +my_via1 = (68, 44) +my_metal2 = (69, 20) +my_metal2_label = (69, 5) +my_metal2_pin = (69, 16) +my_abutment_box = (235, 4) # prBndry ??? +#my_outline = (235, 5) # + +my_pplus = (65,44) # TAP.DRAWING +my_nplus = (65,44) # TAP.DRAWING + +# lclayout internally uses its own layer numbering scheme. +# For the final output the layers can be remapped with a mapping +# defined in this dictioinary. +output_map = { + l_ndiffusion: my_diffusion, + l_pdiffusion: my_diffusion, + l_nwell: my_nwell, # [my_nwell, my_nwell2], # Map l_nwell to two output layers. + l_pwell: my_pwell, # Output layer for pwell. Uncomment this if needed. For instance for twin-well processes. + l_poly: my_poly, + l_poly_contact: my_licon1, + l_pdiff_contact: my_licon1, + l_ndiff_contact: my_licon1, + l_metal1: my_li1, # Metal1 from lclayout gets li1 from SKY130 + l_metal1_label: my_li1_label, + l_metal1_pin: my_li1_pin, + l_via1: my_mcon, + l_metal2: my_metal1, # Metal2 from lclayout gets met1 from SKY130 + l_metal2_label: my_metal1_label, + l_metal2_pin: my_metal1_pin, + l_abutment_box: my_abutment_box, + #l_outline: my_outline, + l_pplus: my_pplus, + l_nplus: my_nplus, + l_border_vertical: (142, 1), + l_border_horizontal: (142, 2), +} + +# These are only the obstruction layers, only these layers will be generated into the OBS section of the LEF files +obstruction_layers = [ + l_poly_contact, + l_pdiff_contact, + l_ndiff_contact, + l_metal1, # Metal1 from lclayout gets li1 from SKY130 + l_via1, + l_metal2, # Metal2 from lclayout gets met1 from SKY130 +] + +output_map_magic = { + l_nwell: 'nwell', + l_pwell: 'pwell', + l_via1: 'viali', + l_poly: 'poly', + l_abutment_box: ['abutment'], + l_metal1: 'li1', + l_metal2: 'met1', + l_metal1_label: 'li1', + l_metal2_label: 'met1', + l_metal1_pin: 'li1', + l_metal2_pin: 'met1', + l_ndiffusion: 'ndiffusion', + l_pdiffusion: 'pdiffusion', + l_poly_contact: 'polycont', + l_pdiff_contact: 'pdiffc', + l_ndiff_contact: 'ndiffc', + l_nplus: 'allnactivetap', + l_pplus: 'allpactivetap' +} + + +# Define a list of output writers. +output_writers = [ + MagWriter( + tech_name='sky130A', + scale_factor=0.2, # Scale all coordinates by this factor (rounded down to next integer). + output_map=output_map_magic + ), + + LefWriter( + db_unit=1e-6, # LEF Fileformat always needs Microns + obstruction_layers=obstruction_layers, + output_map=output_map_magic, # Not supported yet but will be soon + use_rectangles_only=True, + site="unit" + ), + + GdsWriter( + db_unit=db_unit, + output_map=output_map + ), + + OasisWriter( + db_unit=db_unit, + output_map=output_map + ) + +] + +# Define how layers can be used for routing. +# Example for a layer that can be used for horizontal and vertical tracks: {'MyLayer1' : 'hv'} +# Example for a layer that can be contacted but not used for routing: {'MyLayer2' : ''} +routing_layers = { + l_ndiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_pdiffusion: '', # Allow adding shapes on diffusion layer but without using it for routing. This is used to automatically add the necessary enclosure around contacts. + l_poly: '', + l_metal1: 'hv', + l_metal2: 'hv', +} + +# Minimum spacing rules for layer pairs. +min_spacing = { + (l_ndiffusion, l_ndiffusion): 270*nm, # (difftap.3) + #(l_ndiffusion, l_outline): 270/2*nm, # (difftap.3) + (l_pdiffusion, l_ndiffusion): 270*nm, # (difftap.3) + #(l_pdiffusion, l_outline): 270/2*nm, # (difftap.3) + (l_pdiffusion, l_pdiffusion): 270*nm, # (difftap.3) + (l_ndiffusion, l_poly_contact): 190*nm, # (licon.14) + (l_pdiffusion, l_poly_contact): 190*nm, # (licon.14) + (l_nwell, l_nwell): 1270*nm, # (nwell.2a) + (l_nwell, l_pwell): 250*nm, # p_well not needed for SKY130, but lclayout uses it for sizing the wells! + (l_pwell, l_pwell): 1270*nm, # p_well not needed for SKY130 + (l_poly, l_ndiffusion): 75*nm, # (poly.4) + (l_poly, l_pdiffusion): 75*nm, # (poly.4) + (l_poly, l_poly): 210*nm, # (poly.2) + #(l_poly, l_outline): 210/2*nm, # (poly.2) + (l_poly, l_pdiff_contact): 155*nm, # 55*nm # (licon.11) + (l_poly, l_ndiff_contact): 155*nm, # 55*nm # (licon.11) + (l_pdiff_contact, l_pdiff_contact): 270*nm, # (difftap.3) + #(l_pdiff_contact, l_outline): 270/2*nm, # (difftap.3) + (l_ndiff_contact, l_ndiff_contact): 270*nm, # (difftap.3) + #(l_ndiff_contact, l_outline): 270/2*nm, # (difftap.3) + (l_pdiff_contact, l_ndiff_contact): 270*nm, # (difftap.3) + (l_metal1, l_metal1): 170*nm, # (li.3) # !!!! WARNING: Spacing to huge_met1 (>=?nm) needs to be 280nm ! + #(l_metal1, l_outline): 170/2*nm, # (li.3) # !!!! WARNING: Spacing to huge_met1 (>=?nm) needs to be 280nm ! +# (l_metal1, l_border_vertical): 190*nm, # To move the VIAs at the right place +# (l_metal2, l_border_vertical): 190*nm, # To move the VIAs at the right place + + (l_metal2, l_metal2): 140*nm, # (m1.2) # huge_met2 + # We need metal2 at the border for the power lanes, so we dont put border rules + (l_via1, l_via1): 190*nm, # (ct.2) + #(l_via1, l_outline): 190/2*nm, # (ct.2) + #(l_via1, l_diff_contact): 2*l, # NO RULES FOR LICON-MCON spacing found + #(l_via1, l_ndiffusion): 2*l, # NO RULES FOR MCON-DIFF spacing found + #(l_via1, l_pdiffusion): 2*l, # NO RULES FOR MCON-DIFF spacing found + (l_poly_contact, l_pdiff_contact): 170*nm, # (licon.2) + #(l_poly_contact, l_outline): 170/2*nm, # (licon.2) + (l_poly_contact, l_ndiff_contact): 170*nm, # (licon.2) + (l_ndiffusion, l_pplus): 75*nm, + (l_pdiffusion, l_nplus): 75*nm, +} + +# Layer for the pins. +pin_layer = l_metal2 # lclayout.metal2 = sky130.metal1 + +# Power stripe layer +power_layer = l_metal1 # , l_metal2] # lclayout.metal2 = sky130.metal1 + +# Layers that can be connected/merged without changing the schematic. +# This can be used to resolve spacing/notch violations by just filling the space. +connectable_layers = {l_nwell, l_pwell, l_poly} +# Width of the gate polysilicon stripe. +# is reused as the minimum_width for the l_poly layer +gate_length = 150*nm # (poly.1a) + +# Minimum length a polysilicon gate must overlap the silicon. +gate_extension = 130*nm # (poly.8) + +# Minimum distance of active area to upper or lower boundary of the cell. Basically determines the y-offset of the transistors. +transistor_offset_y = 240*nm # !!! This likely needs to be tuned later on # The 150/2*nm might have to be removed + +# Standard cell dimensions. +# A 'unit cell' corresponds to the dimensions of the smallest possible cell. Usually an inverter. +# `unit_cell_width` also corresponds to the pitch of the gates because gates are spaced on a regular grid. +unit_cell_width = 1440*nm # 480*3 (unit SITE) # 1380*nm # 920 is 2*0.46um (unithd SITE), 8 * 130*nm +unit_cell_height = 3330*nm # (unit SITE) # 2720*nm #270*nm # 32 * 130*nm # minimum 16um due to pwell width + nwell-pwell spacing +#assert unit_cell_height >= 16*um, "minimum 16um due to pwell width + nwell-pwell spacing" +# due to nwell size and spacing requirements routing_grid_pitch_y * 8 # * 8 + +# Routing pitch +routing_grid_pitch_x = unit_cell_width // 6 # // 4 +routing_grid_pitch_y = 135*nm # unit_cell_height // 8 // 2 + +# Translate routing grid such that the bottom left grid point is at (grid_offset_x, grid_offset_y) +grid_offset_x = routing_grid_pitch_x +grid_offset_y = 0 # (routing_grid_pitch_y // 2 ) -10 + +# Width of power rail. +power_rail_width = 480*nm # compatible to SKY130 # 3*130*nm # decided by the standard cell library architect + +# Minimum width of polysilicon gate stripes. +# It increases w and l from the spice netlist, so it must be width from the spice netlist +minimum_gate_width_nfet = 150*nm # (poly.1a) +minimum_gate_width_pfet = 150*nm # (poly.1a) + +# Minimum width for pins. +minimum_pin_width = 130*nm + +# Width of routing wires. +wire_width = { + l_ndiffusion: 150*nm, # (difftap.1) + l_pdiffusion: 150*nm, # (difftap.2) + l_poly: 150*nm, # (poly.1a) + l_metal1: 170*nm, # (li.1) + l_metal2: 140*nm, # (m1.1) +} + +# Width of horizontal routing wires (overwrites `wire_width`). +wire_width_horizontal = { + l_ndiffusion: 150*nm, # (difftap.1) + l_pdiffusion: 150*nm, # (difftap.2) + l_poly: 150*nm, # (poly.1a) + l_metal1: 170*nm, # (li.1) + l_metal2: 140*nm, # (m1.1) +} + +# Side lengths of vias (square shaped). +via_size = { + l_poly_contact: 170*nm, # (ct.1) + l_ndiff_contact: 170*nm, # (ct.1) + l_pdiff_contact: 170*nm, # (ct.1) + l_via1: 170*nm # (licon.1) +# l_via2: 150*nm # (via.1a) +} + +# Minimum width rules. +minimum_width = { + l_ndiffusion: 150*nm, # (difftap.1) + l_pdiffusion: 150*nm, # (difftap.1) + l_poly: gate_length, + l_metal1: 170*nm, # (li.1) + l_metal2: 140*nm, # (m1.1) + l_nwell: 1000*nm +} + +# Minimum enclosure rules. +# Syntax: {(outer layer, inner layer): minimum enclosure, ...} +minimum_enclosure = { + # Via enclosure + (l_ndiffusion, l_ndiff_contact): 60*nm, # (licon.5a) + (l_pdiffusion, l_pdiff_contact): 60*nm, # (licon.5a) + (l_poly, l_poly_contact): 80*nm, # (licon.8a) !!! OR (licon.4) ? + (l_metal1, l_pdiff_contact): 80*nm, # (li.5) + (l_metal1, l_ndiff_contact): 80*nm, # (li.5) + (l_metal1, l_poly_contact): 80*nm, # (li.5) + (l_metal1, l_via1): 0*nm, # this was 0,# (ct.4) + (l_metal2, l_via1): 60*nm,# (m1.4) + + # l_*well must overlap l_*diffusion +# (l_nwell, l_pdiffusion): 180*nm+130*nm, # (difftap.8) # This causes notches, I am trying to get rid of them + (l_pwell, l_ndiffusion): 180*nm, # (difftap.8) + (l_abutment_box, l_nwell): 0, # The nwell and pwell should not go beyond the abutment + (l_abutment_box, l_pwell): 0, + (l_nplus, l_ndiff_contact): 80*nm, # Implicitly encodes the size of well taps. + (l_pplus, l_pdiff_contact): 80*nm, # Implicitly encodes the size of well taps. + +} + +# Minimum notch rules. +minimum_notch = { + l_ndiffusion: 130*nm, + l_pdiffusion: 130*nm, + l_poly: 130*nm, + l_metal1: 130*nm, + l_metal2: 130*nm, + l_nwell: 5*130*nm, + l_pwell: 5*130*nm, +} + +# Minimum area rules. +min_area = { + l_metal1: 0.0561 * um * um ,# !!! TEMPORARILY DISABLED, PLEASE ENABLE AGAIN + l_metal2: 0.083 * um * um ,# !!! TEMPORARILY DISABLED, PLEASE ENABLE AGAIN +} + +# ROUTING # + +# Cost for changing routing direction (horizontal/vertical). +# This will avoid creating zig-zag routings. +orientation_change_penalty = 100000 + +# Routing edge weights per data base unit. +weights_horizontal = { + l_ndiffusion: 120000, # (mohms/square) taken from spreadsheet "Layer resistances and capacitances" + l_pdiffusion: 197000, # (mohms/square) + l_poly: 48200*10, # (mohms/square) # 10 to avoid routing + l_metal1: 1280, # SKY130_Li1 Local Interconnect! (mohms/square) + l_metal2: 125, # SKY130_Metal1 +} +weights_vertical = { + l_ndiffusion: 120000, # (mohms/square) taken from spreadsheet "Layer resistances and capacitances" + l_pdiffusion: 197000, # (mohms/square) + l_poly: 48200*10, # (mohms/square) # 10 to avoid routing + l_metal1: 1280, # SKY130_Li1 Local Interconnect! (mohms/square) + l_metal2: 125, # SKY130_Metal1 +} + +viafactor = 1 + +# Via weights. +via_weights = { + (l_metal1, l_ndiffusion): 15000*viafactor, # LICON + (l_metal1, l_pdiffusion): 15000*viafactor, # LICON + (l_metal1, l_poly): 15000*viafactor, # LICON + (l_metal1, l_metal2): 152000*viafactor, # MCON +# (l_metal1, l_nplus): 1, # Contact to Well Taps, the value doesn't matter +# (l_metal1, l_pplus): 1, + +} + +# Enable double vias between layers. +multi_via = { + (l_metal1, l_poly): 1, + (l_metal1, l_metal2): 1, +} + +if( min_spacing[(l_pdiff_contact, l_pdiff_contact)] < min_spacing[(l_pdiffusion,l_pdiffusion)]+2*minimum_enclosure[(l_pdiffusion, l_pdiff_contact)]): + newmin=min_spacing[(l_pdiffusion,l_pdiffusion)]+2*minimum_enclosure[(l_pdiffusion, l_pdiff_contact)] + print("Minimum Spacing "+str(min_spacing[(l_pdiff_contact, l_pdiff_contact)])+" for pdiff_contact too small because of pdiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_pdiffusion,l_pdiffusion)])+"+2*"+str(minimum_enclosure[(l_pdiffusion, l_pdiff_contact)])+") Fixing minimum_spacing") + min_spacing[(l_pdiff_contact, l_pdiff_contact)]=newmin + +if( min_spacing[(l_ndiff_contact, l_ndiff_contact)] < min_spacing[(l_ndiffusion,l_ndiffusion)]+2*minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]): + newmin=min_spacing[(l_ndiffusion,l_ndiffusion)]+2*minimum_enclosure[(l_ndiffusion, l_ndiff_contact)] + print("Minimum Spacing "+str(min_spacing[(l_ndiff_contact, l_ndiff_contact)])+" for ndiff_contact too small because of ndiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_ndiffusion,l_ndiffusion)])+"+2*"+str(minimum_enclosure[(l_ndiffusion, l_ndiff_contact)])+") Fixing minimum_spacing") + min_spacing[(l_ndiff_contact, l_ndiff_contact)]=newmin + +if( min_spacing[(l_pdiff_contact, l_ndiff_contact)] < min_spacing[(l_pdiffusion,l_ndiffusion)]+minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]+minimum_enclosure[(l_pdiffusion, l_pdiff_contact)]): + newmin=min_spacing[(l_pdiffusion,l_ndiffusion)]+minimum_enclosure[(l_ndiffusion, l_ndiff_contact)]+minimum_enclosure[(l_pdiffusion, l_pdiff_contact)] + print("Minimum Spacing "+str(min_spacing[(l_ndiff_contact, l_ndiff_contact)])+" for pdiff_contact - ndiff_contact too small because of ndiffusion, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_pdiffusion,l_ndiffusion)])+"+"+str(minimum_enclosure[(l_ndiffusion, l_ndiff_contact)])+"+"+str(minimum_enclosure[(l_pdiffusion, l_pdiff_contact)])+") Fixing minimum_spacing") + min_spacing[(l_pdiff_contact, l_ndiff_contact)]=newmin + +if((l_poly_contact, l_poly_contact) in min_spacing and min_spacing[(l_poly_contact, l_poly_contact)] < min_spacing[(l_poly,l_poly)]+2*minimum_enclosure[(l_poly, l_poly_contact)]): + newmin=min_spacing[(l_poly,l_poly)]+2*minimum_enclosure[(l_poly, l_poly_contact)] + print("Minimum Spacing "+str(min_spacing[(l_poly_contact, l_poly_contact)])+" for poly_contact too small because of polysilicon, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_poly,l_poly)])+"+"+str(minimum_enclosure[(l_poly, l_poly_contact)])+"+"+str(minimum_enclosure[(l_poly, l_poly_contact)])+") Fixing minimum_spacing") + min_spacing[(l_poly_contact, l_poly_contact)]=newmin + +if((l_poly_contact, l_poly_contact) in min_spacing and min_spacing[(l_poly_contact, l_poly_contact)] < min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_poly_contact)]): + newmin=min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_poly_contact)] + print("Minimum Spacing "+str(min_spacing[(l_poly_contact, l_poly_contact)])+" for poly_contact too small because of local interconnect, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal1,l_metal1)])+"+"+str(minimum_enclosure[(l_metal1, l_poly_contact)])+"+"+str(minimum_enclosure[(l_metal1, l_poly_contact)])+") Fixing minimum_spacing") + min_spacing[(l_poly_contact, l_poly_contact)]=newmin + +if( min_spacing[(l_via1, l_via1)] < min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_via1)]): + newmin=min_spacing[(l_metal1,l_metal1)]+2*minimum_enclosure[(l_metal1, l_via1)] + print("Minimum Spacing "+str(min_spacing[(l_via1, l_via1)])+" for via1 too small because of local interconnect, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal1,l_metal1)])+"+2*"+str(minimum_enclosure[(l_metal1, l_via1)])+") Fixing minimum_spacing") + min_spacing[(l_via1, l_via1)]=newmin + +if( min_spacing[(l_via1, l_via1)] < min_spacing[(l_metal2,l_metal2)]+2*minimum_enclosure[(l_metal2, l_via1)]): + newmin=min_spacing[(l_metal2,l_metal2)]+2*minimum_enclosure[(l_metal2, l_via1)] + print("Minimum Spacing "+str(min_spacing[(l_via1, l_via1)])+" for via1 too small because of metal1, minimum should be "+ str(newmin)+"(="+str(min_spacing[(l_metal2,l_metal2)])+"+2*"+str(minimum_enclosure[(l_metal2, l_via1)])+") Fixing minimum_spacing") + min_spacing[(l_via1, l_via1)]=newmin + + + + #(l_poly_contact, l_pdiff_contact): 170*nm, # (licon.2) + #(l_poly_contact, l_ndiff_contact): 170*nm, # (licon.2) +#unit_cell_height=10 +#routing_grid_pitch_y=4 + +#print("unit_cell_height: "+str(unit_cell_height)) +#print("routing_grid_pitch_y: "+str(routing_grid_pitch_y)) +middle=unit_cell_height//2 +#print("Middle: "+str(middle)) +gridpoints=1+unit_cell_height//routing_grid_pitch_y +#print("gridpoints: "+str(gridpoints)) +odd=gridpoints &1 +#print("odd: "+str(odd)) + +if odd==1: + grid_offset_y=middle-((gridpoints-1)//2)*routing_grid_pitch_y +else: + grid_offset_y=middle+routing_grid_pitch_y//2-(gridpoints//2)*routing_grid_pitch_y + +#print("grid_offset_y: "+str(grid_offset_y)) +grid_ys = list(range(grid_offset_y, grid_offset_y + unit_cell_height +1, routing_grid_pitch_y)) +print("grid_before: "+str(grid_ys)) +grid_ys[2] += 110*nm +grid_ys[-3] -= 110*nm +grid_ys[14] -= 10*nm +grid_ys[1] = 0 +grid_ys[-2] = unit_cell_height +grid_ys.pop(-1) +grid_ys.pop(0) +print("grid_after: "+str(grid_ys)) + + + +def powervias(unit_cell_width): + return list(range(240*nm,unit_cell_width,480*nm)) + +power_vias=powervias diff --git a/Tech.SKY130/libresilicon.m b/Tech.SKY130/libresilicon.m new file mode 100644 index 00000000..473e6e0a --- /dev/null +++ b/Tech.SKY130/libresilicon.m @@ -0,0 +1,14 @@ +* This is a template NMOS model that should be further improved + +.model NMOS_VTL nmos level = 54 + +.model PMOS_VTL pmos level = 54 + +.model nmos nmos level = 54 + +.model pmos pmos level = 54 + +.model nfet nmos level = 54 + +.model pfet pmos level = 54 + diff --git a/Tech.SKY130/libresilicon.tech b/Tech.SKY130/libresilicon.tech new file mode 100644 index 00000000..ace45be8 --- /dev/null +++ b/Tech.SKY130/libresilicon.tech @@ -0,0 +1,3745 @@ +#---------------------------------------------------------- +# Copyright (c) 2020 R. Timothy Edwards +# Revisions: See below +# +# This file is an Open Source foundry process describing +# the SkyWater S8 hybrid 0.18um / 0.13um fabrication +# process. The file may be distributed under the terms +# of the Apache 2.0 license agreement. +# +#---------------------------------------------------------- +# This file is designed to be used with magic versions +# 8.3.24 or newer. +#---------------------------------------------------------- +tech + format 35 + sky130A +end + +version + version 20200508 + description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC" +end + +#---------------------------------------------------------- +# Status 7/10/20: Rev 1 (alpha): +# First public release +#-------------------------------------------------------------- + +#-------------------------------------------------------------- +# Supported device types +#-------------------------------------------------------------- +# device name magic ID layer description +#------------------------------------------------------------- +# nshort nfet standard nFET +# nshort scnfet standard nFET in standard cell** +# nlowvt nfetlvt low Vt nFET +# sonos_p/e nsonos SONOS nFET +# pshort pfet standard pFET +# pshort scpfet standard pFET in standard cell** +# plowvt pfetlvt low Vt pFET +# phighvt pfethvt high Vt pFET +# ntvnative --- native nFET +# phv mvpfet thickox pFET +# nhv mvnfet thickox nFET +# nhvnative mvnnfet thickox native nFET +# ndiode ndiode n+ diff diode +# ndiode_h mvndiode thickox n+ diff diode +# pdiode pdiode p+ diff diode +# pdiode_h mvpdiode thickox p+ diff diode +# ndiode_native nndiode diode with nndiff +# ndiode_lvt ndiodelvt low Vt n+ diff diode +# pdiode_lvt pdiodelvt low Vt p+ diff diode +# pdiode_hvt pdiodehvt high Vt p+ diff diode +# nwdiode --- nwell diode +# dnwdiode_psub --- deep nwell diode to substrate +# dnwdiode_pw --- deep nwell diode to pwell +# xcmimc1 mimcap MiM cap 1st plate +# xcmimc2 mimcap2 MiM cap 2nd plate +# mrdn rdn n+ diff resistor +# mrdn_hv mvrdn thickox n+ diff resistor +# mrdp rdp p+ diff resistor +# mrdp_hv mvrdp thickox p+ diff resistor +# mrl1 rli local interconnect resistor +# mrp1 npres n+ poly resistor +# xhrpoly_* ppres (*) p+ poly resistor (300 Ohms/sq) +# uhrpoly_* xres (*) p+ poly resistor (2k Ohms/sq) +# xcnwvc varactor varactor (low Vt?) +# xcnwvc2 varactorhvt high Vt varactor +# xchvnwc mvvaractor thickox varactor +# xpwres rpw pwell resistor (in deep nwell) +# +# (*) Note that ppres may extract into some generic type +# called "xhrpoly", but only specific sizes of xhrpoly are +# allowed, and these are created from fixed layouts like the +# types below. +# +# (**) nFET and pFET in standard cells are the same as devices +# outside of the standard cell except for the DRC rule for +# FET to diffusion contact spacing (which is 0.05um, not 0.055um) +# +# To avoid creating a large number of types, a few ID layers are +# used in conjunction with standard devices types: "lvt" for +# low threshold voltage, and "hvt" for high threshold voltage. +# "dnwell" is used as an identifier layer where appropriate. +# Layer HVI (thick oxide) is treated differently, and types +# "mv*" are defined where thick oxide is required. +# +#------------------------------------------------------------- +# The following devices are not extracted but are represented +# only by script-generated subcells in the PDK. +#------------------------------------------------------------- +# nshortesd ESD nFET +# nhvesd ESD thickox nFET +# nhvnativeesd ESD native nFET +# phvesd ESD thickox pFET +# fnpass flash nFET device +# npnpar1x* parasitic NPN +# npn_1x1_2p0_hv thickox gated parasitic NPN +# pnppar parasitic PNP +# pnppar5x parasitic PNP +# xesd_ndiode_h_*** ESD n+ diode +# xesd_pdiode_h_*** ESD p+ diode +# reslocsub local substrate island indicator +# xcmvpp Vpp cap +# xcmvpp_2 Vpp cap +# xcmvpp_* Vpp cap +# xcmvpp* Vpp cap +# balun balun inductor +# ind4 inductor +# fuse metal fuse device +#-------------------------------------------------------------- + +#----------------------------------------------------- +# Tile planes +#----------------------------------------------------- + +planes + dwell,dw + well,w + active,a + locali,li1,li + metal1,m1 + metal2,m2 + metal3,m3 + cap1,c1 + metal4,m4 + cap2,c2 + metal5,m5 + block,b + comment,c +end + +#----------------------------------------------------- +# Tile types +#----------------------------------------------------- + +types +# Deep nwell + dwell dnwell,dnw + +# Wells + well nwell,nw + -well pwell,pw + -well rpw,rpwell + -well obswell + +# Transistors + active nmos,ntransistor,nfet + -active scnmos,scntransistor,scnfet + active pmos,ptransistor,pfet + -active scpmos,scptransistor,scpfet + -active nnmos,nntransistor + active mvnmos,mvntransistor,mvnfet + active mvpmos,mvptransistor,mvpfet + -active mvnnmos,mvnntransistor,mvnnfet,nnfet + -active varactor,varact,var + -active mvvaractor,mvvaract,mvvar + + -active pmoslvt,pfetlvt + -active pmoshvt,pfethvt + -active nmoslvt,nfetlvt + -active varactorhvt,varacthvt,varhvt + -active nsonos,sonos + +# Diffusions + active ndiff,ndiffusion,ndif + active pdiff,pdiffusion,pdif + -active mvndiff,mvndiffusion,mvndif + -active mvpdiff,mvpdiffusion,mvpdif + active ndiffc,ndcontact,ndc + active pdiffc,pdcontact,pdc + -active mvndiffc,mvndcontact,mvndc + -active mvpdiffc,mvpdcontact,mvpdc + active psubdiff,psubstratepdiff,ppdiff,ppd,psd + active nsubdiff,nsubstratendiff,nndiff,nnd,nsd + -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd + -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd + active psubdiffcont,psubstratepcontact,psc + active nsubdiffcont,nsubstratencontact,nsc + -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc + -active mvnsubdiffcont,mvnsubstratencontact,mvnsc + -active obsactive + -active mvobsactive + +# Poly + active poly,p,polysilicon + active polycont,pc,pcontact,polycut,polyc + active xpolycontact,xpolyc,xpc + +# Resistors + -active npolyres,npres,mrp1 + -active ppolyres,ppres,xhrpoly + -active xpolyres,xpres,xres,uhrpoly + -active ndiffres,rnd,rdn,rndiff + -active pdiffres,rpd,rdp,rpdiff + -active mvndiffres,mvrnd,mvrdn,mvrndiff + -active mvpdiffres,mvrpd,mvrdp,mvrpdiff + -active rmp + +# Diodes + -active pdiode,pdi + -active ndiode,ndi + -active nndiode,nndi + -active pdiodec,pdic + -active ndiodec,ndic + -active nndiodec,nndic + -active mvpdiode,mvpdi + -active mvndiode,mvndi + -active mvpdiodec,mvpdic + -active mvndiodec,mvndic + -active pdiodelvt,pdilvt + -active pdiodehvt,pdihvt + -active ndiodelvt,ndilvt + -active pdiodelvtc,pdilvtc + -active pdiodehvtc,pdihvtc + -active ndiodelvtc,ndilvtc + +# Local Interconnect + locali locali,li1,li + -locali corelocali,coreli1,coreli + -locali rlocali,rli1,rli + locali viali,vial,lic,licon,m1c,v0 + -locali obsli1,obsli + -locali obsli1c,obslic,obslicon + +# Metal 1 + metal1 metal1,m1,met1 + -metal1 rmetal1,rm1,rmet1 + metal1 via1,m2contact,m2cut,m2c,via,v,v1 + -metal1 obsm1 + -metal1 padl + +# Metal 2 + metal2 metal2,m2,met2 + -metal2 rmetal2,rm2,rmet2 + metal2 via2,m3contact,m3cut,m3c,v2 + -metal2 obsm2 + +# Metal 3 + metal3 metal3,m3,met3 + -metal3 rmetal3,rm3,rmet3 + -metal3 obsm3 + metal3 via3,v3 + + -cap1 mimcap,mim,capm + -cap1 mimcapcontact,mimcapc,mimcc,capmc + +# Metal 4 + metal4 metal4,m4,met4 + -metal4 rmetal4,rm4,rmet4 + -metal4 obsm4 + metal4 via4,v4 + + -cap2 mimcap2,mim2,capm2 + -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c + +# Metal 5 + metal5 metal5,m5,met5 + -metal5 rm5,rmetal5,rmet5 + -metal5 obsm5 + + +# Miscellaneous + -block glass + -block fillblock + -comment comment + -comment obscomment + +end + +#----------------------------------------------------- +# Magic contact types +#----------------------------------------------------- + +contact + pc poly locali + ndc ndiff locali + pdc pdiff locali + nsc nsd locali + psc psd locali + ndic ndiode locali + ndilvtc ndiodelvt locali + nndic nndiode locali + pdic pdiode locali + pdilvtc pdiodelvt locali + pdihvtc pdiodehvt locali + xpc xpc locali + + mvndc mvndiff locali + mvpdc mvpdiff locali + mvnsc mvnsd locali + mvpsc mvpsd locali + mvndic mvndiode locali + mvpdic mvpdiode locali + + lic locali metal1 + obslic obsli obsm1 + + via1 metal1 metal2 + via2 metal2 metal3 + via3 metal3 metal4 + via4 metal4 metal5 + stackable + + # MiM cap contacts are not stackable! + mimcc mimcap metal4 + mim2cc mimcap2 metal5 + + padl m1 m2 m3 m4 m5 glass + +end + +#----------------------------------------------------- +# Layer aliases +#----------------------------------------------------- + +aliases + + allwellplane nwell + allnwell nwell,obswell + + allnfets nfet,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos + allpfets pfet,scpfet,mvpfet,pfethvt,pfetlvt + allfets allnfets,allpfets,varactor,mvvaractor,varhvt + + allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt + allnactive allnactivenonfet,allnfets + allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets + allnactivetap *nsd,*mvnsd,var,varhvt,mvvar + + allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt + allpactive allpactivenonfet,allpfets + allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets + allpactivetap *psd,*mvpsd + + allactivenonfet allnactivenonfet,allpactivenonfet + allactive allactivenonfet,allfets + + allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres + + allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,scnfet,nfetlvt,nsonos + allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,scpfet,pfetlvt,pfethvt + alldifflv allndifflv,allpdifflv + allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt + allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt + alldifflvnonfet allndifflvnonfet,allpdifflvnonfet + + allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet + allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet + alldiffmv allndiffmv,allpdiffmv + allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet + allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet + alldiffmvnontap allndiffmvnontap,allpdiffmvnontap + allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres + allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres + alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet + + alldiffnonfet alldifflvnonfet,alldiffmvnonfet + alldiff alldifflv,alldiffmv + + allpolyres mrp1,xhrpoly,uhrpoly,rmp + allpolynonfet *poly,allpolyres,xpc + allpolynonres *poly,allfets,xpc + + allpoly allpolynonfet,allfets + allpolynoncap *poly,xpc,allfets,allpolyres + + allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc + allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc + allndiffcontmv mvndc,mvnsc,mvndic + allpdiffcontmv mvpdc,mvpsc,mvpdic + allndiffcont allndiffcontlv,allndiffcontmv + allpdiffcont allpdiffcontlv,allpdiffcontmv + alldiffcontlv allndiffcontlv,allpdiffcontlv + alldiffcontmv allndiffcontmv,allpdiffcontmv + alldiffcont alldiffcontlv,alldiffcontmv + + allcont alldiffcont,pc + + allres allpolyres,allactiveres + + allli *locali,coreli,rli + allm1 *m1,rm1 + allm2 *m2,rm2 + allm3 *m3,rm3 + allm4 *m4,rm4 + allm5 *m5,rm5 + + allpad padl + + psub pwell + +end + +#----------------------------------------------------- +# Layer drawing styles +#----------------------------------------------------- + +styles + styletype mos + dnwell cwell + nwell nwell + pwell pwell + rpwell pwell ptransistor_stripes + ndiff ndiffusion + pdiff pdiffusion + nsd ndiff_in_nwell + psd pdiff_in_pwell + nfet ntransistor ntransistor_stripes + scnfet ntransistor ntransistor_stripes + pfet ptransistor ptransistor_stripes + scpfet ptransistor ptransistor_stripes + var polysilicon ndiff_in_nwell + ndc ndiffusion metal1 contact_X'es + pdc pdiffusion metal1 contact_X'es + nsc ndiff_in_nwell metal1 contact_X'es + psc pdiff_in_pwell metal1 contact_X'es + + pfetlvt ptransistor ptransistor_stripes implant1 + pfethvt ptransistor ptransistor_stripes implant2 + nfetlvt ntransistor ntransistor_stripes implant1 + nsonos ntransistor implant3 + varhvt polysilicon ndiff_in_nwell implant2 + + mvndiff ndiffusion hvndiff_mask + mvpdiff pdiffusion hvpdiff_mask + mvnsd ndiff_in_nwell hvndiff_mask + mvpsd pdiff_in_pwell hvpdiff_mask + mvnfet ntransistor ntransistor_stripes hvndiff_mask + mvnnfet ntransistor ndiff_in_nwell hvndiff_mask + mvpfet ptransistor ptransistor_stripes + mvvar polysilicon ndiff_in_nwell hvndiff_mask + mvndc ndiffusion metal1 contact_X'es hvndiff_mask + mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask + mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask + mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask + + poly polysilicon + pc polysilicon metal1 contact_X'es + npolyres polysilicon silicide_block nselect2 + ppolyres polysilicon silicide_block pselect2 + xpc polysilicon pselect2 metal1 contact_X'es + rmp polysilicon poly_resist_stripes + + pdiode pdiffusion pselect2 + ndiode ndiffusion nselect2 + pdiodec pdiffusion pselect2 metal1 contact_X'es + ndiodec ndiffusion nselect2 metal1 contact_X'es + + nndiode ndiffusion nselect2 implant3 + ndiodelvt ndiffusion nselect2 implant1 + pdiodelvt pdiffusion pselect2 implant1 + pdiodehvt pdiffusion pselect2 implant2 + pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es + pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es + ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es + + mvpdiode pdiffusion pselect2 hvpdiff_mask + mvndiode ndiffusion nselect2 hvndiff_mask + mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask + mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask + nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask + + locali metal1 + coreli metal1 + rli metal1 poly_resist_stripes + lic metal1 metal2 via1arrow + obsli metal1 + obslic metal1 metal2 via1arrow + + metal1 metal2 + rm1 metal2 poly_resist_stripes + obsm1 metal2 + m2c metal2 metal3 via2arrow + metal2 metal3 + rm2 metal3 poly_resist_stripes + obsm2 metal3 + m3c metal3 metal4 via3alt + metal3 metal4 + rm3 metal4 poly_resist_stripes + obsm3 metal4 + mimcap metal3 mems + mimcc metal3 contact_X'es mems + mimcap2 metal4 mems + mim2cc metal4 contact_X'es mems + via3 metal4 metal5 via4 + metal4 metal5 + rm4 metal5 poly_resist_stripes + obsm4 metal5 + via4 metal5 metal6 via5 + metal5 metal6 + rm5 metal6 poly_resist_stripes + obsm5 metal6 + + glass overglass + mrp1 poly_resist poly_resist_stripes + xhrpoly poly_resist silicide_block + uhrpoly poly_resist + ndiffres ndiffusion ndop_stripes + pdiffres pdiffusion pdop_stripes + mvndiffres ndiffusion hvndiff_mask ndop_stripes + mvpdiffres pdiffusion hvpdiff_mask pdop_stripes + comment comment + error_p error_waffle + error_s error_waffle + error_ps error_waffle + fillblock cwell + + obswell cwell + obsactive implant4 + + padl metal6 via6 overglass + + magnet substrate_field_implant + rotate via3alt + fence via5 +end + +#----------------------------------------------------- +# Special paint/erase rules +#----------------------------------------------------- + +compose + compose nfet poly ndiff + compose pfet poly pdiff + compose var poly nsd + + compose mvnfet poly mvndiff + compose mvpfet poly mvpdiff + compose mvvar poly mvnsd + + paint ndc nwell pdc + paint nfet nwell pfet + paint scnfet nwell scpfet + paint ndiff nwell pdiff + paint psd nwell nsd + paint psc nwell nsc + + paint pdc pwell ndc + paint pfet pwell nfet + paint scpfet pwell scnfet + paint pdiff pwell ndiff + paint nsd pwell psd + paint nsc pwell psc + + paint pdc coreli pdc + paint ndc coreli ndc + paint pc coreli pc + paint nsc coreli pc + paint psc coreli pc + paint viali coreli viali + + paint coreli pdc pdc + paint coreli ndc ndc + paint coreli pc pc + paint coreli nsc nsc + paint coreli psc psc + paint coreli viali viali + + paint m4 obsm4 m4 + paint m5 obsm5 m5 +end + +#----------------------------------------------------- +# Electrical connectivity +#----------------------------------------------------- + +connect + *nwell,*nsd,*mvnsd,dnwell *nwell,*nsd,*mvnsd,dnwell + pwell,*psd,*mvpsd pwell,*psd,*mvpsd + *li,coreli *li,coreli + *m1 *m1 + *m2 *m2 + *m3 *m3 + *m4 *m4 + *m5 *m5 + *mimcap *mimcap + *mimcap2 *mimcap2 + allnactivenonfet allnactivenonfet + allpactivenonfet allpactivenonfet + *poly,xpc,allfets *poly,xpc,allfets +end + +#----------------------------------------------------- +# CIF/GDS output layer definitions +#----------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size + +cifoutput + +#---------------------------------------------------------------- +style gdsii +# NOTE: This section is used for actual GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + gridlimit 5 + +#---------------------------------------------------------------- +# Create a temp layer from the cell bounding box for use in +# generating ID layers. Note that "boundary", unlike "bbox", +# requires the FIXED_BBOX property (abutment box) in the cell. +#---------------------------------------------------------------- + templayer CELLBOUND + boundary + +#---------------------------------------------------------------- +# BOUND +#---------------------------------------------------------------- + layer BOUND CELLBOUND + calma 235 4 + +# Create a boundary outside of an abutment box, so that layers +# can be made to stretch to the abutment box edges. First strink +# so that any box that would be so small as to interact with +# itself will be removed. + + templayer CELLRING CELLBOUND + shrink 345 + grow 545 + and-not CELLBOUND + +#---------------------------------------------------------------- +# DNWELL +#---------------------------------------------------------------- + + layer DNWELL dnwell + calma 64 18 + + layer PWRES rpw + and dnwell + calma 64 13 + +#---------------------------------------------------------------- +# NWELL +#---------------------------------------------------------------- + + layer NWELL allnwell + bloat-all rpw dnwell + and-not rpw,pwell + calma 64 20 + + layer WELLTXT + labels allnwell noport + calma 64 16 + + layer WELLPIN + labels allnwell port + calma 64 5 + +#---------------------------------------------------------------- +# SUB (text/port only) +#---------------------------------------------------------------- + + layer SUBTXT + labels pwell noport + calma 122 16 + + layer SUBPIN + labels pwell port + calma 64 59 + +#---------------------------------------------------------------- +# DIFF +#---------------------------------------------------------------- + + layer DIFF allnactivenontap,allpactivenontap,allactiveres + labels allnactivenontap,allpactivenontap + calma 65 20 + +#---------------------------------------------------------------- +# TAP +#---------------------------------------------------------------- + + layer TAP allnactivetap,allpactivetap + labels allnactivetap,allpactivetap + calma 65 44 + +#---------------------------------------------------------------- +# PPLUS, NPLUS (PSDM, NSDM) +#---------------------------------------------------------------- + + templayer basePPLUS pdiffres,mvpdiffres + grow 15 + or xhrpoly,uhrpoly,xpc + grow 110 + bloat-or allpactivetap * 125 allnactivenontap 0 + bloat-or allpactivenontap * 125 allnactivetap 0 + bridge 380 380 + + templayer extendPPLUS basePPLUS,CELLRING + grow 185 + shrink 185 + and-not CELLRING + + layer PPLUS basePPLUS,extendPPLUS + close 265000 + calma 94 20 + + templayer baseNPLUS ndiffres,mvndiffres + grow 125 + bloat-or allnactivetap * 125 allpactivenontap 0 + bloat-or allnactivenontap * 125 allpactivetap 0 + bridge 380 380 + + templayer extendNPLUS baseNPLUS,CELLRING + grow 185 + shrink 185 + and-not CELLRING + + layer NPLUS baseNPLUS,extendNPLUS + close 265000 + calma 93 44 + +#---------------------------------------------------------------- +# LVTN +#---------------------------------------------------------------- + + layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 125 44 + +#---------------------------------------------------------------- +# HVTP +#---------------------------------------------------------------- + + layer HVTP pfethvt,varhvt,*pdiodehvt + grow 180 + bridge 380 380 + grow 185 + shrink 185 + close 265000 + calma 78 44 + +#---------------------------------------------------------------- +# SONOS +#---------------------------------------------------------------- + + layer SONOS nsonos + grow 100 + grow-min 410 + bridge 500 410 + grow 250 + shrink 250 + calma 80 20 + +#---------------------------------------------------------------- +# SONOS requires COREID around area (areaid.ce). Also, the +# coreli layer indicates a cell needing COREID. +#---------------------------------------------------------------- + + layer COREID + bloat-all nsonos,coreli CELLBOUND + calma 81 2 + +#---------------------------------------------------------------- +# STDCELL applies to all cells containing scnfet or scpfet. +#---------------------------------------------------------------- + + layer STDCELL scnfet + bloat-all scpfet,scnfet CELLBOUND + calma 81 4 + +#---------------------------------------------------------------- +# RPM +#---------------------------------------------------------------- + + layer RPM + bloat-all xhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 86 20 + +#---------------------------------------------------------------- +# URPM (2kOhms/sq. poly implant) +#---------------------------------------------------------------- + + layer URPM + bloat-all uhrpoly xpc + grow 200 + grow-min 1270 + grow 420 + shrink 420 + calma 79 20 + +#---------------------------------------------------------------- +# LDNTM (Tip implant for SONOS FETs) +#---------------------------------------------------------------- + + layer LDNTM + bloat-all nsonos *ndiff + grow 185 + grow 345 + shrink 345 + calma 11 44 + +#---------------------------------------------------------------- +# HVNTM (Tip implant for MV ndiff devices) +#---------------------------------------------------------------- + + templayer hvntm_block *mvpsd + grow 185 + + layer HVNTM + bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff + bloat-all mvvaractor *mvnsd + and-not hvntm_block + grow 185 + grow 345 + shrink 345 + calma 125 20 + +#---------------------------------------------------------------- +# POLY +#---------------------------------------------------------------- + + layer POLY allpoly + calma 66 20 + + layer POLYTXT + labels allpoly noport + calma 66 16 + + layer POLYPIN + labels allpoly port + calma 66 5 + +#---------------------------------------------------------------- +# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26) +#---------------------------------------------------------------- + + templayer baseTHKOX *mvpsd + grow-min 470 + or alldiffmv,mvvar + grow 185 + bloat-all alldiffmv nwell + grow-min 600 + bridge 700 600 + + templayer extendTHKOX baseTHKOX,CELLRING + grow 345 + shrink 345 + and-not CELLRING + + layer THKOX baseTHKOX,extendTHKOX + calma 75 20 + +#---------------------------------------------------------------- +# CONT (LICON) +#---------------------------------------------------------------- + + layer CONT allcont + squares-grid 0 170 170 + calma 66 44 + + # Contact for pres is different than other LICON contacts + # See rules LICON 1b, 1c (width/length) and 2b (spacing) + templayer xpc_horiz xpc + shrink 1007 + grow 1007 + + layer CONT xpc + and-not xpc_horiz + # Force long edge vertical for contacts narrower than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 190 520 80 2000 350 + calma 66 44 + + layer CONT xpc + and xpc_horiz + # Force long edge vertical for contacts wider than 2um + # Minimum space is 350 but 520 satisfies no. of contacts rule + slots 80 2000 350 80 190 520 + calma 66 44 + +#---------------------------------------------------------------- +# NPC (Nitride poly cut) +# surrounds CONT (LICON) on poly only (i.e., pc) +#---------------------------------------------------------------- + + layer NPC pc + squares-grid 0 170 170 + grow 100 + bridge 270 270 + grow 130 + shrink 130 + calma 95 20 + + # NPC is also generated on xhrpoly and uhrpoly resistors + + layer NPC xpc,xhrpoly,uhrpoly + # xpc surrounds precision_resistor by 0.095um + grow 95 + grow 130 + shrink 130 + calma 95 20 + +#---------------------------------------------------------------- +# Device markers +#---------------------------------------------------------------- + + layer DIFFRES rdn,mvrdn,rdp,mvrdp + calma 65 13 + + layer POLYRES mrp1 + calma 66 13 + + # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers + layer POLYSHORT rmp + calma 66 15 + + # POLYRES extends to edge of contact cut + layer POLYRES xhrpoly,uhrpoly + grow 60 + and xpc + or xhrpoly,uhrpoly + calma 66 13 + + layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt + # To be done: Expand to include anode, cathode, and guard ring + calma 81 23 + +#---------------------------------------------------------------- +# LI +#---------------------------------------------------------------- + layer LI allli + calma 67 20 + + layer LITXT + labels *locali,coreli noport + calma 67 16 + + layer LIPIN + labels *locali,coreli port + calma 67 5 + + layer LIRES rli + labels rli + calma 67 13 + +#---------------------------------------------------------------- +# MCON +#---------------------------------------------------------------- + layer MCON lic + squares-grid 0 170 190 + calma 67 44 + +#---------------------------------------------------------------- +# MET1 +#---------------------------------------------------------------- + layer MET1 allm1 + calma 68 20 + + layer MET1TXT + labels allm1 noport + calma 68 16 + + layer MET1PIN + labels allm1 port + calma 68 5 + + layer MET1RES rm1 + labels rm1 + calma 68 13 + +#---------------------------------------------------------------- +# VIA1 +#---------------------------------------------------------------- + layer VIA1 via1 + squares-grid 55 150 170 + calma 68 44 + +#---------------------------------------------------------------- +# MET2 +#---------------------------------------------------------------- + layer MET2 allm2 + calma 69 20 + + layer MET2TXT + labels allm2 noport + calma 69 16 + + layer MET2PIN + labels allm2 port + calma 69 5 + + layer MET2RES rm2 + labels rm2 + calma 69 13 + +#---------------------------------------------------------------- +# VIA2 +#---------------------------------------------------------------- + layer VIA2 via2 + squares-grid 40 200 200 + calma 69 44 + +#---------------------------------------------------------------- +# MET3 +#---------------------------------------------------------------- + layer MET3 allm3 + calma 70 20 + + layer MET3TXT + labels allm3 noport + calma 70 16 + + layer MET3PIN + labels allm3 port + calma 70 5 + + layer MET3RES rm3 + labels rm3 + calma 70 13 + +#---------------------------------------------------------------- +# VIA3 +#---------------------------------------------------------------- + layer VIA3 via3 + or mimcc + squares-grid 60 200 200 + calma 70 44 + +#---------------------------------------------------------------- +# MET4 +#---------------------------------------------------------------- + layer MET4 allm4 + calma 71 20 + + layer MET4TXT + labels allm4 noport + calma 71 16 + + layer MET4PIN + labels allm4 port + calma 71 5 + + layer MET4RES rm4 + labels rm4 + calma 71 13 + +#---------------------------------------------------------------- +# VIA4 +#---------------------------------------------------------------- + layer VIA4 via4 + or mim2cc + squares-grid 190 800 800 + calma 71 44 + +#---------------------------------------------------------------- +# MET5 +#---------------------------------------------------------------- + layer MET5 allm5 + calma 72 20 + + layer MET5TXT + labels allm5 noport + calma 72 16 + + layer MET5PIN + labels allm5 port + calma 72 5 + + layer MET5RES rm5 + labels rm5 + calma 72 13 + + + +#---------------------------------------------------------------- +# GLASS +#---------------------------------------------------------------- + layer GLASS glass + calma 76 20 + +#---------------------------------------------------------------- +# CAPM +#---------------------------------------------------------------- + layer CAPM *mimcap + labels mimcap + calma 89 44 + + layer CAPM2 *mimcap2 + labels mimcap2 + calma 97 44 + +#---------------------------------------------------------------- +# Chip top level marker for DRC latchup rules to check 15um +# distance to taps (otherwise 6um is used) +#---------------------------------------------------------------- + + layer LOWTAPDENSITY + bbox top + # Clear 200um for pads + 50um for required high tap density + # in critical area. + shrink 250000 + calma 81 14 + +#---------------------------------------------------------------- +# FILLBLOCK +#---------------------------------------------------------------- + layer FILLOBSM1 fillblock + calma 62 24 + + layer FILLOBSM2 fillblock + calma 105 52 + + layer FILLOBSM3 fillblock + calma 107 24 + + layer FILLOBSM4 fillblock + calma 112 4 + + render DNWELL cwell -0.1 0.1 + render NWELL nwell 0.0 0.2062 + render DIFF ndiffusion 0.2062 0.12 + render TAP pdiffusion 0.2062 0.12 + render POLY polysilicon 0.3262 0.18 + render CONT via 0.5062 0.43 + render LI metal1 0.9361 0.10 + render MCON via 1.0361 0.34 + render MET1 metal2 1.3761 0.36 + render VIA1 via 1.7361 0.27 + render MET2 metal3 2.0061 0.36 + render VIA2 via 2.3661 0.42 + render MET3 metal4 2.7861 0.845 + render VIA3 via 3.6311 0.39 + render MET4 metal5 4.0211 0.845 + render VIA4 via 4.8661 0.505 + render MET5 metal6 5.3711 1.26 + render CAPM metal8 2.4661 0.2 + render CAPM2 metal9 3.7311 0.2 + +#---------------------------------------------------------------- +style drc +#---------------------------------------------------------------- +# NOTE: This style is used for DRC only, not for GDS output +#---------------------------------------------------------------- + scalefactor 10 nanometers + options calma-permissive-labels + + # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside + templayer dnwell_shrink dnwell + shrink 1030 + + templayer nwell_missing dnwell + grow 400 + and-not dnwell_shrink + and-not nwell + + # SONOS nFET devices must be in deep nwell + templayer dnwell_missing nsonos + and-not dnwell + + # Define MiM cap bottom plate for spacing rule + templayer mim_bottom + bloat-all *mimcap *metal3 + + # Define MiM2 cap bottom plate for spacing rule + templayer mim2_bottom + bloat-all *mimcap2 *metal4 + + # Note that metal fill is performed by the foundry and so is not + # an option for a cifoutput style. + + # Check latchup rule (15um minimum from tap LICON center to any + # non-tap diffusion. Note that to count as a tap, the diffusion + # must be contacted to LI + + templayer ptap_reach psc,mvpsc + and-not dnwell + # grow total is 15um. grow in 0.84um increments to ensure that + # no nwell ring is crossed + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 840 + and-not nwell,dnwell + grow 635 + and-not nwell,dnwell + + templayer ptap_missing *ndiff,*mvndiff + and-not dnwell + and-not ptap_reach + + templayer ntap_reach nsc,mvnsc + # grow total is 15um. grow in 1.27um increments to ensure that + # no nwell ring is crossed. There is no difference between + # ntaps in and out of deep nwell. + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 1270 + and nwell + grow 945 + and nwell + + templayer ntap_missing *pdiff,*mvpdiff + and-not dnwell + and-not ntap_reach + + templayer dptap_reach psc,mvpsc + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 840 + and-not nwell + and dnwell + grow 635 + and-not nwell + and dnwell + + templayer dptap_missing *ndiff,*mvndiff + and dnwell + and-not dptap_reach + + templayer m1_small_hole *m1 + close 140000 + + templayer m1_hole_empty m1_small_hole + and-not *m1 + + templayer m2_small_hole *m2 + close 140000 + + templayer m2_hole_empty m2_small_hole + and-not *m2 + + +end + +#----------------------------------------------------------------------- +cifinput +#----------------------------------------------------------------------- +# NOTE: All values in this section MUST be multiples of 25 +# or else magic will scale below the allowed layout grid size +#----------------------------------------------------------------------- + +style vendorimport + scalefactor 10 nanometers + gridlimit 5 + + options ignore-unknown-layer-labels no-reconnect-labels + + ignore NPC + ignore SEALID + ignore NPNID + ignore PNPID + ignore CAPID + ignore LDNTM + ignore HVNTM + ignore POLYMOD + ignore LOWTAPDENSITY + + layer nwell NWELL,WELLTXT,WELLPIN + labels NWELL + labels WELLTXT text + labels WELLPIN port + + layer pwell SUBTXT,SUBPIN + labels SUBTXT text + labels SUBPIN port + + layer dnwell DNWELL + labels DNWELL + + layer rpw PWRES + and DNWELL + labels PWRES + + templayer ndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and-not THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + labels TAPPIN port + + layer ndiff ndiffarea + + # Copy ndiff areas up for contact checks + templayer xndifcheck ndifcheck + copyup ndifcheck + + templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and-not NWELL + and-not PPLUS + and-not DIODE + and-not DIFFRES + and THKOX + and NPLUS + copyup ndifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvndiff mvndiffarea + + # Copy ndiff areas up for contact checks + templayer mvxndifcheck mvndifcheck + copyup mvndifcheck + + layer ndiode DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + labels DIFF + + layer ndiodelvt DIFF + and NPLUS + and DIODE + and-not NWELL + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + labels DIFF + + templayer ndiodearea DIODE + and NPLUS + and-not THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer ndiffres DIFFRES + and NPLUS + and-not THKOX + labels DIFF + + templayer pdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and-not DIODE + and-not THKOX + and PPLUS + copyup pdifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer pdiff pdiffarea + + layer mvndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and-not LVTN + labels DIFF + + layer nndiode DIFF + and NPLUS + and DIODE + and THKOX + and-not POLY + and-not PPLUS + and LVTN + labels DIFF + + templayer mvndiodearea DIODE + and NPLUS + and THKOX + and-not NWELL + copyup DIODE,NPLUS + + layer mvndiffres DIFFRES + and NPLUS + and THKOX + labels DIFF + + templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN + and-not POLY + and NWELL + and-not NPLUS + and THKOX + and-not DIODE + and-not DIFFRES + and PPLUS + copyup mvpdifcheck + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvpdiff mvpdiffarea + + # Copy pdiff areas up for contact checks + templayer xpdifcheck pdifcheck + copyup pdifcheck + + layer pdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodelvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + and DIODE + labels DIFF + + layer pdiodehvt DIFF + and PPLUS + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + and DIODE + labels DIFF + + templayer pdiodearea DIODE + and PPLUS + and-not THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, regardless of the presence of a well. + + templayer pfetarea DIFF + and-not NPLUS + and-not THKOX + and POLY + + layer pfet pfetarea + and-not LVTN + and-not HVTP + and-not STDCELL + labels DIFF + + layer scpfet pfetarea + and-not LVTN + and-not HVTP + and STDCELL + labels DIFF + + layer pfetlvt pfetarea + and LVTN + labels DIFF + + layer pfethvt pfetarea + and HVTP + labels DIFF + + # Always force nwell under pfet (nwell encloses pdiff by 0.18) + layer nwell pfetarea + grow 180 + + # Copy mvpdiff areas up for contact checks + templayer mvxpdifcheck mvpdifcheck + copyup mvpdifcheck + + layer mvpdiode DIFF + and PPLUS + and-not POLY + and-not NPLUS + and THKOX + and DIODE + labels DIFF + + templayer mvpdiodearea DIODE + and PPLUS + and THKOX + copyup DIODE,PPLUS + + # Define pfet areas as known pdiff, + # regardless of the presence of a + # well. + + templayer mvpfetarea DIFF + and-not NPLUS + and THKOX + and POLY + + layer mvpfet mvpfetarea + labels DIFF + + layer pdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and-not THKOX + and-not DIODE + and-not DIFFRES + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer pdiffres DIFFRES + and PPLUS + and NWELL + and-not THKOX + labels DIFF + + layer nfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and-not LVTN + and-not SONOS + and-not STDCELL + labels DIFF + + layer scnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and-not LVTN + and-not SONOS + and STDCELL + labels DIFF + + layer nfetlvt DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and-not SONOS + labels DIFF + + layer nsonos DIFF + and POLY + and-not PPLUS + and NPLUS + and-not THKOX + and LVTN + and SONOS + labels DIFF + + templayer nsdarea DIFF + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and-not THKOX + copyup nsubcheck + + layer nsd nsdarea + labels DIFF + + layer nsd TAP,TAPPIN + and NPLUS + labels TAP + labels TAPPIN port + + templayer nsdexpand nsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer xnsubcheck nsubcheck + copyup nsubcheck + + templayer psdarea DIFF + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and-not THKOX + and-not pfetexpand + copyup psubcheck + + layer psd psdarea + labels DIFF + + layer psd TAP,TAPPIN + and PPLUS + and-not THKOX + labels TAP + labels TAPPIN port + + templayer psdexpand psdarea + grow 500 + + layer mvpdiff DIFF,DIFFTXT,DIFFPIN + and-not NPLUS + and-not POLY + and THKOX + and mvpfetexpand + labels DIFF + labels DIFFTXT text + labels DIFFPIN port + + layer mvpdiffres DIFFRES + and PPLUS + and NWELL + and THKOX + and-not mvrdpioedge + labels DIFF + + layer mvnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and-not LVTN + and THKOX + labels DIFF + + layer mvnnfet DIFF + and POLY + and-not PPLUS + and NPLUS + and LVTN + and THKOX + labels DIFF + + templayer mvnsdarea DIFF + and NPLUS + and NWELL + and-not POLY + and-not PPLUS + and THKOX + copyup mvnsubcheck + + layer mvnsd mvnsdarea + labels DIFF + + layer mvnsd TAP,TAPPIN + and NPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvnsdexpand mvnsdarea + grow 500 + + # Copy nsub areas up for contact checks + templayer mvxnsubcheck mvnsubcheck + copyup mvnsubcheck + + templayer mvpsdarea DIFF + and PPLUS + and-not NWELL + and-not POLY + and-not NPLUS + and THKOX + and-not mvpfetexpand + copyup mvpsubcheck + + layer mvpsd mvpsdarea + labels DIFF + + layer mvpsd TAP,TAPPIN + and PPLUS + and THKOX + labels TAP + labels TAPPIN port + + templayer mvpsdexpand mvpsdarea + grow 500 + + # Copy psub areas up for contact checks + templayer xpsubcheck psubcheck + copyup psubcheck + + templayer mvxpsubcheck mvpsubcheck + copyup mvpsubcheck + + layer psd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and-not pfetexpand + and psdexpand + + layer nsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and-not THKOX + and nsdexpand + + layer mvpsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and-not mvpfetexpand + and mvpsdexpand + + layer mvnsd DIFF + and-not PPLUS + and-not NPLUS + and-not POLY + and THKOX + and mvnsdexpand + + templayer hresarea POLY + and RPM + grow 3000 + + templayer uresarea POLY + and URPM + grow 3000 + + templayer diffresarea DIFFRES + and-not THKOX + grow 3000 + + templayer mvdiffresarea DIFFRES + and THKOX + grow 3000 + + templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea + + layer pfet POLY + and DIFF + and diffresarea + and-not NPLUS + and-not STDCELL + + layer scpfet POLY + and DIFF + and diffresarea + and-not NPLUS + and STDCELL + + templayer xpolyterm RPM,URPM + and POLY + and-not POLYRES + # add back the 0.06um contact surround in the direction of the resistor + grow 60 + and POLY + + layer xpc xpolyterm + + templayer polyarea POLY + and-not POLYRES + and-not POLYSHORT + and-not DIFF + and-not RPM + and-not URPM + copyup polycheck + + layer poly polyarea,POLYTXT,POLYPIN + labels POLY + labels POLYTXT text + labels POLYPIN port + + # Copy (non-resistor) poly areas up for contact checks + templayer xpolycheck polycheck + copyup polycheck + + layer mrp1 POLY + and POLYRES + and-not RPM + and-not URPM + labels POLY + + layer rmp POLY + and POLYSHORT + labels POLY + + layer xhrpoly POLY + and POLYRES + and RPM + and-not URPM + and PPLUS + and NPC + and-not xpolyterm + labels POLY + + layer uhrpoly POLY + and POLYRES + and URPM + and-not RPM + and NPC + and-not xpolyterm + labels POLY + + templayer ndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and-not THKOX + + layer ndc ndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndcbase + labels CONT + + templayer nscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and-not THKOX + + layer nsc nscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nscbase + labels CONT + + templayer pdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and-not THKOX + + layer pdc pdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcbase + labels CONT + + templayer pdcnowell CONT + and DIFF + and PPLUS + and pfetexpand + and LI + and-not THKOX + + layer pdc pdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdcnowell + labels CONT + + templayer pscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not pfetexpand + and LI + and-not THKOX + + layer psc pscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pscbase + labels CONT + + templayer pcbase CONT + and POLY + and-not DIFF + and-not RPM,URPM + and LI + + layer pc pcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pcbase + labels CONT + + templayer ndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and-not LVTN + + layer ndic ndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndicbase + labels CONT + + templayer ndilvtcbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not THKOX + and LVTN + + layer ndilvtc ndilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndilvtcbase + labels CONT + + templayer pdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and-not HVTP + + layer pdic pdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdicbase + labels CONT + + templayer pdilvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and LVTN + and-not HVTP + + layer pdilvtc pdilvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdilvtcbase + labels CONT + + templayer pdihvtcbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and-not THKOX + and-not LVTN + and HVTP + + layer pdihvtc pdihvtcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdihvtcbase + labels CONT + + templayer mvndcbase CONT + and DIFF + and NPLUS + and-not NWELL + and LI + and THKOX + + layer mvndc mvndcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndcbase + labels CONT + + templayer mvnscbase CONT + and DIFF,TAP + and NPLUS + and NWELL + and LI + and THKOX + + layer mvnsc mvnscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnscbase + labels CONT + + templayer mvpdcbase CONT + and DIFF + and PPLUS + and NWELL + and LI + and THKOX + + layer mvpdc mvpdcbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcbase + labels CONT + + templayer mvpdcnowell CONT + and DIFF + and PPLUS + and mvpfetexpand + and MET1 + and THKOX + + layer mvpdc mvpdcnowell + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdcnowell + labels CONT + + templayer mvpscbase CONT + and DIFF,TAP + and PPLUS + and-not NWELL + and-not mvpfetexpand + and LI + and THKOX + + layer mvpsc mvpscbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpscbase + labels CONT + + templayer mvndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and-not LVTN + and THKOX + + layer mvndic mvndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndicbase + labels CONT + + templayer nndicbase CONT + and DIFF + and NPLUS + and DIODE + and-not POLY + and-not PPLUS + and LVTN + and THKOX + + layer nndic nndicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or nndicbase + labels CONT + + templayer mvpdicbase CONT + and DIFF + and PPLUS + and DIODE + and-not POLY + and-not NPLUS + and THKOX + + layer mvpdic mvpdicbase + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdicbase + labels CONT + + layer locali LI,LITXT,LIPIN + and-not LIRES,LISHORT + and-not COREID + labels LI + labels LITXT text + labels LIPIN port + + layer coreli LI,LITXT,LIPIN + and-not LIRES,LISHORT + and COREID + labels LI + labels LITXT text + labels LIPIN port + + layer rli LI + and LIRES,LISHORT + labels LIRES,LISHORT + + layer lic MCON + grow 95 + shrink 95 + shrink 85 + grow 85 + or MCON + labels MCON + + layer m1 MET1,MET1TXT,MET1PIN + and-not MET1RES,MET1SHORT + labels MET1 + labels MET1TXT text + labels MET1PIN port + + layer rm1 MET1 + and MET1RES,MET1SHORT + labels MET1RES,MET1SHORT + + layer mimcap MET3 + and CAPM + labels CAPM + + layer mimcc VIA3 + and CAPM + grow 60 + grow 40 + shrink 40 + labels CAPM + + layer mimcap2 MET4 + and CAPM2 + labels CAPM2 + + layer mim2cc VIA4 + and CAPM2 + grow 190 + grow 210 + shrink 210 + labels CAPM2 + + + templayer m2cbase VIA1 + grow 55 + + layer m2c m2cbase + grow 30 + shrink 30 + shrink 130 + grow 130 + or m2cbase + + layer m2 MET2,MET2TXT,MET2PIN + and-not MET2RES,MET2SHORT + labels MET2 + labels MET2TXT text + labels MET2PIN port + + layer rm2 MET2 + and MET2RES,MET2SHORT + labels MET2RES,MET2SHORT + + templayer m3cbase VIA2 + grow 40 + + layer m3c m3cbase + grow 60 + shrink 60 + shrink 140 + grow 140 + or m3cbase + + layer m3 MET3,MET3TXT,MET3PIN + and-not MET3RES,MET3SHORT + and-not CAPM + labels MET3 + labels MET3TXT text + labels MET3PIN port + + layer rm3 MET3 + and MET3RES,MET3SHORT + labels MET3RES,MET3SHORT + + + templayer via3base VIA3 + and-not CAPM + grow 60 + + layer via3 via3base + grow 40 + shrink 40 + shrink 160 + grow 160 + or via3base + + layer m4 MET4,MET4TXT,MET4PIN + and-not MET4RES,MET4SHORT + and-not CAPM2 + labels MET4 + labels MET4TXT text + labels MET4PIN port + + layer rm4 MET4 + and MET4RES,MET4SHORT + labels MET4RES,MET4SHORT + + layer m5 MET5,MET5TXT,MET5PIN + and-not MET5RES,MET5SHORT + labels MET5 + labels MET5TXT text + labels MET5PIN port + + layer rm5 MET5 + and MET5RES,MET5SHORT + labels MET5RES,MET5SHORT + + templayer via4base VIA4 + and-not CAPM2 + grow 190 + + layer via4 via4base + grow 210 + shrink 210 + shrink 590 + grow 590 + or via4base + + + # Find diffusion not covered in + # NPLUS or PPLUS and pull it into + # the next layer up + + templayer gentrans DIFF + and-not PPLUS + and-not NPLUS + and POLY + copyup DIFF,POLY + + templayer gendiff DIFF,TAP + and-not PPLUS + and-not NPLUS + and-not POLY + copyup DIFF + + # Handle contacts found by copyup + + templayer ndiccopy CONT + and LI + and DIODE + and NPLUS + and-not THKOX + + layer ndic ndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndiccopy + labels CONT + + templayer mvndiccopy CONT + and LI + and DIODE + and NPLUS + and THKOX + + layer mvndic mvndiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndiccopy + labels CONT + + templayer pdiccopy CONT + and LI + and DIODE + and PPLUS + and-not THKOX + + layer pdic pdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdiccopy + labels CONT + + templayer mvpdiccopy CONT + and LI + and DIODE + and PPLUS + and THKOX + + layer mvpdic mvpdiccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdiccopy + labels CONT + + templayer ndccopy CONT + and ndifcheck + + layer ndc ndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or ndccopy + labels CONT + + templayer mvndccopy CONT + and mvndifcheck + + layer mvndc mvndccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvndccopy + labels CONT + + templayer pdccopy CONT + and pdifcheck + + layer pdc pdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pdccopy + labels CONT + + templayer mvpdccopy CONT + and mvpdifcheck + + layer mvpdc mvpdccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpdccopy + labels CONT + + templayer pccopy CONT + and polycheck + + layer pc pccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or pccopy + labels CONT + + templayer nsccopy CONT + and nsubcheck + + layer nsc nsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or nsccopy + labels CONT + + templayer mvnsccopy CONT + and mvnsubcheck + + layer mvnsc mvnsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvnsccopy + labels CONT + + templayer psccopy CONT + and psubcheck + + layer psc psccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or psccopy + labels CONT + + templayer mvpsccopy CONT + and mvpsubcheck + + layer mvpsc mvpsccopy + grow 85 + shrink 85 + shrink 85 + grow 85 + or mvpsccopy + labels CONT + + # Find contacts not covered in + # metal and pull them into the + # next layer up + + templayer gencont CONT + and LI + and-not DIFF,TAP + and-not POLY + and-not DIODE + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT,LI + + templayer barecont CONT + and-not LI + and-not nsubcheck + and-not psubcheck + and-not mvnsubcheck + and-not mvpsubcheck + copyup CONT + + layer glass GLASS,PADTXT,PADPIN + labels GLASS + labels PADTXT text + labels PADPIN port + + templayer boundary BOUND,STDCELL,PADCELL + boundary + + layer comment LVSTEXT + labels LVSTEXT text + + layer comment TTEXT + labels TTEXT text + + layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4 + +# MOS Varactor + + layer var POLY + and DIFF + and NPLUS + and NWELL + and-not THKOX + and-not HVTP + grow 25 + labels POLY + + layer varhvt POLY + and DIFF + and NPLUS + and NWELL + and-not THKOX + and HVTP + grow 25 + labels POLY + + layer mvvar POLY + and DIFF + and NPLUS + and NWELL + and THKOX + grow 25 + labels POLY + + calma NWELL 64 20 + calma DIFF 65 20 + calma DNWELL 64 18 + calma PWRES 64 13 + calma TAP 65 44 + # LVTN + calma LVTN 125 44 + # HVTP + calma HVTP 78 44 + # SONOS (TUNM) + calma SONOS 80 20 + # NPLUS = NSDM + calma NPLUS 93 44 + # PPLUS = PSDM + calma PPLUS 94 20 + # HVI + calma THKOX 75 20 + # NPC + calma NPC 95 20 + # P+ POLY MASK + calma RPM 86 20 + calma URPM 79 20 + calma LDNTM 11 44 + calma HVNTM 125 20 + # Poly resistor ID mark + calma POLYRES 66 13 + # Diffusion resistor ID mark + calma DIFFRES 65 13 + calma POLY 66 20 + calma POLYMOD 66 83 + # Diode ID mark + calma DIODE 81 23 + # Bipolar NPN mark + calma NPNID 82 20 + # Bipolar PNP mark + calma PNPID 82 20 + # Capacitor ID + calma CAPID 82 64 + # Core area ID mark + calma COREID 81 2 + # Standard cell ID mark + calma STDCELL 81 4 + # Padframe cell ID mark + calma PADCELL 81 3 + # Seal ring ID mark + calma SEALID 81 1 + # Low tap density ID mark + calma LOWTAPDENSITY 81 14 + + # LICON + calma CONT 66 44 + calma LI 67 20 + calma MCON 67 44 + + calma MET1 68 20 + calma VIA1 68 44 + calma MET2 69 20 + calma VIA2 69 44 + calma MET3 70 20 + calma VIA3 70 44 + calma MET4 71 20 + calma VIA4 71 44 + calma MET5 72 20 + calma GLASS 76 20 + + calma SUBPIN 64 59 + calma PADPIN 76 5 + calma DIFFPIN 65 6 + calma TAPPIN 65 5 + calma WELLPIN 64 5 + calma LIPIN 67 5 + calma POLYPIN 66 5 + calma MET1PIN 68 5 + calma MET2PIN 69 5 + calma MET3PIN 70 5 + calma MET4PIN 71 5 + calma MET5PIN 72 5 + + calma LIRES 67 13 + calma MET1RES 68 13 + calma MET2RES 69 13 + calma MET3RES 70 13 + calma MET4RES 71 13 + calma MET5RES 72 13 + + calma POLYSHORT 66 15 + calma LISHORT 67 15 + calma MET1SHORT 68 15 + calma MET2SHORT 69 15 + calma MET3SHORT 70 15 + calma MET4SHORT 71 15 + calma MET5SHORT 72 15 + + calma SUBTXT 122 16 + calma PADTXT 76 16 + calma DIFFTXT 65 16 + calma POLYTXT 66 16 + calma WELLTXT 64 16 + calma LITXT 67 16 + calma MET1TXT 68 16 + calma MET2TXT 69 16 + calma MET3TXT 70 16 + calma MET4TXT 71 16 + calma MET5TXT 72 16 + + calma BOUND 235 4 + + calma LVSTEXT 83 44 + + calma CAPM 89 44 + calma CAPM2 97 44 + + calma FILLOBSM1 62 24 + calma FILLOBSM2 105 52 + calma FILLOBSM3 107 24 + calma FILLOBSM4 112 4 + +end + +#----------------------------------------------------- +# Digital flow maze router cost parameters +#----------------------------------------------------- + +mzrouter +end + +#----------------------------------------------------- +# Vendor DRC rules +#----------------------------------------------------- + +drc + + style drc variants (fast),(full),(routing) + + scalefactor 10 + + cifstyle drc + + variants (fast),(full) + +#----------------------------- +# DNWELL +#----------------------------- + + # ORIGINAL RULE: width dnwell 3000 "Deep N-well width < %d (Dnwell 2)" + width dnwell 3000 "Deep N-well width < %d (Dnwell 2) [paint dnwell]" + spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3) [erase dnwell]" + spacing dnwell allnwell 4500 surround_ok "Deep N-well spacing to N-well < %d (Nwell 7) [erase dnwell,nwell obswell]" + cifmaxwidth nwell_missing 0 bend_illegal \ + "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)" + cifmaxwidth dnwell_missing 0 bend_illegal \ + "SONOS nFET must be in Deep N-well (Tunm 6a)" + +#----------------------------- +# NWELL +#----------------------------- + + # ORIGINAL RULE: width allnwell 840 "N-well width < %d (Nwell 1)" + width allnwell 840 "N-well width < %d (Nwell 1) [paint nwell,obswell]" + spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a) [erase nwell obswell]" + +#----------------------------- +# DIFF +#----------------------------- + + width *ndiff,nfet,scnfet,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,*psd,*pdiode,pdiffres \ + 150 "Diffusion width < %d (Diff/tap 1)" + width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \ + "MV Diffusion width < %d (Diff/tap 14)" + # ORIGINAL RULE: width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)" + width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1) [paint mvnsubstratencontact,mvnsubstratendiff,mvpsubstratepcontact,mvpsubstratepdiff]" + extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)" + extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)" + extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)" + extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)" + # ORIGINAL RULE: width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)" + width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a) [paint mvpdiffres]" + spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok "Diffusion spacing < %d (Diff/tap 3) [erase ndcontact ndiffres ndiffusion ndiode ndiodec nfetlvt nsonos nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec pfethvt pfetlvt psubstratepcontact psubstratepdiff ptransistor scntransistor scptransistor varactor varactorhvt]" + spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok "MV Diffusion spacing < %d (Diff/tap 15a) [erase mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnntransistor mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvptransistor mvvaractor nndiode nndiodec]" + spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok "MV Diffusion to MV tap spacing < %d (Diff/tap 3) [erase mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor nndiode nndiodec,mvnsubstratencontact mvnsubstratendiff mvpsubstratepcontact mvpsubstratepdiff]" + spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b) [erase mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnntransistor mvntransistor mvvaractor nndiode nndiodec,mvpsubstratepcontact mvpsubstratepdiff]" + spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal "MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19) [erase mvnsubstratencontact mvnsubstratendiff mvpdcontact mvpdiffusion mvpdiode mvpdiodec mvptransistor mvvaractor,mvpsubstratepcontact mvpsubstratepdiff psubstratepcontact psubstratepdiff]" + spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal "N-Diffusion spacing to N-well < %d (Diff/tap 9) [erase ndcontact ndiffusion ndiode ndiodec ntransistor,nwell obswell]" + spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal "N-Diffusion spacing to N-well < %d (Diff/tap 9) [erase mvndcontact mvndiffusion mvndiode mvndiodec mvnntransistor mvntransistor,nwell obswell]" + spacing *psd allnwell 130 touching_illegal "P-tap spacing to N-well < %d (Diff/tap 11) [erase psubstratepcontact psubstratepdiff,nwell obswell]" + spacing *mvpsd allnwell 130 touching_illegal "P-tap spacing to N-well < %d (Diff/tap 11) [erase mvpsubstratepcontact mvpsubstratepdiff,nwell obswell]" + surround *nsd allnwell 180 absence_illegal "N-well overlap of N-tap < %d (Diff/tap 10) [erase nsubstratencontact nsubstratendiff,nwell obswell]" + surround *mvnsd allnwell 330 absence_illegal "N-well overlap of MV N-tap < %d (Diff/tap 19) [erase mvnsubstratencontact mvnsubstratendiff,nwell obswell]" + surround *pdiff,*pdiode,pfet,scpfet allnwell 180 absence_illegal "N-well overlap of P-Diffusion < %d (Diff/tap 8) [erase pdcontact pdiffusion pdiode pdiodec ptransistor scptransistor,nwell obswell]" + surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal "N-well overlap of P-Diffusion < %d (Diff/tap 17) [erase mvpdcontact mvpdiffusion mvpdiode mvpdiodec mvptransistor,nwell obswell]" + surround mvvar allnwell 560 absence_illegal "N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b) [erase mvvaractor,nwell obswell]" + spacing *mvndiode *mvndiode 1070 touching_ok "MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3) [erase mvndiode mvndiodec]" + + # Butting junction rules + edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction" + edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \ + "N-Diffusion to P-tap spacing < %d across butted junction" + edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction" + edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \ + "P-Diffusion to N-tap spacing < %d across butted junction" + + edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction" + edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \ + "MV N-Diffusion to MV P-tap spacing < %d across butted junction" + edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction" + edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \ + "MV P-Diffusion to MV N-tap spacing < %d across butted junction" + + variants (full) + + # Latchup rules + cifmaxwidth ptap_missing 0 bend_illegal \ + "N-diff distance to P-tap must be < 15.0um (LU 2)" + cifmaxwidth dptap_missing 0 bend_illegal \ + "N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)" + cifmaxwidth ntap_missing 0 bend_illegal \ + "P-diff distance to N-tap must be < 15.0um (LU 3)" + + variants * + +#----------------------------- +# POLY +#----------------------------- + + # ORIGINAL RULE: width allpoly 150 "Poly width < %d (Poly 1a)" + width allpoly 150 "Poly width < %d (Poly 1a) [paint mvnntransistor,mvntransistor,mvptransistor,mvvaractor,nfetlvt,npolyres,nsonos,ntransistor,pcontact,pfethvt,pfetlvt,polysilicon,ppolyres,ptransistor,rmp,scntransistor,scptransistor,varactor,varactorhvt,xpolycontact,xpolyres]" + spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2) [erase mvnntransistor mvntransistor mvptransistor mvvaractor nfetlvt npolyres nsonos ntransistor pcontact pfethvt pfetlvt polysilicon ppolyres ptransistor rmp scntransistor scptransistor varactor varactorhvt xpolycontact xpolyres]" + spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \ + "Poly spacing to Diffusion < %d (Poly 4a)" + spacing npres *nsd 480 touching_illegal "Poly resistor spacing to N-tap < %d (Poly 9) [erase npolyres,nsubstratencontact nsubstratendiff]" + overhang *ndiff,rndiff nfet,scnfet 250 "N-Diffusion overhang of nmos < %d (Poly 7)" + overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \ + "N-Diffusion overhang of nmos < %d (Poly 7)" + overhang *pdiff,rpdiff pfet,scpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)" + overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)" + overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)" + rect_only allfets "No bends in transistors (Poly 11)" + rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)" + extend xpc/a xhrpoly,uhrpoly 2160 \ + "Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)" + spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal "Distance between precision resistors < %d (RPM 2 + 2 * RPM 3) [erase ppolyres xpolyres]" + +#-------------------------------------------------------------------- +# NPC (Nitride Poly Cut) +#-------------------------------------------------------------------- + +# Layer NPC is defined automatically around poly contacts (grow 0.1um) + +#-------------------------------------------------------------------- +# CONT (LICON, contact between poly/diff and LI) +#-------------------------------------------------------------------- + + # ORIGINAL RULE: width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)" + width ndc/li 170 "N-diffusion contact width < %d (LIcon 1) [paint ndcontact/li]" + # ORIGINAL RULE: width nsc/li 170 "N-tap contact width < %d (LIcon 1)" + width nsc/li 170 "N-tap contact width < %d (LIcon 1) [paint nsubstratencontact/li]" + # ORIGINAL RULE: width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)" + width pdc/li 170 "P-diffusion contact width < %d (LIcon 1) [paint pdcontact/li]" + # ORIGINAL RULE: width psc/li 170 "P-tap contact width < %d (LIcon 1)" + width psc/li 170 "P-tap contact width < %d (LIcon 1) [paint psubstratepcontact/li]" + # ORIGINAL RULE: width ndic/li 170 "N-diode contact width < %d (LIcon 1)" + width ndic/li 170 "N-diode contact width < %d (LIcon 1) [paint ndiodec/li]" + # ORIGINAL RULE: width pdic/li 170 "P-diode contact width < %d (LIcon 1)" + width pdic/li 170 "P-diode contact width < %d (LIcon 1) [paint pdiodec/li]" + # ORIGINAL RULE: width pc/li 170 "Poly contact width < %d (LIcon 1)" + width pc/li 170 "Poly contact width < %d (LIcon 1) [paint pcontact/li]" + + # ORIGINAL RULE: width xpc/li 350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)" + width xpc/li 350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5) [paint xpolycontact/li]" + + # ORIGINAL RULE: width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)" + width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1) [paint mvndcontact/li]" + # ORIGINAL RULE: width mvnsc/li 170 "N-tap contact width < %d (LIcon 1)" + width mvnsc/li 170 "N-tap contact width < %d (LIcon 1) [paint mvnsubstratencontact/li]" + # ORIGINAL RULE: width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)" + width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1) [paint mvpdcontact/li]" + # ORIGINAL RULE: width mvpsc/li 170 "P-tap contact width < %d (LIcon 1)" + width mvpsc/li 170 "P-tap contact width < %d (LIcon 1) [paint mvpsubstratepcontact/li]" + # ORIGINAL RULE: width mvndic/li 170 "N-diode contact width < %d (LIcon 1)" + width mvndic/li 170 "N-diode contact width < %d (LIcon 1) [paint mvndiodec/li]" + # ORIGINAL RULE: width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)" + width mvpdic/li 170 "P-diode contact width < %d (LIcon 1) [paint mvpdiodec/li]" + + spacing allpdiffcont allndiffcont 170 touching_illegal "Diffusion contact spacing < %d (LIcon 2) [erase mvpdcontact mvpdiodec mvpsubstratepcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact,mvndcontact mvndiodec mvnsubstratencontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact]" + spacing allndiffcont allndiffcont 170 touching_ok "Diffusion contact spacing < %d (LIcon 2) [erase mvndcontact mvndiodec mvnsubstratencontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact]" + spacing allpdiffcont allpdiffcont 170 touching_ok "Diffusion contact spacing < %d (LIcon 2) [erase mvpdcontact mvpdiodec mvpsubstratepcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact]" + spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2) [erase pcontact]" + + spacing pc alldiff 190 touching_illegal "Poly contact spacing to diffusion < %d (LIcon 14) [erase pcontact,mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor ndcontact ndiffres ndiffusion ndiode ndiodec nfetlvt nndiode nndiodec nsonos nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec pfethvt pfetlvt psubstratepcontact psubstratepdiff ptransistor scntransistor scptransistor]" + spacing pc allpfets 235 touching_illegal "Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a) [erase pcontact,mvptransistor pfethvt pfetlvt ptransistor scptransistor]" + + spacing ndc,pdc nfet,pfet 55 touching_illegal "Diffusion contact to gate < %d (LIcon 11) [erase ndcontact pdcontact,ntransistor ptransistor]" + spacing ndc,pdc scnfet,scpfet 50 touching_illegal "Diffusion contact to standard cell gate < %d (LIcon 11) [erase ndcontact pdcontact,scntransistor scptransistor]" + spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal "Diffusion contact to gate < %d (LIcon 11) [erase mvndcontact mvpdcontact,mvnntransistor mvntransistor mvptransistor]" + spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d () [erase mvndcontact ndcontact,mvndiffres ndiffres]" + spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d () [erase mvpdcontact pdcontact,mvpdiffres pdiffres]" + spacing nsc varactor,varhvt 250 touching_illegal "Diffusion contact to varactor gate < %d (LIcon 10) [erase nsubstratencontact,varactor varactorhvt]" + spacing mvnsc mvvar 250 touching_illegal "Diffusion contact to varactor gate < %d (LIcon 10) [erase mvnsubstratencontact,mvvaractor]" + + surround ndc/a *ndiff,nfet,scnfet,nfetlvt 40 absence_illegal "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a) [erase ndcontact/a,ndcontact ndiffusion nfetlvt ntransistor scntransistor]" + surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 40 absence_illegal "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a) [erase pdcontact/a,pdcontact pdiffusion pfethvt pfetlvt ptransistor scptransistor]" + surround ndic/a *ndi 40 absence_illegal "N-diode overlap of N-diode contact < %d (LIcon 5a) [erase ndiodec/a,ndiode ndiodec]" + surround pdic/a *pdi 40 absence_illegal "P-diode overlap of N-diode contact < %d (LIcon 5a) [erase pdiodec/a,pdiode pdiodec]" + + surround ndc/a *ndiff,nfet,scnfet,nfetlvt 60 directional "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c) [erase ndcontact/a,ndcontact ndiffusion nfetlvt ntransistor scntransistor]" + surround pdc/a *pdiff,pfet,scpfet,pfethvt,pfetlvt 60 directional "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c) [erase pdcontact/a,pdcontact pdiffusion pfethvt pfetlvt ptransistor scptransistor]" + surround ndic/a *ndi 60 directional "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c) [erase ndiodec/a,ndiode ndiodec]" + surround pdic/a *pdi 60 directional "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c) [erase pdiodec/a,pdiode pdiodec]" + + surround nsc/a *nsd 120 directional "N-tap overlap of N-tap contact < %d in one direction (LIcon 7) [erase nsubstratencontact/a,nsubstratencontact nsubstratendiff]" + surround psc/a *psd 120 directional "P-tap overlap of P-tap contact < %d in one direction (LIcon 7) [erase psubstratepcontact/a,psubstratepcontact psubstratepdiff]" + + surround mvndc/a *mvndiff,mvnfet 40 absence_illegal "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a) [erase mvndcontact/a,mvndcontact mvndiffusion mvntransistor]" + surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a) [erase mvpdcontact/a,mvpdcontact mvpdiffusion mvptransistor]" + surround mvndic/a *mvndi 40 absence_illegal "N-diode overlap of N-diode contact < %d (LIcon 5a) [erase mvndiodec/a,mvndiode mvndiodec]" + surround mvpdic/a *mvpdi 40 absence_illegal "P-diode overlap of N-diode contact < %d (LIcon 5a) [erase mvpdiodec/a,mvpdiode mvpdiodec]" + + surround mvndc/a *mvndiff,mvnfet 60 directional "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c) [erase mvndcontact/a,mvndcontact mvndiffusion mvntransistor]" + surround mvpdc/a *mvpdiff,mvpfet 60 directional "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c) [erase mvpdcontact/a,mvpdcontact mvpdiffusion mvptransistor]" + surround mvndic/a *mvndi 60 directional "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c) [erase mvndiodec/a,mvndiode mvndiodec]" + surround mvpdic/a *mvpdi 60 directional "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c) [erase mvpdiodec/a,mvpdiode mvpdiodec]" + + surround mvnsc/a *mvnsd 120 directional "N-tap overlap of N-tap contact < %d in one direction (LIcon 7) [erase mvnsubstratencontact/a,mvnsubstratencontact mvnsubstratendiff]" + surround mvpsc/a *mvpsd 120 directional "P-tap overlap of P-tap contact < %d in one direction (LIcon 7) [erase mvpsubstratepcontact/a,mvpsubstratepcontact mvpsubstratepdiff]" + + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal "Poly overlap of poly contact < %d (LIcon 8) [erase pcontact/a,npolyres pcontact polysilicon ppolyres xpolyres]" + surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional "Poly overlap of poly contact < %d in one direction (LIcon 8a) [erase pcontact/a,npolyres pcontact polysilicon ppolyres xpolyres]" + + exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a + exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a + +#------------------------------------------------------------- +# LI - Local interconnect layer +#------------------------------------------------------------- + + # ORIGINAL RULE: width *li,rli 170 "Local interconnect width < %d (LI 1)" + width *li,rli 170 "Local interconnect width < %d (LI 1) [paint licon,locali,mvndcontact,mvndiodec,mvnsubstratencontact,mvpdcontact,mvpdiodec,mvpsubstratepcontact,ndcontact,ndiodec,ndiodelvtc,nndiodec,nsubstratencontact,pcontact,pdcontact,pdiodec,pdiodehvtc,pdiodelvtc,psubstratepcontact,rlocali,xpolycontact]" + # ORIGINAL RULE: width coreli 140 "Core local interconnect width < %d (LI c1)" + width coreli 140 "Core local interconnect width < %d (LI c1) [paint corelocali]" + spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (LI 3) [erase corelocali licon locali mvndcontact mvndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact pcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact rlocali xpolycontact,corelocali licon locali mvndcontact mvndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact obsli1 obslicon pcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact rlocali xpolycontact]" + spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (LI c2) [erase corelocali,corelocali licon locali mvndcontact mvndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact obsli1 obslicon pcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact rlocali xpolycontact]" + + surround pc/li *li 80 directional "Local interconnect overlap of poly contact < %d in one direction (LI 5) [erase pcontact/li,licon locali mvndcontact mvndiodec mvnsubstratencontact mvpdcontact mvpdiodec mvpsubstratepcontact ndcontact ndiodec ndiodelvtc nndiodec nsubstratencontact pcontact pdcontact pdiodec pdiodehvtc pdiodelvtc psubstratepcontact xpolycontact]" + + surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \ + *li,rli 80 directional \ + "Local interconnect overlap of diffusion contact < %d in one direction (LI 5)" + + area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)" + +#------------------------------------------------------------- +# MCON - Contact between local interconnect and metal1 +#------------------------------------------------------------- + + # ORIGINAL RULE: width lic/m1 170 "Mcon width < %d (Mcon 1)" + width lic/m1 170 "Mcon width < %d (Mcon 1) [paint licon/m1]" + spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2) [erase licon/m1,licon/m1 obslicon/m1]" + + exact_overlap lic/m1 + +#------------------------------------------------------------- +# METAL1 - +#------------------------------------------------------------- + + # ORIGINAL RULE: width *m1,rm1 140 "Metal1 width < %d (Met1 1)" + width *m1,rm1 140 "Metal1 width < %d (Met1 1) [paint licon,m2contact,metal1,padl,rmetal1]" + spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2) [erase licon m2contact metal1 padl rmetal1,licon m2contact metal1 obslicon obsm1 padl rmetal1]" + area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)" + + surround lic/m1 *met1 30 absence_illegal "Metal1 overlap of local interconnect contact < %d (Met1 4) [erase licon/m1,licon m2contact metal1 padl]" + surround lic/m1 *met1 60 directional "Metal1 overlap of local interconnect contact < %d in one direction (Met1 5) [erase licon/m1,licon m2contact metal1 padl]" + +variants (fast),(full) + widespacing allm1 3000 allm1,*obsm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)" + widespacing *obsm1 3000 allm1 280 touching_ok \ + "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)" + +variants (full) + cifmaxwidth m1_hole_empty 0 bend_illegal \ + "Min area of metal1 holes > 0.14um^2 (Met1 7)" +variants * + +#-------------------------------------------------- +# VIA1 +#-------------------------------------------------- + + # ORIGINAL RULE: width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)" + width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a) [paint m2contact/m1]" + spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a) [erase m2contact]" + surround v1/m1 *m1 30 directional "Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a) [erase m2contact/m1,licon m2contact metal1 padl]" + surround v1/m2 *m2 30 directional "Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4) [erase m2contact/m2,m2contact m3contact metal2 padl]" + + exact_overlap v1/m2 + +#-------------------------------------------------- +# METAL2 - +#-------------------------------------------------- + + # ORIGINAL RULE: width allm2 140 "Metal2 width < %d (Met2 1)" + width allm2 140 "Metal2 width < %d (Met2 1) [paint m2contact,m3contact,metal2,padl,rmetal2]" + spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (Met2 2) [erase m2contact m3contact metal2 padl rmetal2,m2contact m3contact metal2 obsm2 padl rmetal2]" + area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)" + +variants (fast),(full) + widespacing allm2 3000 allm2,obsm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)" + widespacing obsm2 3000 allm2 280 touching_ok \ + "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)" + +variants (full) + cifmaxwidth m2_hole_empty 0 bend_illegal \ + "Min area of metal2 holes > 0.14um^2 (Met2 7)" +variants * + +#-------------------------------------------------- +# VIA2 +#-------------------------------------------------- + + # ORIGINAL RULE: width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)" + width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4) [paint m3contact/m2]" + + spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4) [erase m3contact]" + + surround v2/m2 *m2 45 directional "Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4) [erase m3contact/m2,m2contact m3contact metal2 padl]" + surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4) [erase m3contact/m3,m3contact metal3 padl via3]" + + exact_overlap v2/m2 + +#-------------------------------------------------- +# METAL3 - +#-------------------------------------------------- + + # ORIGINAL RULE: width allm3 300 "Metal3 width < %d (Met3 1)" + width allm3 300 "Metal3 width < %d (Met3 1) [paint m3contact,metal3,padl,rmetal3,via3]" + spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (Met3 2) [erase m3contact metal3 padl rmetal3 via3,m3contact metal3 obsm3 padl rmetal3 via3]" + area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)" + +variants (fast),(full) + widespacing allm3 3000 allm3,obsm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)" + widespacing obsm3 3000 allm3 400 touching_ok \ + "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)" +variants * + + +#-------------------------------------------------- +# VIA3 - Requires 1 Module +#-------------------------------------------------- + + # ORIGINAL RULE: width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)" + width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4) [paint via3/m3]" + spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4) [erase via3]" + surround v3/m3 *m3 30 directional "Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4) [erase via3/m3,m3contact metal3 padl via3]" + surround v3/m4 *m4 5 absence_illegal "Metal4 overlap of Via3 < %d (Met4 3 - Via3 4) [erase via3/m4,metal4 mimcapcontact padl via3 via4]" + + exact_overlap v3/m3 + +#----------------------------- +# METAL4 - METAL4 Module +#----------------------------- + +variants * + + # ORIGINAL RULE: width allm4 300 "Metal4 width < %d (Met4 1)" + width allm4 300 "Metal4 width < %d (Met4 1) [paint metal4,mimcapcontact,padl,rmetal4,via3,via4]" + spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (Met4 2) [erase metal4 mimcapcontact padl rmetal4 via3 via4,metal4 mimcapcontact obsm4 padl rmetal4 via3 via4]" + area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)" + +variants (fast),(full) + widespacing allm4 3000 allm4,obsm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)" + widespacing obsm4 3000 allm4 400 touching_ok \ + "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)" +variants * + +#-------------------------------------------------- +# VIA4 - Requires 1 Module +#-------------------------------------------------- + + # ORIGINAL RULE: width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)" + width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4) [paint via4/m4]" + spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4) [erase via4]" + surround v4/m5 *m5 120 absence_illegal "Metal5 overlap of Via4 < %d (Met5 3 - Via4 4) [erase via4/m5,metal5 mimcap2contact padl via4]" + + exact_overlap v4/m4 + +#----------------------------- +# 1 - 1 Module +#----------------------------- + + # ORIGINAL RULE: width allm5 1600 "Metal5 width < %d (Met5 1)" + width allm5 1600 "Metal5 width < %d (Met5 1) [paint metal5,mimcap2contact,padl,rmetal5,via4]" + spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2) [erase metal5 mimcap2contact padl rmetal5 via4,metal5 mimcap2contact obsm5 padl rmetal5 via4]" + area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)" + + + +#-------------------------------------------------- +# NMOS, PMOS +#-------------------------------------------------- + + extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)" + # Except: Note that standard cells allow transistor width minimum 0.36um + # ORIGINAL RULE: width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)" + width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b) [paint pfetlvt]" + + spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal "N-tap spacing to field poly < %d (Poly 5) [erase mvnsubstratencontact mvnsubstratendiff nsubstratencontact nsubstratendiff,npolyres pcontact polysilicon ppolyres rmp xpolycontact xpolyres]" + spacing *psd,*mvpsd allpolynonfet 55 touching_illegal "P-tap spacing to field poly < %d (Poly 5) [erase mvpsubstratepcontact mvpsubstratepdiff psubstratepcontact psubstratepdiff,npolyres pcontact polysilicon ppolyres rmp xpolycontact xpolyres]" + + # Full edge rule required to describe FET to butted tap distance + edge4way *psd *ndiff 300 *ndiff *psd 300 \ + "Butting P-tap spacing to NMOS gate < %d (Poly 6)" + edge4way *nsd *pdiff 300 *pdiff *nsd 300 \ + "Butting N-tap spacing to PMOS gate < %d (Poly 6)" + edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \ + "Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)" + edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \ + "Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)" + + # No LV FETs in HV diff + spacing pfet,scpfet,pfetlvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal "LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22) [erase pdcontact pdiffusion pfethvt pfetlvt ptransistor scptransistor,mvpdcontact mvpdiffusion]" + + spacing nfet,scnfet,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal "LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22) [erase ndcontact ndiffusion nfetlvt ntransistor scntransistor varactor varactorhvt,mvndcontact mvndiffusion]" + + # No HV FETs in LV diff + spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal "MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22) [erase mvpdcontact mvpdiffusion mvptransistor,pdcontact pdiffusion]" + + spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal "MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22) [erase mvndcontact mvndiffusion mvntransistor mvvaractor,ndcontact ndiffusion]" + + # Minimum length of MV FETs. Note that this is larger than the minimum + # width (0.29um), so an edge rule is required + + edge4way mvndiff mvnfet 500 mvnfet 0 0 \ + "MV NMOS minimum length < %d (Poly 13)" + + edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \ + "MV Varactor minimum length < %d (Poly 13)" + + edge4way mvpdiff mvpfet 500 mvpfet 0 0 \ + "MV PMOS minimum length < %d (Poly 13)" + +#-------------------------------------------------- +# mrp1 (N+ poly resistor) +#-------------------------------------------------- + + # ORIGINAL RULE: width mrp1 330 "mrp1 resistor width < %d (Poly 3)" + width mrp1 330 "mrp1 resistor width < %d (Poly 3) [paint npolyres]" + +#-------------------------------------------------- +# xhrpoly (P+ poly resistor) +#-------------------------------------------------- + + # ORIGINAL RULE: width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)" + width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a) [paint ppolyres]" + # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27. + +#-------------------------------------------------- +# uhrpoly (P+ poly resistor, 2kOhm/sq) +#-------------------------------------------------- + + # ORIGINAL RULE: width uhrpoly 350 "uhrpoly resistor width < %d" + width uhrpoly 350 "uhrpoly resistor width < %d [paint xpolyres]" + spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal "xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9) [erase ppolyres xpolycontact xpolyres,mvndcontact mvndiffres mvndiffusion mvndiode mvndiodec mvnntransistor mvnsubstratencontact mvnsubstratendiff mvntransistor mvpdcontact mvpdiffres mvpdiffusion mvpdiode mvpdiodec mvpsubstratepcontact mvpsubstratepdiff mvptransistor ndcontact ndiffres ndiffusion ndiode ndiodec nfetlvt nndiode nndiodec nsonos nsubstratencontact nsubstratendiff ntransistor pdcontact pdiffres pdiffusion pdiode pdiodec pfethvt pfetlvt psubstratepcontact psubstratepdiff ptransistor scntransistor scptransistor]" + +#------------------------------------ +# MOS Varactor device rules +#------------------------------------ + + overhang *nsd var,varhvt 250 \ + "N-Tap overhang of Varactor < %d (Var 4)" + + overhang *mvnsd mvvar 250 \ + "N-Tap overhang of Varactor < %d (Var 4)" + + # ORIGINAL RULE: width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)" + width var,varhvt,mvvar 180 "Varactor length < %d (Var 1) [paint mvvaractor,varactor,varactorhvt]" + extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)" + +#----------------------------------------------------------- +# MiM CAP (CAPM) - +#----------------------------------------------------------- + + # ORIGINAL RULE: width *mimcap 2000 "MiM cap width < %d (Capm 1)" + width *mimcap 2000 "MiM cap width < %d (Capm 1) [paint mimcap,mimcapcontact]" + spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a) [erase mimcap mimcapcontact]" + spacing *mimcap via2/m3 1270 touching_illegal "MiM cap spacing to via2 < %d (Capm 5) [erase mimcap mimcapcontact,m3contact/m3]" + surround *mimcc *mimcap 200 absence_illegal "MiM cap must surround MiM cap contact by %d (Capm 4) [erase mimcapcontact,mimcap mimcapcontact]" + rect_only *mimcap "MiM cap must be rectangular (Capm 7) + + surround *mimcap *metal3/m3 140 absence_illegal "Metal3 must surround MiM cap by %d (Capm 3) [erase mimcap mimcapcontact,m3contact/m3 metal3/m3 padl/m3 via3/m3]" + spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8) [erase m3contact,mimcap mimcapcontact]" + spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8) [erase via3,mimcap mimcapcontact]" + # (resolve scaling issue!) + # cifspacing mim_bottom mim_bottom 1200 touching_ok \ + # "MiM cap bottom plate spacing < %d (Capm 2b)" + + # MiM cap contact rules (VIA3) + + # ORIGINAL RULE: width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)" + width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4) [paint mimcapcontact/m3]" + spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4) [erase mimcapcontact]" + surround mimcc/m4 *m4 5 directional "Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4) [erase mimcapcontact/m4,metal4 mimcapcontact padl via3 via4]" + exact_overlap mimcc/m3 + + # ORIGINAL RULE: width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)" + width *mimcap2 2000 "MiM cap width < %d (Cap2m 1) [paint mimcap2,mimcap2contact]" + spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a) [erase mimcap2 mimcap2contact]" + spacing *mimcap2 via3/m4 1270 touching_illegal "MiM cap spacing to via3 < %d (Cap2m 5) [erase mimcap2 mimcap2contact,via3/m4]" + surround *mim2cc *mimcap2 200 absence_illegal "MiM cap must surround MiM cap contact by %d (Cap2m 4) [erase mimcap2contact,mimcap2 mimcap2contact]" + rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7) + + surround *mimcap2 *metal4/m4 140 absence_illegal "Metal4 must surround MiM cap by %d (Cap2m 3) [erase mimcap2 mimcap2contact,metal4/m4 mimcapcontact/m4 padl/m4 via3/m4 via4/m4]" + spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8) [erase via3,mimcap2 mimcap2contact]" + spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8) [erase via4,mimcap2 mimcap2contact]" + # (resolve scaling issue!) + # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \ + # "MiM2 cap bottom plate spacing < %d (Cap2m 2b)" + + # MiM cap contact rules (VIA4) + + # ORIGINAL RULE: width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)" + width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4) [paint mimcap2contact/m4]" + spacing mim2cc mim2cc 420 touching_ok "MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4) [erase mimcap2contact]" + surround mim2cc/m5 *m5 120 absence_illegal "Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4) [erase mimcap2contact/m5,metal5 mimcap2contact padl via4]" + exact_overlap mim2cc/m4 + + +#---------------------------- +# End DRC style +#---------------------------- + +end + +#---------------------------- +# LEF format definitions +#---------------------------- + +lef + + masterslice pwell pwell PWELL substrate + masterslice nwell nwell NWELL + + routing li li1 LI1 LI li + + routing m1 met1 MET1 m1 + routing m2 met2 MET2 m2 + routing m3 met3 MET3 m3 + routing m4 met4 MET4 m4 + routing m5 met5 MET5 m5 + + cut lic mcon MCON Mcon + cut m2c via via1 VIA VIA1 cont2 via12 + cut m3c via2 VIA2 cont3 via23 + cut via3 via3 VIA3 cont4 via34 + cut via4 via4 VIA4 cont5 via45 + + obs obsli li1 + obs obsm1 met1 + obs obsm2 met2 + obs obsm3 met3 + + obs obsm4 met4 + obs obsm5 met5 + + obs obslic mcon + +end + +#----------------------------------------------------- +# Device and Parasitic extraction +#----------------------------------------------------- + + +extract + style ngspice variants (lvs),(sim),(si) + cscale 1 + # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all + # dimensions must be in units of microns in the extract file. + # Use extract style "ngspice(si)" to override this and produce + # a file with SI units for length/area. + + variants (lvs),(sim) + lambda 1E6 + variants (si) + lambda 1.0 + variants * + + units microns + step 7 + sidehalo 2 + + # NOTE: MiM cap layers have been purposely put out of order, + # may want to reconsider. + + planeorder dwell 0 + planeorder well 1 + planeorder active 2 + planeorder locali 3 + planeorder metal1 4 + planeorder metal2 5 + planeorder metal3 6 + planeorder metal4 7 + planeorder metal5 8 + planeorder block 9 + planeorder comment 10 + planeorder cap1 11 + planeorder cap2 12 + + height dnwell -0.1 0.1 + height nwell,pwell 0.0 0.2062 + height alldiff 0.2062 0.12 + height allpoly 0.3262 0.18 + height alldiffcont 0.3262 0.61 + height pc 0.5062 0.43 + height allli 0.9361 0.10 + height lic 1.0361 0.34 + height allm1 1.3761 0.36 + height v1 1.7361 0.27 + height allm2 2.0061 0.36 + height v2 2.3661 0.42 + height allm3 2.7861 0.845 + height v3 3.6311 0.39 + height allm4 4.0211 0.845 + height v4 4.8661 0.505 + height allm5 5.3711 1.26 + height mimcap 2.4661 0.2 + height mimcap2 3.7311 0.2 + height mimcc 2.6661 0.12 + height mim2cc 3.9311 0.09 + + # Antenna check parameters + # Note that checks w/diode diffusion are not modeled + model partial + antenna poly sidewall 50 none + antenna allcont surface 3 none + antenna li sidewall 75 0 450 + antenna lic surface 3 0 18 + antenna m1,m2,m3 sidewall 400 2600 400 + antenna v1 surface 3 0 18 + antenna v2 surface 6 0 36 + antenna m4,m5 sidewall 400 2600 400 + antenna v3,v4 surface 6 0 36 + + tiedown alldiffnonfet + + substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell + +# Layer resistance: Use document xp018-PDS-v4_2_1.pdf + +# Resistances are in milliohms per square +# Optional 3rd argument is the corner adjustment fraction +# Device values come from trtc.cor (typical corner) + resist (dnwell)/dwell 2200000 + resist (pwell)/well 3050000 + resist (nwell)/well 1700000 + resist (rpw)/well 3050000 0.5 + resist (*ndiff,nsd)/active 120000 + resist (*pdiff,*psd)/active 197000 + resist (*mvndiff,mvnsd)/active 114000 + resist (*mvpdiff,*mvpsd)/active 191000 + + resist ndiffres/active 120000 0.5 + resist pdiffres/active 197000 0.5 + resist mvndiffres/active 114000 0.5 + resist mvpdiffres/active 191000 0.5 + resist mrp1/active 48200 0.5 + resist xhrpoly/active 319800 0.5 + resist uhrpoly/active 2000000 0.5 + + resist (allpolynonres)/active 48200 + resist rmp/active 48200 + + resist (allli)/locali 12200 + resist (allm1)/metal1 125 + resist (allm2)/metal2 125 + resist (allm3)/metal3 47 + resist (allm4)/metal4 47 + resist (allm5)/metal5 29 + + contact ndc,nsc 15000 + contact pdc,psc 15000 + contact mvndc,mvnsc 15000 + contact mvpdc,mvpsc 15000 + contact pc 15000 + contact lic 152000 + contact m2c 4500 + contact m3c 3410 + contact mimcc 4500 + contact mim2cc 3410 + contact via3 3410 + contact via4 380 + +#------------------------------------------------------------------------- +# Parasitic capacitance values: Use document (...) +#------------------------------------------------------------------------- +# This uses the new "default" definitions that determine the intervening +# planes from the planeorder stack, take care of the reflexive sideoverlap +# definitions, and generally clean up the section and make it more readable. +# +# Also uses "units microns" statement. All values are taken from the +# document PEX/xRC/cap_models. Fringe capacitance values are approximated. +# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps. +#------------------------------------------------------------------------- +# Remember that device capacitances to substrate are taken care of by the +# models. Thus, active and poly definitions ignore all "fet" types. +# fet types are excluded when computing parasitic capacitance to +# active from layers above them because poly is a shield; fet types are +# included for parasitics from layers above to poly. Resistor types +# should be removed from all parasitic capacitance calculations, or else +# they just create floating caps. Technically, the capacitance probably +# should be split between the two terminals. Unsure of the correct model. +#------------------------------------------------------------------------- + +#n-well +# NOTE: This value not found in PEX files +defaultareacap nwell well 120 + +#n-active +# Rely on device models to capture *ndiff area cap +# Do not extract parasitics from resistors +# defaultareacap allnactivenonfet active 790 +# defaultperimeter allnactivenonfet active 280 + +#p-active +# Rely on device models to capture *pdiff area cap +# Do not extract parasitics from resistors +# defaultareacap allpactivenonfet active 810 +# defaultperimeter allpactivenonfet active 300 + +#poly +# Do not extract parasitics from resistors +# defaultsidewall allpolynonfet active 22 +# defaultareacap allpolynonfet active 106 +# defaultperimeter allpolynonfet active 57 + + defaultsidewall *poly active 23 + defaultareacap *poly active nwell,obswell,pwell well 106 + defaultperimeter *poly active nwell,obswell,pwell well 55 + +#locali + defaultsidewall allli locali 33 + defaultareacap allli locali nwell,obswell,pwell well 37 + defaultperimeter allli locali nwell,obswell,pwell well 55 + defaultoverlap allli locali nwell well 37 + +#locali->diff + defaultoverlap allli locali allactivenonfet active 37 + defaultsideoverlap allli locali allactivenonfet active 55 + +#locali->poly + defaultoverlap allli locali allpolynonres active 94 + defaultsideoverlap allli locali allpolynonres active 52 + defaultsideoverlap *poly active allli locali 25 + +#metal1 + defaultsidewall allm1 metal1 45 + defaultareacap allm1 metal1 nwell,obswell,pwell well 26 + defaultperimeter allm1 metal1 nwell,obswell,pwell well 41 + defaultoverlap allm1 metal1 nwell well 26 + +#metal1->diff + defaultoverlap allm1 metal1 allactivenonfet active 26 + defaultsideoverlap allm1 metal1 allactivenonfet active 41 + +#metal1->poly + defaultoverlap allm1 metal1 allpolynonres active 45 + defaultsideoverlap allm1 metal1 allpolynonres active 47 + defaultsideoverlap *poly active allm1 metal1 17 + +#metal1->locali + defaultoverlap allm1 metal1 allli locali 114 + defaultsideoverlap allm1 metal1 allli locali 59 + defaultsideoverlap allli locali allm1 metal1 35 + +#metal2 + defaultsidewall allm2 metal2 50 + defaultareacap allm2 metal2 nwell,obswell,pwell well 17 + defaultperimeter allm2 metal2 nwell,obswell,pwell well 41 + defaultoverlap allm2 metal2 nwell well 38 + +#metal2->diff + defaultoverlap allm2 metal2 allactivenonfet active 17 + defaultsideoverlap allm2 metal2 allactivenonfet active 41 + +#metal2->poly + defaultoverlap allm2 metal2 allpolynonres active 24 + defaultsideoverlap allm2 metal2 allpolynonres active 41 + defaultsideoverlap *poly active allm2 metal2 11 + +#metal2->locali + defaultoverlap allm2 metal2 allli locali 38 + defaultsideoverlap allm2 metal2 allli locali 46 + defaultsideoverlap allli locali allm2 metal2 22 + +#metal2->metal1 + defaultoverlap allm2 metal2 allm1 metal1 134 + defaultsideoverlap allm2 metal2 allm1 metal1 67 + defaultsideoverlap allm1 metal1 allm2 metal2 48 + +#metal3 + defaultsidewall allm3 metal3 63 + defaultoverlap allm3 metal3 nwell well 12 + defaultareacap allm3 metal3 nwell,obswell,pwell well 12 + defaultperimeter allm3 metal3 nwell,obswell,pwell well 41 + +#metal3->diff + defaultoverlap allm3 metal3 allactive active 12 + defaultsideoverlap allm3 metal3 allactive active 41 + +#metal3->poly + defaultoverlap allm3 metal3 allpolynonres active 16 + defaultsideoverlap allm3 metal3 allpolynonres active 44 + defaultsideoverlap *poly active allm3 metal3 9 + +#metal3->locali + defaultoverlap allm3 metal3 allli locali 21 + defaultsideoverlap allm3 metal3 allli locali 47 + defaultsideoverlap allli locali allm3 metal3 15 + +#metal3->metal1 + defaultoverlap allm3 metal3 allm1 metal1 35 + defaultsideoverlap allm3 metal3 allm1 metal1 55 + defaultsideoverlap allm1 metal1 allm3 metal3 27 + +#metal3->metal2 + defaultoverlap allm3 metal3 allm2 metal2 86 + defaultsideoverlap allm3 metal3 allm2 metal2 70 + defaultsideoverlap allm2 metal2 allm3 metal3 44 + +#metal4 + defaultsidewall allm4 metal4 67 +# defaultareacap alltopm metal4 well 6 + areacap allm4/m4 8 + defaultoverlap allm4 metal4 nwell well 8 + defaultperimeter allm4 metal4 well 37 + +#metal4->diff + defaultoverlap allm4 metal4 allactivenonfet active 8 + defaultsideoverlap allm4 metal4 allactivenonfet active 37 + +#metal4->poly + defaultoverlap allm4 metal4 allpolynonres active 10 + defaultsideoverlap allm4 metal4 allpolynonres active 38 + defaultsideoverlap *poly active allm4 metal4 6 + +#metal4->locali + defaultoverlap allm4 metal4 allli locali 12 + defaultsideoverlap allm4 metal4 allli locali 40 + defaultsideoverlap allli locali allm4 metal4 10 + +#metal4->metal1 + defaultoverlap allm4 metal4 allm1 metal1 15 + defaultsideoverlap allm4 metal4 allm1 metal1 43 + defaultsideoverlap allm1 metal1 allm4 metal4 16 + +#metal4->metal2 + defaultoverlap allm4 metal4 allm2 metal2 20 + defaultsideoverlap allm4 metal4 allm2 metal2 46 + defaultsideoverlap allm2 metal2 allm4 metal4 22 + +#metal4->metal3 + defaultoverlap allm4 metal4 allm3 metal3 84 + defaultsideoverlap allm4 metal4 allm3 metal3 71 + defaultsideoverlap allm3 metal3 allm4 metal4 43 + +#metal5 + defaultsidewall allm5 metal5 127 +# defaultareacap allm5 metal5 well 6 + areacap allm5/m5 6 + defaultoverlap allm5 metal5 nwell well 6 + defaultperimeter allm5 metal5 well 39 + +#metal5->diff + defaultoverlap allm5 metal5 allactivenonfet active 6 + defaultsideoverlap allm5 metal5 allactivenonfet active 39 + +#metal5->poly + defaultoverlap allm5 metal5 allpolynonres active 7 + defaultsideoverlap allm5 metal5 allpolynonres active 40 + defaultsideoverlap *poly active allm5 metal5 6 + +#metal5->locali + defaultoverlap allm5 metal5 allli locali 8 + defaultsideoverlap allm5 metal5 allli locali 41 + defaultsideoverlap allli locali allm5 metal5 8 + +#metal5->metal1 + defaultoverlap allm5 metal5 allm1 metal1 9 + defaultsideoverlap allm5 metal5 allm1 metal1 43 + defaultsideoverlap allm1 metal1 allm5 metal5 12 + +#metal5->metal2 + defaultoverlap allm5 metal5 allm2 metal2 11 + defaultsideoverlap allm5 metal5 allm2 metal2 46 + defaultsideoverlap allm2 metal2 allm5 metal5 16 + +#metal5->metal3 + defaultoverlap allm5 metal5 allm3 metal3 20 + defaultsideoverlap allm5 metal5 allm3 metal3 54 + defaultsideoverlap allm3 metal3 allm5 metal5 28 + +#metal5->metal4 + defaultoverlap allm5 metal5 allm4 metal4 68 + defaultsideoverlap allm5 metal5 allm4 metal4 83 + defaultsideoverlap allm4 metal4 allm5 metal5 47 + +# Devices: Use document (...) + +variants (sim) + + device msubcircuit pshort pfet,scpfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w + + device msubcircuit nshort nfet,scnfet *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device msubcircuit sonos_e nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w + device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w + device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w + device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w + + device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w + device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w + device msubcircuit nhvnative mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w + + device rsubcircuit short rmp *poly space/w,pwell,nwell error l=l w=w + device rsubcircuit short rli1 *li,coreli space/w,pwell,nwell error l=l w=w + device rsubcircuit short rmetal1 *metal1 space/w,pwell,nwell error l=l w=w + device rsubcircuit short rmetal2 *metal2 space/w,pwell,nwell error l=l w=w + device rsubcircuit short rmetal3 *metal3 space/w,pwell,nwell error l=l w=w + device rsubcircuit short rm4 *m4 space/w,pwell,nwell error l=l w=w + device rsubcircuit short rm5 *m5 space/w,pwell,nwell error l=l w=w + + device rsubcircuit xhrpoly xhrpoly xpc pwell,space/w error l=l w=w + device rsubcircuit uhrpoly uhrpoly xpc pwell,space/w error l=l w=w + device rsubcircuit mrp1 mrp1 *poly pwell,space/w error l=l w=w + + device rsubcircuit mrdn ndiffres *ndiff pwell,space/w error l=l w=w + device rsubcircuit mrdp pdiffres *pdiff nwell error l=l w=w + device rsubcircuit xpwres rpw pwell dnwell error l=l w=w + + device rsubcircuit mrdn_hv mvndiffres *mvndiff pwell,space/w error l=l w=w + device rsubcircuit mrdp_hv mvpdiffres *mvpdiff nwell error l=l w=w + + device subcircuit pdiode *pdiode nwell a=a p=p + device msubcircuit ndiode *ndiode pwell,space/w a=a p=p + device subcircuit pdiode_h *mvpdiode nwell a=a p=p + device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p + + # These are parasitic devices + device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=a p=p + device subcircuit pdiode_lvt *pdiodelvt nwell a=a p=p + device subcircuit pdiode_hvt *pdiodehvt nwell a=a p=p + device msubcircuit ndiode_native *nndiode pwell,space/w a=a p=p + + device subcircuit xcmimc1 *mimcap m3 nwell,pwell,space/w error a=a p=p s=subs + device subcircuit xcmimc2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=a p=p s=subs + + variants (lvs),(si) + + device mosfet pshort scpfet,pfet pdiff,pdiffres,pdc nwell + device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell + device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell + device mosfet nshort scnfet,nfet ndiff,ndiffres,ndc pwell,space/w + device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w + device mosfet sonos_e nsonos ndiff,ndiffres,ndc pwell,space/w + device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell + device mosfet nhv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w + device mosfet nhvnative mvnnfet *mvndiff,mvndiffres pwell,space/w + + # These devices always extract as subcircuits + device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w + device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w + device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w + + device resistor short rmp *poly + device resistor short rli1 *li,coreli + device resistor short rmetal1 *metal1 + device resistor short rmetal2 *metal2 + device resistor short rmetal3 *metal3 + device resistor short rm4 *m4 + device resistor short rm5 *m5 + + device resistor xhrpoly xhrpoly xpc + device resistor uhrpoly uhrpoly xpc + device resistor mrp1 mrp1 *poly + device resistor mrdn ndiffres *ndiff + device resistor mrdp pdiffres *pdiff + device resistor mrdn_hv mvndiffres *mvndiff + device resistor mrdp_hv mvpdiffres *mvpdiff + device resistor xpwres rpw pwell + + device pdiode pdiode *pdiode nwell a=a p=p + device ndiode ndiode *ndiode pwell,space/w a=a p=p + device pdiode pdiode_h *mvpdiode nwell a=a p=p + device ndiode ndiode_h *mvndiode pwell,space/w a=a p=p + + # These are parasitic devices + device ndiode ndiode_lvt *ndiodelvt pwell,space/w a=a p=p + device pdiode pdiode_lvt *pdiodelvt nwell a=a p=p + device pdiode pdiode_hvt *pdiodehvt nwell a=a p=p + device ndiode ndiode_native *nndiode pwell,space/w a=a p=p + + device subcircuit pdiode_h *mvpdiode nwell a=a p=p + device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p + + + device capacitor xcmimc1 *mimcap *m3 1 + device capacitor xcmimc2 *mimcap2 *m4 1 + +end + +#----------------------------------------------------- +# Wiring tool definitions +#----------------------------------------------------- + +wiring + # All wiring values are in nanometers + scalefactor 10 + + contact lic 170 li 0 0 m1 30 60 + contact v1 260 m1 0 30 m2 0 30 + contact v2 280 m2 0 45 m3 25 0 + contact v3 320 m3 0 30 m4 5 5 + contact v4 1180 m4 0 m5 120 + + contact pc 170 poly 50 80 li 0 80 + contact pdc 170 pdiff 40 60 li 0 80 + contact ndc 170 ndiff 40 60 li 0 80 + contact psc 170 psd 40 60 li 0 80 + contact nsc 170 nsd 40 60 li 0 80 + +end + +#----------------------------------------------------- +# Plain old router. . . +#----------------------------------------------------- + +router +end + +#------------------------------------------------------------ +# Plowing (restored in magic 8.2, need to fill this section) +#------------------------------------------------------------ + +plowing +end + +#----------------------------------------------------------------- +# No special plot layers defined (use default PNM color choices) +#----------------------------------------------------------------- + +plot + style pnm + default + draw fillblock no_color_at_all + draw nwell cwell +end + diff --git a/Tech.SKY130/nmos.sp b/Tech.SKY130/nmos.sp new file mode 100644 index 00000000..5dcab40a --- /dev/null +++ b/Tech.SKY130/nmos.sp @@ -0,0 +1 @@ +w=0.420u l=0.150u diff --git a/Tech.SKY130/pmos.sp b/Tech.SKY130/pmos.sp new file mode 100644 index 00000000..f1fc5c3c --- /dev/null +++ b/Tech.SKY130/pmos.sp @@ -0,0 +1 @@ +w=0.840u l=0.150u diff --git a/Tech.SKY130/template.lef b/Tech.SKY130/template.lef new file mode 100755 index 00000000..d0c6b4fc --- /dev/null +++ b/Tech.SKY130/template.lef @@ -0,0 +1,177 @@ +# LEF file generated by lefgen from LibreSilicon version 0.1 +# + +VERSION 5.4 ; +NAMESCASESENSITIVE ON ; +BUSBITCHARS "[]" ; +DIVIDERCHAR "/" ; +UNITS + DATABASE MICRONS 1000 ; +END UNITS + +USEMINSPACING OBS ON ; +USEMINSPACING PIN OFF ; +CLEARANCEMEASURE EUCLIDEAN ; + + +MANUFACTURINGGRID 0.15 ; + +LAYER nwell + TYPE MASTERSLICE ; +END nwell + +LAYER nactive + TYPE MASTERSLICE ; +END nactive + +LAYER pactive + TYPE MASTERSLICE ; +END pactive + +LAYER poly + TYPE MASTERSLICE ; +END poly + +LAYER cc + TYPE CUT ; + SPACING 0.9 ; +END cc + +LAYER metal1 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 3.2e-05 ; +END metal1 + +LAYER via + TYPE CUT ; + SPACING 0.9 ; +END via + +LAYER metal2 + TYPE ROUTING ; + DIRECTION VERTICAL ; + PITCH 2.4 ; + OFFSET 1.2 ; + WIDTH 0.9 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.09 ; + CAPACITANCE CPERSQDIST 1.6e-05 ; +END metal2 + +LAYER via2 + TYPE CUT ; + SPACING 0.9 ; +END via2 + +LAYER metal3 + TYPE ROUTING ; + DIRECTION HORIZONTAL ; + PITCH 3 ; + OFFSET 1.5 ; + WIDTH 1.5 ; + SPACING 0.9 ; + RESISTANCE RPERSQ 0.05 ; + CAPACITANCE CPERSQDIST 1e-05 ; +END metal3 + +SPACING + SAMENET cc via 0.150 ; + SAMENET via via2 0.150 ; +END SPACING + +VIA M2_M1 DEFAULT + LAYER metal1 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; +END M2_M1 + +VIA M3_M2 DEFAULT + LAYER metal2 ; + RECT -0.600 -0.600 0.600 0.600 ; + LAYER via2 ; + RECT -0.300 -0.300 0.300 0.300 ; + LAYER metal3 ; + RECT -0.900 -0.900 0.900 0.900 ; +END M3_M2 + + +VIARULE viagen21 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.3 ; + METALOVERHANG 0 ; + LAYER via ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 1.5 BY 1.5 ; +END viagen21 + +VIARULE viagen32 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + WIDTH 1.8 TO 180 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER metal2 ; + DIRECTION VERTICAL ; + WIDTH 1.2 TO 120 ; + OVERHANG 0.6 ; + METALOVERHANG 0 ; + LAYER via2 ; + RECT -0.3 -0.3 0.3 0.3 ; + SPACING 2.1 BY 2.1 ; +END viagen32 + +VIARULE TURN1 GENERATE + LAYER metal1 ; + DIRECTION HORIZONTAL ; + LAYER metal1 ; + DIRECTION VERTICAL ; +END TURN1 + +VIARULE TURN2 GENERATE + LAYER metal2 ; + DIRECTION HORIZONTAL ; + LAYER metal2 ; + DIRECTION VERTICAL ; +END TURN2 + +VIARULE TURN3 GENERATE + LAYER metal3 ; + DIRECTION HORIZONTAL ; + LAYER metal3 ; + DIRECTION VERTICAL ; +END TURN3 + +SITE corner + CLASS PAD ; + SYMMETRY R90 Y ; + SIZE 300.000 BY 300.000 ; +END corner + +SITE IO + CLASS PAD ; + SYMMETRY Y ; + SIZE 90.000 BY 300.000 ; +END IO + +SITE core + CLASS CORE ; + SYMMETRY Y ; + SIZE 2.400 BY 30.000 ; +END core + diff --git a/Technology/spice/ls1unmos.mod b/Technology/spice/ls1unmos.mod new file mode 100644 index 00000000..e227089c --- /dev/null +++ b/Technology/spice/ls1unmos.mod @@ -0,0 +1,15 @@ +* +* Long channel models from CMOS Circuit Design, Layout, and Simulation, +* Level=3 models VDD=5V, see CMOSedu.com +* +.MODEL NMOS4 NMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5 ++ PHI = 0.7 VTO = 0.8 DELTA = 3.0 ++ UO = 650 ETA = 3.0E-6 THETA = 0.1 ++ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3 ++ RSH = 0 NFS = 1E12 TPG = 1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 + diff --git a/Technology/spice/ls1upmos.mod b/Technology/spice/ls1upmos.mod new file mode 100644 index 00000000..7390c5b6 --- /dev/null +++ b/Technology/spice/ls1upmos.mod @@ -0,0 +1,14 @@ +* +* Long channel models from CMOS Circuit Design, Layout, and Simulation, +* Level=3 models VDD=5V, see CMOSedu.com +* +.MODEL PMOS4 PMOS LEVEL = 3 ++ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6 ++ PHI = 0.7 VTO = -0.9 DELTA = 0.1 ++ UO = 250 ETA = 0 THETA = 0.1 ++ KP = 40E-6 VMAX = 5E4 KAPPA = 1 ++ RSH = 0 NFS = 1E12 TPG = -1 ++ XJ = 500E-9 LD = 100E-9 ++ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 ++ CJ = 400E-6 PB = 1 MJ = 0.5 ++ CJSW = 300E-12 MJSW = 0.5 diff --git a/Tools/caravel/cells.pl b/Tools/caravel/cells.pl new file mode 100755 index 00000000..fc7b34d8 --- /dev/null +++ b/Tools/caravel/cells.pl @@ -0,0 +1,84 @@ +#!/usr/bin/perl -w + +# Generates the Verilog code for a single caravel userspace module + +my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; + + + +print <) +{ + next if((-s $mag)<=50); + #print `ls -la $mag`; + my $cell=$mag; $cell=~s/\.mag$/.cell/; $cell=~s/\/mag\//\/cell\//; + my $lib=$mag; $lib=~s/\.mag$/.lib/; $lib=~s/\/mag\//\/lib\//; + my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/); + next unless(-f $cell); + #next unless(-f $lib); + #next unless(-f $ENV{'CARAVEL'}."/cells/mag/$name.mag"); + + open CELL,"<$cell"; + print "module $name(\n"; + + my $counter=0; + while() + { + if(m/^\.inputs (.*)/) + { + foreach my $inp(sort split " ",$1) + { + my $io=$nextio++; + print " ".($counter?",":"")."inout $inp // input $io\n"; + $counter++; + } + } + if(m/^\.outputs (.*)/) + { + foreach my $outp(sort split " ",$1) + { + my $io=$nextio++; + print " ".($counter?",":"")."inout $outp // output $io\n"; + $counter++; + } + } + + } + close CELL; + print " \`ifdef USE_POWER_PINS\n"; + if($ENV{'PDK'}=~m/^gf180mcu/i) + { + print " ,inout vdd // cell power supply\n"; + print " ,inout vss // cell ground supply\n"; + } + elsif($ENV{'PDK'}=~m/^sky130/i) + { + print " ,inout VPWR // cell power supply\n"; + print " ,inout VGND // cell ground supply\n"; + } + else + { + print STDERR "WARNING: Environment variable \$PDK is not defined, therefore we can only guess the names of the power pins to be vdd/vss!\n"; + print " ,inout vdd // cell power supply\n"; + print " ,inout vss // cell ground supply\n"; + } + print " \`endif\n"; + print ");\n"; + print "endmodule\n\n"; +} + diff --git a/Tools/caravel/configgen.pl b/Tools/caravel/configgen.pl new file mode 100755 index 00000000..6a257083 --- /dev/null +++ b/Tools/caravel/configgen.pl @@ -0,0 +1,74 @@ +#!/usr/bin/perl -w +use strict; + +# Generates the configuration file for a single Caravel user space + +my $lefs=join("\",\"",map { $ENV{'PWD'}."/".$_ } ); +my $gds =join("\",\"",map { $ENV{'PWD'}."/".$_ } ); +my $libs=join("\",\"",map { $ENV{'PWD'}."/".$_ } ); +my $verilog=$ENV{'PWD'}."/verilog/rtl/user_proj_cells.v"; +# "EXTRA_LIBS": ["dir::../../cells/lib/libres*.lib"], +# +print STDERR "lefs: $lefs\ngds: $gds\nlibs: $libs\nverilog: $verilog\n"; + +#"CLOCK_TREE_SYNTH": 0, + +print </dev/null + +echo "Cleaning up old files" +rm -f $CARAVEL/cells/lib/*.lib $CARAVEL/cells/lef/orig/*.lef $CARAVEL/cells/lef/*.lef $CARAVEL/cells/gds/*.gds $CARAVEL/cells/mag/*.mag + +cd $STDCELLLIB/Catalog + +# The DRC Expander and the DRC Fixer need to run earlier in the StdCellLib instead, this would be too late: +#perl $CARAVEL/scripts/drcexpander.pl $PDK_ROOT/sky130A/libs.tech/magic/sky130A.tech >$CARAVEL/sky130Aexpanded.tech +#perl ../Tools/perl/drcfixall.pl $CARAVEL/sky130Aexpanded.tech + +echo "Copying files that were created by StdCellLib" +cp *.mag $CARAVEL/cells/mag/ +cp *.lib $CARAVEL/cells/lib/ +cp *.cell $CARAVEL/cells/cell/ +cp *.sp $CARAVEL/cells/sp/ +cp outputlib/*.lef $CARAVEL/cells/lef/orig/ +cp outputlib/*.gds $CARAVEL/cells/gds/ +rm $CARAVEL/cells/mag/demoboard.mag + +echo "Removing cells with DRC issues left" +cd $CARAVEL/cells/mag +rm -f corr.*.mag +perl $CARAVEL/scripts/removeDRCcells.pl + +echo "Now cleaning up the files for Sky130" +cd $CARAVEL/cells/lef +perl fixup.pl + +cd $CARAVEL/cells/mag +perl fixup.pl + +cd $CARAVEL/cells/sp +perl fixup.pl + +cd $CARAVEL/cells/lib +rm -f libresilicon.lib new.lib +libertymerge -b $STDCELLLIB/Catalog/libresilicon.libtemplate -o libresilicon.lib -u *.lib +perl removenl.pl >new.lib +mv new.lib libresilicon.lib + +echo "Now generating the demo wafer, the macro placement and the test-bench" + +perl $CARAVEL/scripts/generator.pl >$CARAVEL/verilog/rtl/user_proj_example.v +perl $CARAVEL/scripts/cells.pl >$CARAVEL/verilog/rtl/user_proj_cells.v +perl $CARAVEL/scripts/placement.pl >$CARAVEL/openlane/user_proj_example/macro_placement.cfg + +cd $CARAVEL +#bash my.sh +echo "Now building the Caravel user-project" +make user_proj_example && make user_project_wrapper + + +echo "Now we should git submit ..." + +echo "Deployment done."; diff --git a/Tools/caravel/drcexpander.pl b/Tools/caravel/drcexpander.pl new file mode 100755 index 00000000..997be2c5 --- /dev/null +++ b/Tools/caravel/drcexpander.pl @@ -0,0 +1,374 @@ +print STDERR "DRC Expander - expands the DRC rules in MAGIC tech files and annotates the layers that might cause the DRC issues\n"; + +# Original tech file: +my $tech=$ARGV[0] || "/usr/local/lib/magic/sys/sky130A.tech"; +my $expand=0; +my $debug=0; +my $createrules=0; # Create code for rules instead of expanding the tech file + +print STDERR "Processing the original tech file: $tech\n"; + +#our %contacts=(); +our %alias=(); + +# Required DRC rules for SKY130: area,cifmaxwidth,edge4way,exact_overlap,extend,overhang,rect_only,spacing,surround,width +my $rules=< \$l$_\n\" if(\$debug);\n" if($types[$_] eq "type-list"); + print " my \$text=\$$_;\n" if($types[$_] eq "why"); + push @typelists,$_ if($types[$_] eq "type-list"); + } + print " print \" "; + foreach(1 .. scalar(@types)-1) + { + print "\$$_ " if($types[$_] eq "other"); + print "\$vl$_ " if($types[$_] eq "type-list"); + if($types[$_] eq "why") + { + print "\\\"\$$_ "; + #print "[erase ".join(",",@typelists)."]"; + foreach my $tl (@typelists) + { + print "[erase \$l$tl]"; + } + print "\\\""; + } + } + print "\\n\";\n"; + print " }\n"; + print "\n"; + # $1 $vl1 $vl2 $4 $5 \"$6 [erase $l1]".(($vl1 eq $vl2)?"":"[erase $l2]")."\"\n"; + + +} + +exit if($createrules); + +#magic: tech layers allli +# At first we are reading through the original tech file to search for all the virtual layers that need to be expanded +open IN,"<$tech"; +undef $/; +my $content=; +$/="\n"; +$content=~s/\\\n//sg; + +foreach(split("\n",$content)) +{ + s/\\//g; + if(m/^\s*(spacing|surround)\s+(\S+)\s+(\S+)\s+/) + { + my $a2=$2; + my $a3=$3; + $alias{$a2}=1; + $alias{$a3}=1; + foreach(split(",",$a2)) + { + $alias{$_}=1; + $alias{$1}=1 if(m/^([^\/]+)/); + } + foreach(split(",",$a3)) + { + $alias{$_}=1; + $alias{$1}=1 if(m/^([^\/]+)/); + } + } + # Rule: width type-list width error + if(m/^\s*(width)\s+(\S+)\s+(\S+)\s+"([^"]*)"\s*$/) + { + $alias{$2}=1; + foreach(split(",",$2)) + { + $alias{$_}=1; + } + } +} +close IN; + + +if($debug) +{ + print STDERR "BEFORE:\n"; + foreach(sort keys %alias) + { + print STDERR "$_ -> $alias{$_}\n"; + } +} + +# No we are asking magic what those virtual layers actually mean + print STDERR "Running magic -T $tech ...\n"; + if(open OUT,"|magic -dnull -noconsole -T $tech >magic.layers.out") + { + print OUT "puts \"CUT HERE -------- CUT HERE\"\n"; + foreach(sort keys %alias) + { + s/\(// unless(m/\)/); + s/\)// unless(m/\(/); + #print STDERR "[tech layers $_]\n"; + print OUT "puts \"EXPANDING: $_\"\n"; + print OUT "puts [tech layers $_]\n"; + } + print OUT "puts \"CUT HERE -------- CUT HERE\"\n"; + print OUT "quit -noprompt\n"; + close OUT; + + # Now we are retrieving the answer from Magic: + if(open IN,") + { + if(m/^EXPANDING: (\S+)/) + { + my $next=; + chomp $next; + $alias{$1}=$next; + } + } + close IN; + } + else + { + die "Could not get the results from magic!\n"; + } + } + else + { + die "Could not run magic!\n"; + } + print STDERR "Done with magic.\n"; + + +if($debug) +{ + print STDERR "\n\nAFTER:\n"; + foreach(sort keys %alias) + { + print STDERR "$_ -> $alias{$_}\n"; + } + exit; +} + +open IN,"<$tech"; + +# This function expands a single layer-list into all the physical layers it means +sub allLayers($) +{ + #if($_[0] !~ m/\//) # If we do not look for "images" (which are signalled by / in the typelist and are currently not supported by magic), then we can just use the whole typelist which is more efficient. + #{ + #return split " ",$alias{$_[0]} ; + #} + + my @a=split ",",$_[0]; + my %b=(); + foreach(@a) + { + print STDERR "piece: $_\n" if($debug); + if(m/(\/\S+)/ && defined($alias{$_}) && $alias{$_}) + { + print STDERR "WE FOUND A SLASH AND AN ALIAS\n" if($debug); + my $image=$1; + foreach my $part(split " ",$alias{$_}) + { + print STDERR "PART: $part\n" if($debug); + $b{$part.(($part =~ m/\//)?"":$image)}=1; + } + } + elsif(m/^([^\/]+)(\/\S+)/) # This is a workaround for bugs in magic that hopefully get fixed + { + print STDERR "WE FOUND A SLASH BUT NO ALIAS\n" if($debug); + my $image=$2; + my $short=$1; + foreach my $part(split " ",$alias{$short}) + { + print STDERR "PART: $part\n" if($debug); + $b{$part.$image}=1; + } + } + else + { + print STDERR "NO SLASH OR ALIAS\n" if($debug); + foreach my $part(split " ",$alias{$_}) + { + $b{$part}=1; + } + } + } + return sort keys %b; +} + +my $section=""; +our %drckind=(); +# Finally we are processing the whole tech file and annotating the rules: +while() +{ + while($_=~m/\\$/) + { + $_.=; + } + if(m/^(\w+)/) + { + $section=$1; + } + # if($section eq "contact" && m/^\s+(\w+)/) + #{ + # my $a=$_; + # $a=~s/^\s+//; $a=~s/\s+$//; + # my @a=split(/\s+/,$a); + # my $cont=shift(@a); + # foreach my $cnt(@a) + # { + # print STDERR "CONTACT: $cont -> $cnt\n"; + # $contacts{$cont}{$cnt}=1; + # $contacts{$cnt}{$cont}=1; + # } + #} + #if($section eq "aliases" && m/^\s+(\w+)/) + #{ + # my $a=$_; + # $a=~s/^\s+//; $a=~s/\s+$//; + # my @a=split(/\s+/,$a); + # my $cont=shift(@a); + # foreach my $cnt(@a) + # { + # print STDERR "ALIAS: $cont -> $cnt\n"; + # $alias{$cont}=$cnt; + # } + #} + my $oneline=$_; + $oneline=~s/\n//sg; + tr/\\//; + if($section eq "drc") + { + if(m/^\s*(\w+)/) + { + $drckind{$1}=1; + } + } + + + if(m/^\s*(spacing|surround)\s+(\S+)\s+(\S+)\s+(\d+)\s+\\?\s*(\w+)\s+\\?\s*"([^"]+)"/) + { + #print " # ORIGINAL RULE:$oneline\n"; + my $vl1=$2; + my $vl2=$3; + my $text=$6; + my $l1=join " ",allLayers($vl1); + print STDERR "L1: $vl1 -> $l1\n" if($debug); + my $l2=join " ",allLayers($vl2); + print STDERR "L2: $vl2 -> $l2\n" if($debug); + + if($expand) + { + foreach my $layer1(allLayers($vl1)) + { + foreach my $layer2(allLayers($vl2)) + { + #print " $1 $layer1 $layer2 $4 $5 \"$6 [erase $layer1]".(($layer1 eq $layer2)?"":"[erase $layer2]")."\"\n"; + } + } + } + else + { + print " $1 $vl1 $vl2 $4 $5 \"$6 [erase $l1".(($vl1 eq $vl2)?"":",$l2")."]\"\n"; + } + #print "\n"; + } + # Rule: width type-list width error + elsif(m/^\s*(width)\s+(\S+)\s+(\S+)\s+"([^"]*)"\s*$/) + { + print " # ORIGINAL RULE:$oneline\n"; + my $vl2=$2; + print STDERR "ALLLAYERS $vl2\n" if($debug); + my $l2=join ",",allLayers($vl2); # For painting we need a different strategy to try each layer individually + print STDERR "INFO: vl2=$vl2 l2=$l2\n" if($debug); + my $text=$4; + print " $1 $vl2 $3 \"$4 [paint $l2]\"\n"; + } + + + else + { + print $_; + } +} +close IN; + +print STDERR "".join(",", sort keys %drckind)."\n"; diff --git a/Tools/caravel/feedback2mag.pl b/Tools/caravel/feedback2mag.pl new file mode 100755 index 00000000..9b4d689c --- /dev/null +++ b/Tools/caravel/feedback2mag.pl @@ -0,0 +1,32 @@ +print STDERR "Convert feedback to a .mag file\n"; +my $example=<>\n"; +while() +{ + if(m/box (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) + { + print "rect ".int($1/1)." ".int($2/1)." ".int($3/1)." ".int($4/1)."\n"; + } + if(m/(\d+\.?\d*)um (\d+\.?\d*)um (\d+\.\d*)um (\d+\.?\d*)um/) + { + print "rect ".int($1*200)." ".int($2*200)." ".int($3*200)." ".int($4*200)."\n"; + } +} +print "<< end >>\n"; diff --git a/Tools/caravel/fixup_lef.pl b/Tools/caravel/fixup_lef.pl new file mode 100755 index 00000000..06a0e9c4 --- /dev/null +++ b/Tools/caravel/fixup_lef.pl @@ -0,0 +1,150 @@ +#!/usr/bin/perl -w +use strict; + +print STDERR "Fixing up .LEF files\n"; + +my $magictech=$ARGV[0] || "sky130A"; + +my %layersToDo=("li1"=>1,"mcon"=>1,"locali"=>1,"metal1"=>1); + + + +sub readfile($) +{ + if(open MYRIN,"<$_[0]") + { + my $old=$/; + undef $/; + my $content=; + close MYRIN; + $/=$old; + return $content; + } + return undef; +} + + +foreach my $origlef () +{ + my $lef=$origlef; $lef=~s/^orig\///; + my $mag="../mag/$lef"; $mag=~s/\.lef$/\.mag/; + print STDERR "origlef: $origlef\n lef: $lef\n mag:$mag\n"; + my $obs=""; + + + + if(open(MAGIN,"<$mag")) + { + print "Extracting Obstruction information from $mag\n"; + my $active=0; + my $factor=100.0; + while() + { + if(m/magscale (\d+) (\d+)/) + { + $factor=100.0*$2; + } + if(m/<< (\w+) >>/) + { + $active=defined($layersToDo{$1}); + $obs.=" LAYER $1 ;\n" if($active); + } + if(m/rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/ && $active) + { + $obs.=" RECT ( ".($1/$factor)." ".($2/$factor)." ) ( ".($3/$factor)." ".($4/$factor)." ) ;\n"; + } + } + close MAGIN; + } + else + { + print "ERROR: Could not open magic file $mag : $!\n"; + } + + #print "$mag\n$obs\n"; + #next; + + my $content=readfile("orig/$lef"); + $content=~s/\sOBS\s.*?\sEND\s//sg; + open OUT,">$lef.temp"; + print OUT $content; + close OUT; + + my $cell=$lef; $cell=~s/\.lef//; + print "$lef\n"; + # open LEFIN,"$lef"; + our $pin=""; + my $filled=0; + our $macro="NOTTOBEFOUND"; + + #print "$obs\n"; + foreach(split "\n",$content) # while() + { + $_.="\n"; + $macro=$1 if(m/MACRO\s+(\w+)/); + $pin=$1 if(m/PIN\s+(\w+)/); + #s/SYMMETRY X Y R90/SITE unit/; + #s/SITE CORE/SYMMETRY X Y R90/; + #s/SITE unit.*//; + s/metal2/met1/; + s/VDD/VPWR/; + s/GND/VGND/; + s/USE SIGNAL/USE POWER/ if($pin eq "VDD" || $pin eq "VPWR"); + s/USE POWER/USE GROUND/ if($pin eq "GND" || $pin eq "VGND"); # GND braucht USE GROUND statt USE POWER + + if(m/^\s*END\s+$macro/ && !$filled) # Inject the obstructions here + { + print LEFOUT "\n OBS\n$obs\n end\n"; + $filled=1; + } + #print $_; + print LEFOUT $_; + #print "$macro\n"; + #print $_; + if(m/FOREIGN/) + { + if(open(MAG,"<$mag")) + { + my $layer=""; + while() + { + if(m/<< (\w+) >>/) + { + $layer=$1; + } + if(m/rect 0 0 (\d+) (\d+)/) + { + next if($layer eq "checkpaint"); + my $h=$1; + my $w=$2; + my $factor=0.01; + #print "$lef -> ".($1*$factor)." ".($2*$factor)."\n"; + #print LEFOUT " SIZE ".($1*$factor)." BY ".($2*$factor)." ;\n"; + } + if(m/string FIXED_BBOX 0 0 (\d+) (\d+)/) + { + my $h=$1; + my $w=$2; + my $factor=0.01; + #print "$lef -> ".($1*$factor)." ".($2*$factor)."\n"; + #print LEFOUT " SIZE ".($1*$factor)." BY ".($2*$factor)." ;\n"; + } + + } + close MAG; + } + } + } + close LEFOUT; + #close LEFIN; + + system "cp $lef $lef.beforemagic"; + + open MAGIC,"|magic -dnull -noconsole -T $magictech"; + print MAGIC "lef read $lef\n"; + print MAGIC "load $cell\n"; + print MAGIC "lef write $lef\n"; + print MAGIC "quit\n"; + close MAGIC; +} diff --git a/Tools/caravel/fixup_mag.pl b/Tools/caravel/fixup_mag.pl new file mode 100755 index 00000000..9e614836 --- /dev/null +++ b/Tools/caravel/fixup_mag.pl @@ -0,0 +1,114 @@ +#!/usr/bin/perl -w +use strict; + +print STDERR "Fixing up .mag files\n"; + +my $magictech=$ARGV[0] || "sky130A"; + +foreach my $mag (<*.mag>) +{ + my $name=$mag; $name=~s/\.mag$//; + next if($mag=~m/^sky130_/); + next if($mag=~m/^demo/); + system "cp $mag $mag.beforemagic"; + + my $width=150; + my $min=100; + my $max=200; + + open IN,"<$mag.beforemagic"; + open OUT,">$mag"; + my $currentlayer=""; + while() + { + if(m/<< (\w+) >>/) + { + $currentlayer=$1; + } + if(m/rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/ && $currentlayer eq "viali") + { + if($2<0 || $2>640) + { + print OUT "<< locali >>\n$_"; + print OUT "<< metal1 >>\n$_"; + print OUT "<< viali >>\n"; + next; + } + } + s/\bVDD\b/VPWR/g; + s/\bGND\b/VGND/g; + print OUT $_; + if(m/string FIXED_BBOX 0 0 (\d+) (\d+)/) + { + $width=$1; $min=$1-31; $max=$min+31; + print "min: $min max: $max\nmagic $mag\nbox $min 17 $max 649\n"; + print OUT "<< viali >>\n"; + foreach(0 .. ($max /96)-3) + { + print OUT "rect ".(127+$_*96)." -17 ".(161+$_*96)." 17\n"; + print OUT "rect ".(127+$_*96)." 649 ".(161+$_*96)." 683\n"; + } + } + + } + + close IN; + close OUT; + +my $cmd=<; + close MYRIN; + $/=$old; + return $content; + } + return undef; +} + +foreach my $sp (<*.sp>) +{ + my $content=readfile($sp); + $content=~s/\bvdd\b/VPWR/g; + $content=~s/\bgnd\b/VGND/g; + open OUT,">$sp"; + print OUT $content; + close OUT; +} diff --git a/Tools/caravel/generator.pl b/Tools/caravel/generator.pl new file mode 100755 index 00000000..4e0dcb7c --- /dev/null +++ b/Tools/caravel/generator.pl @@ -0,0 +1,197 @@ +#!/usr/bin/perl -w + +my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; + +print STDERR "Generates Verilog for user_proj_example\n"; + +print STDERR "Warning: environment variable CARAVEL not defined! Please define it.\n" unless (-d $ENV{'CARAVEL'}."/cells/mag/"); + + +print <) +{ + next if((-s $mag)<=50); + #print `ls -la $mag`; + my $cell=$mag; $cell=~s/\.mag$/.cell/; $cell=~s/\/mag\//\/cell\//; + my $lib=$mag; $lib=~s/\.mag$/.lib/; $lib=~s/\/mag\//\/lib\//; + + my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/); + next unless(-f $cell); + #next unless(-f $lib); + #next unless(-f $ENV{'CARAVEL'}."/cells/mag/$name.mag"); + + open CELL,"<$cell"; + print "$name $name(\n"; + print " `ifdef USE_POWER_PINS\n"; + print " \.VPWR(vccd1),\n"; # ??? Should we do 3.3V or 1.8V ? + print " \.VGND(vssd1),\n"; + print " `endif\n"; + + my $counter=0; + while() + { + if(m/^\.inputs (.*)/) + { + foreach my $inp(sort split " ",$1) + { + my $io=$nextio++; + if($io<$MPRJ_IO_PADS) + { + print " ".($counter?', ':'')."\.$inp(io_in_wire[$io])\n"; + $conf.="assign io_oeb[$io] = 1'b1;\n"; + $inout{"io$io"}="ioin"; + $counter++; + } + else + { + my $la=$io-$MPRJ_IO_PADS; + print " ".($counter?', ':'')."\.$inp(la_data_in_wire[$la])\n"; + $inout{"io$io"}="lain"; + $counter++; + } + } + } + if(m/^\.outputs (.*)/) + { + foreach my $outp(sort split " ",$1) + { + my $io=$nextio++; + if($io<$MPRJ_IO_PADS) + { + print " ".($counter?', ':'')."\.$outp(io_out[$io])\n"; + $driven{"io_out[$io]"}=1; + $conf.="assign io_oeb[$io] = 1'b0;\n"; + $inout{"io$io"}="ioout"; + $counter++; + } + else + { + my $la=$io-$MPRJ_IO_PADS; + print " ".($counter?', ':'')."\.$outp(la_data_out[$la])\n"; + $driven{"la_data_out[$la]"}=1; + $inout{"io$io"}="laout"; + $counter++; + } + } + } + + } + close CELL; + + print ");\n"; +} + + foreach(0 .. 127) + { + print "assign la_data_out[$_] = 1'b0;\n" if(!defined($driven{"la_data_out[$_]"})); + } + foreach(0 .. $MPRJ_IO_PADS-1) + { + print "assign io_out[$_] = 1'b0;\nassign io_oeb[$_] =1'b0;\n" if(!defined($driven{"io_out[$_]"})); + } + + print "assign wbs_ack_o = 1'b1;\n"; + print "assign wbs_dat_o = 32'b0;\n"; + +print $conf; +print "endmodule\n"; +print "`default_nettype wire\n"; diff --git a/Tools/caravel/gitpush.sh b/Tools/caravel/gitpush.sh new file mode 100755 index 00000000..4a276233 --- /dev/null +++ b/Tools/caravel/gitpush.sh @@ -0,0 +1,5 @@ +git add cells/ def/user_proj_example.def lef/user_proj_example.lef openlane/user_proj_example/config.tcl openlane/user_proj_example/macro_placement.cfg signoff/user_proj_example/final_summary_report.csv verilog/rtl/user_proj_cells.v verilog/rtl/user_proj_example.v +git add gds/user_proj_example.gds.gz +git add gds/user_project_wrapper.gds.gz +git add mag/user_project_wrapper.mag +git add maglef/user_proj_example.mag spi/lvs/user_proj_example.spice verilog/gl/user_proj_example.v verilog/dv diff --git a/Tools/caravel/iogenerator.pl b/Tools/caravel/iogenerator.pl new file mode 100755 index 00000000..4bf69448 --- /dev/null +++ b/Tools/caravel/iogenerator.pl @@ -0,0 +1,144 @@ +#!/usr/bin/perl -w +use strict; + +print STDERR "Generating IO configuration\n"; + +my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; + +print STDERR "Warning: environment variable CARAVEL not defined! Please define it.\n" unless (-d $ENV{'CARAVEL'}."/cells/mag/"); + + +print <) +{ + next if((-s $mag)<=50); + #print `ls -la $mag`; + my $cell=$mag; $cell=~s/\.mag$/.cell/; $cell=~s/\/mag\//\/cell\//; + my $lib=$mag; $lib=~s/\.mag$/.lib/; $lib=~s/\/mag\//\/lib\//; + + my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/); + print STDERR "$mag $cell $lib\n"; + next unless(-f $cell); + #next unless(-f $lib); + #next unless(-f $ENV{'CARAVEL'}."/cells/mag/$name.mag"); + + open CELL,"<$cell"; + + while() + { + if(m/^\.inputs (.*)/) + { + foreach my $inp(sort split " ",$1) + { + my $io=$nextio++; + if($io<$MPRJ_IO_PADS) + { + $setting{$io}="GPIO_MODE_USER_STD_INPUT_PULLDOWN"; + } + else + { + # Logic Analyzer does not need IO pins to be configured + } + } + } + if(m/^\.outputs (.*)/) + { + foreach my $outp(sort split " ",$1) + { + my $io=$nextio++; + if($io<$MPRJ_IO_PADS) + { + $setting{$io}="GPIO_MODE_USER_STD_OUTPUT"; + } + else + { + # Logic Analyzer... + } + } + } + + } + close CELL; +} + +foreach(5 .. 37) +{ + print "`define USER_CONFIG_GPIO_$_"."_INIT `".($setting{$_}||"GPIO_MODE_USER_STD_INPUT_NOPULL")."\n"; +} + +print "`endif // __USER_DEFINES_H\n"; diff --git a/Tools/caravel/placement.pl b/Tools/caravel/placement.pl new file mode 100755 index 00000000..bab0901e --- /dev/null +++ b/Tools/caravel/placement.pl @@ -0,0 +1,32 @@ +#!/usr/bin/perl -w + +print STDERR "Generates macro placement file for all cells - not needed\n"; + +my $width=0.48; +my $height=3.33; + + +my $row=8; + +my $xpos=($row%2)? $width*80 : 44.640+0.480; + +our $nextla=$height*$row; + + + +my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; + +foreach my $mag(sort ) +{ + next if((-s $mag)<=50); + #print `ls -la $mag`; + my $cell=$mag; $cell=~s/\.mag$/.cell/; $cell=~s/\/mag\//\/cell\//; + next unless(-f $cell); + my $lib=$mag; $lib=~s/\.mag$/.lib/; $lib=~s/\/mag\//\/lib\//; + #next unless(-f $lib); + my $name=""; $name=$1 if($mag=~m/([\w\-\.]+)\.mag$/); + next unless(-f $ENV{'CARAVEL'}."/cells/mag/$name.mag"); + + print "$name $xpos $nextla N\n"; + $nextla+=$height*2; +} diff --git a/Tools/caravel/removeDRCcells.pl b/Tools/caravel/removeDRCcells.pl new file mode 100755 index 00000000..dec9908d --- /dev/null +++ b/Tools/caravel/removeDRCcells.pl @@ -0,0 +1,38 @@ +#!/usr/bin/perl -w + +print STDERR "Remove cells that have DRC errors from the Caravel so that we only have good cells on the Caravel\n"; + +foreach my $mag (<*.mag>) +{ + my $cell=$mag; $cell=~s/\.mag$//; + #print "Checking $cell\n"; + my $STDCELLLIB=$ENV{'STDCELLLIB'}; + my $drc=0; + if(open(IN,"<$STDCELLLIB/Catalog/$cell.drc")) + { + while() + { + $drc=$1 if(m/Number of DRC errors: (\d+)/); + } + close IN; + } + else + { + print "Warning: Could not find DRC: $STDCELLLIB/$cell.drc $!\n"; + $drc=1; + } + $drc=1 if(!-f "$STDCELLLIB/Catalog/$cell.mag"); + if($drc) + { + print "Removing cell with $drc DRC issues: $cell\n"; + unlink $mag; + unlink "../lef/orig/$cell.lef"; + unlink "../lef/$cell.lef"; + unlink "../gds/$cell.gds"; + unlink "../lib/$cell.lib"; + unlink "../cell/$cell.cell"; + unlink "../sp/$cell.sp"; + } + +} + diff --git a/Tools/caravel/removenl.pl b/Tools/caravel/removenl.pl new file mode 100755 index 00000000..a56fede2 --- /dev/null +++ b/Tools/caravel/removenl.pl @@ -0,0 +1,17 @@ +#!/usr/bin/perl -w + +print STDERR "Fixups for the LIBERTY files\n"; + +open IN,"; +$content=~s/area/pg_pin (VPWR) { voltage_name : "VPWR"; pg_type : "primary_power"; } pg_pin (VGND) { voltage_name : "VGND"; pg_type : "primary_ground"; } area/g; + +#$content=~s/"\s*\n/"/gs; +#$content=~s/;\s*\n/;/gs; +#$content=~s/\n//gs; # Why did we remove the newlines? - it now works without removing them +$content=~s/\\//gs; + + + +print $content; diff --git a/Tools/caravel/scale10.py b/Tools/caravel/scale10.py new file mode 100755 index 00000000..57b2cca2 --- /dev/null +++ b/Tools/caravel/scale10.py @@ -0,0 +1,10 @@ +import glob +import gdsfactory as gf + +# Rescale GDS files + +for a in glob.glob("*.gds"): + print(a) + b=gf.read.import_gds(a,read_metadata=True) + b.write_gds(a,unit=1e-07) + diff --git a/Tools/caravel/stdcells_tb.v b/Tools/caravel/stdcells_tb.v new file mode 100644 index 00000000..75d4e3c7 --- /dev/null +++ b/Tools/caravel/stdcells_tb.v @@ -0,0 +1,268 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + +`timescale 1 ns / 1 ps + +module stdcells_tb; + reg clock; + reg RSTB; + reg CSB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + wire [7:0] mprj_io_0; + + assign mprj_io_0 = mprj_io[7:0]; + // assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]}; + + assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz; + // assign mprj_io[3] = 1'b1; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + + `ifdef ENABLE_SDF + initial begin + $sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ; + $sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ; + $sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ; + $sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ; + $sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ; + $sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ; + $sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ; + $sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ; + $sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ; + $sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ; + $sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ; + $sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ; + $sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ; + $sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ; + $sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ; + end + `endif + + initial begin + $dumpfile("stdcells.vcd"); + $dumpvars(0, stdcells_tb); + + // Repeat cycles of 10000 clock edges as needed to complete testbench + repeat (50) begin + repeat (1000) @(posedge clock); + $display("+1000 cycles"); + end + $display("%c[1;31m",27); + `ifdef GL + $display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed"); + `else + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + `endif + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe Output pins [7:0] + wait(mprj_io_0 == 8'hEE); + + `ifdef GL + $display("Monitor: Test 1 StdCellLib IO (GL) Failed"); + `else + $display("Monitor: Test 1 StdCellLib IO (RTL) Failed"); + `endif + $finish; + end + initial begin + // Observe Output pins [7:0] + wait(mprj_io_0 == 8'hFE); + + `ifdef GL + $display("Monitor: Test 1 StdCellLib IO (GL) Success"); + `else + $display("Monitor: Test 1 StdCellLib IO (RTL) Success"); + `endif + $finish; + end + + + initial begin + RSTB <= 1'b0; + CSB <= 1'b1; // Force CSB high + #2000; + RSTB <= 1'b1; // Release reset + #3_00_000; + CSB = 1'b0; // CSB can be released + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #100; + power1 <= 1'b1; + #100; + power2 <= 1'b1; + #100; + power3 <= 1'b1; + #100; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3; + wire VDD1V8; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vddio_2 (VDD3V3), + .vssio (VSS), + .vssio_2 (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda1_2 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa1_2 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("stdcells.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + +endmodule +`default_nettype wire diff --git a/Tools/caravel/testgen.pl b/Tools/caravel/testgen.pl new file mode 100755 index 00000000..641e3ab8 --- /dev/null +++ b/Tools/caravel/testgen.pl @@ -0,0 +1,68 @@ +#!/usr/bin/perl -w +use strict; + +print STDERR "Generating testbench firmware file for Caravel to test all the functions (this is a ATPG)\n"; + +open IN,"<$ARGV[0]"; + +print <; +my @l=split "->",$header; +my @ins=sort split " ",$l[0]; +my @outs=sort split " ",$l[1]; +my %map=(); + +my $reg=0; +my @io=(); +print " printf(\"Initializing the Inputs of the cell:\\n\");\n"; +foreach(@ins) +{ + print " reg_mprj_io_$reg = GPIO_MODE_MGMT_STD_INPUT; // $_\n"; + $io[$reg>>5]|=1<<($reg&31); + $reg++; +} +print " printf(\"Initializing the Outputs of the cell:\\n\");\n"; +foreach(@outs) +{ + $map{$_}=$reg++; + + print " reg_mprj_io_$reg = GPIO_MODE_USER_STD_OUTPUT; // $_\n"; +} + +print " reg_mprj_xfer=1;\n"; +print " while (reg_mprj_xfer == 1);\n"; + +foreach(0 .. 3) +{ + print "reg_la".$_."_ena=".sprintf("0x%08X",$io[$_]).";\n" if(defined($io[$_])); +} + +my $counter=0; +print " printf(\"Starting the tests:\\n\");\n"; + +while() +{ + last if(m/^function:/); + @l=split " ",$_; + my $if=0; + foreach(@l) + { + if(m/(\w+)=(\d)/) + { + print " assert(reg_la".$map{$1}."_data==$2); //$1\n"; + } + else + { + print " reg_la".$if."_data=$_; //$ins[$if]\n"; + } + $if++; + } + print " printf(\"Test $counter successful\\n\");\n\n"; + + $counter++; +} diff --git a/Tools/caravel/viewer.pl b/Tools/caravel/viewer.pl new file mode 100755 index 00000000..321e1726 --- /dev/null +++ b/Tools/caravel/viewer.pl @@ -0,0 +1,15 @@ +#!/usr/bin/perl -w + +my $STDCELLLIB=$ENV{'STDCELLLIB'} || "/home/philipp/libresilicon/StdCellLib"; +my $CARAVEL=$ENV{'CARAVEL'} || "/media/philipp/Daten/skywater/caravel-stdcelllib-stdcells"; +my $magictech=$ARGV[0] || "sky130A"; + + +open OUT,"|magic -noconsole -T $magictech"; +foreach(<$CARAVEL/cells/lef/*.lef>) +{ + print OUT "lef read $_\n"; +} +print OUT "def read ".$ARGV[0]."\n"; +#print OUT "select top\n"; +close OUT; diff --git a/Tools/cell.5 b/Tools/cell.5 index 3f753c86..126733f8 100644 --- a/Tools/cell.5 +++ b/Tools/cell.5 @@ -42,7 +42,7 @@ .\" .\" GNU General Public License v3.0 - http://www.gnu.org/licenses/gpl-3.0.html .\" /////////////////////////////////////////////////////////////////// -.Dd April 12, 2019 +.Dd August 19, 2019 .Dt CELL 5 "Standard Cell Library" .Os LibreSilicon .Sh NAME @@ -82,6 +82,9 @@ indicates the end of file. All circuit lines are an ordered, white-space-separated list of strings (also terminated by the end of the line) describing one circuit (a pMOS or nMOS transistor) with some arguments. .Pp Every circuits line contains this arguments in the following order: +.Bd -literal +type gate drain source bulk stacked xgrid ygrid size +.Ed .Bl -ohang .It Em type The transistor type used for this circuit (e.g., pmos or nmos). @@ -101,6 +104,8 @@ This coordinates rising up from left (1st grid position is 1) to right. .It Em ygrid Y-position (as integer) inside the grid; always positive for pMOS transistors and always negative for nMOS transistors. This coordinates are aligned to the output with zero. +.It Em size +Size (as integer) of the mosfet; representing the number of minimum sized transister length for width parameter. .El .Sh AUTHORS .An chipforge Aq popcorn@nospam.chipforge.org diff --git a/Tools/perl/annotate.pl b/Tools/perl/annotate.pl new file mode 100755 index 00000000..3bcab351 --- /dev/null +++ b/Tools/perl/annotate.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl -w + +foreach() +{ + next if(-f "$_.ann"); + system "klayout -l librecell.lyp $_"; + print "Is it good?\n"; + my $val=; + print "So you think $val?\n"; + if($val=~m/[eq]/i) + { + exit; + } + if($val=~m/[yn]/) + { + open OUT,">$_.ann"; + print OUT $val; + close OUT; + } +} diff --git a/Tools/perl/bisect.pl b/Tools/perl/bisect.pl new file mode 100755 index 00000000..685dfbd6 --- /dev/null +++ b/Tools/perl/bisect.pl @@ -0,0 +1,61 @@ +#!/usr/bin/perl -w +use strict; + +my $cellname=$ARGV[0] || "INV"; +my $placer=""; +my $deb=0; + +open IN,"<../Tech/librecell_tech.py.bad"; +my @bad=; +close IN; + +open IN,"<../Tech/librecell_tech.py.good"; +my @good=; +close IN; + +my $ndiffs=0; + +foreach(0 .. scalar(@bad)-1) +{ + $ndiffs++ if($bad[$_] ne $good[$_]); +} + +print "Different lines between librecell_tech.py.good and librecell_tech.py.bad: $ndiffs\n"; + +my $prev=undef; + +my %badlist=(); + +foreach my $variant (0 .. $ndiffs+1) +{ + open OUT,">../Tech/librecell_tech.$variant.py"; + my $counter=0; + foreach(0 .. scalar(@bad)-1) + { + if($bad[$_] ne $good[$_]) + { + $counter++; + print OUT defined($badlist{$counter})?$good[$_]:($counter>$variant)?$good[$_]:$bad[$_]; + } + else + { + print OUT $good[$_]; + } + + } + close OUT; + my $ret=system "lclayout --output-dir debuglib --tech ../Tech/librecell_tech.$variant.py --netlist $cellname.sp --cell $cellname -v $placer --placement-file $cellname.place --ignore-lvs ".($deb?"--debug-routing-graph ":"")." >>$cellname.$variant.log 2>>$cellname.$variant.err "; + print "Variant: $variant Return: $ret\n"; + + if($ret != 0) # indicates an error + { + print "Bad Line found: \n"; + system "diff ../Tech/librecell_tech.$variant.py ../Tech/librecell_tech.".($variant-1).".py"; + $badlist{$variant}=1; + } + +} + +print "Activating the best option:\n"; +system "cp -f ../Tech/librecell_tech.".($ndiffs+1).".py ../Tech/librecell_tech.py"; + diff --git a/Tools/perl/buildreport.pl b/Tools/perl/buildreport.pl new file mode 100755 index 00000000..32c29f30 --- /dev/null +++ b/Tools/perl/buildreport.pl @@ -0,0 +1,229 @@ +#!/usr/bin/perl -w + +# This tool generates a HTML build report + +my $reportnew="buildreportnew.html"; +my $report="buildreport.html"; + +open OUT,">$reportnew"; +print OUT ""; +print OUT '' if(!-f ".done"); +print OUT < +body +{ + font-family: Verdana, Helvetica, sans-serif; + font-size: 100%; + color: black; + background-color: #f8f8f8; + margin: 10; + padding: 0 0 25px 0 +} + +div, form +{ + margin: 0; + padding: 0 +} + +p, ul, ol, table +{ + padding: 0; + margin: 0.8em 0; + border-collapse: collapse; +} +th +{ + text-align: left; + font-size: 100%; + background-color: #f0f0f0; + padding: 3px 3px 3px 3px; +} +td +{ + padding: 3px 3px 3px 3px; + vertical-align: middle; +} + +a { color: #DE0019; text-decoration: underline } +a:link { color: #DE0019; text-decoration: underline } +a:visited { color: #DE0019; text-decoration: underline } +a:hover { color: black; text-decoration: underline } +a:active { color: white; background-color: black; text-decoration: underline } +a:focus { color: white; background-color: black; text-decoration: underline } + + img, +a img, +a:link img, +a:visited img, +a:hover img, +a:active img, +a:focus img +{ border: 0px none white; } + + + +EOF +; +print OUT "Build Report Libresilicon"; +print OUT "

Build Report

"; +print OUT "Generated: ".localtime()." by LibreSilicon Standard Cell Library Generator
\n"; + +print OUT "

Input files: PDK, DRC, layer definitions, process parameters:

"; +print OUT "These input files are necessary to define the rules and parameters for the standard cell library. All those files are collected in the Tech directory.
"; +my %inputs=("drc.lydrc"=>"DRC rules for KLayout GDS Viewer", + "librecell_tech.py"=>"Cell layouting rules, DRC","libresilicon.m"=>"Transistor BSIM model SPICE parameters (*.lib files in other tools)","libresilicon.tech"=>"Magic Layers and Parasitic extraction parameters","nmos.sp"=>"Transistor size template for SPICE models","pmos.sp"=>"Transistor size template for SPICE models","template.lef"=>"Template for the header of Library Exchange Format LEF Files"); +print OUT ""; +foreach(sort keys %inputs) +{ + print OUT ""; +} +print OUT "
FilenameDescription
".(-f "../Tech/$_"? "✓$_":"X$_")."$inputs{$_}
"; + +print OUT "

Standard Cells:

\n"; +print OUT "These are the generated standard cells. "; +print OUT "You can click on the green ticks and the error messages to get more details or download the files. By moving the mouse over the header line you will get explanations for each column.
\n"; + +print OUT ""; +print OUT ""; + +my $maxmem=0; +my $maxtime=0; +my $ncells=0; +my $nsvgs=0; + +foreach my $file (<*.cell>) +{ + my $errfile=$file; $errfile=~s/\.cell$/.err/; + my $logfile=$file; $logfile=~s/\.cell$/.log/; + my $magfile=$file; $magfile=~s/\.cell$/.mag/; + my $drcfile=$file; $drcfile=~s/\.cell$/.drc/; + my $libfile=$file; $libfile=~s/\.cell$/.lib/; + my $svgfile=$file; $svgfile=~s/\.cell$/.svg/; + my $usagefile=$file; $usagefile=~s/\.cell$/.usage/; + my $schfile="doc/".$file; $schfile=~s/\.cell$/_svg.png/; + my $pngfile=$file; $pngfile=~s/\.cell$/.png/; + my $leffile="outputlib/".$file; $leffile=~s/\.cell$/.lef/; + my $gdsfile="outputlib/".$file; $gdsfile=~s/\.cell$/.gds/; + my $spfile=$file; $spfile=~s/\.cell$/.sp/; + my $spicefile=$file; $spicefile=~s/\.cell$/.spice/; + my $runfile=$file; $runfile=~s/\.cell$/.running/; + my $dontlayoutfile=$file; $dontlayoutfile=~s/\.cell$/.dontlayout/; + + my $area=""; + my $lvs=""; + my $euler=""; + my $layouttime=""; + my $nets=""; + my $errors=""; + my $routing=""; + my $ports=0; + my $b1=(-f $runfile)?"":""; + my $b2=(-f $runfile)?"":""; + my $drccount=0; + my $thistime=0; + + if(open DRC,"<$drcfile") + { + while() + { + $drccount=$1 if(m/Number of DRC errors: (\d+)/); + } + } + $ncells++ if(-f $file); + $nsvgs++ if(-f $svgfile); + + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + print OUT ""; + + if(open LIB,"<$libfile") + { + while() + { + $area=$1 if m/area:\s*(\d+)\.?\d*\s*/; + } + close LIB; + } + if(open LIB,"<$errfile") + { + while() + { + $lvs=$1 if(m/LVS result: (\w+)/ && $lvs eq ""); + $euler=$1 if m/Number of deduplicated eulertours: (\d+)/; + $layouttime=$1 if(m/INFO:\s*Done\s*\(Total duration: ([\d:.]+)\s*\)/); + $nets=$1 if(m/Nets output: (\d+)/); + $routing=$1 if(m/Routing iteration (\d+)/); + $ports=scalar(split(",",$1)) if(m/Subcircuit ports: (.*)/); + $errors.=$1." " if(m/AssertionError: (.*)/); + $errors.=$1." " if(m/Exception: (.*)/); + $errors.=$1." " if(m/ERROR: (.*)/); + $errors.=$1." " if(m/(Segmentation fault \(core dumped\))/); + $errors=~s/LVS check failed!//; + } + close LIB; + } + if(open USG,"<$usagefile") + { + while() + { + if(m/Elapsed \(wall clock\) time \(h:mm:ss or m:ss\): ([\d:]+)/) + { + my @ar=split ":",$1; + my $sec=$ar[-1]+$ar[-2]*60+($ar[-3]||0)*60*60; + #print "$1 -> $sec\n"; + $thistime+=$sec; + $maxtime=$thistime if($thistime > $maxtime); + } + if(m/Maximum resident set size \(kbytes\): (\d+)/) + { + $maxmem=$1 if($1 > $maxmem); + } + } + close USG; + } + $layouttime=~s/\.\d+$//; + $lvs=~s/FAILED/FAILED<\/font>/; + $lvs=""; # LVS engine is currently broken + + $errors.=" This cell is currently building..." if(-f $runfile); + $errors.=" This cell has been excluded from building " if(-f $dontlayoutfile); + + print OUT ""; + + print OUT ""; + + +} +print OUT "
CellcellMagicLayoutSchematicLogErrDRCLibertyLEFGDSSPICEParasiticAreaLVSEulerLayoutTimeNetsPortsIterat.Errors
$b1$file$b2".(-f $file ? "✓":"X")."".(-f $magfile ? "✓":"X")."".(-f $svgfile ? "✓":"X")."".(-f $schfile ? "✓":"X")."".(-f $logfile ? "✓":"X")."".(-f $errfile ? "✓":"X")."".(-f $drcfile ? "✓ $drccount":"X")."".(-f $libfile ? "✓":"X")."".(-f $leffile ? "✓":"X")."".(-f $gdsfile ? "✓":"X")."".(-f $spfile?"✓":"X")."".(-f $spicefile?"✓":"X")."$area$lvs$euler$layouttime ".int($thistime/60)."$nets$ports$routing$errors

"; + + +print OUT "

Output files (needed by RTL2GDS tools like qflow, OpenROAD, Cadence, Synopsys, ...):

"; +print OUT "These are the resulting output files, you can download and use them with other EDA tools to build your chips:
\n"; +my %outputs=("libresilicon.sp"=>"SPICE netlist with all cells","libresilicon.lib"=>"LIBERTY File with Characterization of all cells, can be viewed with libertyviz","libresilicon.lef"=>"Library Exchange Format (LEF) File with all cells","library.gds"=>"GDS-II file with masks for all cells, can be viewed with KLayout","../Documents/StdCellLib.pdf"=>"PDF Documentation of the Standard cell library","demoboard.mag"=>"Demoboard: ".(-s "demoboard.svg"?"":"")." with all cells"); +print OUT ""; +foreach(sort keys %outputs) +{ + print OUT ""; +} +print OUT "
FilenameDescription
".(-f $_? "✓ $_":"X$_")."$outputs{$_}
"; + +print OUT "Stats: Max memory per cell: ".int($maxmem/1024)."MB , Max time per cell: ".sprintf("%d:%02d:%02d",int($maxtime/60/60),int(($maxtime%3600)/60), $maxtime %60)." Cells: $ncells SVGs: $nsvgs

"; + +print OUT "If you want to build your own standard cell library, you can try our Online Standard Cell Library Generator or download the generator software and run it yourself.
\n"; + +print OUT ""; +close OUT; +rename $reportnew,$report; +print "firefox $report\n"; + diff --git a/Tools/perl/cell2circle.pl b/Tools/perl/cell2circle.pl new file mode 100755 index 00000000..714f76b1 --- /dev/null +++ b/Tools/perl/cell2circle.pl @@ -0,0 +1,141 @@ +#!/usr/bin/perl -w +use strict; + +print "Generating a Schematic file for KiCad's EESchema from a cell netlist\n"; + +open IN,"<$ARGV[0]"; +open OUT,">$ARGV[0].sch"; + +my $pi=3.1415926; + +print OUT <) +{ + push @devs,$_ if(m/^(pmos|nmos|res)/); + $inputs=$1 if(m/^\.inputs (.*)/); + $outputs=$1 if(m/^\.outputs (.*)/); +} + +sub Wire($$$$) +{ +print OUT <$_[1]?$_[1]:$_[0]; +} +sub mymax +{ + return $_[1] if(!defined($_[0])); + return $_[0] if(!defined($_[1])); + return $_[0]>$_[1]?$_[0]:$_[1]; +} + + +# Loading the .cell file: +open IN,"<$cellfn" or die "Could not open file: $!\n"; +# Using graphviz dot to do the placement of the transistors and resistors on the schematic +open OUT,"|dot >$cellfn.g"; + +# Graphviz header +print OUT <) +{ + push @devs,$_ if(m/^(pmos|nmos|res)/); + $inputs=$1 if(m/^\.inputs (.*)/); + $outputs=$1 if(m/^\.outputs (.*)/); +} +close IN; + +# Defining nodes and edges in the graphviz graph +my $count=0; +foreach(@devs) +{ + if(m/^(n|p)mos (\w+) (\w+) (\w+)/) + { + my ($t,$g,$s,$d)=(lc($1),$2,$3,$4); + my $dev="$t"."mos".$count; + print OUT "$dev [shape=\"rectangle\"]\n"; # node + print OUT "$g -> $dev\n" unless($g=~m/(vdd|gnd)/); # edge + print OUT "$g [shape=\"point\"]\n" if($g=~m/^\d+$/); + print OUT "$g [fillcolor=\"yellow\", style=\"filled\"]\n" if($g=~m/^\w+$/); + print OUT "$dev -> $s\n" unless($s=~m/(vdd|gnd)/); # edge + print OUT "$s [shape=\"point\"]\n" if($s=~m/^\d+$/); + print OUT "$s [fillcolor=\"yellow\", style=\"filled\"]\n" if($s=~m/^\w+$/); + print OUT "$d -> $dev\n" unless($d=~m/(vdd|gnd)/); # edge + print OUT "$d [shape=\"point\"]\n" if($d=~m/^\d+$/); + print OUT "$d [fillcolor=\"yellow\", style=\"filled\"]\n" if($d=~m/^\w+$/); + + $count++; + } + elsif(m/^res (\w+) (\w+) (\d+)/) + { + my ($n1,$n2)=($1,$2); + my $dev="res".$count; + print OUT "$dev [shape=\"rectangle\"]\n"; + print OUT "$n1 -> $dev\n" unless($n1=~m/(vdd|gnd)/); + print OUT "$dev -> $n2\n" unless($n2=~m/(vdd|gnd)/); + $count++; + } +} + +print OUT "}\n"; +close OUT; + +# Now generating SVG output for debugging +system "dot -T svg <$cellfn.g >$cellfn.svg"; +print "firefox $cellfn.svg\n"; + +our %coordx=(); +our %coordy=(); + +# Reading the resulting graphviz file and extracting the coordinates +open IN,"<$cellfn.g"; +undef $/; +my $g=; +my %stat=(); +while($g=~s/(pmos|nmos|res)(\d+)\s*\[height=\d+\.?\d*,\s*pos="(\d+\.?\d*),(\d+\.?\d*)"//sm) +{ + $coordx{$2}=$3; + $stat{'minx'}=mymin($stat{'minx'},$3); + $stat{'maxx'}=mymax($stat{'maxx'},$3); + $coordy{$2}=$4; + $stat{'miny'}=mymin($stat{'miny'},$4); + $stat{'maxy'}=mymax($stat{'maxy'},$4); + #print "$2 $3 $4\n"; +} +close IN; + +#print "X: $stat{minx} - $stat{maxx}\n"; +#print "Y: $stat{miny} - $stat{maxy}\n"; + +#Generating a Schematic file for KiCad's EESchema from a cell netlist + +open OUT,">$ARGV[0].sch"; + +print OUT <; $ntech=~s/[\n\r]//s; + close IN; +} +if(open IN,"<../Tech/pmos.sp") +{ + print "Loading tech specs from pmos.sp file\n"; + $ptech=; $ptech=~s/[\n\r]//s; + close IN; +} + + +print "NMOS Tech specs: $ntech\n"; +print "PMOS Tech specs: $ptech\n"; + +my @cells=<*.cell>; +my $cell=undef; + +if(scalar(@ARGV)) +{ + $cell=$ARGV[0]; + $cell=~s/\.cell$//; + @cells=$cell.".cell"; +} + +open OUT,">".($cell?"$cell.sp":"libresilicon.sp"); +print OUT "*** Spice netlist generated by cell2spice.pl".($cell?" from cell file $cell.cell":"")." ***\n\n"; + +print "Params: ".scalar(@ARGV)." ".scalar(@cells)."\n"; + +foreach my $fn (@cells) +{ + my $short=$fn; $short=~s/\.cell//; + my $transistors=""; + print "Opening $fn\n"; + open IN,"<$fn" || die "Error opening cell file: $!\n"; + my $M=0; + my $ios=""; + while() + { + if(m/^\.(inputs|outputs) (.*)/) + { + $ios.=" ".$2; + } + if(m/^([pn]mos) (\w+) (\w+) (\w+)/i) + { + my($t,$g,$d,$s)=($1,$2,$3,$4); + my $x=($t eq "pmos")?"vdd":"gnd"; + $transistors.="M$M ".uc("$d $g $s $x")." $t ".(($t eq "pmos") ? $ptech:$ntech)."\n"; + #M1 vdd B a_2_6# vdd pmos w=0.5u l=0.05u + #M2 Y a_2_6# vdd vdd pmos w=0.5u l=0.05u + #M3 a_9_6# A a_2_6# gnd nmos w=0.5u l=0.05u + #M4 gnd B a_9_6# gnd nmos w=0.5u l=0.05u + #M5 Y a_2_6# gnd gnd nmos w=0.25u l=0.05u + #$transistors.="+ ad=0p pd=0u as=0p ps=0u\n"; + $M++; + } + if(m/^res (\w+) (\w+) (\w+)/i) + { + my($n1,$n2,$v)=($1,$2,$3); + $transistors.="R$M ".uc($n1)." ".uc($n2)." ".uc($v)."\n"; + $M++; + } + } + $ios=~s/,/ /g;$ios=~s/ / /g; $ios=~s/^ //; $ios=~s/ $//; + print OUT ".subckt $short ".uc("vdd gnd $ios")."\n"; + print OUT $transistors; + print OUT ".ends $short\n\n"; + close IN; +} + +close OUT; + diff --git a/Tools/perl/charter2caravel.pl b/Tools/perl/charter2caravel.pl new file mode 100755 index 00000000..a2b35c4d --- /dev/null +++ b/Tools/perl/charter2caravel.pl @@ -0,0 +1,388 @@ +#!/usr/bin/perl -w + +my $doverification=1; +my $maxios=38+128-2; # How many IOs does one Caravel have? +my $maxdesigns=1; # How many Caravels do you want to use maximum? +our $githubuser=$ENV{'GITHUB_USER'} || "thesourcerer8"; # GitHub Username for the Repository URL +our $efablessuser=$ENV{'EFABLESS_USER'} || "philippguehring"; # EFabless GIT username +our $CARAVEL=""; +our @repos=(); +our %assigned=(); +our $ngroups=0; +my $usedios=0; +my $totalios=0; +my $group=1; + +print "Chartering one or more Caravels ...\n"; + +open IN,"<../Tech/caravel-env.sh"; +print "Loading Caravel environment variables.\n"; +while() +{ + if(m/^export (\w+)="([^"]+)"/) + { + $ENV{$1}=$2; + print "Setting Caravel variable $1 to $2\n"; + } +} +close IN; + +my $magictech=$ENV{'PDK'} || "gf180mcuD"; # MAGIC Technology name (.tech filename) +$ENV{'PDK'}=$magictech; + +sub getCellLibrary($) +{ + return "gf180mcu_fd_sc_mcu9t5v0" if($_[0]=~m/gf180/i); + return "sky130_fd_sc_hd" if($_[0]=~m/sky130/i); + return ""; +} + +my $celllibrary=getCellLibrary($ENV{'PDK'}); + +my $branch=$ENV{'CARAVEL_BRANCH'} || "gfmpw-1c"; # Git Branch for the Caravel User Project + +sub system_v($) +{ + print "$_[0]\n"; + return system($_[0]); +} + +sub step($) +{ + print "$_[0]\n"; + print STDERR "$_[0]\n"; +} + +sub nextgroup($) +{ + $CARAVEL="gf180_stdcelllib_$_[0]"; + $CARAVEL="sky130_stdcelllib_$_[0]" if($ENV{'PDK'}=~m/sky130/i); + + if($ngroups>=$maxdesigns) + { + print STDERR "Stopping at the defined limit of maximum $maxdesigns designs.\n"; + return(undef); + } + unless(-d $CARAVEL) + { + system_v "git clone git\@github.com:efabless/caravel_user_project.git -b $branch $CARAVEL"; + return(undef) unless(-d $CARAVEL); + } + push @repos,$CARAVEL; + $ngroups++; + return $CARAVEL; +} + +sub addcell($$) +{ + my ($group,$cn)=@_; + print "Adding cell $cn to group $group\n"; + $assigned{$CARAVEL}{$cn}=1; + mkdir "$CARAVEL/cells"; + mkdir "$CARAVEL/cells/mag"; + mkdir "$CARAVEL/cells/lib"; + mkdir "$CARAVEL/cells/cell"; + mkdir "$CARAVEL/cells/sp"; + mkdir "$CARAVEL/cells/lef"; + mkdir "$CARAVEL/cells/lef/orig"; + mkdir "$CARAVEL/cells/gds"; + mkdir "$CARAVEL/cells/truthtable"; + system "cp $cn.mag $CARAVEL/cells/mag/"; + system "cp $cn.lib $CARAVEL/cells/lib/" if(-f "$cn.lib"); + system_v "perl ../Tools/perl/dummychar.pl $cn >$CARAVEL/cells/lib/$cn.lib" unless(-f "$cn.lib"); + system "cp $cn.cell $CARAVEL/cells/cell/"; + system "cp $cn.sp $CARAVEL/cells/sp/"; + system "cp $cn.truthtable.txt $CARAVEL/cells/truthtable/"; + system "cp outputlib/$cn.lef $CARAVEL/cells/lef/orig/"; + system "cp outputlib/$cn.gds $CARAVEL/cells/gds/"; +} + +sub endgroup($) +{ + my $CARAVEL=$_[0]; + + #$ENV{'STD_CELL_LIBRARY'}='sky130_fd_sc_ls'; + $ENV{'STDCELLLIB'}='../'; # /home/philipp/libresilicon/StdCellLib + $ENV{'OPENLANE_ROOT'}=$ENV{'PWD'}."/$CARAVEL/dependencies/openlane_src"; # =$(readlink -f $(pwd)/../openlane ) + #$ENV{'OPENLANE_TAG'}="gfmpw-0c"; + $ENV{'CARAVEL'}=$ENV{'PWD'}."/$CARAVEL"; # =$(pwd) + $ENV{'CARAVEL_ROOT'}=$ENV{'PWD'}."/$CARAVEL/caravel"; + $ENV{'PDK_ROOT'}=$ENV{'PDK_ROOT'} || ($ENV{'PWD'}."/$CARAVEL/dependencies/pdks"); # =$(readlink -f $(pwd)/../pdk ) + #$ENV{'PDK'}="gf180mcuD"; + $ENV{'MCW_ROOT'}=$ENV{'PWD'}."/$CARAVEL/mgmt_core_wrapper"; + #$ENV{'PATH'}.=#export PATH=$PATH:$(readlink -f $(pwd)../openlane_summary/ ) + print "Writing Environment file for easy debugging, just \"source env.sh\" when you need it:\n"; + open OUT,">$CARAVEL/env.sh"; + foreach(qw(STDCELLLIB OPENLANE_ROOT CARAVEL CARAVEL_ROOT PDK_ROOT PDK MCW_ROOT)) + { + print OUT "export $_=\"".$ENV{$_}."\"\n"; + } + close OUT; + + + my $pdk=$ENV{'PDK'}; + my $foundry=($pdk=~m/^sky/i)?"SkyWater":($pdk=~m/^gf/i)?"GlobalFoundries":($pdk=~m/^ls/i)?"LibreSilicon":($pdk=~m/^tsmc/i)?"TSMC":"Unknown foundry"; + open OUT,">$CARAVEL/info.yaml"; + print OUT <$CARAVEL/README.md"; + print OUT <verilog/rtl/user_defines.v"; + + + chdir "cells/lef"; + step("fixup_lef $CARAVEL"); + system "perl ../../../../Tools/caravel/fixup_lef.pl ../../../../Tech/libresilicon.tech"; + chdir "../../../"; + chdir "$CARAVEL/cells/mag"; + step("fixup_mag $CARAVEL"); + system "perl ../../../../Tools/caravel/fixup_mag.pl ../../../../Tech/libresilicon.tech" if($magictech eq "sky130A"); + chdir "../../../"; + chdir "$CARAVEL/cells/sp"; + step("fixup_sp $CARAVEL"); + system "perl ../../../../Tools/caravel/fixup_sp.pl ../../../../Tech/libresilicon.tech"; + chdir "../../../"; + chdir "$CARAVEL/cells/gds"; + step("fixup_gds $CARAVEL"); + #system "python3 ../../../../Tools/caravel/scale10.py"; + chdir "../../../"; + + + chdir "$CARAVEL/cells/lib"; + step("libertymerge"); + system_v "libertymerge -b ../../../libresilicon.libtemplate -o libresilicon.lib -u *.lib"; + step("removenl"); + system "perl ../../../../Tools/caravel/removenl.pl >new.lib"; + rename "libresilicon.lib","libresilicon.lib.orig"; + rename "new.lib","libresilicon.lib"; + chdir "../../../"; + + step("config"); + chdir $CARAVEL; + + system_v "perl ../../Tools/caravel/configgen.pl >openlane/user_proj_example/config.json"; + + +open OUT,">openlane/user_proj_example/config.tcl"; +print OUT <>openlane/user_proj_example/pin_order.cfg")) + { + foreach(16..37) + { + print OUT "io_in\\[$_\\]\n"; + print OUT "io_out\\[$_\\]\n"; + print OUT "io_oeb\\[$_\\]\n"; + } + close OUT; + } + + + + step("generator"); + chdir $CARAVEL; + system "perl ../../Tools/caravel/generator.pl >verilog/rtl/user_proj_example.v"; + step("cells"); + system "perl ../../Tools/caravel/cells.pl >verilog/rtl/user_proj_cells.v"; + step("placement"); + system "perl ../../Tools/caravel/placement.pl >openlane/user_proj_example/macro_placement.cfg"; + + step("verification"); + mkdir "verilog/dv/stdcells",0755; + mkdir "verilog/dv/cocotb",0755; + system "cp ../../Tools/caravel/stdcells_tb.v verilog/dv/stdcells/"; + system "cp verilog/dv/io_ports/Makefile verilog/dv/stdcells/" if(-f "verilog/dv/io_ports/Makefile"); + chdir "cells/cell"; + system_v "perl ../../../../Tools/perl/testgen.pl >../../verilog/dv/stdcells/stdcells.c"; + chdir "../../"; + + step("make setup"); + system_v "make setup"; + step("make user_proj_example"); + system_v "make user_proj_example && make user_project_wrapper"; + if($doverification) + { + system_v "make simenv"; + system_v "make verify-stdcells-rtl"; + } + system_v "make dist"; + + if(0) + { + system_v "git add cells env.sh verilog/rtl/user_proj_cells.v verilog/rtl/user_proj_example.v openlane/user_proj_example/* info.yaml verilog/dv/stdcells"; + system_v "git commit -m \"Automatically generated files\""; + system_v "git add -u ."; + system_v "git add gds/*"; + system_v "git commit -m \"Openlane generated files\""; + system_v "git remote remove origin"; + system_v "git remote add origin git\@github.com:$githubuser/$CARAVEL.git"; + system_v "echo git push origin HEAD:main -f"; + } + else + { + #system_v "git clone ssh://git\@repositories.efabless.com/$efablessuser/$CARAVEL.git"; + system_v "git remote rename origin upstream"; + system_v "git remote add origin ssh://git\@repositories.efabless.com/$efablessuser/$CARAVEL.git"; + #system_v "cd gf180_stdcelllib_1"; + #system_v "git checkout -b main"; + system_v "touch README.rst"; + system_v "git add README.rst"; + system_v "git commit -m \"Add README file\""; + system_v "echo git push -u origin main"; + + } + chdir ".."; +} + +print "Selecting first group:\n"; +nextgroup($group); +# Too complex cells:AAOAOI33111.cell AAOOAAOI2224.cell AOAAOI2124.cell OAAAOI2132.cell OAAOAOI21311.cell OAAOI224.cell OAOOAAOI21132.cell AAAAOI3322.cell AAAOAI3221.cell AAAOAOI33311.cell AAAOI222.cell +my @cells=qw(NAND2.cell AAAOI333.cell AAOI22.cell AOAI221.cell AOI21.cell ASYNC1.cell ASYNC2.cell ASYNC3.cell INV.cell MARTIN1989.cell MUX2.cell MUX3.cell MUX4.cell MUX8.cell NAND3.cell NAND4.cell NOR2.cell NOR3.cell NOR4.cell OAI41.cell OOOOAI3332.cell OR4.cell sutherland1989.cell vanberkel1991.cell ); +#push @cells,<*.cell>; +my %seen=(); + +print "Adding all the cells onboard the Caravels:\n"; +foreach my $cell (@cells) +{ + next if(defined($seen{$cell})); + $seen{$cell}=1; + my $thisios=0; + my $cn=$cell; $cn=~s/\.cell$//; + next if(-f "cn.dontuse"); + if(! -s "$cn.truthtable.v") + { + print "The cell $cell has an empty and unusable truthtable.\n"; + next; + } + if(-f "outputlib/$cn.gds") + { + open IN,"<$cell"; + while() + { + if(m/^\.(inputs|outputs) (.*)$/) + { + @ins=split(" ",$2); + $thisios+=@ins; + } + } + close IN; + $totalios+=$thisios; + if(($usedios+$thisios)>$maxios) + { + $usedios=0; + $group++; + print "NEXT GROUP\n"; + my $res=nextgroup($group); + last unless($res); + } + $usedios+=$thisios; + $totalios+=$thisios; + print "$group $cn $thisios\n"; + addcell($group,$cn); + } + +} +print "Now shipping all the Caravels\n"; +endgroup($_) foreach(@repos); +print "All Caravels are done.\n"; diff --git a/Tools/perl/demoboard.pl b/Tools/perl/demoboard.pl new file mode 100755 index 00000000..4f598b29 --- /dev/null +++ b/Tools/perl/demoboard.pl @@ -0,0 +1,156 @@ +#!/usr/bin/perl -w + +my $times=$ARGV[0] || 1; + +my @cells=(); + +foreach my $cell (<*.cell>) +{ + my $name=$cell; $name=~s/\.cell$//; + next unless (-f "$name.mag"); + push @cells,$cell foreach(1 .. $times); +} + +my $squared=sqrt(scalar(@cells)||1); + +print STDERR "Cells: ".scalar(@cells)." Squared: $squared\n"; + +sub mymin($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[1]:$_[0]; +} + +sub mymax($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[0]:$_[1]; +} + + + +my $counter=0; +our $x=0; +our $y=0; + +my $now=0; # time(); # 0 indicates that DRC needs to be run + +my $usedtech="scmos"; + +our $labels=""; + +our $row=0; + +our $printedheader=0; + +our $magscale=undef; + +our $usebbox=1; + + +foreach(@cells) +{ + my @mins=(); + my @maxs=(); + my $mag=$_; $mag=~s/\.cell$/.mag/; + my $name=$_; $name=~s/\.cell$//; + my $timestamp="0"; # Indicates that DRC needs to be run + + if(open(IN,"<$mag")) + { + my $layer=""; + while() + { + $magscale=$1 if(m/^magscale (\d+ \d+)/); + $usedtech=$1 if(m/^tech (\w+)/); + #$timestamp=$1 if(m/^timestamp (\d+)/); + # + if(m/^<< (\w+) >>/) + { + $layer=$1; + } + if(m/^string FIXED_BBOX (-?\d+) (-?\d+) (-?\d+) (-?\d+)$/ && $usebbox) + { + @mins=($2,$1); + @maxs=($4,$3); + } + next if($layer eq "checkpaint"); + if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/ && !$usebbox) + { + #print STDERR "$name min:@mins max:@maxs $_"; + my @a=split " ",$_; + foreach(1 .. 4) + { + $mins[$_&1]=mymin($mins[$_&1],$a[$_]); + $maxs[$_&1]=mymax($maxs[$_&1],$a[$_]); + } + } + } + close IN; + } + next unless(defined($maxs[0])); + + print STDERR "$name maxs: ".join("/",@maxs)." "; + print STDERR "mins: ".join("/",@mins)." "; + + + if(!$printedheader) + { + print <> +rect -100 -100 10000 10000 +EOF +; + $printedheader=1; + } + + + + my $height=$maxs[0]+$mins[0]; + my $width=$maxs[1]-$mins[1]; + print STDERR "Cell-Width: $width Cell-Height: $height\n"; + + my $dir=($row%2)?"-1":"1"; + + my $bx=$x; + my $by=$y; # -$mins[0]; + + if($row%2) + { + $bx=$x+$width; + $by=$y+$height; # +$mins[0]; + } + print "use $name $name"."_0\n"; + print "timestamp $timestamp\n"; + print "transform $dir 0 $bx 0 $dir $by\n"; + print "box 0 0 $width $height\n"; + #print STDERR "$name $width $height\n"; + + my $lx=$x+int($width/2); + my $ly=$y+int($height/2); + + $labels.="flabel space $lx $ly $lx $ly 0 FreeSans 80 0 0 0 $name\n"; + + $x+=$width; + if(int($counter/$squared)>int(($counter-1)/$squared)) + { + $x=0; + $y+=$height; + $row++; + } + + $counter++; +} +print "<< labels >>\n"; +print $labels; + +print "<< end >>\n"; + + diff --git a/Tools/perl/disp2svg.pl b/Tools/perl/disp2svg.pl new file mode 100755 index 00000000..c20aebec --- /dev/null +++ b/Tools/perl/disp2svg.pl @@ -0,0 +1,40 @@ +#!/usr/bin/perl -w +use strict; + +my $data=<' + + +EOF +; +# +while($a=) #foreach my $a(split "\n",$data) +{ + if($a=~m/routing_nodes: \{(.*?)\}/) + { + foreach my $c (split('\), \(',$1)) + { + if($c=~m/(\d+), (\d+)/) + { + print "\n"; + } + } + } + if($a=~m/terminal_region: \((.*?)\)/) + { + my $d=$1; $d=~s/,/;/g; + my @l=split(';',$d); + print ""; + } +} + +print ""; diff --git a/Tools/perl/dorest.pl b/Tools/perl/dorest.pl new file mode 100755 index 00000000..63e4dc81 --- /dev/null +++ b/Tools/perl/dorest.pl @@ -0,0 +1,10 @@ +foreach (<*.cell>) +{ + my $cellname=$_; + $cellname=~s/\.cell$//; + next if(-f "$cellname.mag"); + print "We should do $_\n"; + system "touch $_"; + $ENV{'CELL'}=$cellname; + system "make layout"; +} diff --git a/Tools/perl/draw.pl b/Tools/perl/draw.pl new file mode 100755 index 00000000..f32a660b --- /dev/null +++ b/Tools/perl/draw.pl @@ -0,0 +1,168 @@ +#!/usr/bin/perl -w +use strict; + +##Initialze pointer +my $x=0; +my $y=0; + +my $psc_width=4; +my $psc_height=4; +my $psc_spacing=4; + +my $poly_width=2; +my $ndc_width=4; # NSC? +my $poly_to_ndc_spacing=1; + +my $nwell_over_active=6; + +my $poly_over_active=5; + +my $ground_strip_height=4; +my $power_strip_height=4; +my $nsc_width=4; +my $nsc_height=4; +my $nsc_spacing=4; +my $extension_over_active=3; +my $poly_to_active_spacing=1; +my $metal_width=3; +my $ndc_to_ndc_spacing=2; +my $active_width=3; +my $ndiff_height=17; +my $pdiff_height=17; + + + +my $fnin=$ARGV[0] || "../../Catalog/INV.cell"; +my $fnout=$ARGV[1] || "output.mag"; + +my @inputs=(); +my @outputs=(); + +# Loading the cell file and parsing the inputs and outputs: +# TODO: This does not work when the inputs and ouputs are not added in the header! +if(open(IN,"<$fnin")) +{ + print "Parsing $fnin\n"; + while() + { + @inputs=split " ",$1 if(m/\.inputs (.*)/); + @outputs=split " ",$1 if(m/\.outputs (.*)/); + } + close IN; +} + +# Generating the euler path from the cell netlist. We need the nmos transistors and we need the VDD+GND nets. +# TODO: The pmos euler network might not work for the calculated nmos network. How do we want to handle that? +my $euler=`perl euler.pl --network nmos --power $fnin`; +my @eulerp=split ",",$euler; + +my @eulers=(); +foreach(@eulerp) +{ + push @eulers,$_ if(m/^[A-W]\d*$/); # We extract only the inputs from the euler path which also contained the nets +} + + +print "Inputs: ".join(",",@inputs)." Outputs: ".join("-",@outputs)." Euler: $euler Eulers: ".join(",",@eulers)."\n"; + + +my $number_of_inputs=scalar(@inputs); +print "Number of Inputs: $number_of_inputs\n"; + +if($number_of_inputs==0) +{ + print STDERR "Error: No inputs found.\n"; + exit; +} + +# Now the graphical dimensions are calculated, primarily based on the number of inputs: +my $poly_spacing= $ndc_width + $poly_to_ndc_spacing*2 ; # =6 +my $ndiff_width=$poly_width*$number_of_inputs+$poly_spacing*($number_of_inputs+1); # 12+42=54; +my $ground_strip_width=$nwell_over_active+$ndiff_width+$nwell_over_active; # =66 +my $nwell_width=$ground_strip_width; # 66 +my $nwell_height=$extension_over_active+$psc_height+$poly_over_active+$ndiff_height+$nwell_over_active; # =35 +my $pdiff_width=$ndiff_width; +my $poly_height=52; # TODO this hardcoded value needs to be made dynamic # $extension_over_active+$ndiff_height+$nwell_over_active+?+$pdiff_height+$nwell_over_active +my $power_strip_width=$ground_strip_width; # 66 + + +# Now generate the file for the tool magic: +open MAG,">$fnout"; +print MAG "magic\ntech scmos\ntimestamp ".time()."\n"; + +#box draws a box at position ($x $y $sizex $sizey label) +sub box +{ + print MAG "<< $_[4] >>\nrect $_[0] $_[1] ".($_[0]+$_[2])." ".($_[1]+$_[3])."\n"; + if(defined($_[5])) + { + my $midx=$_[0]+$_[2]/2; + my $midy=$_[1]+$_[3]/2; + print MAG "<< labels >>\n"; + print MAG "rlabel $_[4] $midx $midy $midx $midy 1 $_[5]\n"; + } +} + + +##Create ground strips### +box($x,$y,$ground_strip_width,$ground_strip_height,"metal1","gnd!"); + + +##Create p-substrate contact## +my $psc_box_position=$x-4; +my $number_of_psc=$ground_strip_width/8; +for my $i (1 .. $number_of_psc) +{ + $psc_box_position+=8; + box($psc_box_position,$y,$psc_width,$psc_height,"psc"); + #box move right $psc_spacing +} + +##Create n-diff area## +my $ndiff_box_position_x=$x+6; +my $ndiff_box_position_y=$y+9; +box($ndiff_box_position_x,$ndiff_box_position_y,$ndiff_width,$ndiff_height,"ndiff"); + +#Create n-well area## +my $nwell_box_position_x=$x+0; +my $nwell_box_position_y=$y+32; +box($nwell_box_position_x,$nwell_box_position_y,$nwell_width,$nwell_height,"nwell"); + +##Create p-diff area## +my $pdiff_box_position_x=$x+6; +my $pdiff_box_position_y=$y+38; +box($pdiff_box_position_x,$pdiff_box_position_y,$pdiff_width,$pdiff_height,"pdiff"); + +##Create poly-strips## +my $poly_box_position_x=$x+12; +my $poly_box_position_y=$y+6; +my $number_of_poly_strips=$number_of_inputs; +foreach my $i (1 .. $number_of_inputs) +{ + box($poly_box_position_x,$poly_box_position_y,$poly_width,$poly_height,"poly",$eulers[$i-1]); + $poly_box_position_x+=8; +} + +##Create power strips### +box($x,$y+60,$power_strip_width,$power_strip_height,"metal1","vdd!"); + +##Create n-substrate contact## +my $nsc_box_position_x=$x-4; +my $nsc_box_position_y=$y+60; +my $number_of_nsc=int($power_strip_width/8); + +foreach my $i (1 .. $number_of_nsc) +{ + $nsc_box_position_x+=8; + box($nsc_box_position_x,$nsc_box_position_y,$nsc_width,$nsc_height,"nsc"); + #box move right $nsc_spacing +} + +print MAG "<< end >>\n"; +close MAG; +system "magic -d XR $fnout"; +# Now we need magic 4.2 with kairos support compiled in for SVG export: +open MAGIC "|magic -d XR $fnout -noconsole"; +print MAGIC "plot svg $fnsvg\nquit\n"; +close MAGIC; + diff --git a/Tools/perl/drccheck.pl b/Tools/perl/drccheck.pl new file mode 100755 index 00000000..eafe0f53 --- /dev/null +++ b/Tools/perl/drccheck.pl @@ -0,0 +1,56 @@ +#!/usr/bin/perl -w + +my $mag=$ARGV[0] || ""; $mag=~s/\.mag$//i; + +my $tech=$ARGV[1] || "../Tech/libresilicon.tech"; + +print "drccheck.pl - Check DRC rules with magic\n"; +print "Usage: drccheck.pl input.mag\n" if(scalar(@ARGV)<1); + +my $style="drc(fast)"; # "drc(full)"; + +if(-f "$mag.mag") +{ + open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; + my $outfile="$mag.drc"; + + print OUT < \$l$_\n\" if(\$debug);\n" if($types[$_] eq "type-list"); + print " my \$text=\$$_;\n" if($types[$_] eq "why"); + push @typelists,$_ if($types[$_] eq "type-list"); + } + print " print \" "; + foreach(1 .. scalar(@types)-1) + { + print "\$$_ " if($types[$_] eq "other"); + print "\$vl$_ " if($types[$_] eq "type-list"); + if($types[$_] eq "why") + { + print "\\\"\$$_ "; + #print "[erase ".join(",",@typelists)."]"; + foreach my $tl (@typelists) + { + print "[erase \$l$tl]"; + } + print "\\\""; + } + } + print "\\n\";\n"; + print " }\n"; + print "\n"; + # $1 $vl1 $vl2 $4 $5 \"$6 [erase $l1]".(($vl1 eq $vl2)?"":"[erase $l2]")."\"\n"; + + +} + +exit if($createrules); + +#magic: tech layers allli +# At first we are reading through the original tech file to search for all the virtual layers that need to be expanded +open IN,"<$tech"; +undef $/; +my $content=; +$/="\n"; +$content=~s/\\\n//sg; + +foreach(split("\n",$content)) +{ + s/\\//g; + if(m/^\s*(spacing|surround)\s+(\S+)\s+(\S+)\s+/) + { + my $a2=$2; + my $a3=$3; + $alias{$a2}=1; + $alias{$a3}=1; + foreach(split(",",$a2)) + { + $alias{$_}=1; + $alias{$1}=1 if(m/^([^\/]+)/); + } + foreach(split(",",$a3)) + { + $alias{$_}=1; + $alias{$1}=1 if(m/^([^\/]+)/); + } + } + # Rule: width type-list width error + if(m/^\s*(width)\s+(\S+)\s+(\S+)\s+"([^"]*)"\s*$/) + { + $alias{$2}=1; + foreach(split(",",$2)) + { + $alias{$_}=1; + } + } +} +close IN; + + +if($debug) +{ + print STDERR "BEFORE:\n"; + foreach(sort keys %alias) + { + print STDERR "$_ -> $alias{$_}\n"; + } +} + +# No we are asking magic what those virtual layers actually mean + print STDERR "Running magic -T $tech ...\n"; + if(open OUT,"|magic -dnull -noconsole -T $tech >magic.layers.out") + { + print OUT "puts \"CUT HERE -------- CUT HERE\"\n"; + foreach(sort keys %alias) + { + s/\(// unless(m/\)/); + s/\)// unless(m/\(/); + #print STDERR "[tech layers $_]\n"; + print OUT "puts \"EXPANDING: $_\"\n"; + print OUT "puts [tech layers $_]\n"; + } + print OUT "puts \"CUT HERE -------- CUT HERE\"\n"; + print OUT "quit -noprompt\n"; + close OUT; + + # Now we are retrieving the answer from Magic: + if(open IN,") + { + if(m/^EXPANDING: (\S+)/) + { + my $next=; + chomp $next; + $alias{$1}=$next; + } + } + close IN; + } + else + { + die "Could not get the results from magic!\n"; + } + } + else + { + die "Could not run magic!\n"; + } + print STDERR "Done with magic.\n"; + + +if($debug) +{ + print STDERR "\n\nAFTER:\n"; + foreach(sort keys %alias) + { + print STDERR "$_ -> $alias{$_}\n"; + } + exit; +} + +open IN,"<$tech"; + +# This function expands a single layer-list into all the physical layers it means +sub allLayers($) +{ + #if($_[0] !~ m/\//) # If we do not look for "images" (which are signalled by / in the typelist and are currently not supported by magic), then we can just use the whole typelist which is more efficient. + #{ + #return split " ",$alias{$_[0]} ; + #} + + my @a=split ",",$_[0]; + my %b=(); + foreach(@a) + { + print STDERR "piece: $_\n" if($debug); + if(m/(\/\S+)/ && defined($alias{$_}) && $alias{$_}) + { + print STDERR "WE FOUND A SLASH AND AN ALIAS\n" if($debug); + my $image=$1; + foreach my $part(split " ",$alias{$_}) + { + print STDERR "PART: $part\n" if($debug); + $b{$part.(($part =~ m/\//)?"":$image)}=1; + } + } + elsif(m/^([^\/]+)(\/\S+)/) # This is a workaround for bugs in magic that hopefully get fixed + { + print STDERR "WE FOUND A SLASH BUT NO ALIAS\n" if($debug); + my $image=$2; + my $short=$1; + foreach my $part(split " ",$alias{$short}) + { + print STDERR "PART: $part\n" if($debug); + $b{$part.$image}=1; + } + } + else + { + print STDERR "NO SLASH OR ALIAS\n" if($debug); + foreach my $part(split " ",$alias{$_}) + { + $b{$part}=1; + } + } + } + return sort keys %b; +} + +my $section=""; +our %drckind=(); +# Finally we are processing the whole tech file and annotating the rules: +while() +{ + while($_=~m/\\$/) + { + $_.=; + } + if(m/^(\w+)/) + { + $section=$1; + } + # if($section eq "contact" && m/^\s+(\w+)/) + #{ + # my $a=$_; + # $a=~s/^\s+//; $a=~s/\s+$//; + # my @a=split(/\s+/,$a); + # my $cont=shift(@a); + # foreach my $cnt(@a) + # { + # print STDERR "CONTACT: $cont -> $cnt\n"; + # $contacts{$cont}{$cnt}=1; + # $contacts{$cnt}{$cont}=1; + # } + #} + #if($section eq "aliases" && m/^\s+(\w+)/) + #{ + # my $a=$_; + # $a=~s/^\s+//; $a=~s/\s+$//; + # my @a=split(/\s+/,$a); + # my $cont=shift(@a); + # foreach my $cnt(@a) + # { + # print STDERR "ALIAS: $cont -> $cnt\n"; + # $alias{$cont}=$cnt; + # } + #} + my $oneline=$_; + $oneline=~s/\n//sg; + tr/\\//; + if($section eq "drc") + { + if(m/^\s*(\w+)/) + { + $drckind{$1}=1; + } + } + + + if(m/^\s*(spacing|surround)\s+(\S+)\s+(\S+)\s+(\d+)\s+\\?\s*(\w+)\s+\\?\s*"([^"]+)"/) + { + #print " # ORIGINAL RULE:$oneline\n"; + my $vl1=$2; + my $vl2=$3; + my $text=$6; + my $l1=join " ",allLayers($vl1); + print STDERR "L1: $vl1 -> $l1\n" if($debug); + my $l2=join " ",allLayers($vl2); + print STDERR "L2: $vl2 -> $l2\n" if($debug); + + if($expand) + { + foreach my $layer1(allLayers($vl1)) + { + foreach my $layer2(allLayers($vl2)) + { + #print " $1 $layer1 $layer2 $4 $5 \"$6 [erase $layer1]".(($layer1 eq $layer2)?"":"[erase $layer2]")."\"\n"; + } + } + } + else + { + print " $1 $vl1 $vl2 $4 $5 \"$6 [erase $l1".(($vl1 eq $vl2)?"":",$l2")."]\"\n"; + } + #print "\n"; + } + # Rule: width type-list width error + elsif(m/^\s*(width)\s+(\S+)\s+(\S+)\s+"([^"]*)"\s*$/) + { + print " # ORIGINAL RULE:$oneline\n"; + my $vl2=$2; + print STDERR "ALLLAYERS $vl2\n" if($debug); + my $l2=join ",",allLayers($vl2); # For painting we need a different strategy to try each layer individually + print STDERR "INFO: vl2=$vl2 l2=$l2\n" if($debug); + my $text=$4; + print " $1 $vl2 $3 \"$4 [paint $l2]\"\n"; + } + + + else + { + print $_; + } +} +close IN; + +print STDERR "".join(",", sort keys %drckind)."\n"; diff --git a/Tools/perl/drcfix.pl b/Tools/perl/drcfix.pl new file mode 100755 index 00000000..7529a33d --- /dev/null +++ b/Tools/perl/drcfix.pl @@ -0,0 +1,160 @@ +#!/usr/bin/perl -w +use File::Basename (); + +if(scalar(@ARGV)<1) +{ + print "Usage: drcfix.pl problematic.mag [techfile.tech] [DRC rule deck]\n"; + exit; +} + +# Rules we have to deal with: + +#Local interconnect spacing < 0.17um (LI 3) +#Metal1 spacing < 0.14um (Met1 2) + +print "Handling $ARGV[0]\n"; +open IN,"<".$ARGV[0]; +my $mag=$ARGV[0];$mag=~s/\.drc$/.mag/; $mag=~s/\.mag\.mag/\.mag/; +my $output="corr_$mag"; +my $tcl=$mag; $tcl=~s/\.mag$/.drc.tcl/; +my $mode=0; +my $try=1; +my $debug=1; + +sub form($) +{ + return int($_[0]*100); +} + +my $insert=""; +our $tech=$ARGV[1] || "../Tech/libresilicon.tech"; +our $drcstyle=$ARGV[2] || ""; + +#sub tryfix($) +#{ + print "Trying the fix on $mag:\nRuning magic ...\n"; + + my $bindir = File::Basename::dirname($0); + open IN,"<$bindir/drcfix.tcl"; + undef $/; + $todo=; + close IN; + + $todo=~s/\$OUTPUT/$output/sg; + $todo=~s/\$MAG/$mag/sg; + $todo=~s/\$DRCSTYLE/$drcstyle/sg; + +if($debug) +{ + open OUT,">$tcl"; + print OUT $todo; + close OUT; + system "magic -dnull -rcfile $tcl -noconsole -T $tech"; +} +else +{ + open OUT,"|magic -dnull -noconsole -nowindow -T $tech"; + print OUT $todo; + close OUT; +} + +#tryfix(); + +if(0) +{ + +while() +{ + if(m/Mcon spacing < 0\.17um \(Mcon 2\)/) + { + $mode="viali"; + my $dummy=; + print "Found my rule\n"; + next; + } + if(m/Diffusion contact spacing < 0.17um \(LIcon 2\)/) + { + $mode="ndiffc"; + my $dummy=; + print "Found my rule\n"; + next; + } + if(m/Local interconnect spacing < 0.17um \(LI 3\)/) + { + $mode="li_spacing"; + my $dummy=; + print "Found my rule\n"; + next; + } + + if(m/\-\-\-\-\-\-\-\-\-\-\-/) + { + $mode=0; + print "End of rule\n"; + next; + } + + + if($mode eq 1) + { + my @line1=split " ",$_; + my $l2=; + my @line2=split " ",$l2; + print "LINE1 (@line1): $_\nLINE2 (@line2): $l2\n"; + if($line1[0] eq $line2[0] && $line1[2] eq $line2[2] && $line1[1]<$line2[1]) + { + print "Vertikal\n"; + print "@line1 - @line2\n"; + $insert.="<< $mode >>\nrect ".form($line1[0])." ".form($line1[3])." ".form($line1[2])." ".form($line2[1])."\n"; + } + elsif($line1[1] eq $line2[1] && $line1[3] eq $line2[3] && $line1[0]<$line2[0]) + { + print "Horizontal\n"; + print "@line1 - @line2\n"; + $insert.="<< $mode >>\nrect ".form($line1[2])." ".form($line1[1])." ".form($line2[3])." ".form($line1[1])."\n"; + } + + } + + + if($mode eq "li_spacing") + { + my @line1=split " ",$_; + my $l2=; + my @line2=split " ",$l2; + print "LINE1 (@line1): $_\nLINE2 (@line2): $l2\n"; + #if($line1[0] eq $line2[0] && $line1[2] eq $line2[2] && $line1[1]<$line2[1]) + #{ + # print "Vertikal\n"; + # print "@line1 - @line2\n"; + tryfix("box position $line1[0] $line1[1]\nbox size $line2[0] $line2[1]\nerase li\n"); + # $insert.="<< $mode >>\nrect ".form($line1[0])." ".form($line1[3])." ".form($line1[2])." ".form($line2[1])."\n"; + #} + #elsif($line1[1] eq $line2[1] && $line1[3] eq $line2[3] && $line1[0]<$line2[0]) + #{ + # print "Horizontal\n"; + # print "@line1 - @line2\n"; + # $insert.="<< $mode >>\nrect ".form($line1[2])." ".form($line1[1])." ".form($line2[3])." ".form($line1[1])."\n"; + #} + + } + + +} +close IN; + +open MAG,"<$mag"; +open CORR,">corr.$mag"; +print "Reading from $mag Writing to corr.$mag\n"; +while() +{ + if(m/<< end >>/) + { + print CORR $insert; + } + print CORR $_; +} +close CORR; +close MAG; + +} diff --git a/Tools/perl/drcfix.tcl b/Tools/perl/drcfix.tcl new file mode 100755 index 00000000..889f1625 --- /dev/null +++ b/Tools/perl/drcfix.tcl @@ -0,0 +1,178 @@ +proc redirect_variable {varname cmd} { + rename puts ::tcl::orig::puts + global __puts_redirect + set __puts_redirect {} + proc puts args { + global __puts_redirect + set __puts_redirect [concat $__puts_redirect [lindex $args end]] + set args [lreplace $args end end] + if {[lsearch -regexp $args {^-nonewline}]<0} { + set __puts_redirect "$__puts_redirect\n" + } + return + } + uplevel $cmd + upvar $varname destination + set destination $__puts_redirect + unset __puts_redirect + rename puts {} + rename ::tcl::orig::puts puts +} + +proc getCheckpoint {} { + #save checkpoint + #return + redirect_variable undostack {undo print 10} + #puts "Undostack: $undostack" + #head=0xd620c840 tail=0xd5b648a0 cur=0xd5b648a0 + regexp {cur=(0x\w+)} $undostack full cur + #puts "cur: $cur" + undo print 20 + return $cur +} + +proc undoToCheckpoint {checkpoint} { + #load checkpoint + #return + redirect_variable undostack {undo print 10} + regexp {cur=(0x\w+)} $undostack full cur + regexp {head=(0x\w+)} $undostack full head + #undo print 20 + if {$head ne 0x0} { + if {$checkpoint == 0x0} { + set checkpoint $head + } + set tries 0 + while {$cur ne $checkpoint && $cur ne 0x0 && $tries < 200 } { + #puts "Undo ..." + undo + #undo print 20 + redirect_variable undostack {undo print 10} + regexp {cur=(0x\w+)} $undostack full cur + incr tries + } + if {$tries > 180} { + puts "WARNING: $tries tries were tried, this is strange" + #undo print 20 + } + } +} + +#getCheckpoint + +proc fix_drc {} { + puts "select top cell" + select top cell + puts "drc style $DRCSTYLE" + drc style $DRCSTYLE + puts "drc on" + drc on + puts "drc check" + drc check + puts "drc catchup" + drc catchup + puts "drc listall catchup" + drc listall catchup + puts "drc find" + drc find + puts "drc check" + drc check + puts "drc catchup" + drc catchup + set ndebugfile 1 + puts "Redirecting Variable" + redirect_variable drccount {drc count total} + puts "Setting checkpoint" + set checkpoint [getCheckpoint] + puts "Checkpoint: $checkpoint" + set nFixed 0 + puts "DRC count: $drccount" + set drcc [string trim [string map {"Total DRC errors found: " ""} $drccount] ] + if {$drcc == 0} return + set yReposition {0 2 -2 9 -9} + + foreach yRepo $yReposition { + puts "Trying Reposition $yRepo" + set nRounds $drcc + puts $drccount + #puts $drcc + for {set i 0} {$i <= $nRounds + 10 } {incr i} { + puts "I am inside the first loop: $i" + if {$drcc > 0} { + redirect_variable drcresult {drc find} + puts "move up $yRepo" + move up $yRepo + puts $drcresult + if {[string first "\[" $drcresult] != -1} { + regexp {\[(erase|paint) ([^\]]+)\]} $drcresult full drccommand layernames + if {$yRepo != 0 } { + puts "This is an addition for Sky130: We have some 20nm wide inter-net spacings that we need to paint on locali, so we reposition the box and try to paint on locali" + set drccommand "paint" + set layernames "locali" + } + if {$drccommand == "erase" } { + redirect_variable bbox {box} + #lambda: 44 x 10 ( 0, 309 ), ( 44, 319 ) 440 + #lambda: 2.00 x 8.50 ( 463.50, 217.50), ( 465.50, 226.00) 17.00 + puts "BOX: $bbox" + regexp {lambda:\s*\d+\.?\d* x \d+\.?\d*\s+\([^\)]*\), \(\s*(\d+\.?\d*),\s*(\d+\.?\d*)} $bbox full boxX boxY + puts "Bounding box for erase: $boxX $boxY" + if {$boxY >= 309 } { + puts "This is an addition for Sky130: We do not want to erase the power rails, so we skip ignore rules outside the core of the cell" + set layernames "" + } + } + foreach drcparts [split $layernames ","] { + puts "Trying layers $drcparts" + foreach layername [split $drcparts " "] { + puts "$drccommand $layername" + $drccommand $layername + puts "done with this layer." + } + # save "$OUTPUT.try.$ndebugfile" + incr ndebugfile + drc check + drc catchup + redirect_variable drccountnew {drc count total} + set drccn [string trim [string map {"Total DRC errors found: " ""} $drccountnew] ] + if {$drccn == 0} { + puts "We have fixed all issues, no need to try more" + save $OUTPUT + puts "File $OUTPUT saved." + quit -noprompt + } + if {$drccn < $drcc} { + puts "Hoory, we fixed a DRC issue" + incr nFixed + set drcc $drccn + set checkpoint [getCheckpoint] + puts "New Checkpoint: $checkpoint" + } else { + puts "Trying to fix this DRC issue did not reduce the number of DRC issues ($drccn vs. $drcc) so we undo and try something else" + undoToCheckpoint $checkpoint + #foreach layername [split $drcparts " "] { + # puts "Undoing $layername" + # #erase $layername + # undo + #} + } + } + } + } + } + } + + if {$nFixed >0} { + puts "We have fixed some issues, $drccn issues are remaining, we give up and save the file now." + save $OUTPUT + puts "File $OUTPUT saved." + } else { + puts "We could not fix any issues." + } +} +puts "Trying to FIX some DRC issues" +load $MAG +puts "Calling fix_drc" +fix_drc +puts "Done trying to FIX some DRC issues" +quit -noprompt diff --git a/Tools/perl/drcfixall.pl b/Tools/perl/drcfixall.pl new file mode 100755 index 00000000..272f4763 --- /dev/null +++ b/Tools/perl/drcfixall.pl @@ -0,0 +1,36 @@ +#!/usr/bin/perl -w + +sub step($) +{ + print "$_[0]\n"; +} + +my $tech=$ARGV[0] || "../Tech/libresilicon.tech"; + +foreach my $magfile (<*.mag>) +{ + next if($magfile=~m/^corr_/); # Ignore correction files + next if($magfile eq "demoboard.mag"); + my $cellname=$magfile; $cellname=~s/\.mag$//; + + step("NEXT STEP: DRC Check with Magic"); + system "../Tools/perl/drccheck.pl $cellname.mag $tech"; + + step("NEXT STEP: DRC Fix"); + system "../Tools/perl/drcfix.pl $cellname.drc $tech"; + + step("NEXT STEP: DRC Check with Magic"); + system "../Tools/perl/drccheck.pl $cellname.mag $tech"; + + if(-f "corr_$cellname.mag") + { + unlink "$cellname.mag"; + rename "corr_$cellname.mag","$cellname.mag"; + print "DRC errors in $cellname corrected. Now running final DRC check:\n"; + step("NEXT STEP: Final DRC check"); + system "../Tools/perl/drccheck.pl $cellname.mag $tech"; + } + + # exit; +} + diff --git a/Tools/perl/dummychar.pl b/Tools/perl/dummychar.pl new file mode 100755 index 00000000..7dab6d35 --- /dev/null +++ b/Tools/perl/dummychar.pl @@ -0,0 +1,124 @@ +#!/usr/bin/perl -w +use strict; + +my $pdk=$ENV{'PDK'}; + +print <; +foreach my $cell(@cells) +{ + $cell=~s/\.cell$//; + my $area=123456; + my @inputs=(); + my @outputs=(); + + open IN,"<$cell.cell"; + $/="\n"; + foreach my $line() + { + @inputs=split(" ",$1) if($line=~m/^\.inputs (\w.*)/i); + @outputs=split(" ",$1) if($line=~m/^\.outputs (\w.*)/i) + } + close IN; + open IN,"<$cell.truthtable.v"; + undef $/; + my %funcs=(); + while() + { + if(m/(\w+) = ((.*))$/) + { + my ($pin,$func)=($1,$2); + $func=~s/ //g; $func=~s/\&\&/\&/g; $func=~s/\|\|/\|/g; + $funcs{$pin}=" function: \"".$func."\";"; + } + } + close IN; + + print < ["B",3], "B" => [1,3,4,5], 3 =>[1,"B",4,5], 4 => ["B",3,5], 5 => ["B",3,4]); - #%graphs=(1 => [2,3], 2=>[1,4],3=>[1,4],4=>[3,2,5,5],5=>[4,4]); #%graphs=(5 => [6,6,7], 6=>[5,5,0,0],0=>[6,6,7],7=>[5,0]); - %graphs=(1=>["A","B"], "A"=>[1,3], "B"=>[1,2], 2=>["B","D"], 3=>["A","C"], "C"=>[3,4], "D"=>[2,4], 4=>["C","D","E","F"], "E"=>[4,5], "F"=>[4,5], 5=>["E","F"]); +# Loading the cell if($ARGV[0] && open(IN,"<$ARGV[0]")) { %graphs=(); - while() + while() # reading each line { - if(m/^(\w+) (\w+) (\w+) ([pn]mos)/i) + if(m/^([pn]mos) (\w+) (\w+) (\w+)/i) # Does the line define a transistor? { - my($g,$d,$s,$t)=($1,$2,$3,$4); - next if(lc($network) eq "pmos" && lc($t) eq "nmos"); - next if(lc($network) eq "nmos" && lc($t) eq "pmos"); + my($t,$g,$d,$s)=($1,$2,$3,$4); # Extract all the parameters from the line + next if(lc($network) eq "pmos" && lc($t) eq "nmos"); # If we only look for pmos transistors we skip nmos transistors + next if(lc($network) eq "nmos" && lc($t) eq "pmos"); # and vice versa print "$_" if($debug); - if($power || $d!~m/(gnd|vdd)/i) + if($power || $d!~m/(gnd|vdd)/i) # We skip power connections when needed { - push @{$graphs{$g}},$d; + push @{$graphs{$g}},$d; # Here we add the gate-drain connection to the graph push @{$graphs{$d}},$g; } if($power || $s!~m/(gnd|vdd)/i) { - push @{$graphs{$g}},$s; + push @{$graphs{$g}},$s; # Here we add the source-gate connection to the graph push @{$graphs{$s}},$g; } } @@ -118,7 +119,10 @@ sub eulerPath { close IN; } +# Done with parsing the cell file. Now the euler path is generated: + my @path = eulerPath(%graphs); +# The euler path has been generated, now it is being written out: if($debug) { print "Original graph:\n"; diff --git a/Tools/perl/flatten.pl b/Tools/perl/flatten.pl new file mode 100755 index 00000000..4027f3dc --- /dev/null +++ b/Tools/perl/flatten.pl @@ -0,0 +1,23 @@ +#!/usr/bin/perl -w + +my $mag=$ARGV[0]; $mag=~s/\.mag$//i; +my $sp=$mag; $sp.=".flat.mag"; +my $flat=$ARGV[1] || $sp; +my $tech=$ARGV[2] || "../Tech/libresilicon.tech"; + +print "flatten.pl - Flatten a hierarchical .mag file into a flattened .mag file\n"; +print "Usage: flatten.pl input.mag output.mag [Technology]\n"; + +if(-f "$mag.mag") +{ + open MAGIC,"|magic -dnull -noconsole -T $tech $mag"; + unlink $flat; + $flat=~s/\.mag$//i; # We need to remove the extension otherwise load will not work + print MAGIC "select top cell\nexpand\nflatten $flat\nload $flat\nsave\n"; + print MAGIC "exit\n"; + close MAGIC; +} +else +{ + print STDERR "Error: Could not load magic file $mag.mag\n"; +} diff --git a/Tools/perl/funclist.pl b/Tools/perl/funclist.pl new file mode 100755 index 00000000..f029e923 --- /dev/null +++ b/Tools/perl/funclist.pl @@ -0,0 +1,26 @@ +#!/usr/bin/perl -w +use strict; +print "Writing functions.html\n"; +open OUT,">functions.html"; +print OUT < +Cell Functions + + +

Cell functions:

+ + +EOF +; + +foreach(<*.cell>) +{ + my $func1=`../Tools/perl/truthtable.pl --format=text $_`; + my $func2=""; $func2=$1 if($func1=~m/FUNCTION: (.*)/); $func2=~s/FUNCTION://; + print OUT ""; +} + +print OUT "
CellFunction
$_$func2
\n"; +close OUT; + +print "You can now execute:\nfirefox functions.html\n"; diff --git a/Tools/perl/gencharlibyml.pl b/Tools/perl/gencharlibyml.pl new file mode 100755 index 00000000..ae025938 --- /dev/null +++ b/Tools/perl/gencharlibyml.pl @@ -0,0 +1,127 @@ +#!/usr/bin/perl -w + +# This tool is automatically used by the StdCellLib flow, it is called by librecells.pl +# If you want to run it manually, run it from the CATALOG directory and make sure that the PDK environment variable is set. + +sub header() +{ + print OUT < if(!scalar(@cells)); + +if(scalar(@cells)>1) # If we have more than one cell we create one yml file for the whole library +{ + my $fn="libresilicon-charlib.yml"; + open OUT,">$fn"; + print "Writing to $fn\n"; + header(); +} + + +foreach my $cell(@cells) +{ + my $cn=$cell; $cn=~s/\.cell$//; + if(! -f "$cn.truthtable.v") + { + print "Skipping $cell due to missing truthtable\n"; + next; + } + print "Handling $cell\n"; + if(scalar(@cells)==1) # If we have only a single cell we create a yml file for that single cell + { + open OUT,">$cn.yml"; + print "Writing to $cn.yml\n"; + header(); + } + open IN,"<$cell"; + print OUT " $cn:\n"; + print OUT " netlist: $cn.spice\n"; + while() + { + if(/^\.inputs (.*?)\s*$/) + { + my $ins=$1; $ins=~s/ /,/g; + print OUT " inputs: [$ins]\n"; + } + if(/^\.outputs (.*?)\s$/) + { + my $outs=$1; $outs=~s/ /,/g; + print OUT " outputs: [$outs]\n"; + } + } + close IN; + + if(open(IN,") + { + if(m/SIZE\s+(\d+\.?\d*)\s+BY\s+(\d+\.\d*)/) + { + my $area=int($1*$2*100); + print OUT " area: $area\n"; + } + } + close IN; + } + if(open(IN,"<$cn.truthtable.v")) + { + print OUT " functions:\n"; + while() + { + s/function: //; s/\&\&/\&/g; s/\|\|/\|/g; s/ //g; s/\!(\w+)/\(!$1\)/g; + print OUT " - $_"; + } + close IN; + } + if(scalar(@cells)==1) + { + close OUT; + } + +} + +if(scalar(@cells)>1) +{ + close OUT; +} diff --git a/Tools/perl/lefgen.pl b/Tools/perl/lefgen.pl new file mode 100755 index 00000000..3797c2fa --- /dev/null +++ b/Tools/perl/lefgen.pl @@ -0,0 +1,28 @@ +#!/usr/bin/perl -w +use strict; + +# This tool compiles a single LEF from a template for the header and the LEF snippets for each cell + +open IN,"<../Tech/template.lef"; +print $_ while(); +close IN; + +foreach(@ARGV) +{ + if(open IN,"<$_") + { + while() + { + print $_; + } + close IN; + } + else + { + print STDERR "Error: Could not open file $_ for reading: $!\n"; + } + print "\n"; +} + + +print "\nEND LIBRARY\n"; diff --git a/Tools/perl/lefsize.pl b/Tools/perl/lefsize.pl new file mode 100755 index 00000000..896eace6 --- /dev/null +++ b/Tools/perl/lefsize.pl @@ -0,0 +1,63 @@ +#!/usr/bin/perl -w +use strict; + + + +sub mymin($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[1]:$_[0]; +} + +sub mymax($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[0]:$_[1]; +} + +foreach my $mag(<*.mag>) +{ + my $cellname=$mag; $cellname=~s/\.mag$//; + next if(defined($ENV{'CELL'}) && $ENV{'CELL'} ne $cellname); + next unless(-f "$cellname.cell"); # We only want generated cells, no demoboards or other stuff + + my @mins=(); + my @maxs=(); + + if(open(IN,"<$mag")) + { + while() + { + if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) + { + my @a=split " ",$_; + foreach(1 .. 4) + { + $mins[$_&1]=mymin($mins[$_&1],$a[$_]); + $maxs[$_&1]=mymax($maxs[$_&1],$a[$_]); + } + } + } + close IN; + } + my @inputs=(); + my @outputs=(); + if(open(IN,"<$cellname.cell")) + { + #print STDERR "Reading $cellname.cell\n"; + while() + { + @inputs=split " ",$1 if(m/^\.inputs (.*)/); + @outputs=split " ",$1 if(m/^\.outputs (.*)/); + } + close IN; + } + else + { + print STDERR "Could not read cell $cellname.cell: $!\n"; + } + my $area=defined($maxs[0])?"SIZE ".($maxs[0]-$mins[0])." BY ".($maxs[1]-$mins[1])." ;":""; + + print "$cellname\n$area\n"; +} + diff --git a/Tools/perl/libgen.pl b/Tools/perl/libgen.pl new file mode 100755 index 00000000..e6dc4a22 --- /dev/null +++ b/Tools/perl/libgen.pl @@ -0,0 +1,463 @@ +#!/usr/bin/perl -w +use strict; + +#Liberty File generator +# + +print <$_[1])?$_[1]:$_[0]; +} + +sub mymax($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[0]:$_[1]; +} + + +my @liste=(); +if(scalar(@ARGV)) +{ + @liste=@ARGV; +} +else +{ + @liste=<*.mag>; +} + +foreach my $mag(@liste) +{ + my $cellname=$mag; $cellname=~s/\.mag$//; + next if(defined($ENV{'CELL'}) && $ENV{'CELL'} ne $cellname); + next unless(-f "$cellname.cell"); # We only want generated cells, no demoboards or other stuff + + my @mins=(); + my @maxs=(); + + if(open(IN,"<$mag")) + { + while() + { + if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) + { + my @a=split " ",$_; + foreach(1 .. 4) + { + $mins[$_&1]=mymin($mins[$_&1],$a[$_]); + $maxs[$_&1]=mymax($maxs[$_&1],$a[$_]); + } + } + } + close IN; + } + my @inputs=(); + my @outputs=(); + if(open(IN,"<$cellname.cell")) + { + #print STDERR "Reading $cellname.cell\n"; + while() + { + @inputs=split " ",$1 if(m/^\.inputs (.*)/); + @outputs=split " ",$1 if(m/^\.outputs (.*)/); + } + close IN; + } + else + { + print STDERR "Could not read cell $cellname.cell: $!\n"; + } + my $area=defined($maxs[0])?($maxs[0]-$mins[0])*($maxs[1]-$mins[1]):1; + + if($mag=~m/^PAD/) + { + print "cell ($cellname) { area : $area; dont_touch : true; }\n"; + } + else + { + + my $output= <$_[1])?$_[1]:$_[0]; +} + +sub mymax($$) +{ + return $_[1] unless(defined($_[0])); + return ($_[0]>$_[1])?$_[0]:$_[1]; +} + + +foreach my $npins(1 .. $maxpins) +{ + my @inputs=(); + + foreach my $mag(0 .. (2**$npins)-1) + { + my $cellname=$mag; $cellname=~s/\.mag$//; + my @outputs=(); + + + if(open(IN,"<$cellname.cell")) + { + print STDERR "Reading $cellname.cell\n"; + while() + { + @inputs=split " ",$1 if(m/^\.inputs (.*)/); + @outputs=split " ",$1 if(m/^\.outputs (.*)/); + } + close IN; + } + else + { + print STDERR "Could not read: $!\n"; + } + my $area=defined($maxs[0])?($maxs[0]-$mins[0])*($maxs[1]-$mins[1]):1; + + if($mag=~m/^PAD/) + { + print "cell ($cellname) { area : $area; dont_touch : true; }\n"; + } + else + { + + my $output= <; $lctimeparams=~tr/\r\n//; + close IN; +} + +sub system_v($) +{ + print "$_[0]\n"; + #print STDERR "$_[0]\n"; + return system($_[0]); +} + + +system_v "../Tools/perl/cell2spice.pl"; + +mkdir "work"; +system "rm -rf work/*"; + +open IN,"<$sp" || die "Could not open file $sp: $!\n"; +while() +{ + if(m/^\.subckt (\w+)/) + { + our $cellname=$1; + next if(defined($ENV{'CELL'}) && $cellname ne $ENV{'CELL'}); + if(-s "$cellname.lib" && (-s "$cellname.mag")>55) + { + print STDERR "INFO: $cellname.lib already exists, so we are skipping it.\n"; + next; + } + unlink "$cellname.done"; + unlink "$cellname.log"; + unlink "$cellname.err"; + open OUT,">$cellname.running"; + close OUT; + + my $usage="/usr/bin/time -v -a -o $cellname.usage"; + + sub step($) + { + print "$_[0]\n"; + open LOG,">>$cellname.log"; + print LOG $_[0]."\n"; + close LOG; + open LOG,">>$cellname.err"; + print LOG $_[0]."\n"; + close LOG; + } + + step("NEXT CELL: $cellname"); + + system_v "../Tools/perl/truthtable.pl --format=text $cellname.cell >$cellname.truthtable.txt"; + system_v "../Tools/perl/truthtable.pl --format=html $cellname.cell >$cellname.truthtable.html"; + system_v "../Tools/perl/truthtable.pl --format=verilog $cellname.cell >$cellname.truthtable.v"; + + + my $placer=""; $placer="--placer hierarchical" if($cellname=~m/^(CLK|DFF|FAX|HAX)/); + if(-f "$cellname.dontlayout") + { + print STDERR "TODO: $cellname is disabled by $cellname.dontlayout this is likely because it takes too much time to generate it\n"; + unlink "$cellname.running"; + next; + } + unlink "outputlib/$cellname.mag"; + step("NEXT STEP: Running cell2spice"); + system_v "../Tools/perl/cell2spice.pl $cellname >>$cellname.log 2>>$cellname.err"; + step("NEXT STEP: Running lclayout"); + + system_v "$usage lclayout --output-dir outputlib --tech ../Tech/librecell_tech.py --netlist $cellname.sp --cell $cellname -v $placer --placement-file $cellname.place --ignore-lvs --debug-routing-graph --route-max-iter 100 >>$cellname.log 2>>$cellname.err"; + + + if(-f "$cellname.mag") + { + system_v("../Tools/perl/paintgridusage.pl $cellname >>$cellname.log 2>>$cellname.err"); + } + + my $magfile="outputlib/$cellname.mag"; + my $gdsfile="outputlib/$cellname.gds"; + if(-f "$cellname.fixed") + { + print "We found a manually fixed $cellname.fixed magic file for testing so we are using that one instead.\n"; + step("NEXT STEP: Fixing file $cellname.fixed -> $cellname.mag"); + system "cp -f $cellname.fixed $cellname.mag"; + } + elsif(-f $magfile && (-s $magfile) > 51) # Has lclayout exported magic directly? + { + # Then we dont have to convert it + open MAGIN,"$cellname.mag"; + my $old=$/; + undef $/; + my $magcontent=; + $/=$old; + $magcontent=~s/tech sky130A/tech sky130A\nmagscale 1 2/s; + $magcontent=~s/<< abutment >>\nrect /<< properties >>\nstring FIXED_BBOX /s; + print MAGOUT $magcontent; + close MAGIN; + close MAGOUT; + } + elsif(-f $gdsfile) + { + print STDERR "lclayout has exported GDS2 but no magic, so we try to convert the GDS2:\n"; + # For this processing step, the refrenced libresilicon.tech file needs to contain the cifinput section to import from GDS and the extract section to do the parasitic extraction: + open OUT,"|magic -dnull -noconsole -T ../Tech/libresilicon.tech >>$cellname.log 2>>$cellname.err"; + print OUT <>$cellname.log 2>>$cellname.err"; + if(-f "corr_$cellname.mag") + { + unlink "$cellname.predrc.mag"; + rename "$cellname.mag","$cellname.predrc.mag"; + rename "corr_$cellname.mag","$cellname.mag"; + + #step("NEXT STEP: DRC Fix - 2nd try, just to make sure"); + #system "../Tools/perl/drcfix.pl $cellname.mag >>$cellname.log 2>>$cellname.err"; + #if(-f "corr_$cellname.mag") + #{ + # unlink "$cellname.mag" ; + # rename "corr_$cellname.mag","$cellname.mag"; + #} + + step("NEXT STEP: Final DRC check"); + print "DRC errors in $cellname corrected. Now running final DRC check:\n"; + system_v "$usage ../Tools/perl/drccheck.pl $cellname.mag"; + } + step("DRC Fixing done."); + + step("NEXT STEP: mag2gds"); + print "The outputlib/$cellname.gds is being overwritten by the GDS file converted by Magic from the .mag file, to propagate the DRC corrections to GDS.\n"; + rename "outputlib/$cellname.gds","outputlib/$cellname.lclayout.gds"; + unlink "$cellname.gds"; + open OUT,"|magic -dnull -noconsole -T ../Tech/libresilicon.tech $cellname.mag >>$cellname.log 2>>$cellname.err"; + print OUT <>$cellname.log 2>>$cellname.err"; + print OUT <>$cellname.ext"; + #system "cat $cellname.ext"; + print "Second magic call:\n"; + step("NEXT STEP: magic3"); + open OUT,"|$usage magic -dnull -noconsole -T ../Tech/libresilicon.tech $cellname.mag >>$cellname.log 2>>$cellname.err"; + print OUT <$cellname.libtemplate 2>>$cellname.err"; + + step("NEXT STEP: Characterization with lctime:"); + $cmd="$usage lctime ".($debug?"--debug":"")." --diff %_p,%_n --liberty $cellname.libtemplate --include ../Tech/libresilicon.m --spice $cellname.spice --cell $cellname --output $cellname.lib $lctimeparams >>$cellname.log 2>>$cellname.err"; # This is for fully extracted parasitics + #system_v($cmd); + + $cmd="$usage lctime ".($debug?"--debug":"")." --diff %_p,%_n --liberty $cellname.libtemplate --include ../Tech/libresilicon.m --spice $cellname.sp --cell $cellname --output $cellname.lib $lctimeparams >>$cellname.log 2>>$cellname.err"; # This is for pure spice files without parasitics + system_v($cmd); + + + step("NEXT STEP: Characterization with CharLib:"); + # system_v("python3 ../Tools/python/gen_CharLib.py"); # Old CharLib and Libretto support + system_v("perl ../Tools/perl/gencharlibyml.pl $cellname.cell"); + $cmd="$usage charlib run $cellname.yml >>$cellname.log 2>>$cellname.err"; # Which Path should we use for CharLib? + system_v($cmd); + + step("NEXT STEP: Visualisation"); + print "Visualisation:\nlibertyviz -l $cellname.lib --cell $cellname --pin Y --related-pin A --table cell_rise\n"; + + step("NEXT STEP: gds2mag"); + #system "gds2mag --config ~/libresilicon/gds2mag/example/example_config.toml -i outputlib/$1.gds -o _$1.mag"; + # exit; # Stop after doing one cell + + step("NEXT STEP: mag2svg"); + system "../Tools/perl/mag2svg.pl $cellname.mag $cellname.svg" if(-f "$cellname.mag"); + step("NEXT STEP: mag2siliwiz"); + system "../Tools/perl/mag2siliwiz.pl <$cellname.mag >$cellname.json" if(-f "$cellname.mag"); + + + unlink "$cellname.running"; + } +} + +if(!defined($ENV{'CELL'})) +{ + print "WRAPUP STEP: Concatenating GDS files\n"; + system_v "python3 ../Tools/python/concat4gds.py outputlib/*.gds"; +} + diff --git a/Tools/perl/ltspice2lclayout.pl b/Tools/perl/ltspice2lclayout.pl new file mode 100755 index 00000000..ba023a74 --- /dev/null +++ b/Tools/perl/ltspice2lclayout.pl @@ -0,0 +1,49 @@ +#!/usr/bin/perl -w +use strict; + +if(scalar(@ARGV) != 2) +{ + print "Usage: $0 \n"; + print "All VDD, GND and all inputs/output nets to the cell must be labled in LTspice.\n"; + exit; +} + +my $circuitname=uc $ARGV[1]; $circuitname=~s/\.\w+$//; $circuitname=~s/.*\///; +if(open(IN,"<$ARGV[0]")) +{ + if(open(OUT,">$ARGV[1]")) + { + my $head=; $head=~s/\r//g; + print OUT "* converted by $0 : $head"; + my %ports=(); + my $circ=""; + while() + { + s/\r//g; + s/ 0 / GND /g; + s/ 0 / GND /g; # This needs to be done 2 times since they are overlapping! + my @a=split(" ",$_); + $circ.=$_ if(m/^[MR]/); + $ports{$a[1]}=1 if(m/^[MR]/ && $a[1]!~m/^(N\d\d\d|\d+)$/); + $ports{$a[2]}=1 if(m/^[MR]/ && $a[2]!~m/^(N\d\d\d|\d+)$/); + $ports{$a[3]}=1 if(m/^[M]/ && $a[3]!~m/^(N\d\d\d|\d+)$/); + $ports{$a[4]}=1 if(m/^[M]/ && $a[4]!~m/^(N\d\d\d|\d+)$/); + } + print OUT "\n.subckt $circuitname ".join(" ",sort keys %ports)."\n"; + print OUT $circ; + print OUT ".ends $circuitname\n"; + close OUT; + print "$ARGV[1] has been written.\n"; + } + else + { + print "Could not open $ARGV[1] for writing: $!\n"; + } + close IN; +} +else +{ + print "Could not open $ARGV[0] for reading: $!\n"; +} + + diff --git a/Tools/perl/mag2siliwiz.pl b/Tools/perl/mag2siliwiz.pl new file mode 100755 index 00000000..1a3736b3 --- /dev/null +++ b/Tools/perl/mag2siliwiz.pl @@ -0,0 +1,76 @@ +#!/usr/bin/perl -w + +# Converting MAGIC files to JSON for https://app.siliwiz.com/ + +my $scale=3; # Scale 1 would be technically correct, but the result is so small that you cannot see much, so Scale 3 is usually better +my $movex=15; +my $movey=25; + +print <; +my $layer="undef"; +my $count=0; +foreach(@lines) +{ + if(m/^<< (\w+) >>/) + { + $layer=layername($1); + } + if(m/^rect (-?\d+) (-?\d+) (-?\d+) (-?\d+)/) + { + print ", " if($count); + print " { \"x\": ".($1*$scale+$movex).", \"y\": ".($2*$scale+$movey).", \"width\": ".(($3-$1)*$scale).", \"height\": ".(($4-$2)*$scale).", \"layer\": \"$layer\" }\n"; + $count++; + } + if(m/^rlabel (\w+) (-?\d+) (-?\d+) (-?\d+) (-?\d+) (-?\d+) (\w+)/) + { + print ", " if($count); + print " { \"x\": ".($2*$scale+$movex).", \"y\": ".($3*$scale+$movey).", \"width\": ".(($4-$2)*$scale).", \"height\": ".(($5-$3)*$scale).", \"layer\": \"".layername($1)."\", \"label\": \"".ioname($7)."\" }\n"; + $count++; + } +} + +print <1); + +print "mag2svg - Convert magic files to SVG\n"; +print "Usage: mag2svg input.mag output.svg\n" if(scalar(@ARGV)<1); + +our %colors=(); +our %styles=(); +our $csscolors=""; + +sub initColors() +{ + my $dir=$ENV{'MAGIC_DIR'} || "/usr/local/lib/magic/sys"; + if(open(IN,"<$dir/mos.24bit.std.cmap")) + { + while() + { + if(m/^(\d+)\s+(\d+)\s+(\d+)\s+(\d+)\s+(\w+)\s*$/) + { + $colors{$4}=sprintf("#%02X%02X%02X",$1,$2,$3); + #print "$4:$colors{$4}\n"; + } + } + close IN; + } + for my $style (<$dir/mos.24bit.dstyle>) + { + open IN,"<$style"; + while() + { + if(m/^(\d+)\s+(\w+)\s+(\d+)\s+(\w+)\s+(\w+)\s+(\d+)\s+(\S+)\s+(\w+)/) + { + my $c=$colors{$3}||sprintf("#%02x%02x%02x",rand()*256,rand()*256,rand()*256); + $styles{$8}=$c; + #print "$8:$c\n"; + } + } + close IN; + } + foreach my $tech (<$dir/*.tech>) + { + #print "tech$tech\n"; + open IN,"<$tech"; + while() + { + if(m/^\s*styles\s*$/) + { + #print "styles found\n"; + while() + { + last if(m/^\s*end\s*$/); + if(m/^\s*(\w+)\s+(\w+)/) + { + my $s=$styles{$2}||""; + #print "$1 $s\n" if($s); + $csscolors.=".$1 { fill:$s; }\n" if($s ne ""); + } + } + } + } + close(IN); + } + +} +initColors(); + +sub mymin($$) +{ + return $_[1] if(!defined($_[0])); + return $_[0] if(!defined($_[1])); + return $_[0]<$_[1]?$_[0]:$_[1]; +} +sub mymax($$) +{ + return $_[1] if(!defined($_[0])); + return $_[0] if(!defined($_[1])); + return $_[0]>$_[1]?$_[0]:$_[1]; +} + +our $usewarning=0; + + + +if(-f "$mag.mag") +{ + # Now we need magic 4.2 with kairos support compiled in for SVG export: + # open MAGIC,"|magic -d XR -noconsole -nowindow -T ../Tech/libresilicon.tech $mag"; + # print MAGIC "plot svg $svg\nexit\n"; + # close MAGIC; + # print "$svg written.\n" if(-f $svg); + # print "Could not generate $svg , perhaps magic is not installed or missing Kairos support?\nThe cairo library development files need to be installed and magic needs to be configured with --with-cairo.\nMake sure that magic configure says 'Cairo: yes' in the summary.\n" if(! -f $svg); + + open IN,"<$mag.mag"; + # + my $layer=""; + my $rects=""; + my @limits=(); + while() + { + if(m/^<< ([^>]+) >>/) + { + $layer=$1; + #print "Layer: $layer\n"; + } + elsif(m/^use/ && !$usewarning) + { + close IN; # We dont need it anymore, we use a different approach now: + #print STDERR "Running magic to flatten the file:\n"; + open MAGIC,"|magic -dnull -noconsole -T $tech $mag"; + my $flat="tmp".int(rand()*10000).".mag"; + unlink $flat; + $flat=~s/\.mag$//i; # We need to remove the extension otherwise load will not work + print MAGIC "select top cell\nexpand\nflatten $flat\nload $flat\nsave\n"; + print MAGIC "exit\n"; + close MAGIC; + #print STDERR "magic flatten done.\n"; + system "$0 $flat.mag $svg $tech"; + unlink $flat; + exit; + } + elsif(m/^rect (\-?\d+\.?\d*) (\-?\d+\.?\d*) (\-?\d+\.?\d*) (\-?\d+\.?\d*)/) + { + #print "Rect\n"; + next if(defined($ignorelayers{$layer})); + my $width=$3-$1; + my $height=$4-$2; + $limits[1]=mymin($limits[1],$1); + $limits[2]=mymin($limits[2],$2); + $limits[3]=mymax($limits[3],$3); + $limits[4]=mymax($limits[4],$4); + my $ny=-$4; + $rects.="\n"; + } + #rlabel metal1 0 61 64 67 0 vdd + elsif(m/rlabel (\S+) (\-?\d+\.?\d*) (\-?\d+\.?\d*) (\-?\d+\.?\d*) (\-?\d+\.?\d*) (\-?\d+\.?\d*) (.*)/) + { + my $x=($2+$4)/2; + my $y=($3+$5)/2; + my $width=$4-$2; + my $height=$5-$3; + my $ny=-$5; + $rects.="\n"; + $ny+=$height; + $rects.="$7\n"; + } + } + close IN; + my $width=($limits[3]||0)-($limits[1]||0); + my $height=($limits[4]||0)-($limits[2]||0); + $limits[2]=-($limits[4] || 0); + if($width) + { + print "Writing $svg\n"; + open OUT,">$svg"; + print OUT < + + +$rects + +EOF + ; + close OUT; + } + else + { + print "Error: Empty magic file!\n"; + } +} +else +{ + print STDERR "Error: Could not load magic file $mag.mag\n"; +} diff --git a/Tools/perl/magscale.pl b/Tools/perl/magscale.pl new file mode 100755 index 00000000..e9e43689 --- /dev/null +++ b/Tools/perl/magscale.pl @@ -0,0 +1,7 @@ +#!/usr/bin/perl -w + +while() +{ + print; + print "magscale 1 2\n" if(m/^tech/); +} diff --git a/Tools/perl/muxgen.pl b/Tools/perl/muxgen.pl new file mode 100755 index 00000000..16c55b82 --- /dev/null +++ b/Tools/perl/muxgen.pl @@ -0,0 +1,26 @@ +#!/usr/bin/perl -w + + +foreach my $n(2 .. 10) +{ + open OUT,">MUX$n.cell"; + print OUT ".AUTOGENERATED by muxgen Perl Script\n"; + my @ins=(); + push @ins,"IN$_" foreach(0 .. $n-1); + push @ins,"S$_" foreach(0 .. $n-1); + print OUT ".inputs ".join(" ",@ins)."\n"; + print OUT ".outputs Z\n"; + print OUT ".ORDER \"MOSFET Gate Drain Source\"\n"; + foreach(0 .. $n-1) + { + print OUT "pmos IN$_ INT$_ vdd\n"; + print OUT "nmos IN$_ INT$_ gnd\n"; + print OUT "pmos S$_ INT$_ Y\n"; + print OUT "nmos S$_ INT$_ Y\n"; + } + print OUT "pmos Y Z vdd\n"; + print OUT "nmos Y Z gnd\n"; + close OUT; + + +} diff --git a/Tools/perl/painter.pl b/Tools/perl/painter.pl new file mode 100755 index 00000000..2590017e --- /dev/null +++ b/Tools/perl/painter.pl @@ -0,0 +1,563 @@ +#!/usr/bin/perl -w + +print <> +rect -310 152 0 156 +rect 824 152 1126 156 +rect -310 128 -210 152 +rect 1026 128 1126 152 +rect -10 80 0 84 +rect 824 80 826 84 +rect -10 72 0 76 +rect 824 72 826 76 +rect -310 4 -210 28 +rect 1026 4 1126 28 +rect -310 0 0 4 +rect 824 0 1126 4 +<< metal2 >> +rect -6 36 -2 162 +rect 810 128 814 164 +rect 18 116 22 124 +rect 50 116 54 124 +rect 82 116 86 124 +rect 114 116 118 124 +rect 146 116 150 124 +rect 178 116 182 124 +rect 210 116 214 124 +rect 242 116 246 124 +rect 274 116 278 124 +rect 306 116 310 124 +rect 338 116 342 124 +rect 370 116 374 124 +rect 402 116 406 124 +rect 434 116 438 124 +rect 466 116 470 124 +rect 498 116 502 124 +rect 530 116 534 124 +rect 562 116 566 124 +rect 594 116 598 124 +rect 626 116 630 124 +rect 658 116 662 124 +rect 690 116 694 124 +rect 722 116 726 124 +rect 754 116 758 124 +rect 786 116 790 124 +rect 802 116 806 124 +rect 10 112 30 116 +rect 42 112 62 116 +rect 74 112 94 116 +rect 106 112 126 116 +rect 138 112 158 116 +rect 170 112 190 116 +rect 202 112 222 116 +rect 234 112 254 116 +rect 266 112 286 116 +rect 298 112 318 116 +rect 330 112 350 116 +rect 362 112 382 116 +rect 394 112 414 116 +rect 426 112 446 116 +rect 458 112 478 116 +rect 490 112 510 116 +rect 522 112 542 116 +rect 554 112 574 116 +rect 586 112 606 116 +rect 618 112 638 116 +rect 650 112 670 116 +rect 682 112 702 116 +rect 714 112 734 116 +rect 746 112 766 116 +rect 778 112 818 116 +rect 26 108 30 112 +rect 58 108 62 112 +rect 90 108 94 112 +rect 122 108 126 112 +rect 154 108 158 112 +rect 186 108 190 112 +rect 218 108 222 112 +rect 250 108 254 112 +rect 282 108 286 112 +rect 314 108 318 112 +rect 346 108 350 112 +rect 378 108 382 112 +rect 410 108 414 112 +rect 442 108 446 112 +rect 474 108 478 112 +rect 506 108 510 112 +rect 538 108 542 112 +rect 570 108 574 112 +rect 602 108 606 112 +rect 634 108 638 112 +rect 666 108 670 112 +rect 698 108 702 112 +rect 730 108 734 112 +rect 762 108 766 112 +rect 26 104 38 108 +rect 58 104 70 108 +rect 90 104 102 108 +rect 122 104 134 108 +rect 154 104 166 108 +rect 186 104 198 108 +rect 218 104 230 108 +rect 250 104 262 108 +rect 282 104 294 108 +rect 314 104 326 108 +rect 346 104 358 108 +rect 378 104 390 108 +rect 410 104 422 108 +rect 442 104 454 108 +rect 474 104 486 108 +rect 506 104 518 108 +rect 538 104 550 108 +rect 570 104 582 108 +rect 602 104 614 108 +rect 634 104 646 108 +rect 666 104 678 108 +rect 698 104 710 108 +rect 730 104 742 108 +rect 762 104 774 108 +rect 2 40 6 100 +rect 34 96 38 104 +rect 66 96 70 104 +rect 98 96 102 104 +rect 130 96 134 104 +rect 162 96 166 104 +rect 194 96 198 104 +rect 226 96 230 104 +rect 258 96 262 104 +rect 290 96 294 104 +rect 322 96 326 104 +rect 354 96 358 104 +rect 386 96 390 104 +rect 418 96 422 104 +rect 450 96 454 104 +rect 482 96 486 104 +rect 514 96 518 104 +rect 546 96 550 104 +rect 578 96 582 104 +rect 610 96 614 104 +rect 642 96 646 104 +rect 674 96 678 104 +rect 706 96 710 104 +rect 738 96 742 104 +rect 770 96 774 104 +rect 794 100 798 112 +rect 794 96 806 100 +rect 802 60 806 96 +rect 50 52 54 60 +rect 82 52 86 60 +rect 114 52 118 60 +rect 146 52 150 60 +rect 178 52 182 60 +rect 210 52 214 60 +rect 242 52 246 60 +rect 274 52 278 60 +rect 306 52 310 60 +rect 338 52 342 60 +rect 370 52 374 60 +rect 402 52 406 60 +rect 434 52 438 60 +rect 466 52 470 60 +rect 498 52 502 60 +rect 530 52 534 60 +rect 562 52 566 60 +rect 594 52 598 60 +rect 626 52 630 60 +rect 658 52 662 60 +rect 690 52 694 60 +rect 722 52 726 60 +rect 754 52 758 60 +rect 786 52 790 60 +rect 802 56 822 60 +rect 10 48 30 52 +rect 50 48 62 52 +rect 82 48 94 52 +rect 114 48 126 52 +rect 146 48 158 52 +rect 178 48 190 52 +rect 210 48 222 52 +rect 242 48 254 52 +rect 274 48 286 52 +rect 306 48 318 52 +rect 338 48 350 52 +rect 370 48 382 52 +rect 402 48 414 52 +rect 434 48 446 52 +rect 466 48 478 52 +rect 498 48 510 52 +rect 530 48 542 52 +rect 562 48 574 52 +rect 594 48 606 52 +rect 626 48 638 52 +rect 658 48 670 52 +rect 690 48 702 52 +rect 722 48 734 52 +rect 754 48 766 52 +rect 786 48 798 52 +rect 26 44 30 48 +rect 58 44 62 48 +rect 90 44 94 48 +rect 122 44 126 48 +rect 154 44 158 48 +rect 186 44 190 48 +rect 218 44 222 48 +rect 250 44 254 48 +rect 282 44 286 48 +rect 314 44 318 48 +rect 346 44 350 48 +rect 378 44 382 48 +rect 410 44 414 48 +rect 442 44 446 48 +rect 474 44 478 48 +rect 506 44 510 48 +rect 538 44 542 48 +rect 570 44 574 48 +rect 602 44 606 48 +rect 634 44 638 48 +rect 666 44 670 48 +rect 698 44 702 48 +rect 730 44 734 48 +rect 762 44 766 48 +rect 794 44 798 48 +rect 26 40 46 44 +rect 58 40 78 44 +rect 90 40 110 44 +rect 122 40 142 44 +rect 154 40 174 44 +rect 186 40 206 44 +rect 218 40 238 44 +rect 250 40 270 44 +rect 282 40 302 44 +rect 314 40 334 44 +rect 346 40 366 44 +rect 378 40 398 44 +rect 410 40 430 44 +rect 442 40 462 44 +rect 474 40 494 44 +rect 506 40 526 44 +rect 538 40 558 44 +rect 570 40 590 44 +rect 602 40 622 44 +rect 634 40 654 44 +rect 666 40 686 44 +rect 698 40 718 44 +rect 730 40 750 44 +rect 762 40 782 44 +rect 794 40 814 44 +rect -6 32 22 36 +rect 34 32 38 40 +rect 66 32 70 40 +rect 98 32 102 40 +rect 130 32 134 40 +rect 162 32 166 40 +rect 194 32 198 40 +rect 226 32 230 40 +rect 258 32 262 40 +rect 290 32 294 40 +rect 322 32 326 40 +rect 354 32 358 40 +rect 386 32 390 40 +rect 418 32 422 40 +rect 450 32 454 40 +rect 482 32 486 40 +rect 514 32 518 40 +rect 546 32 550 40 +rect 578 32 582 40 +rect 610 32 614 40 +rect 642 32 646 40 +rect 674 32 678 40 +rect 706 32 710 40 +rect 738 32 742 40 +rect 770 32 774 40 +rect 802 32 806 40 +use Library/magic/L500_CHAR_r L500_CHAR_r_0 +timestamp 1534323573 +transform 1 0 0 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_o L500_CHAR_o_0 +timestamp 1534323159 +transform 1 0 16 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_5 L500_CHAR_5_0 +timestamp 1534324893 +transform 1 0 32 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_o L500_CHAR_o_1 +timestamp 1534323159 +transform 1 0 32 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_1 L500_CHAR_1_0 +timestamp 1534326485 +transform 1 0 48 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_under L500_CHAR_under_0 +timestamp 1534325915 +transform 1 0 64 0 1 162 +box 0 0 12 4 +use Library/magic/L500_CHAR_n L500_CHAR_n_0 +timestamp 1534323117 +transform 1 0 80 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_a L500_CHAR_a_0 +timestamp 1534325357 +transform 1 0 96 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_n L500_CHAR_n_1 +timestamp 1534323117 +transform 1 0 112 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_d L500_CHAR_d_0 +timestamp 1534321738 +transform 1 0 128 0 1 162 +box 0 0 12 18 +use Library/magic/L500_CHAR_3 L500_CHAR_3_0 +timestamp 1534324785 +transform 1 0 144 0 1 162 +box 0 0 12 18 +use Library/magic/L500_TPAD_blank L500_TPAD_blank_1 +timestamp 1537343441 +transform 1 0 -310 0 1 28 +box 0 0 100 100 +use Library/magic/L500_SIGNATURE_vdd L500_SIGNATURE_vdd_0 +timestamp 1538544897 +transform 1 0 -170 0 1 100 +box 0 0 52 18 +use Library/magic/L500_SIGNATURE_gnd L500_SIGNATURE_gnd_0 +timestamp 1538544897 +transform 1 0 -200 0 1 38 +box 0 0 52 18 +use Library/magic/L500_TPAD_blank L500_TPAD_blank_0 +timestamp 1537343441 +transform 1 0 -110 0 1 28 +box 0 0 100 100 +use Library/magic/T10_NAND3 T10_NAND3_49 +timestamp 1533654785 +transform -1 0 32 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_48 +timestamp 1533654785 +transform -1 0 64 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_47 +timestamp 1533654785 +transform -1 0 96 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_46 +timestamp 1533654785 +transform -1 0 128 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_45 +timestamp 1533654785 +transform -1 0 160 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_44 +timestamp 1533654785 +transform -1 0 192 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_43 +timestamp 1533654785 +transform -1 0 224 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_42 +timestamp 1533654785 +transform -1 0 256 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_41 +timestamp 1533654785 +transform -1 0 288 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_40 +timestamp 1533654785 +transform -1 0 320 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_39 +timestamp 1533654785 +transform -1 0 352 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_38 +timestamp 1533654785 +transform -1 0 384 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_37 +timestamp 1533654785 +transform -1 0 416 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_36 +timestamp 1533654785 +transform -1 0 448 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_35 +timestamp 1533654785 +transform -1 0 480 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_34 +timestamp 1533654785 +transform -1 0 512 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_33 +timestamp 1533654785 +transform -1 0 544 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_32 +timestamp 1533654785 +transform -1 0 576 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_31 +timestamp 1533654785 +transform -1 0 608 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_30 +timestamp 1533654785 +transform -1 0 640 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_29 +timestamp 1533654785 +transform -1 0 672 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_28 +timestamp 1533654785 +transform -1 0 704 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_27 +timestamp 1533654785 +transform -1 0 736 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_26 +timestamp 1533654785 +transform -1 0 768 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_25 +timestamp 1533654785 +transform -1 0 800 0 -1 158 +box 0 0 32 80 +use Library/magic/T10_NAND2 T10_NAND2_1 +timestamp 1533654735 +transform -1 0 824 0 -1 158 +box 0 0 24 80 +use Library/magic/T10_NAND2 T10_NAND2_0 +timestamp 1533654735 +transform 1 0 0 0 1 -2 +box 0 0 24 80 +use Library/magic/T10_NAND3 T10_NAND3_0 +timestamp 1533654785 +transform 1 0 24 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_1 +timestamp 1533654785 +transform 1 0 56 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_2 +timestamp 1533654785 +transform 1 0 88 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_3 +timestamp 1533654785 +transform 1 0 120 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_4 +timestamp 1533654785 +transform 1 0 152 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_5 +timestamp 1533654785 +transform 1 0 184 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_6 +timestamp 1533654785 +transform 1 0 216 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_7 +timestamp 1533654785 +transform 1 0 248 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_8 +timestamp 1533654785 +transform 1 0 280 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_9 +timestamp 1533654785 +transform 1 0 312 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_10 +timestamp 1533654785 +transform 1 0 344 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_11 +timestamp 1533654785 +transform 1 0 376 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_12 +timestamp 1533654785 +transform 1 0 408 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_13 +timestamp 1533654785 +transform 1 0 440 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_14 +timestamp 1533654785 +transform 1 0 472 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_15 +timestamp 1533654785 +transform 1 0 504 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_16 +timestamp 1533654785 +transform 1 0 536 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_17 +timestamp 1533654785 +transform 1 0 568 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_18 +timestamp 1533654785 +transform 1 0 600 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_19 +timestamp 1533654785 +transform 1 0 632 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_20 +timestamp 1533654785 +transform 1 0 664 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_21 +timestamp 1533654785 +transform 1 0 696 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_22 +timestamp 1533654785 +transform 1 0 728 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_23 +timestamp 1533654785 +transform 1 0 760 0 1 -2 +box 0 0 32 80 +use Library/magic/T10_NAND3 T10_NAND3_24 +timestamp 1533654785 +transform 1 0 792 0 1 -2 +box 0 0 32 80 +use Library/magic/L500_TPAD_blank L500_TPAD_blank_2 +timestamp 1537343441 +transform 1 0 826 0 1 28 +box 0 0 100 100 +use Library/magic/L500_SIGNATURE_vdd L500_SIGNATURE_vdd_1 +timestamp 1538544897 +transform 1 0 936 0 1 100 +box 0 0 52 18 +use Library/magic/L500_SIGNATURE_gnd L500_SIGNATURE_gnd_1 +timestamp 1538544897 +transform 1 0 964 0 1 38 +box 0 0 52 18 +use Library/magic/L500_TPAD_blank L500_TPAD_blank_3 +timestamp 1537343441 +transform 1 0 1026 0 1 28 +box 0 0 100 100 +<< end >> + +EOF +; diff --git a/Tools/perl/paintgridusage.pl b/Tools/perl/paintgridusage.pl new file mode 100755 index 00000000..57aed763 --- /dev/null +++ b/Tools/perl/paintgridusage.pl @@ -0,0 +1,68 @@ +#!/usr/bin/perl -w + +print "This tool analyzes the available, used and unused grid:\n"; +my $cellname=$ARGV[0] || "INV"; +open MAGIN,"<$cellname.mag"; +open REPORT,"<$cellname.err"; +#open REPIN,"<$cellname.log"; +open MAGOUT,">$cellname.grid.mag"; +my $fac=5; +my $s=5; +my $t=2; +while() +{ + if(/<< labels >>/) + { + # Unused tracks + while (my $line=) + { + if($line=~m/Unused tracks \(x coordinates\): \[(.*?)\]/) + { + foreach(split(",",$1)) + { + $_=int($_/$fac); + print MAGOUT "<< met1 >>\nrect $_ -100 ".($_+$s)." $t\n"; + } + } + if($line=~m/Unused tracks \(y coordinates\): \[(.*?)\]/) + { + foreach(split(",",$1)) + { + $_=int($_/$fac); + print MAGOUT "<< met1 >>\nrect -100 $_ $t ".($_+$s)."\n"; + } + } + if($line=~m/grid_xs: \[(.*?)\]/) + { + foreach(split(",",$1)) + { + $_=int($_/$fac); + print MAGOUT "<< met2 >>\nrect $_ -200 ".($_+$s)." -110\n"; + } + } + if($line=~m/grid_ys: \[(.*?)\]/) + { + foreach(split(",",$1)) + { + $_=int($_/$fac); + print MAGOUT "<< met2 >>\nrect -200 $_ -100 ".($_+$s)."\n"; + } + } + if($line=~m/via cost: (\d+) \((-?\d+),(-?\d+)\) (\w+)/) + { + my $x=int($2/$fac); + my $y=int($3/$fac); + next unless($4 eq "pdiff_contact"); + print "via cost $1 $2 $3 $4\n"; + print MAGOUT "<< ".($1?"via3":"met3")." >>\nrect $x $y ".($x+$s)." ".($y+$s)."\n"; + } + + } + } + print MAGOUT $_; +} +close MAGIN; +close REPORT; +#close REPIN; +close MAGOUT; +print "Writing to $cellname.grid.mag\n"; diff --git a/Tools/perl/parasitics.pl b/Tools/perl/parasitics.pl new file mode 100755 index 00000000..222229ad --- /dev/null +++ b/Tools/perl/parasitics.pl @@ -0,0 +1,87 @@ +#!/usr/bin/perl -w + +my $mag=$ARGV[0] || ""; $mag=~s/\.mag$//i; +my $sp=$mag; $sp.=".par.sp"; +my $par=$ARGV[1] || $sp; + +my $tech=$ARGV[2] || "../Tech/libresilicon.tech"; + +print "parasitics.pl - Extract parasitics from a .mag file for characterization into a .par.sp (PARasitics-SPice) file\n"; +print "Usage: parasitics.pl input.mag output.par.sp\n"; + +if(-f "$mag.mag") +{ + unlink "$mag.nodes"; + unlink "$mag.res.ext"; + unlink "$mag.spice"; + unlink "$mag.ext"; + unlink "$mag.al"; + unlink "$mag.res.lump"; + unlink "$mag.sim"; + + print "First magic call:\n"; + open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; + print OUT <>$cellname.ext"; +# #system "cat $cellname.ext"; +# print "Second magic call:\n"; +# open OUT,"|magic -dnull -noconsole -T $tech $mag.mag"; +# print OUT <=$trans?$vddgnd:$nsource+1; + + + my $ndrain=($variant%($trans+2)); + $variant=int($variant/($trans+2)) if($varydrains); + $ndrain=$trans if(!$varydrains); + #print "ndrain: $ndrain trans: $trans\n"; + my $drain=($ndrain eq $trans)?"Z":($ndrain>$trans)?"Y":$ndrain+1; + + print "$mosfet $gate $drain $source\n"; + } + print "\n"; +} + + +############ + +foreach my $ntransistors(1 .. $maxtransistors) +{ + print "################ Trying $ntransistors transistors... ################\n"; + my $poss=cellPossibilities($ntransistors); + print "They have $poss possible variants.\n"; + foreach my $i (0 .. $poss-1) + { + print "Trying to generate variant #$i ...\n"; + genCell($ntransistors,$i); + } + +} + + + diff --git a/Tools/perl/report.pl b/Tools/perl/report.pl new file mode 100755 index 00000000..9e761252 --- /dev/null +++ b/Tools/perl/report.pl @@ -0,0 +1,111 @@ +#!/usr/bin/perl -w + +sub readfile($) +{ + if(open MYRIN,"<$_[0]") + { + my $old=$/; + undef $/; + my $content=; + close MYRIN; + $/=$old; + return $content; + } + return undef; +} + +our %stats=(); + +open OUT,">report.csv"; +foreach my $py() +{ + my $params=$1 if($py=~m/ls(.*)\.py$/); + my $err=$py; $err=~s/\.py$/.err/; + my $gerr=$py; $gerr=~s/\.py$/.gerr/; + my $gds=$py; $gds=~s/\.py$/.gds/; + my $good=$py; $good=~s/\.py$/.good/; + my $mag=$py; $mag=~s/\.py$/.mag/; + my $ann=$gds.".ann"; + + my $errcontent=readfile($err); + my $gerrcontent=readfile($err); + my $anncontent=readfile($ann)||""; + my $isgds=-s $gds; + my $isgood=($anncontent=~m/y/i); + my $isworking=-s $mag; + my $error="UNKNOWN"; + my $weight=0; + + if($isworking) + { + $error="working"; + $weight=100; + } + elsif($isgood) + { + $error="good"; + $weight=90; + } + elsif($errcontent=~m/Gate not x-aligned on grid/) # Bug or parameters not checked + { # assert (center_x - tech.grid_offset_x) % tech.routing_grid_pitch_x == 0, Exception("Gate not x-aligned on grid.") + $error="gateXalign"; + } + elsif($errcontent=~m/Terminal node not x-aligned/) # Bug or parameters not checked + { # assert next_x == x, Exception("Terminal node not x-aligned.") + $error="terminalXalign"; + } + elsif($errcontent=~m/Graph has been disconnected/) # Bug or parameters not checked + { # Exception("Graph has been disconnected by removal of reserved nodes.") + $error="GraphDisconnect"; + } + elsif($gerrcontent=~m/ZeroDivisionError:/) # Bug caused by grid_offset_x=0 + { + $error="ZeroDivision"; + } + elsif($errcontent=~m/assert nx\.is_connected\(graph\)/) # Bug or parameters not checked + { + $error="connectedGraph"; + } + elsif($errcontent=~m/Nets without terminals/) # Bug or parameters not checked + { + $error="NetsWithoutTerminals"; + } + elsif($errcontent=~m/min\(\) arg is an empty seq/) # Bug + { + $error="minArgEmpty"; + } + elsif($errcontent=~m/KeyError.*metal1/) # Bug or parameters not checked + { + $error="KeyErrorMetal1"; + } + elsif($errcontent=~m/Keyboard/) # It was interrupted by the user, not a bug + { + unlink $py; + unlink $gds; + unlink $err; + unlink $gerr; + next; + } + elsif($errcontent=~m/has no attribute 'multi_via'/) # Tech file was empty + { + next; + } + else + { + #print "Unknown status: $errcontent\n"; + $error="UNKNOWN-TO-BE-CLASSIFIED"; + } + print OUT "".join(";",split("_",$params)).";".$error.";$weight\n"; + $stats{$error}++; + $stats{$weight}++; + + +} + + +foreach (sort keys %stats) +{ + print "$_: $stats{$_}\n"; +} + + diff --git a/Tools/perl/searchTechRules.pl b/Tools/perl/searchTechRules.pl new file mode 100755 index 00000000..3fe8371b --- /dev/null +++ b/Tools/perl/searchTechRules.pl @@ -0,0 +1,94 @@ +#!/usr/bin/perl -w +use strict; + +print "searchTechRules.pl searches for working Tech Rules\n"; + +system "perl ../Tools/perl/cell2spice.pl"; + +my @params=( + #["unit_cell_width",20,100,5], + #["unit_cell_height",100,200,5], + #["routing_grid_pitch_x",20,20,5], + #["routing_grid_pitch_y",20,20,5], + #["grid_offset_x",5,50,5], + #["grid_offset_y",0,40,5], + #["power_rail_width",30,30,5], + #["minimum_gate_width_nfet",35,35,5], + #["minimum_gate_width_pfet",35,35,5], + #["minimum_pin_width",5,15,5], +); + +mkdir "str"; +chdir "str"; + +our $ende=0; + +my $cell=$ARGV[0] || "INV"; + +while(!$ende) +{ + if(-f ".end") + { + unlink ".end"; + print "Exiting...\n"; + exit; + } + + my %par=(); + my @b=(); + foreach my $a (@params) + { + my $v=$$a[1]+int(rand(($$a[2]-$$a[1]+1)/$$a[3]))*$$a[3]; + print "$$a[0] $$a[1]-$$a[2] steps:$$a[3] -> $v\n"; + exit if($v>$$a[2] || $v<$$a[1]); + #exit if($v ==$$a[2]); + $par{$$a[0]}=$v; + push @b,$v; + } + + my $fn="ls".join("_",@b); + + open IN,"<../../Tech/librecell_tech.py"; + open OUT,">$fn.py"; + while() + { + if(m/(\w+)\s*=/) + { + #print "? $1\n"; + if(defined($par{$1})) + { + #print "Exchanging $par{$1} into $_"; + $_="$1 = $par{$1}\n"; + } + } + print OUT $_; + } + close IN; + close OUT; + + unlink "$cell.gds"; + my $found=""; + system "lclayout --output-dir . --tech $fn.py --netlist ../libresilicon.sp --cell $cell -v --placement-file $cell.place --debug-routing-graph 2>$fn.gerr"; + if(-f "$cell.gds") + { + rename "$cell.gds","$fn.graph.gds"; + $found.="$fn.graph.gds"; + } + + system "lclayout --output-dir . --tech $fn.py --netlist ../libresilicon.sp --cell $cell -v --placement-file $cell.place 2>$fn.err"; + if(-f "$cell.gds") + { + rename "$cell.gds","$fn.final.gds"; + $found.=" $fn.final.gds"; + } + + system "cat $fn.gerr $fn.err"; + + if($found ne "") + { + my $names=""; $names="-l ../librecell.lyp"; + system "klayout $names ../*.gds $found" unless(-f ".hide"); + } + exit; +} + diff --git a/Tools/perl/spice2cell.pl b/Tools/perl/spice2cell.pl new file mode 100755 index 00000000..921b6a52 --- /dev/null +++ b/Tools/perl/spice2cell.pl @@ -0,0 +1,168 @@ +#!/usr/bin/perl -w +use strict; + +if($#ARGV) +{ + print "spice2cell converts SPICE compatible .sp files to Popcorn compatible .cell files\n"; + print "Usage: spice2cell \n"; +} + +# This is an example AND2X1 cell in SPICE format: +my $example=<'I','B'=>'I','C'=>'I','CN'=>'I','CLK'=>'I','D'=>'I','EN'=>'I','Q'=>'O','R'=>'I','S'=>'I','Y'=>'O','YC'=>'O','YS'=>'O','gnd'=>'','vdd'=>'','GND'=>'','VDD'=>'','Z'=>'O','DI'=>'I','DO'=>'O','OEN'=>'I','YPAD'=>'O','gnd2'=>'','vdd2'=>'','GND2'=>'','VDD2'=>'','vss'=>'','VSS'=>''); +my %mosmap=('pfet'=>'pmos','nfet'=>'nmos','nmos'=>'nmos','pmos'=>'pmos','hnfet'=>'nmos','hpfet'=>'pmos','enbsim3'=>'nmos','epbsim3'=>'pmos','sky130_fd_pr__nfet_01v8'=>'nmos','sky130_fd_pr__pfet_01v8'=>'pmos'); +our %internalnets=(); +our $internalcounter=0; +our $OUT; + +# Generates and caches new names for the internal nets, which must be unique per cell +sub internal($) +{ + my $in=$_[0]; + return $in unless($in=~m/\#$/); + #print $OUT "#$in? $internalcounter\n"; + $internalnets{$in}=$internalcounter++ if(!defined($internalnets{$in})); + return $internalnets{$in}; +} +sub internal2($) +{ + my $in=$_[0]; + return $in unless($in=~m/\@/); + #print $OUT "#$in? $internalcounter\n"; + $internalnets{$in}=$internalcounter++ if(!defined($internalnets{$in})); + return $internalnets{$in}; +} + +if($ARGV[0] && open IN,"<$ARGV[0]") +{ + while() + { + if(m/^\.subckt (\w+) (.*)$/ || m/TOP LEVEL CELL: (\w+)\{sch\}()/ || m/^\*\*\.subckt (\w+) (.*)$/ ) + { + $name=$1; + $pins=$2; + %internalnets=(); + $internalcounter=1; + my %pins=(); + $pins{$iomap{$_}}{$_}++ foreach(split " ",$pins); + $seenpins{$_}++ foreach(split " ",$pins); + open $OUT,">".uc($name).".cell"; + print $OUT ".AUTOGENERATED by spice2cell script from $ARGV[0]\n"; + print $OUT ".inputs ".join(" ",reverse sort keys %{$pins{'I'}})."\n"; + print $OUT ".outputs ".join(" ",reverse sort keys %{$pins{'O'}})."\n"; + print $OUT ".ORDER \"MOSFET Gate Drain Source\"\n"; + } + elsif(m/^X?[MNP]\d+ (\w+#?) (\w+#?) (\w+#?) (\w+#?) (pfet|nfet|nmos|pmos|hnfet|hpfet|enbsim3|epbsim3|sky130_fd_pr__nfet_01v8|sky130_fd_pr__pfet_01v8)/i) + { + my ($g,$d,$s,$m)=($2,$1,$3,$5); + if($d=~m/^(vdd|gnd)$/i) + { + print "EXCHANGING SOURCE AND DRAIN: $_"; + ($s,$d)=($d,$s); + } + $g=internal($g); + $d=internal($d); + $s=internal($s); + print $OUT $mosmap{$m}." $g $d $s\n"; + } + elsif(m/^X?[MXNP]\d+ (\w+#?) (\w+#?) (\w+#?) (pfet|nfet|nmos|pmos|hnfet|hpfet|enbsim3|epbsim3|sky130_fd_pr__nfet_01v8|sky130_fd_pr__pfet_01v8)/i) + { + my ($g,$d,$s,$m)=($2,$1,$3,$4); + if($d=~m/^(vdd|gnd)$/i) + { + print "EXCHANGING SOURCE AND DRAIN: $_"; + ($s,$d)=($d,$s); + } + $g=internal($g); + $d=internal($d); + $s=internal($s); + print $OUT "".$mosmap{$m}." $g $d $s\n"; + } + elsif(m/^M(n|p)mos\@\d+ (\w+\@?\d*) (\w+\@?\d*) (\w+\@?\d*) (\w+\@?\d*)/) + { + my ($g,$d,$s,$m)=($3,$2,$4,$1."mos"); + $g=internal2($g); + $d=internal2($d); + $s=internal2($s); + print $OUT $mosmap{$m}." $g $d $s\n"; + } + elsif(m/^R\w+\@\d+ (\w+\@?\d*) (\w+\@?\d*) (\d+\.?\d*)/) + { # Rres@0 net@25 YPAD 100 + my ($n1,$n2,$v)=($1,$2,$3); + $n1=internal2($n1); + $n2=internal2($n2); + print $OUT "res $n1 $n2 $v\n"; + } + elsif(m/R\d+ (\w+#?) (\w+#?) (\d+)/) + { + my ($n1,$n2,$v)=($1,$2,$3); + $n1=internal($n1); + $n2=internal($n2); + print $OUT "res $n1 $n2 $v\n"; + } + elsif(m/^\*/) + { + } + elsif(m/^\+/) + { + } + elsif(m/^\s*$/) + { + } + elsif(m/^\.global (\w+)/i) + { + } + elsif(m/^\.ends?/) + { + $name="UNNAMED"; + $pins=""; + close $OUT; + } + else + { + print STDERR "Error: $_\n"; + } + + } + close IN; +} + +my $undefinedpins=0; +foreach(keys %seenpins) +{ + $undefinedpins++ unless(defined($iomap{$_})); +} + +if($undefinedpins) +{ + print "Not yet defined pins, please update them in the sourcecode:\n("; + foreach(sort keys %seenpins) + { + next if(defined($iomap{$_})); + print "'$_'=>'I'," ; + } + print ")\n"; +} diff --git a/Tools/perl/testgen.pl b/Tools/perl/testgen.pl new file mode 100755 index 00000000..fbd1e0b1 --- /dev/null +++ b/Tools/perl/testgen.pl @@ -0,0 +1,181 @@ +#!/usr/bin/perl -w + +print STDERR "Usage: perl ../Tools/perl/testgen.pl [] >sky130_stdcelllib_test/verilog/dv/stdcells/stdcells.c\n"; + +my @cells=map { s/\.cell$//; s/\.truthtable\.v$//; $_; } (defined($ARGV[0]) && -f $ARGV[0])?[$ARGV[0]]:<*.cell>; +my $useassert=0; + +print < +#include +#include + +char *current_cell=""; +int current_test=0; +EOF +; + +if($useassert) +{ + print <>num)&1); + if(num<64) return ((reg_la1_data>>(num-32))&1); + if(num<96) return ((reg_la2_data>>(num-64))&1); + return ((reg_la3_data>>(num-96))&1); +} +void write_la(int num, int value) +{ + if(num<32) reg_la0_data=reg_la0_data&(0xffffffff-(1<\; $header=~s/\s$//s; + print "// Cell: $cell ($header)\n"; + print " current_cell=\"$cell\";\n"; + + #print STDERR $header; + my @l=split "->",$header; + my @ins=split " ",$l[0]; + my @outs=split " ",$l[1]; + my %map=(); + + my @io=(); + print " print(\"Connecting Inputs of the cell $cell with the management core:\\n\");\n"; + foreach(@ins) + { + $map{$_}=$reg; + print " reg_mprj_io_$reg = GPIO_MODE_MGMT_STD_OUTPUT; // $_\n"; + $io[$reg>>5]|=1<<($reg&31); + $reg++; + } + print " print(\"Connecting the Outputs of the cell $cell with the management core:\\n\");\n"; + foreach(@outs) + { + $map{$_}=$reg; + print " reg_mprj_io_$reg = GPIO_MODE_USER_STD_OUTPUT; // $_\n"; + $reg++; + } + + # Transferring the register values: + print " reg_mprj_xfer=1;\n"; + print " while (reg_mprj_xfer == 1);\n"; + +print <) + { + last if(m/^function:/); + print " current_test=$counter;\n"; + @l=split " ",$_; + my $if=0; + foreach(@l) + { + if(m/(\w+)=HIGH-Z/) + { + print " //We expect HIGH-Z Output on Output $1 here\n"; + } + elsif(m/(\w+)=(\d|HIGH-Z)/) + { + print " assert(get_la(".$map{$1}.")==$2); //$1\n" if($useassert); + if(!$useassert) + { + print " if(get_la(".$map{$1}.")!=$2) //$1\n"; + print " {\n"; + print " print(\"Assertion failed in cell $cell in test #$counter : $1 should be $2\\n\");\n"; + print " reg_mprj_datal = 0xAB51EEEE; // Signal that the simulation has failed\n"; + print " return(-1);\n"; + print " }\n"; + } + } + else + { + print " write_la(".$map{$ins[$if]}.",$_); //$ins[$if]\n"; + } + $if++; + } + print " print(\"Test $counter for cell $cell successful\\n\");\n\n"; + + $counter++; + } + print "print(\"Tests for $cell successful.\\n\");\n\n"; + close IN; +} + +print "print(\"All standard cells have been tested successfully.\\n\");\n\n"; +print "reg_mprj_datal = 0xAB51FEFE; // Signal that the simulation is done\n"; + + +print "}\n"; + +print STDERR "Run the test by running: make verify-stdcells-rtl\n"; diff --git a/Tools/perl/truthtable.pl b/Tools/perl/truthtable.pl index b0d9d3c6..11d776f9 100755 --- a/Tools/perl/truthtable.pl +++ b/Tools/perl/truthtable.pl @@ -2,13 +2,18 @@ use strict; use Getopt::Long; +# Parameters and their default values: our $debug=0; -our $format="text"; # html latex +our $format="text"; # html latex text liberty verilog +# Parsing the commandline parameters: GetOptions ("debug" => \$debug, "v" => \$debug, - "format=s" => \$format); + "format=s" => \$format); # text,html,latex,liberty,verilog,testcad +our $testcadcounter=1; + +# Convert a value to the gray code value: sub bin2gray { return $_[0] ^ ($_[0] >> 1); @@ -19,6 +24,7 @@ sub verb # verbose debug output print $_[0] if($debug); } +# Calculating the truth table for sub truth { my @l=@{$_[0]}; @@ -44,11 +50,37 @@ sub truth { s/\s+$//m; verb "Line: $_\n"; - if(m/^(\w+) (\w+) (\w+) ([pn]mos)/i) + if(m/^res (\w+) (\w+) (\d+\.?\d*)/i) { - my ($s,$g,$d,$tr)=($1,$2,$3,$4); - $g=~s/^(\d+)$/$tr$1/; - $d=~s/^(\d+)$/$tr$1/; + my ($n1,$n2,$v)=($1,$2,$3); + verb "Resistor found\n"; + my $i1=($n1=~m/^(vdd|gnd)$/i)?$n1:(defined($iv{$n1}) && $iv{$n1}=~m/^(vdd|gnd|0|1)$/i)?$iv{$n1}:undef; + verb "i1: ".($i1||"")."\n"; + my $i2=($n2=~m/^(vdd|gnd)$/i)?$n2:(defined($iv{$n2}) && $iv{$n2}=~m/^(vdd|gnd|0|1)$/i)?$iv{$n2}:undef; + verb "i2: ".($i2||"")."\n"; + if((defined($i1) && defined($i2)) && (($i1=~m/vdd/i && $i2=~m/gnd/i) || ($i1=~m/vdd/i && $i2=~m/gnd/i))) + { + die "ERROR: Short circuit detected: $n1->$i1->$iv{$n1} $n2->$i2->$iv{$2}!\n"; + } + if(defined($i1)) + { + verb "Setting: $n2 <= $i1\n"; + $iv{$n2}=$i1; + } + if(defined($i2)) + { + verb "Setting: $n1 <= $i2\n"; + $iv{$n1}=$i2; + } + $hadwork=1 if(defined($i1) || defined($i2)); + push @nexttodo,$_ if((!defined($iv{$n1})) && (!defined($iv{$n2}))); + verb "Status: Net1: $n1-".($iv{$n1}||"")." Net2: $n2-".($iv{$n2}||"")."\n"; + } + if(m/^([pn]mos) (\w+) (\w+) (\w+)/i) + { + my ($tr,$s,$g,$d)=($1,$2,$3,$4); + #$g=~s/^(\d+)$/$tr$1/; This was necessary when popcorn generated same names for different internal nets in nmos and pmos + #$d=~s/^(\d+)$/$tr$1/; But it failed for less structured cells (e.g. transmission gates) verb "Transistor: $_\n"; if(defined($iv{$s})) @@ -58,16 +90,28 @@ sub truth if($t) { verb "Transitor conducting\n"; - my $ig=($g=~m/^(vdd|gnd)$/i)?$g:(defined($iv{$g}) && $iv{$g}=~m/^(vdd|gnd)$/i)?$iv{$g}:undef; - my $id=($d=~m/^(vdd|gnd)$/i)?$d:(defined($iv{$d}) && $iv{$d}=~m/^(vdd|gnd)$/i)?$iv{$d}:undef; + verb "g: $g iv{g}=".($iv{$g}||"")."\n"; + verb "d: $d iv{d}=".($iv{$d}||"")."\n"; + my $ig=($g=~m/^(vdd|gnd)$/i)?$g:(defined($iv{$g}) && $iv{$g}=~m/^(vdd|gnd|0|1)$/i)?$iv{$g}:undef; + verb "ig: ".($ig||"")."\n"; + my $id=($d=~m/^(vdd|gnd)$/i)?$d:(defined($iv{$d}) && $iv{$d}=~m/^(vdd|gnd|0|1)$/i)?$iv{$d}:undef; + verb "id: ".($id||"")."\n"; if((defined($ig) && defined($id)) && (($ig=~m/vdd/i && $id=~m/gnd/i) || ($ig=~m/vdd/i && $id=~m/gnd/i))) { - die "ERROR: Short cirtuit detected: $g->$ig->$iv{$g} $d->$id->$iv{$d}!\n"; + die "ERROR: Short circuit detected: $g->$ig->$iv{$g} $d->$id->$iv{$d}!\n"; + } + if(defined($ig)) + { + verb "Setting: $d <= $ig\n"; + $iv{$d}=$ig; } - $iv{$d}=$ig if(defined($ig)); - $iv{$g}=$id if(defined($id)); - $hadwork=1 if(defined($id) || defined($ig)); + if(defined($id)) + { + verb "Setting: $g <= $id\n"; + $iv{$g}=$id; + } + $hadwork=1 if(defined($id) || defined($ig)); push @nexttodo,$_ if((!defined($iv{$d})) && (!defined($iv{$g}))); verb "Status: Source: $d-".($iv{$d}||"")." Drain: $g-".($iv{$g}||"")."\n"; } @@ -86,6 +130,10 @@ sub truth if(!$hadwork) { verb "No further progress. Exiting.\n"; + foreach(sort keys %iv) + { + verb "Status: $_ : $iv{$_}\n"; + } last; } verb "Still to be done:\n@nexttodo\n\n"; @@ -101,38 +149,70 @@ sub truth return %iv; } -if(!scalar(@ARGV)) + +if(!scalar(@ARGV)) # no parameters were given { print "Calculates the truthtable for a given cell\n"; print "Usage: truthtable.pl \n"; } +# Take all the given filenames from the commandline foreach my $file(@ARGV) { + my $cellname=$file; $cellname=~s/\.cell$//; + + # Open each file if(open(IN,"<$file")) { - print STDERR "Analyzing $file\n"; - my @lines=; + print STDERR "Analyzing $file\n" if($debug); + my @lines=; # Read all lines into an array close IN; my %inputs=(); my %intermediates=(); my %outputs=(); - + my %differential=(); + + # Here we are parsing all transistor lines for input-, output- and intermediate nets + # But this is just a guess: foreach(@lines) { - next if(m/^#/); - $inputs{$1}=1 if(m/^([A-W]\d*) .*[pn]mos/); - $intermediates{$1}=1 if(m/^([X-Y]\d*) .*[pn]mos/); - $outputs{$1}=1 if(m/^\w+ ([X-Z]\d*) .*[pn]mos/); + next if(m/^#/); # Ignore comment lines + #$differential{$1}=$2 if(m/^\.differential (\w+) (\w+)/); + $inputs{$1}=1 if(m/^[pn]mos\s*([A-W]+\d*)/); + $intermediates{$1}=1 if(m/^[pn]mos.*([X-Y]\w*\d*)/); + $outputs{$1}=1 if(m/^[pn]mos.*\w+ ([X-Z]\w*\d*)/); } - delete($outputs{"Y"}) if(defined($outputs{"Z"})); + delete($outputs{"Y"}) if(defined($outputs{"Z"})); # If we have Z, then Y is an internal net and Z is the output net my @ins=sort keys %inputs; my @outs=sort keys %outputs; - my $ninputs=scalar(keys %inputs); my $combinations=2**$ninputs; - my $noutputs=scalar(keys %outputs); + # Now we are parsing for the real inputs and ouputs if they are available + foreach my $line(@lines) + { + @ins=split(" ",$1) if($line=~m/^\.inputs (\w.*)/i); + @outs=split(" ",$1) if($line=~m/^\.outputs (\w.*)/i) + } + $inputs{$_}=1 foreach(@ins); + + foreach my $a(@ins) + { + if($a=~m/_n$/) + { + my $b=$a; $b=~s/_n$/_p/; + if(defined($inputs{$b})) + { + $differential{$a}=$b; + #print STDERR "Differential input detected: $a <-> $b\n"; + } + } + } + + my $ninputs=scalar(@ins); + my $noutputs=scalar(@outs); + my $combinations=2**$ninputs; # We calculate the number of possible combinations in the truthtable + verb "Number of Inputs: $ninputs (".join(",",@ins).") -> Combinations: $combinations\n"; verb "Number of Outputs: $noutputs (".join(",",@outs).")\n"; @@ -141,6 +221,7 @@ sub truth die "ERROR: A cell without an input!\n"; } + # Now we start with the header of the output files: if($format eq "text") { print join(" ",@ins)."->".join(" ",@outs); print "\n"; @@ -159,15 +240,15 @@ sub truth %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% -%% File: StdCellLib/Documents/LaTeX/truthtable_AOI21.tex +%% File: StdCellLib/Documents/LaTeX/truthtable_$cellname.tex %% -%% Purpose: Truth Table File for AOI21 +%% Purpose: Truth Table File for $cellname %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% -%% Copyright (c) 2018 by chipforge +%% Copyright (c) 2019 by chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon @@ -187,44 +268,74 @@ sub truth EOF ; -print " {\(Z = \\lnot ((B1 \\land B0) \\lor A) \\)}\n"; -print " \\begin{table}[h] %\\caption{\\(Z = \\lnot ((B1 \\land B0) \\lor A) \\)}\n"; -print " \\begin{center}\n"; -print " \\begin{tabular}{"; -print "|c" foreach(@ins); -print "|"; -print "|c" foreach(@outs); -print "|} \\hline\n"; -print " "; print join(" & ",@ins)." & ".join(" & ",@outs)." \\\\ \\hline\\hline\n"; + print " {\(Z = \\lnot ((B1 \\land B0) \\lor A) \\)}\n"; + print " \\begin{table}[h] %\\caption{\\(Z = \\lnot ((B1 \\land B0) \\lor A) \\)}\n"; + print " \\begin{center}\n"; + print " \\begin{tabular}{"; + print "|c" foreach(@ins); + print "|"; + print "|c" foreach(@outs); + print "|} \\hline\n"; + print " "; + print join(" & ",@ins)." & ".join(" & ",@outs)." \\\\ \\hline\\hline\n"; } elsif($format eq "html") { - print ""; + print "
".join("",@ins)."".join("",@outs)."
\n\n"; + } + elsif($format eq "testcad") + { + foreach (@ins) + { + print "$testcadcounter PI ".($testcadcounter+1)." ; # $_\n"; + $testcadcounter+=2; + } } + my %values=(); our %sum=(); our %results=(); + # Now we calculate all the truth-table values: foreach my $i(0 .. 2**$ninputs-1) { + # We count from 0 .. 2^n-1 and take the graycode, and then interpret that as a binary value for the input stimulus: + my $output=""; my $gray=bin2gray($i); - print " " if($format eq "latex"); + $output.=" " if($format eq "latex"); + $output.="" if($format eq "html"); foreach(0 .. $ninputs-1) { - print "& " if($format eq "latex" && $_>0); - print "".($gray&(1<<$_))?"1 ":"0 "; + $output.="& " if($format eq "latex" && $_>0); + $output.="" if($format eq "html"); $values{$ins[$_]}=($gray&(1<<$_))?1:0; } + + my $ignoreinvalidinputs=0; # Look for differential inputs that have the same value, and are therefore invalid + foreach my $k1(keys %differential) + { + $ignoreinvalidinputs=1 if($values{$k1} eq $values{$differential{$k1}}); + } + next if($ignoreinvalidinputs); + + print $output; + + # Here we are using the truth function to calculate all network states for the given inputs: my %res=truth(\@lines,\%values); - + # The result is a hash with the intermediate/output netnames as keys and the resulting values as values + + # Now we are analyzing the results foreach my $out (@outs) { - $sum{$out}{$res{$out}}++; + $res{$out}="HIGH-Z" if(!defined($res{$out})); + $sum{$out}{$res{$out}}++; # We are counting the occurance of all output values of the whole truthtable to decide, which value is more often used, which helps to decide whether the function can be represented in a shorter way with a negation my @a=(); foreach(@ins) { - push @a,$res{$_}?"$_":"!$_"; + push @a,$res{$_}?"$_":"(!$_)"; # Here we are collecting all values for a AO representation, e.g. (A && !B && C) || (!A && B && C)) "Sum-of-Product" } - push @{$results{$out}{$res{$out}}},join(" && ",@a); + push @{$results{$out}{$res{$out}}},join($format eq "liberty"?"&":" && ",@a); # Here the single values are put together: (A && !B && C) "Sum-of-Product" } if($format eq "text") @@ -234,28 +345,51 @@ sub truth elsif($format eq "latex") { print "& $res{$_} " foreach(@outs); + print "\\\\ \\hline"; } elsif($format eq "html") { print "" foreach(@outs); } - print "\\\\ \\hline" if($format eq "latex"); - print "\n"; + print "" if($format eq "html"); + print "\n" if($format eq "text" || $format eq "html"); } - foreach my $out (@outs) + print "
".join("",@ins)."".join("",@outs)."
" if($format eq "html"); + $output.="".($gray&(1<<$_))?"1 ":"0 " if($format eq "text" || $format eq "latex" || $format eq "html"); # not for liberty! + $output.="$res{$_}
\n" if($format eq "html"); + + foreach my $out (@outs) # We might have more than one output of a cell { - my $not=$sum{$out}{0}>$sum{$out}{1}?1:0; - if($not) + my $not=($sum{$out}{0}||0)>($sum{$out}{1}||0)?1:0; + # If we have more 0 than 1 results, then the negated inverse is shorted: + # TODO: When there are HIGH-Z outputs we should split the HIGH-Z outputs from the others and give a function for output-enable and HIGH-Z + if($format eq "liberty") + { + print " pin($out) {\n direction: output;\n function:\""; + } + elsif($format eq "testcad") + { + } + else + { + print "function: $out = "; + } + my @list=defined($results{$out}{$not})?@{$results{$out}{$not}}:(); + if(!scalar(@list)) + { + } + elsif($not) { - print "FUNCTION: $out = (".join(" || ",@{$results{$out}{$not}}).")"; + print "(".join($format eq "liberty"?"|":" || ",@list).")"; } else { - print "FUNCTION: $out = ! (".join(" || ",@{$results{$out}{$not}}).")"; + print "!(".join($format eq "liberty"?"|":" || ",@list).")"; } + print $format eq "liberty" ? "\";\n }":" "; + print $format eq "verilog" ? "\n":""; + # TODO: We should try more functional representations like AOI, OAI, OR, NOR and see which one is the shortest representation } - print "\n" if($format eq "text"); + print "\n" if($format eq "text" || $format eq "liberty"); if($format eq "latex") { print < cell +; cell:read-file : filehandler -> cell ; Purpose: ; read in cell file as vector for further usage ; Example: -; (read-cell-file file) => INV-cell +; (cell:read-file file) => INV-cell ; Definition: - (define (read-cell-file file-name) + (define (cell:read-file file-name) (let ((file (open-input-file file-name)) - (return (make-vector 7 '())) + (return (generate-cell)) (netlist '())) (let x ((line (read-line file))) (if (eof-object? line) @@ -107,7 +118,7 @@ ; .cell annotated line, get name [(equal? (substring line 0 4) ".cel") (begin - (cell-id! return (string->symbol (string-copy line 6))) + (cell-id! return (string-upcase (string-copy line 6))) (function (read-line file)) ) ] @@ -115,7 +126,7 @@ ; .clocks annotated line, get list [(equal? (substring line 0 4) ".clo") (begin - (cell-clocks! return (stringlist->symbollist (string-split (string-copy line 7) #[ ]))) + (cell-clocks! return (string-split (string-upcase (string-copy line 7)) #[ ])) (function (read-line file)) ) ] @@ -123,7 +134,7 @@ ; .inputs annotated line, get list [(equal? (substring line 0 4) ".inp") (begin - (cell-inputs! return (stringlist->symbollist (string-split (string-copy line 8) #[ ]))) + (cell-inputs! return (string-split (string-upcase (string-copy line 8)) #[ ])) (function (read-line file)) ) ] @@ -131,7 +142,7 @@ ; .outputs annotated line, get list [(equal? (substring line 0 4) ".out") (begin - (cell-outputs! return (stringlist->symbollist (string-split (string-copy line 9) #[ ]))) + (cell-outputs! return (string-split (string-upcase (string-copy line 9)) #[ ])) (function (read-line file)) ) ] @@ -139,7 +150,7 @@ ; .end annotated line, clean up [(equal? (substring line 0 4) ".end") (begin - (cell-netlist! return (append netlist '())) + (cell-netlist! return netlist) (eof-object) ) ] @@ -147,7 +158,8 @@ ; collect netlist lines [else (begin - (set! netlist (append netlist (list (list->vector (stringlist->symbollist (string-split line #[ ])))))) + (set! netlist (append netlist (list (stringlist->mosfet (string-split line #[ ]))))) +; (set! netlist (cons (stringlist->mosfet (string-split line #[ ])) netlist)) (function (read-line file)) ) ] @@ -158,31 +170,147 @@ ) ; done, close file (close-input-port file) + (sanity-cell? return) return ) ) ) -;; ------------ write description line --------------------------- +;; ------------------------------------------------------------------- +;; WRITE CELL DESCRIPTIONS +;; ------------------------------------------------------------------- + +;; ------------ convert mosfet into string ----------------------- + +; Contract: +; mosfet->string : mosfet -> string + +; Purpose: +; convert mosfet vector into one long string + +; Example: +; (mosfet->string '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => "nmos A Y GND GND 1 1 -1 1" + +; Definition: + (define mosfet->string + (lambda (mosfet) + (string-join + (list + (mosfet-type mosfet) + (mosfet-gate mosfet) + (mosfet-drain mosfet) + (mosfet-source mosfet) + (mosfet-bulk mosfet) + (number->string (mosfet-stacked mosfet)) + (number->string (mosfet-xaxis mosfet)) + (number->string (mosfet-yaxis mosfet)) + (mosfet-size mosfet) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet->string '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "nmos A Y GND GND 1 1 -1 1") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet->string test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ format netlist ----------------------------------- ; Contract: -; write-cell-file : cell -> -- +; netlist->string : netlist -> string + +; Purpose: +; take netlist and format them into string + +; Example +; (netlist->string (cell-netlist INV-cell)) => "pmos A Y VDD VDD 1 1 1 g\nnmos A Y GND GND 1 1 -1 1" + +; Definition: + (define netlist->string + (lambda (netlist) + (cond + [(null? netlist) '()] + [else + (cons (mosfet->string (car netlist)) (netlist->string (cdr netlist)))] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (netlist->string (cell-netlist INV-cell)) '("pmos A Y VDD VDD 1 1 1 g" "nmos A Y GND GND 1 1 -1 1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " netlist->string test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ multiline format ------------------------------- + +; Contract: +; multiline-format : list-of-string -> - + +; Purpose: +; take list-of-string and feed format instruction + +; Example: +; (multiline-format (current-output-port) (netlist->string (cell-netlist INV-cell))) => ("pmos A Y VDD VDD 1 1 1 g" "nmos A Y GND GND 1 1 -1 1") + +; Definitimn: + (define multiline-format + (lambda (at-port stringlist) + (if (null? stringlist) + "" + (begin + (format (at-port) +"~a +" (car stringlist)) + (multiline-format at-port (cdr stringlist)) + ) + ) + ) + ) +#| +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (multiline-formast (current-output-port) (cell-netlist INV-cell)) '("pmos A Y VDD VDD 1 1 1 g" "nmos A Y GND GND 1 1 -1 1") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " netlist->string test" (current-error-port)) + (newline (current-error-port)) + ) + ) +|# +;; ------------ write cell description --------------------------- + +; Contract: +; cell:write-file : cell -> -- ; Purpose: ; write cell description to STDOUT ; Example: -; (write-cell-file INV-cell) => -- +; (cell:write-file INV-cell) => -- ; Definition: - (define write-cell-file + (define cell:write-file (lambda (cell) (let ((at-port current-output-port)) (begin ; first line header (if (null? (cell-text cell)) (format (at-port) -"proudly AUTOGENERATED by \"Popcorn\" R7RS Scheme tool +".AUTOGENERATED by \'Popcorn\' R7RS Scheme tool " ) (format (at-port) "~a @@ -193,26 +321,22 @@ .inputs ~a .outputs ~a " (cell-id cell) - (list->string (cell-inputs cell)) - (list->string (cell-outputs cell))) + (string-join (cell-inputs cell)) + (string-join (cell-outputs cell))) ; optional clock line (if (null? (cell-clocks cell)) - '() + "" (format (at-port) ".clocks ~a -" (list->string (cell-clocks cell))) +" (string-join (cell-clocks cell))) ) ; additional, e.g. schematic (if (null? (cell-additional cell)) - '() - (format (at-port) -"~a -" (cell-additional cell)) + "" + (multiline-format at-port (cell-additional cell)) ) ; netlist - (format (at-port) -"~a -" (cell-netlist cell)) + (multiline-format at-port (netlist->string (cell-netlist cell))) ; done (format (at-port) ".end @@ -222,6 +346,919 @@ ) ) +;; ------------------------------------------------------------------- +;; DRAW NETLIST SCHEMATIC +;; ------------------------------------------------------------------- + +;; ------------ format node name ------------------------------- + +; Contract: +; format-node: node -> string + +; Purpose: +; format fix-length string out ouf node name + +; Example: +; (format-node "A") => "A " + +; Definition: + (define format-node + (lambda (node) + (let ((len (string-length node))) + (cond + [(eq? len 0) (string-append node " ")] + [(eq? len 1) (string-append node " ")] + [(eq? len 2) (string-append node " ")] + [else (string-copy node 0 3)] + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (format-node "A") "A ") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " format-node test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ netlist->sprites ------------------------------- + +; Contract: +; netlist->sprites: list-of-sprite -> hierarchichal list-of-strings + +; Purpose: +; return all strings, representing the netlist as schematic of mosfet circuit + +; Example: +; (netlist->sprites ('#("nmos" "A" "Y" "GND" "GND" 1 1 -1 1))) => '(" | GND " +; " | +-- " +; " A ---| | 1 " +; " | +-- " +; " | Y ")) + +; Definition: + (define mosfet->sprites + (lambda (netlist xpos) + (if (null? netlist) + '() + (let ((mosfet (car netlist)) + (empty-sprite (list " " + " " + " " + " " + " "))) + (if (equal? (mosfet-xaxis mosfet) xpos) + ; mosfet found for this coordinates + (cond + [(mosfet-nmos? mosfet) + (cons + (list (string-append " | " (format-node (mosfet-source mosfet)) " ") + " | +-- " + (string-append (format-node (mosfet-gate mosfet)) "---| | " (format-node (mosfet-size mosfet)) " ") + " | +-- " + (string-append " | " (format-node (mosfet-drain mosfet)) " ")) + (mosfet->sprites (cdr netlist) (+ xpos 1)))] + [(mosfet-pmos? mosfet) + (cons + (list (string-append " | " (format-node (mosfet-drain mosfet)) " ") + " | +-- " + (string-append (format-node (mosfet-gate mosfet)) "--o| | " (format-node (mosfet-size mosfet)) " ") + " | +-- " + (string-append " | " (format-node (mosfet-source mosfet)) " ")) + (mosfet->sprites (cdr netlist) (+ xpos 1)))] + [else + (cons empty-sprite (mosfet->sprites (cdr netlist) (+ xpos 1)))] + ) + ; position (coordinates) is empty + (cons empty-sprite (mosfet->sprites netlist (+ xpos 1))) + ) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet->sprites '(#("nmos" "A" "Y" "GND" "GND" 1 2 -1 "1")) 1) + '((" " + " " + " " + " " + " ") + (" | GND " + " | +-- " + "A ---| | 1 " + " | +-- " + " | Y "))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet->sprites test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ get one sprite line --------------------------- + +; Contract: +; get-one-sprite-line : list-of-sprites -> string + +; Purpose: +; return dedicated line of given sprites as string + +; Example: +; (get-one-sprite-line (mosfet->sprites ('#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) 1) 3) => "---| | 1" + +; Definition: + (define get-one-sprite-line + (lambda (sprites line) + (if (or (null? sprites) (= line 0)) + "" + (string-append (list-ref (car sprites) (- line 1)) (get-one-sprite-line (cdr sprites) line)) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (get-one-sprite-line (mosfet->sprites '(#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") #("nmos" "B" "Y" "GND" "GND" 1 2 -1 "1")) 1) 3) "A ---| | 1 B ---| | 1 ") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " get-one-sprite-line test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ get one row of sprites --------------------------- + +; Contract: +; get-one-sprite-row: list-of-sprites -> list-of-string + +; Purpose: +; return all lines of given sprites as strings + +; Example: +; (get-one-sprite-row (mosfet->sprites ('#("nmos" "A" "Y" "GND" "GND" 1 1 -1)) 1) 5) => ? + +; Definition: + (define get-one-sprite-row + (lambda (sprites lines) + (if (or (null? sprites) (= lines 0)) + '() + (cons (string-append "# " (get-one-sprite-line sprites lines)) (get-one-sprite-row sprites (- lines 1))) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (get-one-sprite-row (mosfet->sprites '(#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") #("nmos" "B" "Y" "GND" "GND" 1 2 -1 "1")) 1) 5) + '("# | Y | Y " + "# | +-- | +-- " + "# A ---| | 1 B ---| | 1 " + "# | +-- | +-- " + "# | GND | GND ")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " get-one-sprite-row test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ get-all-rows ----------------------------------- + +; Contract: +; get-all-rows : netlist highest-row -> list-of-string + +; Purpose: +; crawl netlist and generate ascci-art line by line + +; Example: +; (get-all-rows (cell-netlist INV-cell)) => ? + +; Definition: + (define get-all-rows + (lambda (netlist row) + (cond + [(= row 0) + ; !! connectivity + ; no row zero, go down + (get-all-rows netlist (- row 1))] + ; pullup network + [(> row 0) + (let ((mosfets-on-row (sort-mosfet-ascending (filter-mosfet-row netlist row)))) + (if (null? mosfets-on-row) + '() + (append + (get-one-sprite-row (mosfet->sprites mosfets-on-row 1) 5) + ; !! connectivity + (get-all-rows netlist (- row 1)) + ) + ) + )] + ; pulldown network + [(< row 0) + (let ((mosfets-on-row (sort-mosfet-ascending (filter-mosfet-row netlist row)))) + (if (null? mosfets-on-row) + '() + (append + (get-one-sprite-row (mosfet->sprites mosfets-on-row 1) 5) + ; !! connectivity + (get-all-rows netlist (- row 1)) + ) + ) + )] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (get-all-rows (cell-netlist INV-cell) 1) '("# | VDD " + "# | +-- " + "# A --o| | g " + "# | +-- " + "# | Y " + ; !! connectivity + "# | Y " + "# | +-- " + "# A ---| | 1 " + "# | +-- " + "# | GND ")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " get-all-rows test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ ascii-art schematic ------------------------------- + +; Contract: +; ascii-art-schematic : netlist -> list-of-string + +; Purpose: +; crawl netlist and generate ascii-art line by line + +; Example: +; (ascii-art-schematic (cell-netlist INV-cell)) => ? + +; Definition: + (define ascii-art-schematic + (lambda (netlist) + (let ((yaxis (metric-highest-yaxis netlist))) + (get-all-rows netlist yaxis) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (ascii-art-schematic (cell-netlist INV-cell)) (cell-additional INV-cell)) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " ascii-art-schematic test" (current-error-port)) + (newline (current-error-port)) + ) + ) + + +;; ------------------------------------------------------------------- +;; EXPAND CELL DESCRIPTIONS +;; ------------------------------------------------------------------- + +;; ------------ calculate next free node number --------------- + +; Congtract: +; next-node-number : node-list -> node + +; Purpose: +; search for highest used node in network, calculate next + +; Example: +; (next-node-number "") => N1 + +; Definition: + (define next-node-number + (lambda (node-list) + (let ((sorted-list (sort-nodes-descending node-list))) + (cond + [(null? sorted-list) + (string-append (string (car node-space)) (number->string 1))] ; "N1" + [else + (string-append (string (car node-space)) (number->string (+ (string->number (substring (car sorted-list) 1 (string-length (car sorted-list)))) 1)))] + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (next-node-number '("N1" "N2")) "N3") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " next-node-number test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ calculate next input character node --------------- + +; Congtract: +; next-input-char-node: mosfet -> node + +; Purpose: +; check mosfet input node, calculate next + +; Example: +; (next-input-char-node '#("pmos" "A1 "Y" "GND" "GND" 1 1 -1 "g")) => "B" + +; Definition: + (define next-input-char-node + (lambda (mosfet) + (let ((node (mosfet-gate mosfet))) + (cond + [(null? node) "A"] + [else + (string (car (cdr (memq (string-ref node 0) input-space))))] + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (next-input-char-node '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) "B") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " next-input-char-node test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ calculate next input number node --------------- + +; Congtract: +; next-input-num-node: mosfet -> node + +; Purpose: +; check mosfet input node, calculate next + +; Example: +; (next-input-num-node '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) => "A1" + +; Definition: + (define next-input-num-node + (lambda (mosfet) + (let ((node (mosfet-gate mosfet))) + (cond + [(null? node) "A"] + [(eqv? (string-length node) 1) + (string (string-ref node 0) #\1)] + [else + (string (string-ref node 0) (integer->char (+ 1 (char->integer (string-ref node 1)))))] + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (next-input-num-node '#("pmos" "A1" "Y" "GND" "GND" 1 1 -1 "g")) "A2") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " next-input-num-node test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ calculate next output node ----------------------- + +; Congtract: +; next-output-node: node-list -> node + +; Purpose: +; search for highest used output node, calculate next + +; Example: +; (next-output-node "Y") => "Z" + +; Definition: + (define next-output-node + (lambda (node-list) + (let ((sorted-list (sort-nodes-descending node-list))) + (cond + [(null? sorted-list) "Y"] + [else + (string (car (cdr (memq (string-ref (car sorted-list) 0) output-space))))] + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (next-output-node '("Y")) "Z") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " next-output-node test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ find mosfet to expand --------------------------- + +; Contract: +; find-mosfet-anchor : cell -> mosfet + +; Purpose: +; crawl through network and find transistor to expand + +; Example: +; (find-mosfet-anchor (pullup-network (cell-netlist INV-cell))) => #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define find-mosfet-anchor + (lambda (netlist limit) + (if (null? netlist) + '() + (let ((network (sort-mosfet-descending netlist))) + (let ((candidate (car network))) + (if (< (mosfet-stacked candidate) limit) + ; got it - candidate on path is below limit + candidate + ; waste path away, check next + (find-mosfet-anchor (filter-mosfet-remove network (mosfet-gate candidate)) limit) + ) + ) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (find-mosfet-anchor (pulldown-network (cell-netlist INV-cell)) 2) + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " find-mosfet-anchor test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand netlist serial --------------------------- + +; Contract: +; expand-netlist-serial : netlist new-node new-gate mosfet -> netlist + +; Purpose: +; expand network by mosfet in serial + +; Example: +; (expand-netlist-serial (pulldown-network (cell-netlist INV-cell)) "N2" "B" #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "0")) => +; (#("nmos" "A" "Y" "N2" "GND" 1 1 -1 "1") #("nmos" "B" "N2" "GND" "GND" 2 1 -2 "0")) + +; Definition: + (define expand-netlist-serial + (lambda (netlist new-node new-gate mosfet) + (cond + ; netlist empty? + [(null? netlist)] + ; handle anchor transistor + [(equal? (car netlist) mosfet) + (let ((new-mosfet (generate-mosfet)) + (org-mosfet mosfet)) + (begin + ; use same type as original + (mosfet-type! new-mosfet (mosfet-type org-mosfet)) + ; use new generated gate node + (mosfet-gate! new-mosfet new-gate) + ; use same source as original (hopefully a power rail) + (mosfet-source! new-mosfet (mosfet-source org-mosfet)) + ; use new generated node number between original and new mosfet + (mosfet-source! org-mosfet new-node) + (mosfet-drain! new-mosfet new-node) + ; use same bulk as original + (mosfet-bulk! new-mosfet (mosfet-bulk org-mosfet)) + ; increment stacked transistor number + (mosfet-stacked! new-mosfet (+ (mosfet-stacked org-mosfet) 1)) + ; use same xasis as original + (mosfet-xaxis! new-mosfet (mosfet-xaxis org-mosfet)) + ; increment yaxis number + (if (< (mosfet-yaxis org-mosfet) 0) + ; negative, pulldown network + (mosfet-yaxis! new-mosfet (- (mosfet-yaxis org-mosfet) 1)) + ; positive, pullup network + (mosfet-yaxis! new-mosfet (+ (mosfet-yaxis org-mosfet) 1)) + ) + ; transistor sizing + (mosfet-size! new-mosfet "0") ; !! no size yet + ; return + (append (list new-mosfet org-mosfet) (cdr netlist)) + ) + )] + [else + (cons (car netlist) (expand-netlist-serial (cdr netlist) new-node new-gate mosfet))] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (expand-netlist-serial (pulldown-network (cell-netlist INV-cell)) "N1" "B" #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + '( #("nmos" "B" "N1" "GND" "GND" 2 1 -2 "0") + #("nmos" "A" "Y" "N1" "GND" 1 1 -1 "1"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " expand-netlist-serial test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand netlist parallel --------------------------- + +; Contract: +; expand-netlist-parallel : netlist new-gate mosfet -> netlist + +; Purpose: +; expand network by mosfet in parallel + +; Example: +; (expand-netlist-parallel (pulldown-down (cell-netlist INV-cell)) "B" #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => +; (#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") #("nmos" "B" "Y" "GND" "GND" 1 2 -1 "1")) + +; Definition: + (define expand-netlist-parallel + (lambda (netlist new-gate org-mosfet) + (let ((new-mosfet (generate-mosfet)) + (xaxis (mosfet-xaxis org-mosfet))) + (begin + ; use same type as original + (mosfet-type! new-mosfet (mosfet-type org-mosfet)) + ; use new generated gate node + (mosfet-gate! new-mosfet new-gate) + ; use same source as original + (mosfet-source! new-mosfet (mosfet-source org-mosfet)) + ; use same drain as original + (mosfet-drain! new-mosfet (mosfet-drain org-mosfet)) + ; use same bulk as original + (mosfet-bulk! new-mosfet (mosfet-bulk org-mosfet)) + ; use same stacked transistor number + (mosfet-stacked! new-mosfet (mosfet-stacked org-mosfet)) + ; increment xasis number !! fixme - others transistors has to be shifted? + (if (< xaxis 0) + ; negative, pulldown network + (mosfet-xaxis! new-mosfet (- xaxis 1)) + ; positive, pullup network + (mosfet-xaxis! new-mosfet (+ xaxis 1)) + ) + ; use same yaxis number + (mosfet-yaxis! new-mosfet (mosfet-yaxis org-mosfet)) + ; transistor sizing + (mosfet-size! new-mosfet (mosfet-size org-mosfet)) ; always same size + ; return + (cons new-mosfet netlist) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (expand-netlist-parallel (pulldown-network (cell-netlist INV-cell)) "B" #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + '(#("nmos" "B" "Y" "GND" "GND" 1 2 -1 "1") + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " expand-netlist-parallel test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand netlist w/ buffer ----------------------- + +; Contract: +; expand-netlist-buffer : netlist new-node -> netlist + +; Purpose: +; expand network by adding buffer + +; Example: +; (expand-netlist-buffer (cell-netlist INV-cell) "Y" 1) => (cell-netlist BUF-cell) + +; Definition: + (define expand-netlist-buffer + (lambda (netlist new-node new-output) + (let ((nmos-mosfet (generate-mosfet)) + (pmos-mosfet (generate-mosfet)) + (xaxis (metric-highest-xaxis netlist))) + (begin + ; use pMOS and nMOS as types + (mosfet-type! pmos-mosfet "pmos") + (mosfet-type! nmos-mosfet "nmos") + ; use new generated node as gate + (mosfet-gate! pmos-mosfet new-node) + (mosfet-gate! nmos-mosfet new-node) + ; use power rails for source + (mosfet-source! pmos-mosfet (car supply-space)) + (mosfet-source! nmos-mosfet (car ground-space)) + ; use same drain as original + (mosfet-drain! pmos-mosfet new-output) + (mosfet-drain! nmos-mosfet new-output) + ; use same bulk as source + (mosfet-bulk! pmos-mosfet (car supply-space)) + (mosfet-bulk! nmos-mosfet (car ground-space)) + ; use same stacked transistor always one + (mosfet-stacked! pmos-mosfet 1) + (mosfet-stacked! nmos-mosfet 1) + ; increment xasis number + (mosfet-xaxis! pmos-mosfet (+ xaxis 1)) + (mosfet-xaxis! nmos-mosfet (+ xaxis 1)) + ; use default yaxis numbers + (mosfet-yaxis! pmos-mosfet 1) + (mosfet-yaxis! nmos-mosfet -1) + ; transistor sizing + (mosfet-size! pmos-mosfet "g") + (mosfet-size! nmos-mosfet "1") + ; return + (cons pmos-mosfet (cons nmos-mosfet netlist)) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (replace-nodes (expand-netlist-buffer (cell-netlist INV-cell) "N1" "Z") "Y" "N1") (cell-netlist BUF-cell)) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " expand-netlist-buffer test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand cell nand-wise --------------------------- + +; Contract: +; cell:expand-nand : cell -> cell + +; Purpose: +; expand cell description by adding mosfet nand-like + +; Example: +; (cell:expand-nand INV-cell 2) => NAND2-cell + +; Definition: + (define cell:expand-nand + (lambda (cell stacked-limit buffer-limit cell-name cell-descr) + (let ((netlist (cell-netlist cell))) + (let ((anchor (find-mosfet-anchor (pulldown-network netlist) stacked-limit))) + (let ((complementary (complementary-mosfets netlist anchor)) + (1st-node (next-node-number (intermediate-nodes netlist))) + (new-gate (next-input-char-node anchor))) + (let ((new-netlist (expand-netlist-parallel (expand-netlist-serial netlist 1st-node new-gate anchor) new-gate complementary))) + (let ((2nd-node (next-node-number (intermediate-nodes new-netlist)))) + (begin + ; netlist + (if (and (null? (buffer-network new-netlist)) (>= (metric-highest-stacked new-netlist) buffer-limit)) + ; netlist is yet still not buffered but already on level + (cell-netlist! cell (sort-netlist (replace-nodes (expand-netlist-buffer new-netlist (next-node-number (intermediate-nodes new-netlist)) "Z") "Y" 2nd-node))) + ; already bufferd, set netlist + (cell-netlist! cell (sort-netlist new-netlist)) + ) + ; set new cell-id + (cell-id! cell cell-name) + ; set new cell description + (cell-text! cell cell-descr) + ; set input nodes + (cell-inputs! cell (sort-nodes-descending (input-nodes (cell-netlist cell)))) + ; set output nodes + (cell-outputs! cell (sort-nodes-descending (output-nodes (cell-netlist cell)))) + ; set clock nodes + (cell-clocks! cell (sort-nodes-descending (clock-nodes (cell-netlist cell)))) + ; set additionals + (cell-additional! cell (ascii-art-schematic (cell-netlist cell))) + ) + ) + ) + ) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (cell:expand-nand INV-cell 4 4 "NAND2" "a 2-input Not-AND (or NAND) gate") NAND2-cell) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " cell:expand-nand test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand cell nor-wise --------------------------- + +; Contract: +; cell:expand-nor : cell -> cell + +; Purpose: +; expand cell description by adding mosfet nor-like + +; Example: +; (cell:expand-nor INV-cell 4 4) => NOR2-cell + +; Definition: + (define cell:expand-nor + (lambda (cell stacked-limit buffer-limit cell-name cell-descr) + (let ((netlist (cell-netlist cell))) + (let ((anchor (find-mosfet-anchor (pullup-network netlist) stacked-limit))) + (let ((complementary (complementary-mosfets netlist anchor)) + (1st-node (next-node-number (intermediate-nodes netlist))) + (new-gate (next-input-char-node anchor ))) + (let ((new-netlist (expand-netlist-parallel (expand-netlist-serial netlist 1st-node new-gate anchor) new-gate complementary))) + (let ((2nd-node (next-node-number (intermediate-nodes new-netlist)))) + (begin + ; netlist + (if (and (null? (buffer-network new-netlist)) (>= (metric-highest-stacked new-netlist) buffer-limit)) + ; netlist is yet still not buffered but already on level + (cell-netlist! cell (sort-netlist (replace-nodes (expand-netlist-buffer new-netlist (next-node-number (intermediate-nodes new-netlist)) "Z") "Y" 2nd-node))) + ; already bufferd, set netlist + (cell-netlist! cell (sort-netlist new-netlist)) + ) + ; set new cell-id + (cell-id! cell cell-name) + ; set new cell description + (cell-text! cell cell-descr) + ; set input nodes + (cell-inputs! cell (sort-nodes-descending (input-nodes (cell-netlist cell)))) + ; set output nodes + (cell-outputs! cell (sort-nodes-descending (output-nodes (cell-netlist cell)))) + ; set clock nodes + (cell-clocks! cell (sort-nodes-descending (clock-nodes (cell-netlist cell)))) + ; set additionals + (cell-additional! cell (ascii-art-schematic (cell-netlist cell))) + ) + ) + ) + ) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (cell:expand-nor INV-cell 4 4 "NOR2" "a 2-input Not-OR (or NOR) gate") NOR2-cell) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " cell:expand-nor test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand cell oai-wise --------------------------- + +; Contract: +; cell:expand-oai : cell -> cell + +; Purpose: +; expand cell description by adding mosfet oai-like + +; Example: +; (cell:expand-oai NAND2-cell) => OAI21-cell + +; Definition: + (define cell:expand-oai + (lambda (cell stacked-limit buffer-limit cell-name cell-descr) + (let ((netlist (cell-netlist cell))) + (let ((anchor (find-mosfet-anchor (pullup-network netlist) stacked-limit))) + (let ((complementary (complementary-mosfets netlist anchor)) + (1st-node (next-node-number (intermediate-nodes netlist))) + (new-gate (next-input-num-node anchor ))) + (let ((new-netlist (expand-netlist-parallel (expand-netlist-serial netlist 1st-node new-gate anchor) new-gate complementary))) + (let ((2nd-node (next-node-number (intermediate-nodes new-netlist)))) + (begin + ; netlist + (if (and (null? (buffer-network new-netlist)) (>= (metric-highest-stacked new-netlist) buffer-limit)) + ; netlist is yet still not buffered but already on level + (cell-netlist! cell (sort-netlist (replace-nodes (expand-netlist-buffer new-netlist (next-node-number (intermediate-nodes new-netlist)) "Z") "Y" 2nd-node))) + ; already bufferd, set netlist + (cell-netlist! cell (sort-netlist new-netlist)) + ) + ; set new cell-id + (cell-id! cell cell-name) + ; set new cell description + (cell-text! cell cell-descr) + ; set input nodes + (cell-inputs! cell (sort-nodes-descending (input-nodes (cell-netlist cell)))) + ; set output nodes + (cell-outputs! cell (sort-nodes-descending (output-nodes (cell-netlist cell)))) + ; set clock nodes + (cell-clocks! cell (sort-nodes-descending (clock-nodes (cell-netlist cell)))) + ; set additionals + (cell-additional! cell (ascii-art-schematic (cell-netlist cell))) + ) + ) + ) + ) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (cell:expand-oai NAND2-cell 4 4 "OAI21" "a 2-1-input OR-AND-Invert (or OAI) gate") OAI21-cell) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " cell:expand-oai test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ expand cell aoi-wise --------------------------- + +; Contract: +; cell:expand-aoi : cell -> cell + +; Purpose: +; expand cell description by adding mosfet aoi-like + +; Example: +; (cell:expand-aoi NOR2-cell) => AOI21-cell + +; Definition: + (define cell:expand-aoi + (lambda (cell stacked-limit buffer-limit cell-name cell-descr) + (let ((netlist (cell-netlist cell))) + (let ((anchor (find-mosfet-anchor (pulldown-network netlist) stacked-limit))) + (let ((complementary (complementary-mosfets netlist anchor)) + (1st-node (next-node-number (intermediate-nodes netlist))) + (new-gate (next-input-num-node anchor))) + (let ((new-netlist (expand-netlist-parallel (expand-netlist-serial netlist 1st-node new-gate anchor) new-gate complementary))) + (let ((2nd-node (next-node-number (intermediate-nodes new-netlist)))) + (begin + ; netlist + (if (and (null? (buffer-network new-netlist)) (>= (metric-highest-stacked new-netlist) buffer-limit)) + ; netlist is yet still not buffered but already on level + (cell-netlist! cell (sort-netlist (replace-nodes (expand-netlist-buffer new-netlist (next-node-number (intermediate-nodes new-netlist)) "Z") "Y" 2nd-node))) + ; already bufferd, set netlist + (cell-netlist! cell (sort-netlist new-netlist)) + ) + ; set new cell-id + (cell-id! cell cell-name) + ; set new cell description + (cell-text! cell cell-descr) + ; set input nodes + (cell-inputs! cell (sort-nodes-descending (input-nodes (cell-netlist cell)))) + ; set output nodes + (cell-outputs! cell (sort-nodes-descending (output-nodes (cell-netlist cell)))) + ; set clock nodes + (cell-clocks! cell (sort-nodes-descending (clock-nodes (cell-netlist cell)))) + ; set additionals + (cell-additional! cell (ascii-art-schematic (cell-netlist cell))) + ) + ) + ) + ) + ) + ) + ) + ) +#| +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (cell:expand-aoi NOR2-cell 4 4 "AOI21" "a 2-1-input AND-OR-Invert (or AOI) gate") AOI21-cell) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " cell:expand-aoi test" (current-error-port)) + (newline (current-error-port)) + ) + ) +|# ;; =================================================================== ;; END OF R7RS LIBRARY ;; =================================================================== diff --git a/Tools/popcorn/popcorn-lib.scm b/Tools/popcorn/popcorn-lib.scm index 5fb20863..fcb37735 100644 --- a/Tools/popcorn/popcorn-lib.scm +++ b/Tools/popcorn/popcorn-lib.scm @@ -45,82 +45,1222 @@ (define-library (popcorn-lib) (import (scheme base) + (scheme char) ; digit-value (scheme sort) ; list-sort + (scheme char) ; string-upcase, string-downcase (scheme write) ; display - (scheme time)) ; current-second - (export ; example cells + (scheme time) ; current-second + (srfi 152)) ; string-split + (export ; node spaces + input-space input-space? + output-space output-space? + clock-space clock-space? + node-space node-space? + supply-space supply-space? + ground-space ground-space? + ; mosfet descriptions + generate-mosfet + mosfet-type mosfet-type! + mosfet-nmos? mosfet-nmos! + mosfet-pmos? mosfet-pmos! + mosfet-gate mosfet-gate! + mosfet-drain mosfet-drain! + mosfet-source mosfet-source! + mosfet-bulk mosfet-bulk! + mosfet-stacked mosfet-stacked! + mosfet-xaxis mosfet-xaxis! + mosfet-yaxis mosfet-yaxis! + mosfet-size mosfet-size! + sanity-mosfet? + ; example cells INV-cell + BUF-cell NAND2-cell NOR2-cell + OAI21-cell + AOI21-cell ; cell descriptions - cell-id cell-id! - cell-text cell-text! - cell-inputs cell-inputs! - cell-outputs cell-outputs! - cell-clocks cell-clocks! - cell-netlist cell-netlist! - cell-additional cell-additional! - ; mosfet descriptions - mosfet-type - mosfet-nmos? - mosfet-pmos? - mosfet-gate - mosfet-drain - mosfet-source - mosfet-bulk - mosfet-stacked - mosfet-xaxis - mosfet-yaxis - ; node descriptions - input-space? - output-space? - clock-space? - node-space? - supply-symbol-space? - ground-symbol-space? + generate-cell + cell-id cell-id! + cell-text cell-text! + cell-inputs cell-inputs! + cell-outputs cell-outputs! + cell-clocks cell-clocks! + cell-netlist cell-netlist! + cell-additional cell-additional! + sanity-cell? + ; functions on netlists + buffer-network + pullup-network + pulldown-network + vdd-mosfets + gnd-mosfets + input-mosfets + complementary-mosfets + sort-mosfet-ascending + sort-mosfet-descending + sort-netlist + filter-mosfet-char + filter-mosfet-remove + filter-mosfet-column + filter-mosfet-row + input-nodes + clock-nodes + output-nodes + replace-nodes + intermediate-nodes + sort-nodes-ascending + sort-nodes-descending + ; metrics on netlists + metric-tp-stacked + metric-tn-stacked + metric-highest-stacked + metric-highest-xaxis + metric-highest-yaxis + metric-lowest-yaxis ; auxilary stuff copyleft-year stringlist->csv - stringlist->symbollist - symbollist->stringlist) + stringlist->mosfet) (begin -;; ------------ build-in self test ------------------------------- +;; ------------ build-in self test ------------------------------- + + ; use this switch during development only + (define build-in-self-test? #t) + +;; ------------ build-in sanity checks --------------------------- + + ; use this switch during development only + (define build-in-sanity-checks? #t) + +;; ------------------------------------------------------------------- +;; DESCRIPTION +;; ------------------------------------------------------------------- + +;; In principle every combinatorial cell (in CMOS technology) contains +;; two functional complementary networks. The pull-up network - build +;; with pmos transistors - as well as the pull-down network - build +;; with nmos transistors. + +;; so every netlist becomes, well, a list of transistors + +;; ------------------------------------------------------------------- +;; NODE SPACES +;; ------------------------------------------------------------------- + +;; ------------ input node names ------------------------------- + + (define input-space '(#\A #\B #\C #\D #\E #\F #\H #\I #\K #\L #\M #\P #\R #\S #\T #\U #\W)) + +; Contract: +; input-space? : list-of-ports -> boolean + +; Purpose: +; check whether node is in defined input space for cells + +; Example: +; (input-space? "A0") => #t +; (input-space? "Z") => #f + +; Definition: + (define input-space? + (lambda (node) + (if (memq (string-ref node 0) input-space) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (and (input-space? "A0") (not (input-space? "Z"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " input-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ output node names ------------------------------- + + (define output-space '(#\Q #\Y #\Z)) + +; Contract: +; output-space? list-of-ports -> boolean + +; Purpose: +; check wether node is in defined output space for cells + +; Example: +; (output-space? "A0") => #f +; (output-space? "Z") => #t + +; Definition: + (define output-space? + (lambda (node) + (if (memq (string-ref node 0) output-space) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (and (output-space? "Z") (not (output-space? "A0"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " output-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ clock node names ------------------------------- + + (define clock-space '(#\X)) + +; Contract: +; clock-space? list-of-ports -> boolean + +; Purpose: +; check wether node is in defined clock space for cells + +; Example: +; (clock-space? "X0") => #t + +; Definition: + (define clock-space? + (lambda (node) + (if (memq (string-ref node 0) clock-space) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (clock-space? "X0") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " clock-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ internal node names ------------------------------- + + (define node-space '(#\N)) + +; Contract: +; node-space? list-of-nodes -> boolean + +; Purpose: +; check wether node is in defined node space for cells + +; Example: +; (node-space? "N2") => #t + +; Definition: + (define node-space? + (lambda (node) + (if (member (string-ref node 0) node-space) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (node-space? "N2") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " node-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ supply symbol node name space ------------------- + +; Usually, SCHEME is case-insensitive but some implementations (and R7RS) are not. +; Hence, the member compare has a string-ci=? option. + +; Definition: + (define supply-space (list "VDD" "VCC")) + +; Contract: +; sypply-symbol-space? list-of-ports -> boolean + +; Purpose: +; check wether node is in defined list for sypply symbols + +; Example: +; (supply-space? "Vdd") => #t +; (supply-space? "GND") => #f + +; Definition: + (define supply-space? + (lambda (node) + (if (member node supply-space string-ci=?) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (and (supply-space? "Vdd") (not (supply-space? "gnd"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " supply-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ ground plane node name space ------------------- + +; Usually, SCHEME is case-insensitive but some implementations are not. +; Hence, the member compare has a string-ci=? option. + +; Definition: + (define ground-space (list "GND" "VSS")) + +; Contract: +; ground-space? list-of-ports -> boolean + +; Purpose: +; check wether node is in defined list for ground symbols + +; Example: +; (ground-space? "gnd") => #t +; (ground-space? "vdd") => #f + +; Definition: + (define ground-space? + (lambda (node) + (if (member node ground-space string-ci=?) #t #f) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (and (ground-space? "gnd") (not (ground-space? "vdd"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " ground-space? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------------------------------------------------------------- +;; TRANSISTOR DATA STRUCTURE +;; ------------------------------------------------------------------- + +; define transistor as vector: Example: +; +---------------+ +; #0 | circuit type | "nmos" +; +---------------+ +; #1 | gate node | "A" +; +---------------+ +; #2 | drain node | "X" +; +---------------+ +; #3 | source node | "VDD" +; +---------------+ +; #4 | bulk node | "VDD" +; +---------------+ +; #5 | stacked | 1 +; +---------------+ +; #6 | x-axis point | 1 +; +---------------+ +; #7 | y-axis point | 1 +; +---------------+ +; #7 | size | "g" +; +---------------+ + +; define constants for vector indices + (define |circuit-type#| 0) + (define |gate-node#| 1) + (define |drain-node#| 2) + (define |source-node#| 3) + (define |bulk-node#| 4) + (define |stacked#| 5) + (define |xaxis-point#| 6) + (define |yaxis-point#| 7) + (define |size#| 8) + +;; ------------ generate empty mosfet --------------------------- + +; Contract: +; generate-mosfet : -> mosfet + +; Purpose: +; generate new and empty mosfet vector structure + +; Example: +; (generate-mosfet) => '#() + +; Definition + (define generate-mosfet + (lambda () + (make-vector 9 "") + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (generate-mosfet) #("" "" "" "" "" "" "" "" "")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " generate-mosfet test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-type ------------------- + +; Contract: +; mosfet-type : mosfet -> node + +; Purpose: +; get the mosfet type out of mosfet transistor vector + +; Example: +; (mosfet-type '#("nmos" "A" "Y" "GND" "GND" 1 1 -1)) => "nmos" + +; Definition: + (define mosfet-type + (lambda (mosfet) + (vector-ref mosfet |circuit-type#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-type '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "nmos") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-type test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-type! ------------------- + +; Contract: +; mosfet-type! : mosfet string -> mosfet + +; Purpose: +; set the mosfet type in a mosfet description vector + +; Example: +; (mosfet-type! '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "1") "nmos") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-type! + (lambda (mosfet type) + (vector-set! mosfet |circuit-type#| type) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-type! '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "1") "nmos") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-type! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-nmos? ------------------- + +; Contract: +; mosfet-nmos? : mosfet -> boolean + +; Purpose: +; check the mosfet type out of mosfet transistor vector + +; Example: +; (mosfet-nmos? '#("nmos" "A" "Y" "GND" "GND" 1 1 -1)) => #t + +; Definition: + (define mosfet-nmos? + (lambda (mosfet) + (equal? (vector-ref mosfet |circuit-type#|) "nmos") + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (mosfet-nmos? '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-nmos? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-nmos! ------------------- + +; Contract: +; mosfet-nmos! : mosfet -> mosfet + +; Purpose: +; set the mosfet type in a mosfet description vector to nmos + +; Example: +; (mosfet-nmos! '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-nmos! + (lambda (mosfet) + (vector-set! mosfet |circuit-type#| "nmos") + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-nmos! '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-nmos! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-pmos? ------------------- + +; Contract: +; mosfet-pmos? : mosfet -> boolean + +; Purpose: +; check the mosfet type out of mosfet transistor vector + +; Example: +; (mosfet-pmos? '#("pmos" "A" "Y" "VDD" "VDD" 1 1 -1)) => #t + +; Definition: + (define mosfet-pmos? + (lambda (mosfet) + (equal? (vector-ref mosfet |circuit-type#|) "pmos") + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (mosfet-pmos? '#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-pmos? test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-pmos! ------------------- + +; Contract: +; mosfet-pmos! : mosfet -> mosfet + +; Purpose: +; set the mosfet type in a mosfet description vector to pmos + +; Example: +; (mosfet-pmos! '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) => '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "g") + +; Definition: + (define mosfet-pmos! + (lambda (mosfet) + (vector-set! mosfet |circuit-type#| "pmos") + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-pmos! '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) + '#("pmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-pmos! test" (current-error-port)) + (newline (current-error-port)) + ) + ) +;; ------------ getter function : mosfet-gate ------------------- + +; Contract: +; mosfet-gate : mosfet -> node + +; Purpose: +; get the mosfet gate node out of mosfet transistor vector + +; Example: +; (mosfet-gate '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => "A" + +; Definition: + (define mosfet-gate + (lambda (mosfet) + (vector-ref mosfet |gate-node#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-gate '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "A") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-gate test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-gate! ------------------- + +; Contract: +; mosfet-gate! : mosfet string -> mosfet + +; Purpose: +; set the mosfet gate in a mosfet description vector + +; Example: +; (mosfet-gate! '#("nmos" "B" "Y" "GND" "GND" 1 1 -1 "1") "A") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-gate! + (lambda (mosfet gate) + (vector-set! mosfet |gate-node#| gate) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-gate! '#("nmos" "B" "Y" "GND" "GND" 1 1 -1 "1") "A") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-gate! test" (current-error-port)) + (newline (current-error-port)) + ) + ) +;; ------------ getter function : mosfet-drain ------------------- + +; Contract: +; mosfet-drain : mosfet -> node + +; Purpose: +; get the mosfet drain node out of mosfet transistor vector + +; Example: +; (mosfet-drain '#("nmos" "A" "Y" "VDD" "VDD" 1 1 -1 "1")) => "Y" + +; Definition: + (define mosfet-drain + (lambda (mosfet) + (vector-ref mosfet |drain-node#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-drain '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "Y") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-drain test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-drain! ------------------- + +; Contract: +; mosfet-drain! : mosfet string -> mosfet + +; Purpose: +; set the mosfet drain in a mosfet description vector + +; Example: +; (mosfet-drain! '#("nmos" "A" "Z" "GND" "GND" 1 1 -1 "1") "Y") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-drain! + (lambda (mosfet drain) + (vector-set! mosfet |drain-node#| drain) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-drain! '#("nmos" "A" "Z" "GND" "GND" 1 1 -1 "1") "Y") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-drain! test" (current-error-port)) + (newline (current-error-port)) + ) + ) +;; ------------ getter function : mosfet-source ------------------- + +; Contract: +; mosfet-source : mosfet -> node + +; Purpose: +; get the mosfet source node out of mosfet transistor vector + +; Example: +; (mosfet-source '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => "GND" + +; Definition: + (define mosfet-source + (lambda (mosfet) + (vector-ref mosfet |source-node#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-source '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "GND") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-source test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-source! --------------- + +; Contract: +; mosfet-source! : mosfet string -> mosfet + +; Purpose: +; set the mosfet source in a mosfet description vector + +; Example: +; (mosfet-source! '#("nmos" "A" "Y" "VDD" "GND" 1 1 -1 "1") "GND") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-source! + (lambda (mosfet source) + (vector-set! mosfet |source-node#| source) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-source! '#("nmos" "A" "Y" "VDD" "GND" 1 1 -1 "1") "GND") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-source! test" (current-error-port)) + (newline (current-error-port)) + ) + ) +;; ------------ getter function : mosfet-bulk ------------------- + +; Contract: +; mosfet-bulk : mosfet -> node + +; Purpose: +; get the mosfet bulk node out of mosfet transistor vector + +; Example: +; (mosfet-bulk '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => "GND" + +; Definition: + (define mosfet-bulk + (lambda (mosfet) + (vector-ref mosfet |bulk-node#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-bulk '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "GND") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-bulk test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-bulk! ------------------- + +; Contract: +; mosfet-bulk! : mosfet string -> mosfet + +; Purpose: +; set the mosfet bulk in a mosfet description vector + +; Example: +; (mosfet-bulk! '#("nmos" "A" "Y" "GND" "VDD" 1 1 -1 "1") "GND") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-bulk! + (lambda (mosfet bulk) + (vector-set! mosfet |bulk-node#| bulk) + mosfet + ) + ) - ; use this switch during development only - (define build-in-self-test #t) +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-bulk! '#("nmos" "A" "Y" "GND" "VDD" 1 1 -1 "1") "GND") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-bulk! test" (current-error-port)) + (newline (current-error-port)) + ) + ) -;; ------------------------------------------------------------------- -;; DESCRIPTION -;; ------------------------------------------------------------------- +;; ------------ getter function : mosfet-stacked --------------- -;; In principle every combinatorial cell (in CMOS technology) contains -;; two functional complementary networks. The pull-up network - build -;; with pmos transistors - as well as the pull-down network - build -;; with nmos transistors. +; Contract: +; mosfet-stacked : mosfet -> number -;; so every netlist becomes, well, a list of transistors +; Purpose: +; get the mosfet number of stacked transistors out of mosfet transistor vector + +; Example: +; (mosfet-stacked '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => 1 + +; Definition: + (define mosfet-stacked + (lambda (mosfet) + (vector-ref mosfet |stacked#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-stacked '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) 1) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-stacked test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-stacked! --------------- + +; Contract: +; mosfet-stacked! : mosfet number -> mosfet + +; Purpose: +; set the number of stacked transistors in a mosfet description vector + +; Example: +; (mosfet-stacked! '#("nmos" "A" "Y" "GND" "GND" 0 1 -1 "1") 1) => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-stacked! + (lambda (mosfet stacked) + (vector-set! mosfet |stacked#| stacked) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-stacked! '#("nmos" "A" "Y" "GND" "GND" 0 1 -1 "1") 1) + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-stacked! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-xaxis ------------------- + +; Contract: +; mosfet-xaxis : mosfet -> number + +; Purpose: +; get the mosfet x-axis coordinate out of mosfet transistor vector + +; Example: +; (mosfet-xaxis '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => 1 + +; Definition: + (define mosfet-xaxis + (lambda (mosfet) + (vector-ref mosfet |xaxis-point#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-xaxis '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) 1) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-xaxis test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-xaxis! --------------- + +; Contract: +; mosfet-xaxis! : mosfet number -> mosfet + +; Purpose: +; set the mosfet xaxis in a mosfet description vector + +; Example: +; (mosfet-xaxis! '#("nmos" "A" "Y" "GND" "GND" 1 0 -1 "1") 1) => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-xaxis! + (lambda (mosfet xaxis) + (vector-set! mosfet |xaxis-point#| xaxis) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-xaxis! '#("nmos" "A" "Y" "GND" "GND" 1 0 -1 "1") 1) + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-xaxis! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-yaxis ------------------- + +; Contract: +; mosfet-yaxis : mosfet -> number + +; Purpose: +; get the mosfet y-axis coordinate out of mosfet transistor vector + +; Example: +; (mosfet-yaxis '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => -1 + +; Definition: + (define mosfet-yaxis + (lambda (mosfet) + (vector-ref mosfet |yaxis-point#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-yaxis '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) -1) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-yaxis test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-yaxis! --------------- + +; Contract: +; mosfet-yaxis! : mosfet number -> mosfet + +; Purpose: +; set the mosfet yaxis in a mosfet description vector + +; Example: +; (mosfet-yaxis! '#("nmos" "A" "Y" "GND" "GND" 1 0 -1 "1") 1) => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Definition: + (define mosfet-yaxis! + (lambda (mosfet yaxis) + (vector-set! mosfet |yaxis-point#| yaxis) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-yaxis! '#("nmos" "A" "Y" "GND" "GND" 1 1 0 "1") -1) + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-yaxis! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ getter function : mosfet-size ------------------- + +; Contract: +; mosfet-size: mosfet -> number + +; Purpose: +; get the mosfet size (as multiple of standard size) out of mosfet transistor vector + +; Example: +; (mosfet-size '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) => 1 + +; Definition: + (define mosfet-size + (lambda (mosfet) + (vector-ref mosfet |size#|) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-size '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) "1") + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-size test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ setter function : mosfet-size! --------------- + +; Contract: +; mosfet-size! : mosfet number -> mosfet + +; Purpose: +; set the mosfet size in a mosfet description vector + +; Example: +; (mosfet-size! '#("nmos" "A" "Y" "GND" "GND" 1 0 -1 0) "g") => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "g") + +; Definition: + (define mosfet-size! + (lambda (mosfet size) + (vector-set! mosfet |size#| size) + mosfet + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (mosfet-size! '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "0") "g") + '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "g")) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " mosfet-size! test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ sanity check for mosfet --------------------------- + +; Contract: +; sanity-mosfet? : mosfet -> boolean + +; Purpose: +; check type / sanity for well-formed transistor descriptions + +; Example: +; (sanity-mosfet? mosfet) => #t + +; Definition + (define sanity-mosfet? + (lambda (mosfet) + (if build-in-sanity-checks? + (begin + ; circuit type + (let ((type (mosfet-type mosfet))) + (if (and (string? type) + (or (equal? type "pmos") + (equal? type "nmos"))) + #t + (begin + (display "!! insane mosfet-type check " (current-error-port)) + (display type (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; gate nodes + (let ((gate (mosfet-gate mosfet))) + (if (and (string? gate) + (or + (input-space? gate) + (node-space? gate))) + #t + (begin + (display "!! insane mosfet-gate check " (current-error-port)) + (display gate (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; drain nodes + (let ((drain (mosfet-drain mosfet))) + (if (and (string? drain) + (or (node-space? drain) + (output-space? drain))) + #t + (begin + (display "!! insane mosfet-drain check " (current-error-port)) + (display drain (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; source nodes + (let ((source (mosfet-source mosfet))) + (if (and (string? source) + (or (node-space? source) + (ground-space? source) + (supply-space? source))) + #t + (begin + (display "!! insane mosfet-source check " (current-error-port)) + (display source (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; bulk nodes + (let ((bulk (mosfet-bulk mosfet))) + (if (and (string? bulk) + (or ;(node-space? bulk) !! we do not expect shifted bulks + (ground-space? bulk) + (supply-space? bulk))) + #t + (begin + (display "!! insane mosfet-bulk check " (current-error-port)) + (display bulk (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; stacked transistors + (let ((stacked (mosfet-stacked mosfet))) + (if (and (integer? stacked) + (> stacked 0)) ; positive + #t + (begin + (display "!! insane mosfet-stacked check " (current-error-port)) + (display stacked (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; xaxis coordinates + (let ((xaxis (mosfet-xaxis mosfet))) + (if (and (integer? xaxis) + (> xaxis 0)) ; positive + #t + (begin + (display "!! insane mosfet-xaxis check " (current-error-port)) + (display xaxis (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; yaxis coordinates + (let ((yaxis (mosfet-yaxis mosfet))) + (if (integer? yaxis) ; positive as well as negative + #t + (begin + (display "!! insane mosfet-yaxis check " (current-error-port)) + (display yaxis (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; transistor size + (let ((size (mosfet-size mosfet))) + (if (string? size) + #t + (begin + (display "!! insane mosfet-size check " (current-error-port)) + (display size (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ) + ) + ) + ) + +;; ------------------------------------------------------------------- +;; EXAMPLE CELLS +;; ------------------------------------------------------------------- ;; ------------ Example : INV-cell ------------------------------- ; ^ Vdd ; | ; | --+ -; A --o| | pmos +; A --o| | g ; | --+ ; | ; *---- Y ; | ; | --+ -; A ---| | nmos +; A ---| | 1 ; | --+ ; | ; _|_ Gnd - (define INV-cell '#(INV "a Not (or Inverter) gate" - (A) (Y) () - (#(pmos A Y VDD VDD 1 1 1) - #(nmos A Y GND GND 1 1 -1)) + (define INV-cell '#("INV" "a Not (or Inverter) gate" + ("A") ("Y") () + (#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) + ()) + ) + +;; ------------ Example : BUF-cell ------------------------------- + +; ^ Vdd ^ Vdd +; | | +; | --+ | --+ +; A --o| | g +--o| | g +; | --+ | | --+ +; | | | +; *-----------* *---- Z +; | | | +; | --+ | | --+ +; A ---| | 1 +---| | 1 +; | --+ | --+ +; | | +; _|_ Gnd _|_ Gnd + + (define BUF-cell '#("BUF" "a non-inverting Buffer gate" + ("A") ("Z") () + (#("pmos" "N1" "Z" "VDD" "VDD" 1 2 1 "g") + #("nmos" "N1" "Z" "GND" "GND" 1 2 -1 "1") + #("pmos" "A" "N1" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "N1" "GND" "GND" 1 1 -1 "1")) ()) ) @@ -129,28 +1269,28 @@ ; ^ Vdd ^ Vdd ; | | ; | --+ | --+ -; A --o| | pmos B --o| | pmos +; A --o| | g B --o| | g ; | --+ | --+ ; | | ; *-------------------*---- Y ; | ; | --+ -; A ---| | nmos +; A ---| | 2 ; | --+ -; | +; | N2 ; | ; | --+ -; B ---| | nmos +; B ---| | 2 ; | --+ ; | ; _|_ Gnd - (define NAND2-cell '#(NAND2 "a 2-input Not-AND (or NAND) gate" - (B A) (Y) () - (#(pmos B Y VDD VDD 1 2 1) - #(pmos A Y VDD VDD 1 1 1) - #(nmos A Y N2 GND 1 1 -1) - #(nmos B N2 GND GND 2 1 -2)) + (define NAND2-cell '#("NAND2" "a 2-input Not-AND (or NAND) gate" + ("B" "A") ("Y") () + (#("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g") + #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Y" "N2" "GND" 1 1 -1 "2") + #("nmos" "B" "N2" "GND" "GND" 2 1 -2 "2")) ()) ) @@ -159,71 +1299,176 @@ ; ^ Vdd ; | ; | --+ -; B --o| | pmos +; B --o| | 2g ; | --+ ; | -; | +; | N1 ; | --+ -; A --o| | pmos +; A --o| | 2g ; | --+ ; | ; *-------------------*---- Y ; | | ; | --+ | --+ -; A ---| | nmos B ---| | nmos +; A ---| | 1 B ---| | 1 ; | --+ | --+ ; | | ; _|_ Gnd _|_ Gnd - (define NOR2-cell '#(NAND2 "a 2-input Not-AND (or NAND) gate" - (B A) (Y) () - (#(pmos B N1 VDD VDD 2 1 2) - #(pmos A Z N1 VDD 1 1 1) - #(nmos A Y GND GND 1 1 -1) - #(nmos B Y GND GND 1 2 -1)) + (define NOR2-cell '#("NOR2" "a 2-input Not-OR (or NOR) gate" + ("B" "A") ("Y") () + (#("pmos" "B" "N1" "VDD" "VDD" 2 1 2 "2g") + #("pmos" "A" "Z" "N1" "VDD" 1 1 1 "2g") + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + #("nmos" "B" "Y" "GND" "GND" 1 2 -1 "1")) ()) ) +;; ------------ Example : OAI21-cell --------------------------- + +; ^ Vdd +; | +; | --+ +; B1 --o| | 2g +; | --+ +; ^ Vdd | +; | | N1 +; | --+ | --+ +; A --o| | g B0 --o| | 2g +; | --+ | --+ +; | | +; *-------------------*---- Y +; | +; | --+ +; A ---| | 2 +; | --+ +; | N2 +; *-------------------* +; | | +; | --+ | --+ +; B0 ---| | 2 B1 ---| | 2 +; | --+ | --+ +; | | +; _|_ Gnd _|_ Gnd + + (define OAI21-cell '#("OAI21" "a 2-1-input OR-AND-Invert (or OAI) gate" + ("B1" "B0" "A") ("Y") () + (#("pmos" "B1" "N1" "VDD" "VDD" 2 2 2 "2g") + #("pmos" "B0" "Y" "N1" "VDD" 1 2 1 "2g") + #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Y" "N2" "GND" 1 1 -1 "2") + #("nmos" "B0" "N2" "GND" "GND" 2 1 -2 "2") + #("nmos" "B1" "N2" "GND" "GND" 2 2 -2 "2")) + ()) + ) + +;; ------------ Example : AOI21-cell --------------------------- + +; ^ Vdd ^ Vdd +; | | +; | --+ | --+ +; B0 --o| | 2g B1 --o| | 2g +; | --+ | --+ +; | N1 | +; *-------------------* +; | +; | --+ +; A --o| | 2g +; | --+ +; | +; *-------------------*---- Y +; | | +; | --+ | --+ +; A ---| | 1 B0 ---| | 2 +; | --+ | --+ +; | | +; _|_ Gnd | N2 +; | --+ +; B1 ---| | 2 +; | --+ +; | +; _|_ Gnd + + (define AOI21-cell '#("AOI21" "a 2-1-input AND-OR-Invert (or AOI) gate" + ("B1" "B0" "A") ("Y") () + (#("pmos" "B1" "N1" "VDD" "VDD" 2 2 2 "2g") + #("pmos" "B0" "Y" "N1" "VDD" 2 1 2 "2g") + #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "2g") + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + #("nmos" "B0" "Y" "N2" "GND" 2 2 -1 "2") + #("nmos" "B1" "N2" "GND" "GND" 2 2 -2 "2")) + ()) + ) + ;; ------------------------------------------------------------------- ;; CELL DATA STRUCTURE ;; ------------------------------------------------------------------- ; define cell as vector: ; +---------------+ -; #0 | cell id | 'INV +; #0 | cell id | "INV" ; +---------------+ ; #1 | cell text | "a Not (or Inverter) gate" ; +---------------+ -; #2 | cell inputs | '(A) +; #2 | cell inputs | '("A") ; +---------------+ -; #3 | cell outputs | '(Y) +; #3 | cell outputs | '("Y") ; +---------------+ ; #4 | cell clocks | '() ; for latches ; +---------------+ -; #5 | netlist | '(#(pmos A Y VDD VDD 1 1 1) -; +---------------+ #(nmos A Y GND GND 1 1 -1)) +; #5 | netlist | '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") +; +---------------+ #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) ; #6 | additional | '() ; e.g. handover ASCII-Art ; +---------------+ -; define constants for vector indices - (define |cell-id#| 0) - (define |cell-text#| 1) - (define |cell-inputs#| 2) - (define |cell-outputs#| 3) - (define |cell-clocks#| 4) - (define |cell-netlist#| 5) - (define |cell-additional#| 6) +; define constants for vector indices + (define |cell-id#| 0) + (define |cell-text#| 1) + (define |cell-inputs#| 2) + (define |cell-outputs#| 3) + (define |cell-clocks#| 4) + (define |cell-netlist#| 5) + (define |cell-additional#| 6) + +;; ------------ generate empty cell --------------------------- + +; Contract: +; generate-cell : -> cell + +; Purpose: +; generate new and empty cell vector structure + +; Example: +; (generate-cell) => '#() + +; Definition + (define generate-cell + (lambda () + (make-vector 7 '()) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (generate-cell) #(() () () () () () ())) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " generate-cell test" (current-error-port)) + (newline (current-error-port)) + ) + ) ;; ------------ getter function : cell-id ----------------------- ; Contract: -; cell-id : cell -> symbol +; cell-id : cell -> string ; Purpose: ; get the cell ID out of a cell description vector ; Example: -; (cell-id INV-cell) => 'INV +; (cell-id INV-cell) => "INV" ; Definitions: (define cell-id @@ -233,9 +1478,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (cell-id INV-cell) 'INV) + (if (equal? (cell-id INV-cell) "INV") (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " cell-id test" (current-error-port)) @@ -246,18 +1491,19 @@ ;; ------------ setter function : cell-id! ----------------------- ; Contract: -; cell-id! : cell symbol -> cell +; cell-id! : cell string -> cell ; Purpose: ; set the cell ID in a cell description vector ; Example: -; (cell-id! INV-cell 'INV) => 'INV-cell +; (cell-id! INV-cell "INV") => INV-cell ; Definitions: (define cell-id! (lambda (cell id) (vector-set! cell |cell-id#| id) + cell ) ) @@ -280,7 +1526,7 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin (if (equal? (cell-text INV-cell) "a Not (or Inverter) gate") (display "++ passed" (current-error-port)) @@ -305,19 +1551,20 @@ (define cell-text! (lambda (cell text) (vector-set! cell |cell-text#| text) + cell ) ) ;; ------------ getter function : cell-inputs ------------------- ; Contract: -; cell-inputs : cell -> list-of-symbols +; cell-inputs : cell -> list-of-strings ; Purpose: ; get the cell input list out of a cell description vector ; Example: -; (cell-inputs INV-cell) => '(A) +; (cell-inputs INV-cell) => '("A") ; Definition: (define cell-inputs @@ -327,9 +1574,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (cell-inputs INV-cell) '(A)) + (if (equal? (cell-inputs INV-cell) '("A")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " cell-inputs test" (current-error-port)) @@ -340,31 +1587,32 @@ ;; ------------ setter function : cell-inputs! ------------------- ; Contract: -; cell-inputs! : cell list-of-symbols -> cell +; cell-inputs! : cell list-of-strings -> cell ; Purpose: ; set the cell input list in a cell description vector ; Example: -; (cell-inputs! INV-cell '(A)) => INV-cell +; (cell-inputs! INV-cell '("A")) => INV-cell ; Definition: (define cell-inputs! (lambda (cell list-of-inputs) (vector-set! cell |cell-inputs#| list-of-inputs) + cell ) ) ;; ------------ getter function : cell-outputs ------------------- ; Contract: -; cell-outputs : cell -> list-of-symbols +; cell-outputs : cell -> list-of-strings ; Purpose: ; get the cell output list out of a cell description vector ; Example: -; (cell-outputs INV-cell) => '(Y) +; (cell-outputs INV-cell) => '("Y") ; Definition: (define cell-outputs @@ -374,9 +1622,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (cell-outputs INV-cell) '(Y)) + (if (equal? (cell-outputs INV-cell) '("Y")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " cell-outputs test" (current-error-port)) @@ -387,25 +1635,26 @@ ;; ------------ setter function : cell-outputs! ------------------- ; Contract: -; cell-outputs! : cell list-of-symbols -> cell +; cell-outputs! : cell list-of-strings -> cell ; Purpose: ; set the cell output list of a cell description vector ; Example: -; (cell-outputs! INV-cell '(Y)) => INV-cell +; (cell-outputs! INV-cell '("Y")) => INV-cell ; Definition: (define cell-outputs! - (lambda (cell list-of-symbols) - (vector-set! cell |cell-outputs#| list-of-symbols) + (lambda (cell list-of-strings) + (vector-set! cell |cell-outputs#| list-of-strings) + cell ) ) ;; ------------ getter function : cell-clocks ------------------- ; Contract: -; cell-clocks : cell -> list-of-symbols +; cell-clocks : cell -> list-of-strings ; Purpose: ; get the cell clock list out of a cell description vector @@ -421,7 +1670,7 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin (if (equal? (cell-clocks INV-cell) '()) (display "++ passed" (current-error-port)) @@ -446,6 +1695,7 @@ (define cell-clocks! (lambda (cell list-of-symbols) (vector-set! cell |cell-clocks#| list-of-symbols) + cell ) ) @@ -458,7 +1708,7 @@ ; get the netlist out of a cell description vector ; Example: -; (cell-outputs INV-cell) => '(Y) +; (cell-netlist INV-cell) => '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) ; Definition: (define cell-netlist @@ -468,10 +1718,10 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (cell-netlist INV-cell) '(#(pmos A Y VDD VDD 1 1 1) - #(nmos A Y GND GND 1 1 -1))) + (if (equal? (cell-netlist INV-cell) '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " cell-netlist test" (current-error-port)) @@ -488,19 +1738,21 @@ ; set the netlist in a cell description vector ; Example: -; (cell-outputs! INV-cell '(Y)) => INV-cell +; (cell-netlist! INV-cell '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") +; #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) => INV-cell ; Definition: (define cell-netlist! (lambda (cell netlist) (vector-set! cell |cell-netlist#| netlist) + cell ) ) ;; ------------ getter function : cell-additional --------------- ; Contract: -; cell-additional : cell -> list-of-string +; cell-additional : cell -> list-of-strings ; Purpose: ; get additional informations for the cell out of a cell description vector @@ -516,7 +1768,7 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin (if (equal? (cell-additional INV-cell) '()) (display "++ passed" (current-error-port)) @@ -529,7 +1781,7 @@ ;; ------------ setter function : cell-additional! --------------- ; Contract: -; cell-additional! : cell list-of-string -> cell +; cell-additional! : cell list-of-strings -> cell ; Purpose: ; set additional informations in a cell description vector @@ -541,746 +1793,1313 @@ (define cell-additional! (lambda (cell list-of-symbols) (vector-set! cell |cell-additional#| list-of-symbols) + cell + ) + ) + +;; ------------ sanity check for netlist ----------------------- + +; Contract: +; sanity-netlist? : netlist -> boolean + +; Purpose: +; check sanity for well-formed netlist + +; Example: +; (sanity-netlist? (cell-netlist INV-cell)) => #t + +; Definition + (define sanity-netlist? + (lambda (netlist) + (if build-in-sanity-checks? + (if (and (list? netlist) + ; at least one list member + (> (length netlist) 0) + ; (every) member has to be a mosfet + (sanity-mosfet? (car netlist))) + #t + (begin + (display "!! insane cell-netlist check " (current-error-port)) + (display netlist (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ) + ) + +;; ------------ sanity check for cell --------------------------- + +; Contract: +; sanity-cell? : cell -> boolean + +; Purpose: +; check type / sanity for well-formed cell vector descriptions + +; Example: +; (sanity-cell? INV-cell) => #t + +; Definition + (define sanity-cell? + (lambda (cell) + (if build-in-sanity-checks? + (begin + ; cell-id + (let ((id (cell-id cell))) + (if (and (string? id) + ; one word only + (= (length (string-split id #[ ])) 1)) + #t + (begin + (display "!! insane cell-id check " (current-error-port)) + (display id (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; cell-text + (let ((text (cell-text cell))) + (if (and (string? text) + ; at least one word + (> (length (string-split text #[ ])) 0)) + #t + (begin + (display "!! insane cell-text check " (current-error-port)) + (display text (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; cell-inputs + (let ((inputs (cell-inputs cell))) + (if (and (list? inputs) + ; at least one list member + (> (length inputs) 0) ; !! filler-cells w/o inputs !! + ; (every) member has to be string + (string? (car inputs))) + #t + (begin + (display "!! insane cell-inputs check " (current-error-port)) + (display inputs (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; cell-outputs + (let ((outputs (cell-outputs cell))) + (if (and (list? outputs) + ; at least one list member + (> (length outputs) 0) ; !! filler-cells w/o outputs !! + ; (every) member has to be string + (string? (car outputs))) + #t + (begin + (display "!! insane cell-outputs check " (current-error-port)) + (display outputs (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ; cell-clocks + (let ((clocks (cell-clocks cell))) + (if (list? clocks) + ; at least one list member + (if (null? clocks) + #t + (if (string? (car clocks)) ; (every) member has to be string + #t + (begin + (display "!! insane cell-clocks check " (current-error-port)) + (display clocks (current-error-port)) + (newline (current-error-port)) + #f + ) + ) + ) + ) + ) + ; cell-netlist + (sanity-netlist? (cell-netlist cell)) + ; cell-additional + ) + ) ) ) + (sanity-cell? INV-cell) + (sanity-cell? NAND2-cell) + (sanity-cell? NOR2-cell) + (sanity-cell? OAI21-cell) + (sanity-cell? AOI21-cell) + ;; ------------------------------------------------------------------- -;; TRANSISTOR DATA STRUCTURE +;; FUNCTIONS on NETLISTs ;; ------------------------------------------------------------------- -; define transistor as vector: Example: -; +---------------+ -; #0 | circuit type | 'nmos -; +---------------+ -; #1 | gate node | 'A -; +---------------+ -; #2 | drain node | 'X -; +---------------+ -; #3 | source node | 'VDD -; +---------------+ -; #4 | bulk node | 'VDD -; +---------------+ -; #5 | stucked | 1 -; +---------------+ -; #6 | x-axis point | 1 -; +---------------+ -; #7 | y-axis point | 1 -; +---------------+ +;; ------------ filter network for output buffer --------------- -; define constants for vector indices - (define |circuit-type#| 0) - (define |gate-node#| 1) - (define |drain-node#| 2) - (define |source-node#| 3) - (define |bulk-node#| 4) - (define |stucked#| 5) - (define |xaxis-point#| 6) - (define |yaxis-point#| 7) +; Contract: +; buffer-network : netlist -> netlist -;; ------------ getter function : mosfet-type ------------------- +; Purpose: +; get network with buffering transistors only + +; Example: +; (buffer-network (cell-netlist BUF-cell)) => '(#("pmos" "N1" "Z" "VDD" "VDD" 1 2 1 "g") +; #("nmos" "N1" "Z" "GND" "GND" 1 2 -1 "1")) +; Definition: + (define buffer-network + (lambda (netlist) + (cond + ; empty list? + [(null? netlist) netlist] + + ; mosfet belongs to output, append + [(equal? (mosfet-drain (car netlist)) "Z") + (cons (car netlist) (buffer-network (cdr netlist)))] + + ; mosfet does not drive output, go down + [else + (buffer-network (cdr netlist))] + ) + ) + ) + + ; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (buffer-network (cell-netlist BUF-cell)) '(#("pmos" "N1" "Z" "VDD" "VDD" 1 2 1 "g") #("nmos" "N1" "Z" "GND" "GND" 1 2 -1 "1"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " buffer-network test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter network for pull-up ------------------- ; Contract: -; mosfet-type : mosfet -> node +; pullup-network : netlist -> netlist ; Purpose: -; get the mosfet type out of mosfet transistor vector +; get network with pull-up transistors only + +; Example +; (pullup-network (cell-netlist INV-cell)) => #('pmos "A" "Y" "VDD" 'VDD" 1 1 1 "g") + +; Note: +; Implementation with (map) or (filter) are better? + +; Definition: + (define pullup-network + (lambda (netlist) + (cond + ; empty list? + [(null? netlist) netlist] + + ; exclude mosfet which buffers output, go down + [(eqv? (mosfet-drain (car netlist)) "Z") + (pullup-network (cdr netlist))] + + ; if pMOS than add mosfet to netlist, go down recursive + [(mosfet-pmos? (car netlist)) + (cons (car netlist) (pullup-network (cdr netlist)))] + + ; just go down + [else (pullup-network (cdr netlist))] + ) + ) + ) + + ; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (pullup-network (cell-netlist INV-cell)) '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " pullup-network test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter network for pull-down ------------------- + +; Contract: +; pulldown-network : netlist -> netlist + +; Purpose: +; get network with pull-down transistors only + +; Example: +; (pulldown-network (cell-netlist INV-cell)) => #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Note: +; Implementation with (map) or (filter) are better? + +; Definition: + (define pulldown-network + (lambda (netlist) + (cond + ; empty list? + [(null? netlist) netlist] + + ; exclude mosfet which buffers output, go down + [(eqv? (mosfet-drain (car netlist)) "Z") + (pullup-network (cdr netlist))] + + ; if nMOS than add mosfet to netlist, go down recursive + [(mosfet-nmos? (car netlist)) + (cons (car netlist) (pulldown-network (cdr netlist)))] + + ; just go down + [else (pulldown-network (cdr netlist))] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (pulldown-network (cell-netlist INV-cell)) '(#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " pulldown-network test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter for VDD connected transistors ----------- + +; Contract: +; vdd-mosfets : netlist -> netlist + +; Purpose: +; get all transistors which are connected to VDD + +; Example: +; (vdd-mosfets (cell-netlist INV-cell)) => #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + +; Note: +; Implementation with (map) or (filter) are better? + +; Definition: + (define vdd-mosfets + (lambda (netlist) + (cond + ; empty list? + [(null? netlist) netlist] + + ; if mosfet connected to supply power symbol, add them to netlist and go down recursive + [(supply-space? (mosfet-source (car netlist))) + (cons (car netlist) (vdd-mosfets (cdr netlist)))] + + ; just go down + [else (vdd-mosfets (cdr netlist))] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (vdd-mosfets (cell-netlist INV-cell)) '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " vdd-mosfets test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter for GND connected transistors ----------- + +; Contract: +; gnd-mosfets : netlist -> netlist + +; Purpose: +; get all transistors which are connected to GND + +; Example: +; (gnd-mosfets (cell-netlist INV-cell)) => #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") + +; Note: +; Implementation with (map) or (filter) are better? + +; Definition: + (define gnd-mosfets + (lambda (netlist) + (cond + ; empty list? + [(null? netlist) netlist] + + ; if mosfet connected to ground plane symbol, add them to netlist and go down recursive + [(ground-space? (mosfet-source (car netlist))) + (cons (car netlist) (gnd-mosfets (cdr netlist)))] + + ; just go down + [else (gnd-mosfets (cdr netlist))] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (gnd-mosfets (cell-netlist INV-cell)) '(#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " gnd-mosfets test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter for input connected transistors ----------- + +; Contract: +; input-mosfets : netlist node -> netlist + +; Purpose: +; get all transistors which are connected to input + +; Example: +; (input-mosfets (cell-netlist INV-cell) "A") => INV-cell + +; Note +; Implementation with (map) or (filter) are better? + +; Definitions: + (define input-mosfets + (lambda (netlist node) + (cond + ; empty list? + [(null? netlist) netlist] + + ; if mosfet connected to input node, add them to netlist and go down recursive + [(equal? (mosfet-gate (car netlist)) node) + (cons (car netlist) (input-mosfets (cdr netlist) node))] + + ; just go down + [else (input-mosfets (cdr netlist) node)] + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (input-mosfets (cell-netlist INV-cell) "A") (cell-netlist INV-cell)) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " input-mosfets test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ filter for node connected transistors ----------- + +; Contract: +; complementary-mosfets : netlist transtistor -> netlist + +; Purpose: +; get complementary transistors which is connected to the same input ; Example: -; (mosfet-type '#(nmos A Y VDD substrate 1 1 -1)) => 'nmos +; (complementary-mosfets (cell-netlist INV-cell) #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g")) => #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1") ; Definition: - (define mosfet-type - (lambda (transistor) - (vector-ref transistor |circuit-type#|) + (define complementary-mosfets + (lambda (netlist mosfet) + (let ((input (mosfet-gate mosfet))) + (cond + ; pmos? get first transistor out-of-list + [(mosfet-pmos? mosfet) + (car (input-mosfets (pulldown-network netlist) input))] + + ; nmos? get first transistor out-of-list + [(mosfet-nmos? mosfet) + (car (input-mosfets (pullup-network netlist) input))] + + ; unknown circuit + [else #f] + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-type '#(nmos A Y VDD substrate 1 1 -1)) 'nmos) + (if (equal? (complementary-mosfets (cell-netlist INV-cell) #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g")) #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-type test" (current-error-port)) + (display " complementary-mosfets test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-nmos? ------------------- +;; ------------ mosfets? operator ------------------------------- + +; Purpose: +; sort-operator for sort-mosfet-descending + + (define mosfet>? + (lambda (kar kdr) + (string-ci>? (mosfet-gate kar) (mosfet-gate kdr)) + ) + ) + +;; ------------ sort mosfets ascending --------------------------- ; Contract: -; mosfet-nmos? : mosfet -> boolean +; sort-mosfet-ascending : netlist -> netlist ; Purpose: -; check the mosfet type out of mosfet transistor vector +; sort all transistors regarding their names ; Example: -; (mosfet-nmos? '#(nmos A Y VDD substrate 1 1 -1)) => #t +; (sort-mosfet-ascending '(#("nmos" "B" "N2" "GND" "GND" 2 1 -2 "2") #("nmos" "A" "Y" "N2" GND 1 1 -1 "2"))) => (pulldown-network (cell-netlist NAND2-cell)) ; Definition: - (define mosfet-nmos? - (lambda (transistor) - (equal? (vector-ref transistor |circuit-type#|) 'nmos) + (define sort-mosfet-ascending + (lambda (netlist) + (list-sort mosfet boolean +; sort-mosfets-desscending : netlist -> netlist ; Purpose: -; check the mosfet type out of mosfet transistor vector +; sort all transistors regarding their names ; Example: -; (mosfet-pmos? '#(pmos A Y VDD substrate 1 1 -1)) => #t +; (sort-mosfet-descending '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g"))) => (pullup-network (cell-netlist NAND2-cell)) ; Definition: - (define mosfet-pmos? - (lambda (transistor) - (equal? (vector-ref transistor |circuit-type#|) 'pmos) + (define sort-mosfet-descending + (lambda (netlist) + (list-sort mosfet>? netlist) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (mosfet-pmos? '#(pmos A Y GND substrate 1 1 1)) + (if (equal? (sort-mosfet-descending '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g"))) (pullup-network (cell-netlist NAND2-cell))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-pmos? test" (current-error-port)) + (display " sort-mosfet-descending test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-gate ------------------- +;; ------------ sort netlist ----------------------------------- ; Contract: -; mosfet-gate : mosfet -> node +; sort-netlist : netlist -> netlist ; Purpose: -; get the mosfet gate node out of mosfet transistor vector +; sort pullup network descending, pulldown network ascending ; Example: -; (mosfet-gate '#(nmos A Y VDD substrate 1 1 -1)) => 'A +; (sort-netlist '(#())) => (cell-netlist NAND2-cell) -; Definition: - (define mosfet-gate - (lambda (transistor) - (vector-ref transistor |gate-node#|) +; Definition; + (define sort-netlist + (lambda (netlist) + (let ((pullup (sort-mosfet-descending (pullup-network netlist))) + (pulldown (sort-mosfet-ascending (pulldown-network netlist)))) + (append pullup pulldown) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-gate '#(nmos A Y VDD substrate 1 1 -1)) 'A) + (if (equal? (sort-netlist '(#("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g") + #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Y" "N2" "GND" 1 1 -1 "2") + #("nmos" "B" "N2" "GND" "GND" 2 1 -2 "2"))) (cell-netlist NAND2-cell)) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-gate test" (current-error-port)) + (display " sort-netlist test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-drain ------------------- +;; ------------ filter mosfets with char-group nodes ----------- ; Contract: -; mosfet-drain : mosfet -> node +; filter-mosfet-char : netlist node -> netlist ; Purpose: -; get the mosfet drain node out of mosfet transistor vector +; filter all transistors regarding one char group ; Example: -; (mosfet-drain '#(nmos A Y VDD substrate 1 1 -1)) => 'X +; (filter-mosfet-char '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g")) "A") => '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("nmos" "A" "Y" "N2" "GND" 1 1 -1 "2")) ; Definition: - (define mosfet-drain - (lambda (transistor) - (vector-ref transistor |drain-node#|) + (define filter-mosfet-char + (lambda (netlist node) + (cond + ; emtpy list? + [(null? netlist) netlist] + + ; if mosfet connected to node group, add them to netlist and go down recursive + [(equal? (string-ref (mosfet-gate (car netlist)) 0) (string-ref node 0)) + (cons (car netlist) (filter-mosfet-char (cdr netlist) node))] + + ; just go down + [else (filter-mosfet-char (cdr netlist) node)] + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-drain '#(nmos A Y VDD substrate 1 1 -1)) 'Y) + (if (equal? (filter-mosfet-char (cell-netlist NAND2-cell) "A") '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("nmos" "A" "Y" "N2" "GND" 1 1 -1 "2"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-drain test" (current-error-port)) + (display " filter-mosfet-char" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-source ------------------- +;; ------------ filter mosfet out with char-group nodes ----------- ; Contract: -; mosfet-source : mosfet -> node +; filter-mosfet-remove : netlist node -> netlist ; Purpose: -; get the mosfet source node out of mosfet transistor vector +; filter all transistors out with similiar node group ; Example: -; (mosfet-source '#(nmos A Y VDD substrate 1 1 -1)) => 'VDD +; (filter-mosfet-remove '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g")) "B") => '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g")) ; Definition: - (define mosfet-source - (lambda (transistor) - (vector-ref transistor |source-node#|) + (define filter-mosfet-remove + (lambda (netlist node) + (cond + ; emtpy list? + [(null? netlist) netlist] + + ; if mosfet connected to input node, ignore and go down recursive + [(equal? (string-ref (mosfet-gate (car netlist)) 0) (string-ref node 0)) + (filter-mosfet-remove (cdr netlist) node)] + + ; add mosfet to netlist, and go down + [else (cons (car netlist) (filter-mosfet-remove (cdr netlist) node))] + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-source '#(nmos A Y VDD substrate 1 1 -1)) 'VDD) + (if (equal? (filter-mosfet-remove (cell-netlist AOI21-cell) "B1") '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "2g") #("nmos" "A" "Y" "GND" "GND" 1 1 -1 "1"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-source test" (current-error-port)) + (display " filter-mosfet-remove" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-bulk ------------------- +;; ------------ filter mosfet regarding column number ----------- ; Contract: -; mosfet-bulk : mosfet -> node +; filter-mosfet-column : netlist column -> netlist ; Purpose: -; get the mosfet bulk node out of mosfet transistor vector +; return all transistors in one column ; Example: -; (mosfet-bulk '#(nmos A Y VDD substrate 1 1 -1)) => substrate +; (filter-mosfet-column '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 1) #("pmos" "B" "Y" "VDD" "VDD" 1 1 2 "g")) 2) => '(#("pmos" "B" "Y" "VDD" "VDD" 1 1 2 "g")) ; Definition: - (define mosfet-bulk - (lambda (transistor) - (vector-ref transistor |bulk-node#|) + (define filter-mosfet-column + (lambda (netlist column) + (cond + ; emtpy list? + [(null? netlist) netlist] + + ; if mosfet placed on this column, add them to netlist and go down recursive + [(= (mosfet-xaxis (car netlist)) column) + (cons (car netlist) (filter-mosfet-column (cdr netlist) column))] + + ; just go down + [else (filter-mosfet-column (cdr netlist) column)] + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-bulk '#(nmos A Y VDD substrate 1 1 -1)) 'substrate) + (if (equal? (filter-mosfet-column (cell-netlist NAND2-cell) 2) '(#("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-bulk test" (current-error-port)) + (display " filter-mosfet-column" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-xaxis ------------------- +;; ------------ filter mosfet regarding row number --------------- ; Contract: -; mosfet-xaxis : mosfet -> number +; filter-mosfet-row : netlist row -> netlist ; Purpose: -; get the mosfet x-axis coordinate out of mosfet transistor vector +; return all transistors in one row ; Example: -; (mosfet-xaxis '#(nmos A Y VDD substrate 1 1 -1)) => 1 +; (filter-mosfet-row '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g")) 1) => '(#("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") #("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g")) ; Definition: - (define mosfet-xaxis - (lambda (transistor) - (vector-ref transistor |xaxis-point#|) + (define filter-mosfet-row + (lambda (netlist row) + (cond + ; emtpy list? + [(null? netlist) netlist] + + ; if mosfet placed on this row, add them to netlist and go down recursive + [(= (mosfet-yaxis (car netlist)) row) + (cons (car netlist) (filter-mosfet-row (cdr netlist) row))] + + ; just go down + [else (filter-mosfet-row (cdr netlist) row)] + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-xaxis '#(nmos A Y VDD substrate 1 1 -1)) 1) + (if (equal? (filter-mosfet-row (cell-netlist NAND2-cell) 1) '(#("pmos" "B" "Y" "VDD" "VDD" 1 2 1 "g") #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-xaxis test" (current-error-port)) + (display " filter-mosfet-row" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ getter function : mosfet-yaxis ------------------- +;; ------------ filter for input nodes --------------------------- ; Contract: -; mosfet-yaxis : mosfet -> number +; input-nodes : netlist -> list-of-nodes ; Purpose: -; get the mosfet y-axis coordinate out of mosfet transistor vector +; filter all input nodes from network into one list ; Example: -; (mosfet-yaxis '#(nmos A Y VDD substrate 1 1 -1)) => 1 +; (input-nodes (cell-netlist INV-Cell)) => '("A") ; Definition: - (define mosfet-yaxis - (lambda (transistor) - (vector-ref transistor |yaxis-point#|) + (define input-nodes + (lambda (netlist) + (if (null? netlist) + ; emtpy list? + netlist + (let ((node (mosfet-gate (car netlist))) + (feedback (input-nodes (cdr netlist)))) + (cond + ; node on gate in input-space? + [(and (input-space? node) (not (member node feedback))) + (cons node feedback) + ] + + ; just go down + [else (input-nodes (cdr netlist))] + ) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (mosfet-yaxis '#(nmos A Y VDD substrate 1 1 -1)) -1) + (if (equal? (input-nodes (cell-netlist NOR2-cell)) '("A" "B")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " mosfet-yaxis test" (current-error-port)) + (display " input-nodes test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------------------------------------------------------------- -;; NODE SPACES -;; ------------------------------------------------------------------- - -;; ------------ input node names ------------------------------- - - (define input-space '(A B C D E F G H I L M P R S T U V W)) +;; ------------ replace node on all occurrencies --------------- ; Contract: -; input-space? : list-of-ports -> boolean +; replace-nodes : netlist node node -> netlist ; Purpose: -; check whether node is in defined input space for cells +; crawl netlist for nodes and replace them by another name ; Example: -; (input-space? 'A) => #t -; (input-space? 'Z) => #f +; (replace-nodes (cell-netlist INV-cell) "Y" "Z") => '(#("pmos" "A" "Z" "VDD" "VDD" 1 1 1 "g") +; #("nmos" "A" "Z" "GND" "GND" 1 1 -1 "1")) ; Definition: - (define input-space? - (lambda (node) - (if (memq node input-space) #t #f) + (define replace-nodes + (lambda (netlist old-node new-node) + (if (null? netlist) + netlist + (let ((original (car netlist)) + (mosfet (generate-mosfet))) + (begin + (mosfet-type! mosfet (mosfet-type original)) + (if (equal? (mosfet-gate original) old-node) + (mosfet-gate! mosfet new-node) + (mosfet-gate! mosfet (mosfet-gate original))) + (if (equal? (mosfet-source original) old-node) + (mosfet-source! mosfet new-node) + (mosfet-source! mosfet (mosfet-source original))) + (if (equal? (mosfet-drain original) old-node) + (mosfet-drain! mosfet new-node) + (mosfet-drain! mosfet (mosfet-drain original))) + (if (equal? (mosfet-bulk original) old-node) + (mosfet-bulk! mosfet new-node) + (mosfet-bulk! mosfet (mosfet-bulk original))) + (mosfet-stacked! mosfet (mosfet-stacked original)) + (mosfet-xaxis! mosfet (mosfet-xaxis original)) + (mosfet-yaxis! mosfet (mosfet-yaxis original)) + (mosfet-size! mosfet (mosfet-size original)) + (cons mosfet (replace-nodes (cdr netlist) old-node new-node)) + ) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (and (input-space? 'A) (not (input-space? 'Z))) + (if (equal? (replace-nodes (cell-netlist INV-cell) "Y" "Z") '(#("pmos" "A" "Z" "VDD" "VDD" 1 1 1 "g") + #("nmos" "A" "Z" "GND" "GND" 1 1 -1 "1"))) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " input-space? test" (current-error-port)) + (display " replace-nodes test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ output node names ------------------------------- - - (define output-space '(Q Y Z)) +;; ------------ filter for intermediate nodes ------------------- ; Contract: -; output-space? list-of-ports -> boolean +; intermediate-nodes : netlist -> list-of-nodes ; Purpose: -; check wether node is in defined output space for cells +; filter all internal / intermediate nodes from network into one list ; Example: -; (output-space? 'A) => #f -; (output-space? 'Z) => #t +; (intermediate-nodes (cell-netlist INV-Cell)) => '() +; (intermediate-nodes (cell-netlist NOR2-Cell)) => '("N1") ; Definition: - (define output-space? - (lambda (node) - (if (memq node output-space) #t #f) + (define intermediate-nodes + (lambda (netlist) + (if (null? netlist) + ; emtpy list? + netlist + (let ((node (mosfet-drain (car netlist))) + (feedback (intermediate-nodes (cdr netlist)))) + (cond + ; node on drain in node-space? + [(and (node-space? node) (not (member node feedback))) + (cons node feedback) + ] + + ; just go down + [else (intermediate-nodes (cdr netlist))] + ) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (and (output-space? 'Z) (not (output-space? 'A))) + (if (equal? (intermediate-nodes (cell-netlist NOR2-cell)) '("N1")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " output-space? test" (current-error-port)) + (display " intermediate-nodes test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ clock node names ------------------------------- - - (define clock-space '(X)) +;; ------------ filter for clock nodes --------------------------- ; Contract: -; clock-space? list-of-ports -> boolean +; clock-node : netlist -> list-of-nodes ; Purpose: -; check wether node is in defined clock space for cells +; filter all clock nodes from network into one list ; Example: -; (clock-space? 'X) => #t +; (clock-nodes (cell-netlist INV-Cell)) => '() ; Definition: - (define clock-space? - (lambda (node) - (if (memq node clock-space) #t #f) + (define clock-nodes + (lambda (netlist) + (if (null? netlist) + ; emtpy list? + netlist + (let ((node (mosfet-drain (car netlist))) + (feedback (clock-nodes (cdr netlist)))) + (cond + ; node on input in clock-space? + [(and (clock-space? node) (not (member node feedback))) + (cons node feedback) + ] + + ; just go down + [else (clock-nodes (cdr netlist))] + ) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (clock-space? 'X) + (if (equal? (clock-nodes (cell-netlist INV-cell)) '()) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " clock-space? test" (current-error-port)) + (display " clock-nodes test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ internal node names ------------------------------- - - (define node-space '(N)) +;; ------------ filter for output nodes --------------------------- ; Contract: -; node-space? list-of-nodes -> boolean +; output-node : netlist -> list-of-nodes ; Purpose: -; check wether node is in defined node space for cells +; filter all output nodes from network into one list ; Example: -; (node-space? 'N) => #t +; (output-nodes (cell-netlist INV-Cell)) => '("Y") ; Definition: - (define node-space? - (lambda (node) - (if (memq node node-space) #t #f) + (define output-nodes + (lambda (netlist) + (if (null? netlist) + ; emtpy list? + netlist + (let ((node (mosfet-drain (car netlist))) + (feedback (output-nodes (cdr netlist)))) + (cond + ; node on input in output-space? + [(and (output-space? node) (not (member node feedback))) + (cons node feedback) + ] + + ; just go down + [else (output-nodes (cdr netlist))] + ) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (node-space? 'N) + (if (equal? (output-nodes (cell-netlist INV-cell)) '("Y")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " node-space? test" (current-error-port)) + (display " output-nodes test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ supply symbol node name space ------------------- +;; ------------ length-1st length-2nd) #f] + ; character of 1st name is smaller than 2nd + [(< (char->integer (string-ref kar 0)) (char->integer (string-ref kdr 0))) #t] + [else + (if (> length-1st 1) + ; check numbers + (< (string->number (substring kar 1 length-1st)) (string->number (substring kdr 1 length-2nd))) + ; otherwise false + #f) + ] + ) + ) + ) + ) -; Usually, SCHEME is case-insensitive but some implementations (and R7RS) are not. -; Hence, the list of symbols contains common low-case / upper-case variations. +;; ------------ >node operator ----------------------------------- + + (define >node + (lambda (kar kdr) + (let ((length-1st (string-length kar)) + (length-2nd (string-length kdr))) + (cond + ; 1st name is longer than 2nd + [(> length-1st length-2nd) #t] + ; 1st name is shorter than 2nd + [(< length-1st length-2nd) #f] + ; character of 1st name is bigger than 2nd + [(> (char->integer (string-ref kar 0)) (char->integer (string-ref kdr 0))) #t] + [else + (if (> length-1st 1) + ; check numbers + (> (string->number (substring kar 1 length-1st)) (string->number (substring kdr 1 length-2nd))) + ; otherwise false + #f) + ] + ) + ) + ) + ) -; Definition: - (define supply-symbol-space '(vcc vdd Vcc Vdd VCC VDD)) +;; ------------ sort nodes descending --------------------------- ; Contract: -; sypply-symbol-space? list-of-ports -> boolean +; sort-nodes-desscending : node-list -> node-list ; Purpose: -; check wether node is in defined list for sypply symbols +; sort all nodes regarding their names ; Example: -; (supply-symbol-space? 'Vdd) => #t -; (supply-symbol-space? 'gnd) => #f +; (sort-nodes-descending '("N1" "N2" "N3")) => '("N3" "N2" "N1") ; Definition: - (define supply-symbol-space? - (lambda (node) - (if (memq node supply-symbol-space) #t #f) + (define sort-nodes-descending + (lambda (nodelist) + (list-sort >node nodelist) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (and (supply-symbol-space? 'Vdd) (not (supply-symbol-space? 'gnd))) + (if (equal? (sort-nodes-descending '("N1" "N2" "N3")) '("N3" "N2" "N1")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " supply-symbol-space? test" (current-error-port)) + (display " sort-nodes-descending test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ ground plane node name space ------------------- - -; Usually, SCHEME is case-insensitive but some implementations are not. -; Hence, the list of symbols contains common low-case / upper-case variations. - -; Definition: - (define ground-symbol-space '(gnd vss Gnd Vss GND VSS)) +;; ------------ sort nodes ascending --------------------------- ; Contract: -; ground-symbol-space? list-of-ports -> boolean +; sort-nodes-ascending : node-list -> node-list ; Purpose: -; check wether node is in defined list for ground symbols +; sort all nodes regarding their names ; Example: -; (ground-symbol-space? 'Vdd) => #t -; (ground-symbol-space? 'gnd) => #f +; (sort-nodes-ascending '("N3" "N2" "N1")) => '("N1" "N2" "N3") ; Definition: - (define ground-symbol-space? - (lambda (node) - (if (memq node ground-symbol-space) #t #f) + (define sort-nodes-ascending + (lambda (nodelist) + (list-sort netlist +; metric-tp-stacked : netlist -> number ; Purpose: -; get network with pull-up transistors only +; crawl netlist and get highest number of stacked pmos transistors ; Example: -; (get-pullup-network (cell-netlist INV-cell)) => #('pmos 'A 'Y 'VDD 'VDD 1 1 1) - -; Note: -; Implementation with (map) or (filter) are better? +; (metric-tp-stacked (cell-netlist OAI21-cell)) => 2 ; Definition: - (define get-pullup-network + (define metric-tp-stacked (lambda (netlist) (cond - ; empty list? - [(null? netlist) netlist] - - ; if pMOS than add mosfet to netlist, go down recursive - [(mosfet-pmos? (car netlist)) - (cons (car netlist) (get-pullup-network (cdr netlist)))] - - ; just go down - [else (get-pullup-network (cdr netlist))] + [(null? netlist) 0] + [(mosfet-nmos? (car netlist)) + ; do not check nmos transistors for tp + (metric-tp-stacked (cdr netlist))] + [else + (let ((stacked (mosfet-stacked (car netlist)))) + (max stacked (metric-tp-stacked (cdr netlist))) + ) + ] ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (get-pullup-network (cell-netlist INV-cell)) '(#(pmos A Y VDD VDD 1 1 1))) + (if (equal? (metric-tp-stacked (cell-netlist OAI21-cell)) 2) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " get-pullup-network test" (current-error-port)) + (display " metric-tp-stacked test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ filter network for pull-down ------------------- +;; ------------ stacked nmos transistors ----------------------- ; Contract: -; get-pulldown-network : netlist -> netlist +; metric-tn-stacked : netlist -> number ; Purpose: -; get network with pull-down transistors only +; crawl netlist and get highest number of stacked nmos transistors ; Example: -; (get-pulldown-network (cell-netlist INV-cell)) => #('nmos 'A 'Y 'GND 'GND 1 1 -1) - -; Note: -; Implementation with (map) or (filter) are better? +; (metric-tn-stacked (cell-netlist OAI21-cell)) => 2 ; Definition: - (define get-pulldown-network + (define metric-tn-stacked (lambda (netlist) (cond - ; empty list? - [(null? netlist) netlist] - - ; if nMOS than add mosfet to netlist, go down recursive - [(mosfet-nmos? (car netlist)) - (cons (car netlist) (get-pulldown-network (cdr netlist)))] - - ; just go down - [else (get-pulldown-network (cdr netlist))] + [(null? netlist) 0] + [(mosfet-pmos? (car netlist)) + ; do not check pmos transistors for tn + (metric-tn-stacked (cdr netlist))] + [else + (let ((stacked (mosfet-stacked (car netlist)))) + (max stacked (metric-tn-stacked (cdr netlist))) + ) + ] ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (get-pulldown-network (cell-netlist INV-cell)) '(#(nmos A Y GND GND 1 1 -1))) + (if (equal? (metric-tn-stacked (cell-netlist OAI21-cell)) 2) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " get-pulldown-network test" (current-error-port)) + (display " metric-tn-stacked test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ filter for VDD connected transistors ----------- +;; ------------ stacked both transistors ----------------------- ; Contract: -; get-vdd-mosfets : netlist -> netlist +; metric-highest-stacked : netlist -> number ; Purpose: -; get all transistors which are connected to VDD +; take highest number from pullup / pulldown network ; Example: -; (get-vdd-mosfets (cell-netlist INV-cell)) => #('pmos 'A 'Y 'VDD 'VDD 1 1 1) - -; Note: -; Implementation with (map) or (filter) are better? +; (metric-highest-stacked (cell-netlist NAND2-cell) => 2 ; Definition: - (define get-vdd-mosfets + (define metric-highest-stacked (lambda (netlist) - (cond - ; empty list? - [(null? netlist) netlist] - - ; if mosfet connected to supply power symbol, add them to netlist and go down recursive - [(supply-symbol-space? (mosfet-source (car netlist))) - (cons (car netlist) (get-vdd-mosfets (cdr netlist)))] - - ; just go down - [else (get-vdd-mosfets (cdr netlist))] - ) + (max (metric-tp-stacked netlist) (metric-tn-stacked netlist)) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (get-vdd-mosfets (cell-netlist INV-cell)) '(#(pmos A Y VDD VDD 1 1 1))) + (if (equal? (metric-highest-stacked (cell-netlist NAND2-cell)) 2) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " get-vdd-mosfets test" (current-error-port)) + (display " metric-highest-stacked test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ filter for GND connected transistors ----------- +;; ------------ find highest xaxis number ----------------------- ; Contract: -; get-gnd-mosfets : netlist -> netlist +; metric-highest-xaxis : netlist -> number ; Purpose: -; get all transistors which are connected to GND +; crawl netlist and find highest xaxis number ; Example: -; (get-gnd-mosfets (cell-netlist INV-cell)) => #('nmos 'A 'Y 'GND 'GND 1 1 -1) - -; Note: -; Implementation with (map) or (filter) are better? +; (metric-highest-xaxis (cell-netlist OAI21-cell)) => 2 ; Definition: - (define get-gnd-mosfets + (define metric-highest-xaxis (lambda (netlist) - (cond - ; empty list? - [(null? netlist) netlist] - - ; if mosfet connected to ground plane symbol, add them to netlist and go down recursive - [(ground-symbol-space? (mosfet-source (car netlist))) - (cons (car netlist) (get-gnd-mosfets (cdr netlist)))] - - ; just go down - [else (get-gnd-mosfets (cdr netlist))] + (if (null? netlist) + 0 + (let ((xaxis (mosfet-xaxis (car netlist)))) + (max xaxis (metric-highest-xaxis (cdr netlist))) + ) ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (get-gnd-mosfets (cell-netlist INV-cell)) '(#(nmos A Y GND GND 1 1 -1))) + (if (equal? (metric-highest-xaxis (cell-netlist OAI21-cell)) 2) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " get-gnd-mosfets test" (current-error-port)) + (display " metric-highest-xaxis test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ filter for node connected transistors ----------- +;; ------------ find highest yaxis number ----------------------- ; Contract: -; get-node-mosfets : netlist node -> netlist +; metric-highest-yaxis : netlist -> number ; Purpose: -; get all transistors which are connected to this node +; crawl netlist and find highest yaxis number ; Example: -; (get-node-mosfets (cell-netlist INV-cell) 'Y) => #('nmos 'A 'Y 'GND 'GND 1 1 -1) +; (metric-highest-yaxis (cell-netlist AOI21-cell)) => 2 ; Definition: - (define get-node-mosfets - (lambda (netlist node) - (cond - ; empty list? - [(null? netlist) netlist] + (define metric-highest-yaxis + (lambda (netlist) + (if (null? netlist) + 0 + (let ((yaxis (mosfet-yaxis (car netlist)))) + (max yaxis (metric-highest-yaxis (cdr netlist))) + ) + ) + ) + ) + +; Test: !! replace code by a portable SRFI test environemt + (if build-in-self-test? + (begin + (if (equal? (metric-highest-yaxis (cell-netlist AOI21-cell)) 2) + (display "++ passed" (current-error-port)) + (display "-- failed" (current-error-port))) + (display " metric-highest-yaxis test" (current-error-port)) + (newline (current-error-port)) + ) + ) + +;; ------------ find lowest yaxis number ----------------------- - ; if mosfet connected to node, add them to netlist and go down recursive - ; on source pins .. - [(equal? (mosfet-source (car netlist)) node) - (cons (car netlist) (get-node-mosfets (cdr netlist) node))] +; Contract: +; metric-lowest-yaxis : netlist -> number - ; .. and drain pins - [(equal? (mosfet-drain (car netlist)) node) - (cons (car netlist) (get-node-mosfets (cdr netlist) node))] +; Purpose: +; crawl netlist and find lowest yaxis number - ; just go down - [else (get-node-mosfets (cdr netlist) node)] +; Example: +; (metric-lowest-yaxis (cell-netlist AOI21-cell)) => -2 + +; Definition: + (define metric-lowest-yaxis + (lambda (netlist) + (if (null? netlist) + 0 + (let ((yaxis (mosfet-yaxis (car netlist)))) + (min yaxis (metric-lowest-yaxis (cdr netlist))) + ) ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (get-node-mosfets (cell-netlist INV-cell) 'Y) (cell-netlist INV-cell)) + (if (equal? (metric-lowest-yaxis (cell-netlist AOI21-cell)) -2) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " get-node-mosfets test" (current-error-port)) + (display " metric-lowest-yaxis test" (current-error-port)) (newline (current-error-port)) ) ) -;; ------------ sort mosfets ascending --------------------------- +;; ------------ find mosfet by position ----------------------- -; Contract: -; sort-mosfets-ascending : netlist -> netlist +; Purpose: +; mosfet-by-position : netlist -> mosfet ; Purpose: -; sort all transistors regarding their names +; crawl netlist and find mosfet by positon coordinates ; Example: -; (sort-mosfets-ascending (cell-netlist INV-cell)) => (cell-netlist INV-cell) +; (mosfet-by-position (cell-netlist INV-cell) 1 1) => #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g") ; Definition: - (define sort-mosfet-ascending - (lambda (netlist) - netlist ; !! + (define mosfet-by-position + (lambda (netlist xaxis yaxis) + (if (null? netlist) + netlist + (let ((mosfet (car netlist))) + ; check coordinates + (if (and (equal? (mosfet-xaxis mosfet) xaxis) + (equal? (mosfet-yaxis mosfet) yaxis)) + mosfet + (mosfet-by-position netlist xaxis yaxis)) + ) + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (sort-mosfet-ascending (cell-netlist INV-cell)) (cell-netlist INV-cell)) + (if (equal? (mosfet-by-position (cell-netlist INV-cell) 1 1) #("pmos" "A" "Y" "VDD" "VDD" 1 1 1 "g")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " sort-mosfet-ascending test" (current-error-port)) + (display " mosfet-by-position test" (current-error-port)) (newline (current-error-port)) ) ) @@ -1317,7 +3136,7 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin (if (> (copyleft-year) 2018) (display "++ passed" (current-error-port)) @@ -1341,7 +3160,7 @@ ; Definition: (define stringlist->csv (lambda (string-list) - (if (equal? (cdr string-list) ()) + (if (equal? (length string-list) 1) (car string-list) ; last value in list (string-append (car string-list) ", " (stringlist->csv (cdr string-list))) ) @@ -1349,7 +3168,7 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin (if (equal? (stringlist->csv '("C2" "B1" "A0")) "C2, B1, A0") (display "++ passed" (current-error-port)) @@ -1359,60 +3178,42 @@ ) ) -;; ------------ list of strings into list of symbols ----------- - -; Contract: -; stringlist->symbollist : list-of-strings -> list-of-symbols - -; Purpose: -; convert list of strings (e.g. ports) into list of symbols - -; Example: -; (stringlist->symbollist ("C" "B" "A") => ('C 'B 'A) - -; Definition: - (define stringlist->symbollist - (lambda (string-list) - (map string->symbol string-list) - ) - ) - -; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test - (begin - (if (equal? (stringlist->symbollist (list "C2" "B1" "A0")) '(C2 B1 A0)) - (display "++ passed" (current-error-port)) - (display "-- failed" (current-error-port))) - (display " stringlist->symbollist test" (current-error-port)) - (newline (current-error-port)) - ) - ) - -;; ------------ list of symbols into list of strings ----------- +;; ------------ convert string into mosfet ----------------------- ; Contract: -; symbollist->stringlist : list-of-symbols -> list-of-strings +; stringlist->mosfet : list-of-strings -> mosfet ; Purpose: -; convert list of symbols (e.g. ports) into list of strings +; convert list of strings into mosfet vector ; Example: -; (symbollist->stringlist '(C B A) => ("C" "B" "A") +; (stringlist->mosfet ("nmos" "A" "Y" "GND" "GND" "1" "1" "-1" "0" "0")) => '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 0 0) ; Definition: - (define symbollist->stringlist - (lambda (symbol-list) - (map symbol->string symbol-list) + (define stringlist->mosfet + (lambda (stringlist) + (let ((mosfet (generate-mosfet))) + (mosfet-type! mosfet (string-downcase (list-ref stringlist |circuit-type#|))) + (mosfet-gate! mosfet (string-upcase (list-ref stringlist |gate-node#|))) + (mosfet-drain! mosfet (string-upcase (list-ref stringlist |drain-node#|))) + (mosfet-source! mosfet (string-upcase (list-ref stringlist |source-node#|))) + (mosfet-bulk! mosfet (string-upcase (list-ref stringlist |bulk-node#|))) + (mosfet-stacked! mosfet (string->number (list-ref stringlist |stacked#|))) + (mosfet-xaxis! mosfet (string->number (list-ref stringlist |xaxis-point#|))) + (mosfet-yaxis! mosfet (string->number (list-ref stringlist |yaxis-point#|))) + (mosfet-size! mosfet (string-downcase (list-ref stringlist |size#|))) ; !! use strings + mosfet + ) ) ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (symbollist->stringlist '(C2 B1 A0)) (list "C2" "B1" "A0")) + (if (equal? (stringlist->mosfet '("nmos" "A" "Y" "GND" "GND" "1" "1" "-1" "0")) '#("nmos" "A" "Y" "GND" "GND" 1 1 -1 "0")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) - (display " symbollist->stringlist test" (current-error-port)) + (display " stringlist->mosfet test" (current-error-port)) (newline (current-error-port)) ) ) diff --git a/Tools/popcorn/popcorn-verilog.scm b/Tools/popcorn/popcorn-verilog.scm index 7f991675..07dfc8ab 100644 --- a/Tools/popcorn/popcorn-verilog.scm +++ b/Tools/popcorn/popcorn-verilog.scm @@ -52,14 +52,14 @@ ; popcorn libs also (popcorn-lib) (popcorn-cell)) - (export export-verilog-switch - export-verilog-bench) + (export verilog:export-switch + verilog:export-bench) (begin ;; ------------ build-in self test ------------------------------- ; use this switch during development only - (define build-in-self-test #t) + (define build-in-self-test? #f) ;; ------------------------------------------------------------------- ;; AUXILARY FUNCTIONS @@ -74,7 +74,7 @@ ; transfer a list of input symbols into list of strings ; Example: -; (inputlist->stimulilist '(C B A)) => ("stimuli[2]" "stimuli[1]" "stimuli[0]") +; (inputlist->stimulilist '("C" "B" "A")) => ("stimuli[2]" "stimuli[1]" "stimuli[0]") ; Definition: (define inputlist->stimulilist @@ -89,9 +89,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (inputlist->stimulilist '(C B A)) '("stimuli[2]" "stimuli[1]" "stimuli[0]")) + (if (equal? (inputlist->stimulilist '("C" "B" "A")) '("stimuli[2]" "stimuli[1]" "stimuli[0]")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " inputlist->stimulilist test" (current-error-port)) @@ -108,7 +108,7 @@ ; transfer a list of output symbols into list of strings ; Example: -; (outputlist->responselist '(Z Y X)) => ("response[2]" "response[1]" "response[0]") +; (outputlist->responselist '("Z" "Y")) => ("response[1]" "response[0]") ; Definition: (define outputlist->responselist @@ -123,9 +123,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (outputlist->responselist '(Z Y X)) '("response[2]" "response[1]" "response[0]")) + (if (equal? (outputlist->responselist '("Z" "Y")) '("response[1]" "response[0]")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " outputlist->responselist test" (current-error-port)) @@ -142,7 +142,7 @@ ; transfer a list of clock symbols into list of strings ; Example: -; (clocklist->signallist '(Ckl)) => ("clk_tb") +; (clocklist->signallist '("X")) => ("clk_tb") ; Definition: (define clocklist->signallist @@ -155,9 +155,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (clocklist->signallist (list 'Clk)) '("clk_tb")) + (if (equal? (clocklist->signallist (list "X")) '("clk_tb")) (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " clocklist->signallist test" (current-error-port)) @@ -174,7 +174,7 @@ ; transfer lists of ports into well-formed table format ; Example: -; (portlists->tableformat '(Y A)) => ("\\t%b\\t:%b") +; (portlists->tableformat '("Y" "A")) => ("\\t%b\\t:%b") ; Definition: (define portlists->tableformat @@ -183,7 +183,7 @@ ; empty list? [(null? port-list) ""] ; output port? - [(output-space? (car port-list)) (string-append "\\t:\%b" (portlists->tableformat (cdr port-list)))] + [(output-space? (car port-list)) (string-append "\\t:\\t\%b" (portlists->tableformat (cdr port-list)))] ; inputs and clock [else (string-append "\\t\%b" (portlists->tableformat (cdr port-list)))] ) @@ -191,9 +191,9 @@ ) ; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test + (if build-in-self-test? (begin - (if (equal? (portlists->tableformat '(A Y)) "\\t%b\\t:%b") + (if (equal? (portlists->tableformat '("A" "Y")) "\\t%b\\t:\\t%b") (display "++ passed" (current-error-port)) (display "-- failed" (current-error-port))) (display " portlists->tableformat test" (current-error-port)) @@ -208,16 +208,16 @@ ;; ------------ export verilog header --------------------------- ; Contract: -; export-verilog-header : cell purspose-string-> -- +; verilog:export-header : cell purspose-string-> -- ; Purpose: ; generate Verilog Header on STDOUT ; Example: -; (export-verilog-header INV-cell "Verilog Model") => -- +; (verilog:export-header INV-cell "Verilog Model") => -- ; Definition: - (define export-verilog-header + (define verilog:export-header (lambda (cell purpose-string) (let ((at-port current-output-port)) (begin @@ -236,7 +236,7 @@ // Cell: ~a // // Purpose: ~a -// proudly AUTOGENERATED by \"Popcorn\" R7RS Scheme tool +// AUTOGENERATED by \"Popcorn\" R7RS Scheme tool // // ************ IEEE Std 1364-1995 (Verilog '95 HDL) *********** // @@ -271,21 +271,22 @@ ;; ------------ export verilog footer --------------------------- ; Contract: -; export-verilog-footer : -> -- +; verilog:export-footer : -> -- ; Purpose: ; generate Verilog Footer on STDOUT ; Example: -; (export-verilog-footer) => -- +; (verilog:export-footer) => -- ; Definition: - (define export-verilog-footer + (define verilog:export-footer (lambda () (let ((at-port current-output-port)) (begin (format (at-port) -"endmodule +" +endmodule " ) ) ) @@ -293,22 +294,22 @@ ) ;; ------------------------------------------------------------------- -;; WRITING CELL DESCRIPTIONS +;; WRITING VERILOG MODULE ;; ------------------------------------------------------------------- ;; ------------ export verilog module --------------------------- ; Contract: -; export-verilog-module : cell -> -- +; verilog:export-module : cell -> -- ; Purpose: ; generate Verilog '95 module frame on STDOUT ; Example: -; (export-verilog-module INV-cell) => -- +; (verilog:export-module INV-cell) => -- ; Definition: - (define export-verilog-module + (define verilog:export-module (lambda (cell) (let ((at-port current-output-port)) (format (at-port) @@ -317,13 +318,13 @@ output ~a; input ~a; - parameter vdd = 1'b1; - parameter gnd = 1'b0; + parameter VDD = 1'b1; + parameter GND = 1'b0; " (cell-id cell) - (stringlist->csv (symbollist->stringlist (append (cell-outputs cell) (cell-inputs cell) (cell-clocks cell)))) - (stringlist->csv (symbollist->stringlist (cell-outputs cell))) - (stringlist->csv (symbollist->stringlist (cell-inputs cell))) + (stringlist->csv (append (cell-outputs cell) (cell-inputs cell) (cell-clocks cell))) + (stringlist->csv (cell-outputs cell)) + (stringlist->csv (cell-inputs cell)) ) ) ) @@ -332,16 +333,16 @@ ;; ------------ export verilog mosfet --------------------------- ; Contract: -; export-verilog-mosfet : transistor -> -- +; verilog:export-mosfet : transistor -> -- ; Purpose: ; generate Verilog '95 transistor line on STDOUT ; Example: -; (export-verilog-mosfet '#(nmos A Y VDD substrate 1 1 -1)) => -- +; (verilog:export-mosfet '#(nmos A Y GND GND 1 1 -1)) => -- ; Definition: - (define export-verilog-mosfet + (define verilog:export-mosfet (lambda (mosfet) (let ((at-port current-output-port)) (format (at-port) @@ -355,19 +356,19 @@ ;; ------------ export verilog netlist --------------------------- ; Contract: -; export-verilog-netlist : cell -> -- +; verilog:export-netlist : cell -> -- ; Purpose: ; generate Verilog '95 netlist frame on STDOUT ; Example: -; (export-verilog-netlist INV-cell) => -- +; (verilog:export-netlist INV-cell) => -- ; Definition: - (define export-verilog-netlist + (define verilog:export-netlist (lambda (cell) (let ((at-port current-output-port)) - (map (lambda (n) (export-verilog-mosfet n)) (cell-netlist cell)) + (map (lambda (n) (verilog:export-mosfet n)) (cell-netlist cell)) ) ) ) @@ -375,27 +376,27 @@ ;; ------------ export verilog switch --------------------------- ; Contract: -; export-verilog-switch : cell -> -- +; verilog:export-switch : cell -> -- ; Purpose: ; generate Verilog Switch level description on STDOUT ; Example: -; (export-verilog-switch INV-cell) => --" +; (verilog:export-switch INV-cell) => --" ; Definition: - (define export-verilog-switch + (define verilog:export-switch (lambda (cell) (let ((at-port current-output-port)) (begin ; header - (export-verilog-header cell "Verilog Switch Model") + (verilog:export-header cell "Verilog Switch Model") ; module - (export-verilog-module cell) + (verilog:export-module cell) ; stages - (export-verilog-netlist cell) + (verilog:export-netlist cell) ; footer - (export-verilog-footer) + (verilog:export-footer) ) ) ) @@ -408,16 +409,16 @@ ;; ------------ export verilog definitions ----------------------- ; Contract: -; export-verilog-definitions : -> -- +; verilog:export-definitions : -> -- ; Purpose: ; generate Verilog work bench definitions on STDOUT ; Example: -; (export-verilog-definitions INV-cell) => -- +; (verilog:export-definitions INV-cell) => -- ; Definition: - (define export-verilog-definitions + (define verilog:export-definitions (lambda (cell) (let ((at-port current-output-port)) (begin @@ -461,16 +462,16 @@ module ~a_bench ( ;; ------------ export verilog globals --------------------------- ; Contract: -; export-verilog-globals : -> -- +; verilog:export-globals : -> -- ; Purpose: ; generate Verilog global signal definitions on STDOUT ; Example: -; (export-verilog-globals) => -- +; (verilog:export-globals) => -- ; Definition: - (define export-verilog-globals + (define verilog:export-globals (lambda () (let ((at-port current-output-port)) (begin @@ -505,16 +506,16 @@ end ;; ------------ export verilog dut ------------------------------- ; Contract: -; export-verilog-dut : -> -- +; verilog:export-dut : -> -- ; Purpose: ; generate Verilog device-under-test definitions on STDOUT ; Example: -; (export-verilog-dut INV-cell) => -- +; (verilog:export-dut INV-cell) => -- ; Definition: - (define export-verilog-dut + (define verilog:export-dut (lambda (cell) (let ((input-width (length (cell-inputs cell))) (output-width (length (cell-outputs cell))) @@ -542,16 +543,16 @@ end ;; ------------ export verilog stimulus --------------------------- ; Contract: -; export-verilog-stimulus : -> -- +; verilog:export-stimulus : -> -- ; Purpose ; generate Verilog stimulus functionality on STDOUT ; Example: -; (export-verilog-stimulus INV-cell) => -- +; (verilog:export-stimulus INV-cell) => -- ; Definition: - (define export-verilog-stimulus + (define verilog:export-stimulus (lambda (cell) (let ((at-port current-output-port)) (begin @@ -585,7 +586,7 @@ initial begin t_initialize; - $display(\".table\"); + $display(\"..table\"); for (i=0; i<2**INWIDTH; i=i+1) begin @@ -593,7 +594,7 @@ begin t_step(1); end - $display(\".endtable\"); + $display(\"..endtable\"); $finish; end @@ -616,31 +617,31 @@ end ;; ------------ export verilog work bench ----------------------- ; Contract: -; export-verilog-bench : cell -> -- +; verilog:export-bench : cell -> -- ; Purpose: ; generate Verilog Stimulus (kind of work bench) description on STDOUT ; Example: -; (export-verilog-bench INV-cell) => --" +; (verilog:export-bench INV-cell) => --" ; Definition: - (define export-verilog-bench + (define verilog:export-bench (lambda (cell) (let ((at-port current-output-port)) (begin ; header - (export-verilog-header cell "Verilog Stimulus Work Bench") + (verilog:export-header cell "Verilog Stimulus Work Bench") ; definions - (export-verilog-definitions cell) + (verilog:export-definitions cell) ; globals - (export-verilog-globals) + (verilog:export-globals) ; device under test - (export-verilog-dut cell) + (verilog:export-dut cell) ; stimulus - (export-verilog-stimulus cell) + (verilog:export-stimulus cell) ; footer - (export-verilog-footer) + (verilog:export-footer) ) ) ) diff --git a/Tools/popcorn/popcorn.scm b/Tools/popcorn/popcorn.scm index c96b8904..f671b4ea 100644 --- a/Tools/popcorn/popcorn.scm +++ b/Tools/popcorn/popcorn.scm @@ -68,7 +68,7 @@ (define +version+ (lambda (eigen-name at-port) (format (at-port) -"~a (\"Popcorn\") - Version 2019-04-12 +"~a (\"Popcorn\") - Version 2019-08-13 This source is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -89,40 +89,7 @@ Copyright (c) 2019 by chipforge - " ;; ------------ build-in self test ------------------------------- ; use this switch during development only - (define build-in-self-test #t) - -;; ------------------------------------------------------------------- -;; DESCRIPTION -;; ------------------------------------------------------------------- - -;; In principle every combinatorial cell (in CMOS technology) contains -;; two functional complementary networks. The pull-up network - build -;; with pmos transistors - as well as the pull-down network - build -;; with nmos transistors. - -;; so every netlist becomes, well, a list of transistors - -;; ------------ Example : INV ----------------------------------- - -;; ^ Vdd -;; | -;; | --+ -;; A --o| | pmos -;; | --+ -;; | -;; | -;; *---- Y -;; | -;; | -;; | --+ -;; A ---| | nmos -;; | --+ -;; | -;; _|_ Gnd - - (define INV '(#(pmos A Y VDD VDD 1 1 1) - #(nmos A Y GND GND 1 1 -1)) - ) + (define build-in-self-test? #t) ;; ------------------------------------------------------------------- ;; GLOBAL OPTIONS @@ -135,6 +102,7 @@ Copyright (c) 2019 by chipforge - " (format (at-port) "Usage: ~a - Generate new combinatorial cells -b number set threshold value for output buffer + -c cellname cell name for generated output -e format specify cell export format -h | --help print help screen and exit -H number set cell high in metal tracks @@ -154,6 +122,12 @@ Copyright (c) 2019 by chipforge - " ; -b number (define buffer-limit 4) +; -c cellname + (define cell-name "CELL") + +; -d string + (define cell-descr ".AUTOGENERATED by \'Popcorn\' R7RS Scheme tool") + ; -e format (define export-format 'cell) @@ -164,7 +138,7 @@ Copyright (c) 2019 by chipforge - " (define stacked-limit 4) ; -m method - (define extension-method 'none) + (define expansion-method 'none) ; -T file (define technology-file "scmos.tech") @@ -197,7 +171,25 @@ Copyright (c) 2019 by chipforge - " [(equal? (car arguments) "-b") (let ([value (car (cdr arguments))] [tail (cddr arguments)]) - (set! buffer-limit value) ; !! value check missing + (set! buffer-limit (string->number value)) ; !! value check missing + (set-parameters-with-args! eigen-name tail) + ) + ] + + ; -c cellname + [(equal? (car arguments) "-c") + (let ([value (car (cdr arguments))] + [tail (cddr arguments)]) + (set! cell-name value) + (set-parameters-with-args! eigen-name tail) + ) + ] + + ; -D string + [(equal? (car arguments) "-D") + (let ([value (car (cdr arguments))] + [tail (cddr arguments)]) + (set! cell-descr value) (set-parameters-with-args! eigen-name tail) ) ] @@ -230,7 +222,7 @@ Copyright (c) 2019 by chipforge - " [(equal? (car arguments) "-H") (let ([value (car (cdr arguments))] [tail (cddr arguments)]) - (set! track-high value) ; !! value check missing)] + (set! track-high (string->number value)) ; !! value check missing)] (set-parameters-with-args! eigen-name tail) ) ] @@ -239,7 +231,7 @@ Copyright (c) 2019 by chipforge - " [(equal? (car arguments) "-l") (let ([value (car (cdr arguments))] [tail (cddr arguments)]) - (set! stacked-limit value) ; !! value check missing)] + (set! stacked-limit (string->number value)) ; !! value check missing)] (set-parameters-with-args! eigen-name tail) ) ] @@ -248,7 +240,7 @@ Copyright (c) 2019 by chipforge - " [(equal? (car arguments) "-m") (let ([value (car (cdr arguments))] [tail (cddr arguments)]) - (set! extension-method value) ; !! value check missing)] + (set! expansion-method (string->symbol value)) (set-parameters-with-args! eigen-name tail) ) ] @@ -297,6 +289,18 @@ Copyright (c) 2019 by chipforge - " buffer-limit) (newline (at-port)) + ; -c cellname + (format (at-port) +"Cell Name: ~a" + cell-name) + (newline (at-port)) + + ; -D string + (format (at-port) +"Cell Description: ~a" + cell-descr) + (newline (at-port)) + ; -e format (format (at-port) "Export Format: ~a" @@ -317,8 +321,8 @@ Copyright (c) 2019 by chipforge - " ; -m method (format (at-port) -"Extension Method: ~a" - extension-method) +"Expansion Method: ~a" + expansion-method) (newline (at-port)) ; -T file @@ -342,45 +346,6 @@ Copyright (c) 2019 by chipforge - " ) ) -;; ------------------------------------------------------------------- -;; FUNCTIONS -;; ------------------------------------------------------------------- - -;; ------------ get highest free nmos transistor --------------- - -; Contract: -; get-highest-nmos : netlist -> transistor - -; Purpose: -; find highest nmos transistor, which can be extended - -; Example: -; (get-highest-nmos INV) => #('nmos 'A 'X 'GND 'GND 1 1 -1) - -; Definition: - (define get-highest-nmos - (lambda (netlist) - (cond - ; emtpy list? - [(null? netlist) netlist] - - ;; !! - [else (get-highest-nmos (cdr netlist))] - ) - ) - ) - -; Test: !! replace code by a portable SRFI test environemt - (if build-in-self-test - (begin - (if (equal? (get-highest-nmos INV) '(#(nmos A Y GND GND 1 1 -1))) - (display "++ passed" (current-error-port)) - (display "-- failed" (current-error-port))) - (display " get-node-mosfets test" (current-error-port)) - (newline (current-error-port)) - ) - ) - ;; ------------------------------------------------------------------- ;; MAIN ;; ------------------------------------------------------------------- @@ -399,7 +364,7 @@ Copyright (c) 2019 by chipforge - " ; generate verilog switch-level model [(equal? export-format 'verilog-slm) (begin - (export-verilog-switch (read-cell-file cell-file)) + (verilog:export-switch (cell:read-file cell-file)) 0 ; exit value ) ] @@ -407,35 +372,51 @@ Copyright (c) 2019 by chipforge - " ; generate verilog stimulus work bench [(equal? export-format 'verilog-bench) (begin - (export-verilog-bench (read-cell-file cell-file)) + (verilog:export-bench (cell:read-file cell-file)) 0 ; exit value ) ] -; ; expand cell instead -; [(equal? export-format 'cell) -; (cond -; ; nand-wise -; [(equal? extension-method 'nand) -; (begin -; 0 ; exit value -; ) -; ] -; ; nor-wise -; [(equal? extension-method 'nor) -; (begin -; 0 ; exit value -; ) -; ] -; ; selection failed, unknown extension-method -; [else -; (begin -; (+usage+ eigen-name current-error-port) -; 2 ; exit value - wrong usage -; ) -; ] -; ) -; ] + ; expand cell instead + [(equal? export-format 'cell) + (cond + ; nand-wise + [(equal? expansion-method 'nand) + (begin + (cell:write-file (cell:expand-nand (cell:read-file cell-file) stacked-limit buffer-limit cell-name cell-descr)) + 0 ; exit value + ) + ] + ; nor-wise + [(equal? expansion-method 'nor) + (begin + (cell:write-file (cell:expand-nor (cell:read-file cell-file) stacked-limit buffer-limit cell-name cell-descr)) + 0 ; exit value + ) + ] + ; aoi-wise + [(equal? expansion-method 'aoi) + (begin + (cell:write-file (cell:expand-aoi (cell:read-file cell-file) stacked-limit buffer-limit cell-name cell-descr)) + 0 ; exit value + ) + ] + ; oai-wise + [(equal? expansion-method 'oai) + (begin + (cell:write-file (cell:expand-oai (cell:read-file cell-file) stacked-limit buffer-limit cell-name cell-descr)) + 0 ; exit value + ) + ] + ; selection failed, unknown expansion-method + [else + (begin + (+usage+ eigen-name current-error-port) + 2 ; exit value - wrong usage + ) + ] + ) + ] ; selection failed, unknown export-format value [else diff --git a/Tools/python/concat4gds.py b/Tools/python/concat4gds.py new file mode 100644 index 00000000..f7b31e6b --- /dev/null +++ b/Tools/python/concat4gds.py @@ -0,0 +1,10 @@ +#!/usr/bin/python3 + +import gdspy +import sys + +for a in sys.argv: + gdspy.current_library.read_gds(a) + +gdspy.write_gds("library.gds") + diff --git a/Tools/python/gen_CharLib.py b/Tools/python/gen_CharLib.py new file mode 100644 index 00000000..838f6c61 --- /dev/null +++ b/Tools/python/gen_CharLib.py @@ -0,0 +1,231 @@ +#!/bin/python3 +import glob +import re + +def main(): + cmd_file = 'CharLib.cmd' + gen_lib_common("GF180MCUC", cmd_file) + gen_char_cond("5", cmd_file) + for cell in glob.glob('*.cell'): + sp= re.sub('\.cell$', '.sp', cell) + cellname = re.sub('\.cell$','',cell) + inputs=['A','B'] + outputs=['Y'] + functions=[] + cellfh = open(cell, 'r') + for line in cellfh.readlines(): + line=line.rstrip() + if '.inputs ' in line: + inputs=line[8:].split(' ') + if '.outputs ' in line: + outputs=line[9:].split(' ') + cellfh.close() + verilogfh = open( re.sub('\.cell$', '.truthtable.v', cell)) + for line in verilogfh.readline().split(':')[1:]: + functions.append(re.sub(' ','',re.sub('\|\|','|',re.sub('\&\&','&',re.sub('function','',line))))) + verilogfh.close() + gen_comb("GF180MCUC", cmd_file, cellname, cellname, inputs, outputs, functions, '1', sp) +# gen_comb("OSU350", cmd_file, "NAND2X1", "NAND2", ['A','B'], ['Y'], ['Y=!(A&B)'], '1', 'NETLIST/NAND2X1.spi') +# gen_comb("OSU350", cmd_file, "NAND3X1", "NAND3", ['A','B','C'], ['Y'], ['Y=!(A&B&C)'], '1', 'NETLIST/NAND3X1.spi') +# gen_comb("OSU350", cmd_file, "NAND4X1", "NAND4", ['A','B','C','D'], ['Y'], ['Y=!(A&B&C&D)'], '1', 'NETLIST/NAND4X1.spi') +# gen_comb("OSU350", cmd_file, "NOR2X1", "NOR2", ['A','B'], ['Y'], ['Y=!(A|B)'], '1', 'NETLIST/NOR2X1.spi') +# gen_comb("OSU350", cmd_file, "NOR3X1", "NOR3", ['A','B','C'], ['Y'], ['Y=!(A|B|C)'], '1', 'NETLIST/NOR3X1.spi') +# gen_comb("OSU350", cmd_file, "NOR4X1", "NOR4", ['A','B','C','D'], ['Y'], ['Y=!(A|B|C|D)'], '1', 'NETLIST/NOR4X1.spi') +# gen_comb("OSU350", cmd_file, "AND2X1", "AND2", ['A','B'], ['Y'], ['Y=(A&B)'], '1', 'NETLIST/AND2X1.spi') +# gen_comb("OSU350", cmd_file, "AND3X1", "AND3", ['A','B','C'], ['Y'], ['Y=(A&B&C)'], '1', 'NETLIST/AND3X1.spi') +# gen_comb("OSU350", cmd_file, "AND4X1", "AND4", ['A','B','C','D'], ['Y'], ['Y=(A&B&C&D)'], '1', 'NETLIST/AND4X1.spi') +# gen_comb("OSU350", cmd_file, "OR2X1", "OR2", ['A','B'], ['Y'], ['Y=(A|B)'], '1', 'NETLIST/OR2X1.spi') +# gen_comb("OSU350", cmd_file, "OR3X1", "OR3", ['A','B','C'], ['Y'], ['Y=(A|B|C)'], '1', 'NETLIST/OR3X1.spi') +# gen_comb("OSU350", cmd_file, "OR4X1", "OR4", ['A','B','C','D'], ['Y'], ['Y=(A|B|C|D)'], '1', 'NETLIST/OR4X1.spi') +# gen_comb("OSU350", cmd_file, "AOI21X1", "AOI21", ['A','B','C'], ['Y'], ['Y=!(C|(A&B))'], '1', 'NETLIST/AOI21X1.spi') +# gen_comb("OSU350", cmd_file, "AOI22X1", "AOI22", ['A','B','C','D'], ['Y'], ['Y=!((C&D)|(A&B))'],'1', 'NETLIST/AOI22X1.spi') +# gen_comb("OSU350", cmd_file, "OAI21X1", "OAI21", ['A1','A2','B'], ['YB'], ['YB=!(B&(A1|A2))'], '1', 'NETLIST/OAI21X1.spi') +# gen_comb("OSU350", cmd_file, "OAI22X1", "OAI22", ['A1','A2','B1','B2'], ['YB'], ['YB=!((B1|B2)&(A1|A2))'],'1', 'NETLIST/OAI22X1.spi') +# gen_comb("OSU350", cmd_file, "AO21X1", "AO21", ['A1','A2','B'], ['Y'], ['Y=(B|(A1&A2))'], '1', 'NETLIST/AO21X1.spi') +# gen_comb("OSU350", cmd_file, "AO22X1", "AO22", ['A1','A2','B1','B2'], ['Y'], ['Y=((B1&B2)|(A1&A2))'], '1', 'NETLIST/AO22X1.spi') +# gen_comb("OSU350", cmd_file, "OA21X1", "OA21", ['A1','A2','B'], ['Y'], ['Y=(B&(A1|A2))'], '1', 'NETLIST/OA21X1.spi') +# gen_comb("OSU350", cmd_file, "OA22X1", "OA22", ['A1','A2','B1','B2'], ['Y'], ['Y=((B1|B2)&(A1|A2))'], '1', 'NETLIST/OA22X1.spi') +# gen_comb("OSU350", cmd_file, "XOR2X1", "XOR2", ['A','B'], ['Y'], ['Y=((A&!B)&(!A&B))'], '1', 'NETLIST/XOR2X1.spi') +# gen_comb("OSU350", cmd_file, "XNOR2X1", "XNOR2", ['A','B'], ['Y'], ['Y=((!A&!B)&(A&B))'], '1', 'NETLIST/XNOR2X1.spi') +# gen_seq ("OSU350", cmd_file, "DFFX1", "DFF_PCPU", ['DATA','CLK'], ['Q'], ['Q','QN'], ['Q=IQ','QN=IQN'], '1', 'NETLIST/DFFX1.spi') +# gen_seq ("OSU350", cmd_file, "DFFSR", "DFF_PCPU_NRNS", ['DATA','CLK','NSET','NRST'], ['Q'], ['IQ','IQN'], ['Q=IQ','QN=IQN'], '1', 'NETLIST/DFFARASX1.spi') + exit_CharLib(cmd_file) + +def gen_lib_common(name, cmd_file): + with open(cmd_file,'w') as f: + outlines = [] + outlines.append("# common settings for library\n") + outlines.append("set_lib_name "+str(name)+"\n") + outlines.append("set_dotlib_name "+str(name)+".lib\n") + outlines.append("set_verilog_name "+str(name)+".v\n") + outlines.append("set_cell_name_suffix "+str(name)+"_\n") + outlines.append("set_cell_name_prefix _V1\n") + outlines.append("set_voltage_unit V\n") + outlines.append("set_capacitance_unit pF\n") + outlines.append("set_resistance_unit Ohm\n") + outlines.append("set_current_unit mA\n") + outlines.append("set_leakage_power_unit pW \n") + outlines.append("set_energy_unit fJ \n") + outlines.append("set_time_unit ns\n") + outlines.append("set_vdd_name VDD\n") + outlines.append("set_vss_name VSS\n") + outlines.append("set_pwell_name VPW\n") + outlines.append("set_nwell_name VNW\n") + f.writelines(outlines) + f.close() + +def gen_char_cond(vdd, cmd_file): + with open(cmd_file,'a') as f: + outlines = [] + outlines.append("# characterization conditions \n") + outlines.append("set_process typ\n") + outlines.append("set_temperature 25\n") + outlines.append("set_vdd_voltage "+str(vdd)+"\n") + outlines.append("set_vss_voltage 0\n") + outlines.append("set_pwell_voltage 0\n") + outlines.append("set_nwell_voltage "+str(vdd)+"\n") + outlines.append("set_logic_threshold_high 0.8\n") + outlines.append("set_logic_threshold_low 0.2\n") + outlines.append("set_logic_high_to_low_threshold 0.5\n") + outlines.append("set_logic_low_to_high_threshold 0.5\n") + outlines.append("set_work_dir work\n") + outlines.append("set_simulator /usr/bin/ngspice \n") +# outlines.append("set_simulator /cad/synopsys/hspice/P-2019.06-1/hspice/bin/hspice -CC -port 2990wx:25000 -i \n") + outlines.append("set_run_sim true\n") +# outlines.append("set_run_sim false\n") + outlines.append("set_mt_sim true\n") + outlines.append("set_supress_message false\n") + outlines.append("set_supress_sim_message false\n") + outlines.append("set_supress_debug_message true\n") + outlines.append("set_energy_meas_low_threshold 0.01\n") + outlines.append("set_energy_meas_high_threshold 0.99\n") + outlines.append("set_energy_meas_time_extent 10\n") + outlines.append("set_operating_conditions PVT_3P5V_25C\n") + outlines.append("# initialize workspace\n") + outlines.append("initialize\n") + f.writelines(outlines) + f.close() + +def gen_comb(target, cmd_file, cell_name, logic, inports, outports, funcs, area, netlist): + with open(cmd_file,'a') as f: + outlines = [] + outlines.append("\n") + outlines.append("## add circuit\n") + line_add_cell = 'add_cell -n '+str(cell_name)+' -l '+str(logic)+' -i ' + for w1 in inports: + line_add_cell += str(w1)+' ' + line_add_cell += '-o ' + for w1 in outports: + line_add_cell += str(w1)+' ' + line_add_cell += '-f ' + for w1 in funcs: + line_add_cell += str(w1)+' ' + line_add_cell += '\n' + outlines.append(line_add_cell) +# outlines.append("add_slope {0.1 0.4 1.6 6.4} \n") +# outlines.append("add_load {0.01 0.04 0.16 0.64} \n") + if(target == "ROHM180"): + outlines.append("add_slope {0.1 0.7 4.9} \n") + outlines.append("add_load {0.01 0.1 1.0} \n") + #outlines.append("add_slope {0.1 } \n") + #outlines.append("add_load {0.01 } \n") + elif(target == "OSU350"): + #outlines.append("add_slope {0.1 0.7 4.9} \n") + #outlines.append("add_load {0.01 0.07 0.49} \n") + outlines.append("add_slope {0.1 4.9} \n") + outlines.append("add_load {0.01 0.49} \n") + elif(target == "GF180MCUC"): + #outlines.append("add_slope {0.1 0.7 4.9} \n") + #outlines.append("add_load {0.01 0.07 0.49} \n") + outlines.append("add_slope {0.1 4.9} \n") + outlines.append("add_load {0.01 0.49} \n") + else: + print("target is not registered!\n") + line_add_area = 'add_area '+str(area)+'\n' + outlines.append(line_add_area) + line_add_netlist = 'add_netlist '+str(netlist)+'\n' + outlines.append(line_add_netlist) + if(target == "ROHM180"): + outlines.append("add_model rohmlib/model_rohm180.sp\n") + elif(target == "OSU350"): + outlines.append("add_model NETLIST/model.sp\n") + elif(target == "GF180MCUC"): + outlines.append("add_model NETLIST/model.sp\n") + else: + print("target is not registered!\n") + outlines.append("add_simulation_timestep auto\n") + outlines.append("characterize\n") + outlines.append("export\n") + outlines.append("\n") + f.writelines(outlines) + f.close() + +def gen_seq(target, cmd_file, cell_name, logic, inports, outports, storage, funcs, area, netlist): + with open(cmd_file,'a') as f: + outlines = [] + outlines.append("## add circuit\n") + line_add_flop = 'add_flop -n '+str(cell_name)+' -l '+str(logic) + if((logic == 'DFF_PCPU_NRNS')or(logic == 'DFF_PCNU_NRNS')or(logic == 'DFF_NCPU_NRNS')or(logic == 'DFF_NCNU_NRNS')): + line_add_flop += ' -i '+str(inports[0])+' -c '+str(inports[1])+' -s '+str(inports[2])+' -r '+str(inports[3]) + elif((logic == 'DFF_PCPU_NR')or(logic == 'DFF_PCNU_NR')or(logic == 'DFF_NCPU_NR')or(logic == 'DFF_NCNU_NR')): + line_add_flop += ' -i '+str(inports[0])+' -c '+str(inports[1])+' -r '+str(inports[2]) + elif((logic == 'DFF_PCPU_NS')or(logic == 'DFF_PCNU_NS')or(logic == 'DFF_NCPU_NS')or(logic == 'DFF_NCNU_NS')): + line_add_flop += ' -i '+str(inports[0])+' -c '+str(inports[1])+' -s '+str(inports[2]) + elif((logic == 'DFF_PCPU')or(logic == 'DFF_PCNU')or(logic == 'DFF_NCPU')or(logic == 'DFF_NCNU')): + line_add_flop += ' -i '+str(inports[0])+' -c '+str(inports[1]) + else: + print("function not matched!\n") + line_add_flop += ' -o ' + for w1 in outports: + line_add_flop += str(w1)+' ' + line_add_flop += '-q ' + for w1 in storage: + line_add_flop += str(w1)+' ' + line_add_flop += '-f ' + for w1 in funcs: + line_add_flop += str(w1)+' ' + line_add_flop += '\n' + outlines.append(line_add_flop) + if(target == "ROHM180"): + outlines.append("add_slope {0.1 0.7 4.9} \n") + outlines.append("add_load {0.01 0.1 1.0} \n") + #outlines.append("add_slope {0.1 } \n") + #outlines.append("add_load {0.01 } \n") + elif(target == "OSU350"): + #outlines.append("add_slope {0.1 0.7 4.9} \n") + #outlines.append("add_load {0.01 0.07 0.49} \n") + outlines.append("add_slope {0.1 4.9} \n") + outlines.append("add_load {0.01 0.49} \n") + else: + print("target is not registered!\n") + outlines.append("add_clock_slope auto \n") + line_add_area = 'add_area '+str(area)+'\n' + outlines.append(line_add_area) + line_add_netlist = 'add_netlist '+str(netlist)+'\n' + outlines.append(line_add_netlist) + if(target == "ROHM180"): + outlines.append("add_model rohmlib/model_rohm180.sp\n") + elif(target == "OSU350"): + outlines.append("add_model NETLIST/model.sp\n") + else: + print("target is not registered!\n") + outlines.append("add_simulation_timestep auto\n") + outlines.append("add_simulation_setup_auto\n") + outlines.append("add_simulation_hold_auto\n") + #outlines.append("add_simulation_setup 0.1\n") + #outlines.append("add_simulation_hold 0.1\n") + outlines.append("characterize\n") + outlines.append("export\n") + f.writelines(outlines) + f.close() + +def exit_CharLib(cmd_file): + with open(cmd_file,'a') as f: + outlines = [] + outlines.append("exit\n") + f.writelines(outlines) + f.close() + +if __name__ == '__main__': + main() + diff --git a/Tools/reporter.sh b/Tools/reporter.sh new file mode 100755 index 00000000..8a33e412 --- /dev/null +++ b/Tools/reporter.sh @@ -0,0 +1,11 @@ +#!/bin/bash +echo This script generates a build report every 10 seconds, so that you can monitor the progress of the standard cell generation. +rm -f .done +perl ../Tools/perl/buildreport.pl +firefox buildreport.html & +while [ ! -f .done ] ; +do + perl ../Tools/perl/buildreport.pl + sleep 10 +done + diff --git a/Tools/tcl/_schematic b/Tools/tcl/_schematic index 27834f9e..51b3b57a 100755 --- a/Tools/tcl/_schematic +++ b/Tools/tcl/_schematic @@ -92,17 +92,19 @@ proc length? {path from to netlist} { set length 0 set result 0 + verb "length from $from to $to is $length for $path" + foreach mosfet $netlist { # check mosfet type - if {[string compare -nocase [lindex $mosfet 2] $from] == 0} { - if {[string compare -nocase [lindex $mosfet 1] $to] == 0} { + if {[string compare -nocase [lindex $mosfet 3] $from] == 0} { + if {[string compare -nocase [lindex $mosfet 2] $to] == 0} { if {$length == 0} { # 1st founding set length 1 } } else { # while current $to does not match target, go deeper and check result - set result [expr [length? [list $path $mosfet] [lindex $mosfet 1] $to $netlist] +1] + set result [expr [length? [list $path $mosfet] [lindex $mosfet 2] $to $netlist] +1] if {$result > $length} { # means, last recursive call gots a longer path set length $result @@ -125,7 +127,7 @@ proc tpmos {netlist} { # collect pmos transistors set net {} foreach mosfet $netlist { - if {[string compare -nocase [lindex $mosfet 3] "pmos"] == 0} { + if {[string compare -nocase [lindex $mosfet 0] "pmos"] == 0} { set net [lappend net $mosfet] } } @@ -149,7 +151,7 @@ proc tnmos {netlist} { # collect nmos transistor set net {} foreach mosfet $netlist { - if {[string compare -nocase [lindex $mosfet 3] "nmos"] == 0} { + if {[string compare -nocase [lindex $mosfet 0] "nmos"] == 0} { set net [lappend net $mosfet] } } @@ -188,8 +190,8 @@ proc eval_mosfets {node ttype netlist} { # collect 'ttype' transistor set unsorted {} foreach mosfet $netlist { - if {[string compare -nocase [lindex $mosfet 3] $ttype] == 0} { - if {[string compare -nocase [lindex $mosfet 1] $node] == 0} { + if {[string compare -nocase [lindex $mosfet 0] $ttype] == 0} { + if {[string compare -nocase [lindex $mosfet 2] $node] == 0} { set unsorted [lappend unsorted $mosfet] } } @@ -213,7 +215,7 @@ proc eval_nodes {netlist} { set nodes {} foreach mosfet $netlist { - set nodes [lappend nodes [lindex $mosfet 2]] + set nodes [lappend nodes [lindex $mosfet 3]] } # verbose message @@ -231,7 +233,7 @@ proc outputs? {netlist} { # collect nodes on drain set unsorted {} foreach mosfet $netlist { - set drain [lindex $mosfet 1] + set drain [lindex $mosfet 2] if {![string is entier $drain]} { lappend unsorted $drain } @@ -433,8 +435,8 @@ puts $f " \\wire\{$xstart\}\{$ystart\}\{$xend\}\{$yend\}" proc stages {netlist} { foreach mosfet $netlist { # If there is a transistor with Y as input we definitely have at least 2 stages - verb "Searching for Y: [lindex $mosfet 0]" - if {[string compare -nocase [lindex $mosfet 0] "Y"] == 0} { + verb "Searching for Y: [lindex $mosfet 1]" + if {[string compare -nocase [lindex $mosfet 1] "Y"] == 0} { return 2 } } @@ -564,7 +566,7 @@ if {[file exist $option_cell]} { for {set i 0} {$i < $length} {incr i} { set mosfet [lindex $todo $i] verb "pulldown nmos i:$i xgrid:$xgrid xjunc:$xjunc yjunc:$yjunc mosfet:$mosfet" - puts_nmos $f [lindex $mosfet 0] [string cat "N" [lindex $mosfet 0]] [expr ($i * $xgrid) + $xjunc ] $yjunc + puts_nmos $f [lindex $mosfet 1] [string cat "N" [lindex $mosfet 1]] [expr ($i * $xgrid) + $xjunc ] $yjunc if {$i >= 1} { # TODO: Here we are potentially drawing too many and connecting nets that are not supposed to be connected. We should check for that puts_wire $f [expr ($i * $xgrid) - $xgrid + $xjunc ] $yjunc [expr ($i * $xgrid) + $xjunc ] $yjunc @@ -618,7 +620,7 @@ if {[file exist $option_cell]} { # layout known mosfet for 'node' for {set i 0} {$i < $length} {incr i} { set mosfet [lindex $todo $i] - puts_pmos $f [lindex $mosfet 0] [string cat "P" [lindex $mosfet 0]] [expr ($i * $xgrid) + $xjunc ] $yjunc + puts_pmos $f [lindex $mosfet 1] [string cat "P" [lindex $mosfet 1]] [expr ($i * $xgrid) + $xjunc ] $yjunc if {$i >= 1} { # TODO: Here we are potentially drawing too many and connecting nets that are not supposed to be connected. We should check for that puts_wire $f [expr ($i * $xgrid) - $xgrid + $xjunc ] $yjunc [expr ($i * $xgrid) + $xjunc ] $yjunc diff --git a/Tools/tcl/_switch b/Tools/tcl/_switch index f9a297c7..b4845e54 100755 --- a/Tools/tcl/_switch +++ b/Tools/tcl/_switch @@ -88,7 +88,7 @@ proc inputs? {netlist} { # collect all inputs from all networks set unsorted {} foreach mosfet $netlist { - lappend unsorted [lindex $mosfet 0] + lappend unsorted [lindex $mosfet 1] } # sort inputs @@ -114,7 +114,7 @@ proc outputs? {netlist} { # collect nodes on drain set unsorted {} foreach mosfet $netlist { - set drain [lindex $mosfet 1] + set drain [lindex $mosfet 2] if {![string is entier $drain]} { lappend unsorted $drain } @@ -142,7 +142,7 @@ proc nodes? {netlist} { set nodes {} foreach mosfet $netlist { - set nodes [lappend nodes [lindex $mosfet 2]] + set nodes [lappend nodes [lindex $mosfet 3]] } # verbose message @@ -255,29 +255,29 @@ puts $f "" puts $f "// type name (drain source gate);" foreach mosfet $netlist { - set ttype [lindex $mosfet 3] + set ttype [lindex $mosfet 0] puts -nonewline $f "$ttype " ; # type if {[string compare -nocase $ttype "pmos"] == 0} { -puts -nonewline $f "MP[lindex $mosfet 0] " ; # name +puts -nonewline $f "MP[lindex $mosfet 1] " ; # name } elseif {[string compare -nocase $ttype "nmos"] == 0} { -puts -nonewline $f "MN[lindex $mosfet 0] " ; # name +puts -nonewline $f "MN[lindex $mosfet 1] " ; # name } - set drain [lindex $mosfet 1] + set drain [lindex $mosfet 2] if {[string is entier $drain]} { puts -nonewline $f "\(n$drain, " } else { puts -nonewline $f "\($drain, " } - set src [lindex $mosfet 2] + set src [lindex $mosfet 3] if {[string is entier $src]} { puts -nonewline $f "n$src, " } else { puts -nonewline $f "$src, " } - set gate [lindex $mosfet 0] + set gate [lindex $mosfet 1] if {[string is entier $gate]} { puts $f "n$gate\);" } else { diff --git a/Tools/tcl/popcorn b/Tools/tcl/popcorn index 6fc8a793..4a379891 100755 --- a/Tools/tcl/popcorn +++ b/Tools/tcl/popcorn @@ -116,11 +116,11 @@ proc export! {path cellid library} { # write out puts $f ".AUTOGENERATED by Popcorn Tcl Script" - set myinputs [join [inputs? $cellid] ","] - puts $f ".INPUT $myinputs" - set myoutputs [join [outputs? $cellid] ","] - puts $f ".OUTPUT $myoutputs" - puts $f ".ORDER \"Gate Drain Source MOSFET\"" + set myinputs [join [lsort [inputs? $cellid]] " "] + puts $f ".inputs $myinputs" + set myoutputs [join [lsort [outputs? $cellid]] " "] + puts $f ".outputs $myoutputs" + puts $f ".ORDER \"MOSFET Gate Drain Source\"" set sorted [lsort -dictionary [dict keys [dict get [dict get $library $cellid] pullup]]] @@ -129,7 +129,7 @@ proc export! {path cellid library} { set drain [dict get [dict get [dict get [dict get $library $cellid] pullup] $mosfet] d] set source [dict get [dict get [dict get [dict get $library $cellid] pullup] $mosfet] s] set type [dict get [dict get [dict get [dict get $library $cellid] pullup] $mosfet] t] - puts $f "$gate $drain $source $type" + puts $f "$type $gate $drain $source" } set sorted [lsort -dictionary [dict keys [dict get [dict get $library $cellid] pulldown]]] @@ -139,7 +139,7 @@ proc export! {path cellid library} { set drain [dict get [dict get [dict get [dict get $library $cellid] pulldown] $mosfet] d] set source [dict get [dict get [dict get [dict get $library $cellid] pulldown] $mosfet] s] set type [dict get [dict get [dict get [dict get $library $cellid] pulldown] $mosfet] t] - puts $f "$gate $drain $source $type" + puts $f "$type $gate $drain $source" } # done @@ -159,22 +159,22 @@ proc import {f} { seek $f 0 start while {[gets $f line] >= 0} { if {[lsearch -glob [split $line] ".*"] == -1} { - if {[lindex $line 3] == "pmos"} { - # pullup network - set mosfet [lindex $line 0] + if {[lindex $line 0] == "pmos"} { + verb "pullup network" + set mosfet [lindex $line 1] dict set netlist pullup $mosfet {} - dict set netlist pullup $mosfet g [lindex $line 0] - dict set netlist pullup $mosfet d [lindex $line 1] - dict set netlist pullup $mosfet s [lindex $line 2] - dict set netlist pullup $mosfet t [lindex $line 3] - } elseif {[lindex $line 3] == "nmos"} { - # pulldown network - set mosfet [lindex $line 0] + dict set netlist pullup $mosfet g [lindex $line 1] + dict set netlist pullup $mosfet d [lindex $line 2] + dict set netlist pullup $mosfet s [lindex $line 3] + dict set netlist pullup $mosfet t [lindex $line 0] + } elseif {[lindex $line 0] == "nmos"} { + verb "pulldown network" + set mosfet [lindex $line 1] dict set netlist pulldown $mosfet {} - dict set netlist pulldown $mosfet g [lindex $line 0] - dict set netlist pulldown $mosfet d [lindex $line 1] - dict set netlist pulldown $mosfet s [lindex $line 2] - dict set netlist pulldown $mosfet t [lindex $line 3] + dict set netlist pulldown $mosfet g [lindex $line 1] + dict set netlist pulldown $mosfet d [lindex $line 2] + dict set netlist pulldown $mosfet s [lindex $line 3] + dict set netlist pulldown $mosfet t [lindex $line 0] } } } @@ -267,7 +267,7 @@ proc anchor? {start end network} { # verbose message if {$verbose} { puts "anchor?: $anchor" - set enter [gets stdin] + #set enter [gets stdin] } # done @@ -402,39 +402,41 @@ proc enlarge_nand! {nameing netlist} { verb "enlarge_nand!" verb "start with pulldown network" set network [dict get $netlist pulldown] - set original [anchor_pulldown? $netlist] ; # find anchor transistor + verb "find anchor transistor" + set original [anchor_pulldown? $netlist] + verb "checking original" if {$original eq {}} { set netlist {} } else { - # prepare replacement + verb "prepare replacement" set inode [expr [maxnode? $netlist] +1] ; # get highest node, add 2, for connectivity set gate [dict get [dict get $network $original] g] ; # get gate name set drain [dict get [dict get $network $original] d] ; # get drain side node name / number set src [dict get [dict get $network $original] s] ; # get source side node name / number set type [dict get [dict get $network $original] t] ; # get transistor type - # generate replacement for original with higher node on source + verb "generate replacement for original with higher node on source" dict set orgfet g $original dict set orgfet d $drain dict set orgfet s $inode ; # intermediate node number dict set orgfet t $type - # generate next mosfet name regarding 'proc naming' + verb "generate next mosfet name regarding 'proc naming'" if {$nameing eq "number"} { set newname [input_number! $gate] } else { set newname [input_char! $gate] } - # generate next mosfet itself + verb "generate next mosfet itself" dict set newfet g $newname dict set newfet d $inode dict set newfet s $src dict set newfet t $type - # build new pulldown network + verb "build new pulldown network" dict set pulldown $newname $newfet dict for {key value} $network { if {$key eq $original} { @@ -444,16 +446,16 @@ proc enlarge_nand! {nameing netlist} { } } - # follow up with pullup network + verb "follow up with pullup network" set network [dict get $netlist pullup] - # prepare replacement now on pullup network + verb "prepare replacement now on pullup network $original" set gate [dict get [dict get $network $original] g] ; # get gate name set drain [dict get [dict get $network $original] d] ; # get drain side node name / number set src [dict get [dict get $network $original] s] ; # get source side node name / number set type [dict get [dict get $network $original] t] ; # get transistor type - # generate newfet as "original double" + verb "generate newfet as \"original double\"" dict set newfet g $newname ; # just change the input gate / name dict set newfet d $drain dict set newfet s $src diff --git a/gafrc b/gafrc new file mode 100644 index 00000000..1df4db60 --- /dev/null +++ b/gafrc @@ -0,0 +1,42 @@ +;; ************ LibreSilicon's StdCellLibrary ******************* +;; +;; Organisation: Chipforge +;; Germany / European Union +;; +;; Profile: Chipforge focus on fine System-on-Chip Cores in +;; Verilog HDL Code which are easy understandable and +;; adjustable. For further information see +;; www.chipforge.org +;; there are projects from small cores up to PCBs, too. +;; +;; File: StdCellLib/gafrc +;; +;; Purpose: gEDA / gaf (lepton-EDA?) configuration file +;; +;; ************ gEDA/gaf 1.8.2 **************************** +;; +;; //////////////////////////////////////////////////////////////// +;; +;; Copyright (c) 2019 by chipforge +;; All rights reserved. +;; +;; This Standard Cell Library is licensed under the Libre Silicon +;; public license; you can redistribute it and/or modify it under +;; the terms of the Libre Silicon public license as published by +;; the Libre Silicon alliance, either version 1 of the License, or +;; (at your option) any later version. +;; +;; This design is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +;; See the Libre Silicon Public License for more details. +;; +;; //////////////////////////////////////////////////////////////////// + +;; ---------------------------------------------------------------- +;; LIBRARY DEFINITIONS +;; ---------------------------------------------------------------- + +(source-library "Sources/geda") +(component-library "Sources/geda") +;(component-library "Library/spice") diff --git a/gnetlistrc b/gnetlistrc new file mode 100644 index 00000000..2d35f162 --- /dev/null +++ b/gnetlistrc @@ -0,0 +1,43 @@ +;; ************ LibreSilicon's StdCellLibrary ******************* +;; +;; Organisation: Chipforge +;; Germany / European Union +;; +;; Profile: Chipforge focus on fine System-on-Chip Cores in +;; Verilog HDL Code which are easy understandable and +;; adjustable. For further information see +;; www.chipforge.org +;; there are projects from small cores up to PCBs, too. +;; +;; File: StdCellLib/gnetlistrc +;; +;; Purpose: gEDA / gaf (lepton-EDA?) netlister file +;; +;; ************ gEDA/gaf 1.8.2 **************************** +;; +;; //////////////////////////////////////////////////////////////// +;; +;; Copyright (c) 2019 by chipforge +;; All rights reserved. +;; +;; This Standard Cell Library is licensed under the Libre Silicon +;; public license; you can redistribute it and/or modify it under +;; the terms of the Libre Silicon public license as published by +;; the Libre Silicon alliance, either version 1 of the License, or +;; (at your option) any later version. +;; +;; This design is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +;; See the Libre Silicon Public License for more details. +;; +;; //////////////////////////////////////////////////////////////////// + +;; ---------------------------------------------------------------- +;; SWITCHES +;; ---------------------------------------------------------------- + +(hierarchy-netattrib-mangle "disabled") +(hierarchy-netname-mangle "enabled") +(hierarchy-traversal "disabled") + diff --git a/include.mk b/include.mk index 2bdb4c44..e5270c4e 100644 --- a/include.mk +++ b/include.mk @@ -51,6 +51,8 @@ SYNTHESISDIR = Synthesis TEMPDIR = Intermediate TBENCHDIR = TBench TOOLSDIR = Tools +RELEASEDIR = Library +TECHDIR = Tech # tool variables @@ -70,4 +72,3 @@ SCHEMATIC ?= $(TOOLSDIR)/tcl/_schematic -o $(DOCUMENTSDIR)/LaTeX -i $(CATALOG MANUAL ?= $(TOOLSDIR)/tcl/_manpage -o $(DOCUMENTSDIR)/LaTeX -i $(CATALOGDIR) -g LaTeX SWITCH ?= $(TOOLSDIR)/tcl/_switch -o $(SOURCESDIR)/verilog -i $(CATALOGDIR) -f verilog -.SUFFIXES: # delete all default suffix rules diff --git a/simulation.mk b/simulation.mk index 6d754c7e..7da4f505 100644 --- a/simulation.mk +++ b/simulation.mk @@ -37,12 +37,22 @@ include include.mk -# simulation tool variables +# 3rd party simulation tool variables + +SIMULATOR1 ?= iverilog -g2 # -Wall +SIMULATOR2 ?= vvp # -v +WAVEVIEWER ?= gtkwave + +SPICE ?= ngspice -b -c +#NETLIST ?= gnetlist -g spice-noqsi -o +#NETLIST ?= gnetlist -g spice -o +NETLIST ?= gnetlist -g spice-sdb -o +#NETLIST ?= lepton-netlist -g spice-sdb -o + +# temporary simulation directory + +VERILOGTMP ?= $(SIMULATIONDIR)/verilog -WORKDIR ?= $(SIMULATIONDIR)/verilog -SIMULATOR1 ?= iverilog -g2 # -Wall -SIMULATOR2 ?= vvp # -v -WAVEVIEWER ?= gtkwave .PHONY: clean clean: @@ -50,23 +60,42 @@ clean: -$(RM) $(SIMULATIONDIR)/verilog/*_bench.v -$(RM) $(SIMULATIONDIR)/verilog/*.vpp -$(RM) $(SIMULATIONDIR)/verilog/*.table + -$(RM) $(SIMULATIONDIR)/spice/*_record.txt + -$(RM) $(TBENCHDIR)/spice/*_tb.sp + -$(RM) $(RELEASEDIR)/spice/*.cir # ---------------------------------------------------------------- # RUN VERILOG SIMULATION # ---------------------------------------------------------------- verilog-slm: - $(POPCORN) -e $@ $(CATALOGDIR)/$(CELL).cell > $(SIMULATIONDIR)/verilog/$(CELL).v + $(POPCORN) -e $@ $(CATALOGDIR)/$(CELL) > $(SIMULATIONDIR)/verilog/$(CELL).v verilog-bench: - $(POPCORN) -e $@ $(CATALOGDIR)/$(CELL).cell > $(SIMULATIONDIR)/verilog/$(CELL)_bench.v + $(POPCORN) -e $@ $(CATALOGDIR)/$(CELL) > $(SIMULATIONDIR)/verilog/$(CELL)_bench.v .PHONY: table-file table-file: PROJECT_DEFINES += -DDUMPFILE=\"$@.vcd\" table-file: verilog-slm verilog-bench $(MKDIR) $(TEMPDIR) - $(SIMULATOR1) $(PROJECT_DEFINES) -o $(WORKDIR)/$(CELL)_bench.vpp $(WORKDIR)/$(CELL).v $(WORKDIR)/$(CELL)_bench.v - $(SIMULATOR2) $(WORKDIR)/$(CELL)_bench.vpp | $(GREP) '^\.' | $(SED) 's/^.//g' > $(TEMPDIR)/$(CELL).table + $(SIMULATOR1) $(PROJECT_DEFINES) -o $(VERILOGTMP)/$(CELL)_bench.vpp $(VERILOGTMP)/$(CELL).v $(VERILOGTMP)/$(CELL)_bench.v + $(SIMULATOR2) $(VERILOGTMP)/$(CELL)_bench.vpp | $(GREP) '^\.' | $(SED) 's/^.//g' > $(TEMPDIR)/$(CELL).table ifeq ($(MODE), gui) $(WAVEVIEWER) -f $@.vcd -a $(SIMULATIONDIR)/verilog/$(CELL).do endif + +# ---------------------------------------------------------------- +# RUN SPICE SIMULATION +# ---------------------------------------------------------------- + +record: $(SIMULATIONDIR)/spice/$(CELL)_record.txt + +$(SIMULATIONDIR)/spice/$(CELL)_record.txt: $(RELEASEDIR)/spice/$(CELL).cir $(RELEASEDIR)/spice/BUF2.cir $(TBENCHDIR)/spice/$(CELL)_tb.sp + $(SPICE) $? > $@ + +$(TBENCHDIR)/spice/$(CELL)_tb.sp: $(TBENCHDIR)/geda/$(CELL)_tb.sch $(TBENCHDIR)/spice/$(CELL)_tb.cmd + $(NETLIST) $@ $< + +$(RELEASEDIR)/spice/$(CELL).cir: $(SOURCESDIR)/geda/$(CELL).sch + $(NETLIST) $@ $? + diff --git a/tools.sh b/tools.sh new file mode 100644 index 00000000..47e6da8b --- /dev/null +++ b/tools.sh @@ -0,0 +1,120 @@ +#!/bin/bash + +# To run this installer you can open a Terminal window and enter the following commands: + +# wget https://pdk.libresilicon.com/tools.sh +# bash tools.sh + + +echo "To install the LibreSilicon Standard Cell Generator toolchain, you need:" +echo "Debian/Ubuntu-18.04 or newer" +echo "at least 1.9 GB RAM" + +echo "If the installation interrupts due to a network or power outage, just run the installation script again." + +sudo apt-get update + +echo "The following packages are optional for documentation and visualisation, you can safely say N if you dont want to install them:" +sudo apt-get install npm blender inkscape iverilog +sudo apt-get install gtkwave lsb + +echo Installing required packages on Debian/Ubuntu: +sudo apt-get -y install qflow imagemagick libcairo2-dev tcllib tklib make g++ libreadline-dev python3-cairosvg python3 python3-numpy libblas-dev ngspice z3 tcl8.6-dev tk8.6-dev python3-scipy python3-matplotlib texlive-latex-recommended unzip glpk-utils libglpk-dev python3-pulp git wget gauche python3-toml python3-pytoml python3-pip mmv libglu1-mesa-dev libcurl4-gnutls-dev pdf2svg python3-yaml python3-cffi python3-pyparsing python3-certifi tcl magic libsqlite3-dev python3-setuptools python3-networkx python3-sympy + +sudo apt-get -y install libngspice0 libngspice0-dev python3-gdspy python3-kiwisolver +sudo apt-get -y install libopengl-dev opensta opensta-dev klayout + +#sudo apt-get install geda-gschem geda-gnetlist geda-doc geda-gattrib geda-gsymcheck +sudo apt-get -y install python-z3 +sudo apt-get -y install python3-z3 + +echo Installing required packages on FreeBSD: +pkg install qflow ImageMagick7 cairo tcllib tk87 gcc readline py37-cairosvg python37 py37-numpy blas ngspice_rework z3 py37-z3-solver tcl87 py37-scipy py37-matplotlib texlive-full unzip blender glpk py37-pulp git wget texlive-full gauche py37-toml py37-pytoml iverilog gtkwave py37-pip inkscape ngspice_rework-shlib + + +#echo "Installing Magic since we need magic >= 8.2.145 , as soon as the distribution package is newer than that and comes with cairo support we wont need to compile it ourselves anymore:" +#sudo rm -rf magic-*/ +#MAGICVERSION=8.3.27 +#wget -c http://opencircuitdesign.com/magic/archive/magic-$MAGICVERSION.tgz +#tar xvzf magic-$MAGICVERSION.tgz +#cd magic-$MAGICVERSION +#./configure --with-cairo +#make +#sudo make install +#cd .. + + + +# Due to problems with the KLayout packages we currently have to install it manually: +#wget https://pdk.libresilicon.com/klayout.egg-info +#sudo cp klayout.egg-info /usr/lib/python3/dist-packages/klayout.egg-info + +#git clone https://github.com/KLayout/klayout +#cd klayout +#python3 setup.py build --parallel 1 +#sudo python3 setup.py install +#cd .. + + +#echo Installing librecell +#sudo rm -rf librecell +#git clone https://codeberg.org/tok/librecell +#echo "Python >= 3.6 is needed!" +#python3 --version +#cd librecell/librecell-common +#sudo python3 setup.py install +#cd ../.. +#cd librecell/librecell-meta +#sudo python3 setup.py install +#cd ../.. +#cd librecell/librecell-lib +#sudo python3 setup.py install +#cd ../.. +#cd librecell/librecell-layout +#sudo python3 setup.py install +#cd ../.. + + + +echo Installing Circdia +wget -c http://www.taylorgruppe.de/circdia/circdia.zip +sudo mkdir -p /usr/share/texlive/texmf-dist/tex/circdia +sudo unzip -u -o -d /usr/share/texlive/texmf-dist/tex/circdia circdia.zip +sudo mktexlsr + +# We try to use libngspice0 and libngspice0-dev perhaps we dont need this code anymore: +#echo Installing ngspice +#wget -O ngspice-31.tar.gz https://sourceforge.net/projects/ngspice/files/ng-spice-rework/31/ngspice-31.tar.gz/download +#tar xvzf ngspice-31.tar.gz +#cd ngspice-31 +#./configure --with-ngshared --enable-shared +#make +#sudo make install +#cd .. + +#echo "Installing gdspy (GDS for Python), if it has not been installed already" +#sudo pip3 install gdspy + +echo "Installing PySpice (SPICE for Python)" +sudo pip3 install PySpice + +#echo "Installing Sphinx Verilog" +#sudo pip3 install sphinxcontrib-verilog-diagrams + +#echo "Installing netlistsvg" +#sudo npm install -g netlistsvg + +# If you do not want to generate a standard cell library, then uncomment the following line to stop here +#exit + +#echo Installing StdCellLib +#git clone https://github.com/thesourcerer8/StdCellLib +#cd StdCellLib/Catalog +#make catalog +#make importQflow + +echo "Installation of the StdCellLib is finished." +echo "To build a whole standard cell library you can now run:" +echo "make layout ; make doc ; perl ../Tools/perl/buildreport.pl ; cd .. ; make dist" +#sudo make qflow +