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Feedback Request: Drawing Cells for Magic #6

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0e16eb8
Added abutment rules, removed unnecessary lines
thesourcerer8 Nov 29, 2020
9450421
Adapted cell sizing to SKY130 and OSU130 cells
thesourcerer8 Nov 30, 2020
4ea7f2c
Changed behaviour for empty .mag files
thesourcerer8 Dec 2, 2020
3800dfc
Incorrect GDS layer and datatype fixed, thanks to diadatp!
thesourcerer8 Dec 3, 2020
192a936
Removed automatic qflow deployment
thesourcerer8 Dec 10, 2020
f91c961
Made LEF rectangles
thesourcerer8 Dec 10, 2020
83c522b
Improved DRC compliance
thesourcerer8 Dec 10, 2020
60686e9
Fixed transistor size
thesourcerer8 Dec 12, 2020
e0a53cb
Separated ndiff_contact and pdiff_contact
thesourcerer8 Dec 12, 2020
4efde24
Added separate debugging directory
thesourcerer8 Dec 12, 2020
7d0c9cb
Tool to extract augment the cell size size in LEFs from .mag
thesourcerer8 Dec 12, 2020
7f698ed
Improved DRC rules
thesourcerer8 Dec 12, 2020
c7895da
Fixed remaining DRC issues for INV
thesourcerer8 Dec 15, 2020
45ecfa9
Added DRC check tool
thesourcerer8 Dec 16, 2020
be1ec09
DRC fix tool
thesourcerer8 Dec 16, 2020
cb90253
Added DRC fixing into the flow
thesourcerer8 Dec 16, 2020
156ff27
Added DRC fixing into the flow
thesourcerer8 Dec 16, 2020
be1a9e7
Added DRC reports to clean target
thesourcerer8 Dec 16, 2020
3041617
DRC checks updated and filtered
thesourcerer8 Dec 19, 2020
2d5dcc1
Added Docker installation script
thesourcerer8 Dec 25, 2020
7234073
Removed the broken six.py
thesourcerer8 Dec 25, 2020
db58198
Adding bash script to enter the docker container
thesourcerer8 Dec 25, 2020
9ee080c
Removed double newlines
thesourcerer8 Mar 9, 2021
31d2166
Fixed double filename extensions
thesourcerer8 Mar 9, 2021
d27aa62
Placement caching, might be caching too much
thesourcerer8 Mar 12, 2021
a1b5a41
Added lctime configuration file lctime.conf
thesourcerer8 Apr 9, 2021
0ce816a
Fixed filenames for truthtable generation
thesourcerer8 Apr 13, 2021
51e65e9
Automatic Test generator for Caravel
thesourcerer8 Apr 13, 2021
82adf12
Cleaning up DRC results
thesourcerer8 Apr 25, 2021
08bf66b
Seperated NMOS and PMOS SPICE sizing
thesourcerer8 Apr 25, 2021
286b7d4
Switched from "unithd" to "unit" since high-density is too dense for …
thesourcerer8 Apr 25, 2021
b06cdae
Added support for differential inputs
thesourcerer8 May 1, 2021
0139666
Automated differential inputs with _n and _p
thesourcerer8 May 1, 2021
08c474c
Added differential input support for lctime
thesourcerer8 May 1, 2021
617bb7d
Fixed the sizing for the SPICE models
thesourcerer8 May 1, 2021
1f32bc8
Splitted transistor.sp into nmos and pmos for correct sizing
thesourcerer8 May 1, 2021
c1aae5c
Starting Well-Tap support
thesourcerer8 May 1, 2021
a4c2d6e
DRC fixing comes to life
thesourcerer8 May 7, 2021
45441be
Updated the Buildreport for new output of Librecell
thesourcerer8 May 23, 2021
2fa2b45
Counting the number of DRC errors
thesourcerer8 May 23, 2021
8872c4f
Added a missing word
thesourcerer8 Jun 8, 2021
f631925
Greatly improved DRC check and fixing tools
thesourcerer8 Jun 8, 2021
1a75a88
Expanded the DRC rules with the DRC rule expander
thesourcerer8 Jun 8, 2021
c93b1b0
Fixed nwell shape
thesourcerer8 Jun 8, 2021
0aeb5af
Fixed namespace for container
thesourcerer8 Jun 8, 2021
d570162
Changed correction naming convention
thesourcerer8 Jun 9, 2021
367164c
Added annotations for minimum width rules
thesourcerer8 Jun 9, 2021
c4a1732
Added checkpoint support and painting support
thesourcerer8 Jun 9, 2021
7e16a70
Updated the documentation
thesourcerer8 Jun 10, 2021
2944706
Fixed the rounding error with the labels
thesourcerer8 Jun 12, 2021
cb7c2f4
Timestamp 0 indicates that DRC needs to be run
thesourcerer8 Jun 13, 2021
e079542
Print the usage only when needed
thesourcerer8 Jun 13, 2021
f4f94c1
Various improvements
thesourcerer8 Jun 13, 2021
a8964dc
Fixed workflow around DRC, re-generate GDS when necessary
thesourcerer8 Jun 13, 2021
1c7a01d
Fixed abutment and ignored outlying checkpaints
thesourcerer8 Jun 16, 2021
f41dc56
Deactivated Well-Taps again
thesourcerer8 Jun 17, 2021
bed8e85
Switched from the last (second) to the first LVS result
thesourcerer8 Jun 17, 2021
11b7c29
Multiplication of cells so that you can use it even with a single cell
thesourcerer8 Jun 17, 2021
2685845
Improved error handling
thesourcerer8 Jun 17, 2021
e2f60d5
Faster error handling
thesourcerer8 Jun 18, 2021
c1ee6f1
Fixed permissions
thesourcerer8 Jun 18, 2021
60e36c4
Added seperate obstruction list
thesourcerer8 Jun 18, 2021
54a809b
Fixed GDS files reference
thesourcerer8 Jun 18, 2021
215b2c9
Fixed DRC correction
thesourcerer8 Jun 18, 2021
d37759e
Cleaning up pre-DRC layout files
thesourcerer8 Jun 18, 2021
25546ae
Preserving pre-DRC layouts
thesourcerer8 Jun 18, 2021
8d34374
Fixed DRC fixing, improved logging
thesourcerer8 Jun 18, 2021
12277e3
Removed corrupting second DRC fix try
thesourcerer8 Jun 18, 2021
5749982
Ignored checkpaint (DRC TODO) layer
thesourcerer8 Jun 18, 2021
7768967
Demoboard rendering
thesourcerer8 Jun 18, 2021
c73820e
Adapted for new librecell version
thesourcerer8 Jun 18, 2021
5b49fa8
New transistor files
thesourcerer8 Jun 18, 2021
464e370
Corrected the grid coordinates
thesourcerer8 Jun 19, 2021
44532b0
New version
thesourcerer8 Jun 20, 2021
c54bb46
Corrected Via positioning
thesourcerer8 Jun 22, 2021
3cfa59a
We dont need to fix the demoboard
thesourcerer8 Jun 24, 2021
8708f3e
Added DRC fixing mechanisms for the issues we have
thesourcerer8 Jun 24, 2021
4a34d1c
Prevented overwriting of mag files with debug files
thesourcerer8 Jun 26, 2021
ed86cfc
Fixed scaling (but we still need magscale support for lclayout)
thesourcerer8 Jun 26, 2021
c9b42c8
Added magscale support
thesourcerer8 Jun 26, 2021
14d682c
Scaling support
thesourcerer8 Jun 26, 2021
b5835f2
Added xschem+sky130 support
thesourcerer8 Oct 22, 2021
d10ccdf
New Asynchronous cells
thesourcerer8 Oct 22, 2021
e790beb
Various improvements
thesourcerer8 Nov 12, 2021
1190b64
drc check needs a box
thesourcerer8 Nov 12, 2021
3010cb6
Used select top to automatically select the right size
thesourcerer8 Nov 12, 2021
ff611e9
workaround for lclayout problems with lowercase filenames
thesourcerer8 Nov 12, 2021
c94d3e8
Improved predrc filenames
thesourcerer8 Nov 12, 2021
4cf37b3
Improved Magic handling
thesourcerer8 Nov 12, 2021
5bfc6ba
MUX generator for transmission gates
thesourcerer8 Sep 8, 2022
e52e19b
MUX generator with Transmission Gates
thesourcerer8 Sep 8, 2022
11365c0
Bugfix: Inputs were missing
thesourcerer8 Sep 9, 2022
fcf91c0
Fixed ouput naming
thesourcerer8 Sep 9, 2022
95c231d
Added error message for mouse-over titles when files are missing
thesourcerer8 Oct 30, 2022
00d4791
Executable
thesourcerer8 Nov 21, 2022
6e1af49
Made names uppercase
thesourcerer8 Nov 21, 2022
817e8f0
Adding DRC Expander script to expand MAGIC .tech files
thesourcerer8 Nov 24, 2022
3575c5a
Adding support for GF180MCU from GlobalFoundries
thesourcerer8 Nov 24, 2022
fb67368
Display missing filenames
thesourcerer8 Nov 26, 2022
f41df47
Analyzing memory usage and time
thesourcerer8 Nov 27, 2022
24d424b
Logging resource usage
thesourcerer8 Nov 27, 2022
4ca5186
Removed warnings and debug code
thesourcerer8 Nov 27, 2022
d528d7e
Fixed report filenames
thesourcerer8 Nov 27, 2022
8f85d06
Adding a generator for CharLib characterization
thesourcerer8 Nov 28, 2022
eda2c42
Adding support for CharLib
thesourcerer8 Nov 28, 2022
b988334
Fixed typos
thesourcerer8 Nov 29, 2022
4741ddd
Reduced update frequency of buildreport to 2 minutes
thesourcerer8 Dec 1, 2022
89d9cda
Adding tool to divide and conquer the cells on several test-chips
thesourcerer8 Dec 1, 2022
4b48264
Adding tools for Caravel deployment
thesourcerer8 Dec 1, 2022
dda8c9c
Made the PDK parameterizable
thesourcerer8 Dec 1, 2022
fc9f7fc
Made building a single cell template possible, to avoid error messages
thesourcerer8 Dec 1, 2022
d08db79
Building the liberty templates just for a single cell
thesourcerer8 Dec 1, 2022
e03be1c
Various updates
thesourcerer8 Dec 1, 2022
6677226
Added more verbose output
thesourcerer8 Dec 1, 2022
6a116e7
Added warning message if environment variable is missing
thesourcerer8 Dec 1, 2022
85a1c55
Updated environment variables for newer Caravel
thesourcerer8 Dec 2, 2022
df2aebd
Configuration generator for caravel config.json files
thesourcerer8 Dec 2, 2022
6a9c017
Config generator, filename fix
thesourcerer8 Dec 2, 2022
35596ef
Expanded LEF and GDS files, since Openlane doesn't seem to be capable
thesourcerer8 Dec 4, 2022
10ee6c8
Adding environment file for debugging
thesourcerer8 Dec 4, 2022
1ac8a01
GPIO definitions
thesourcerer8 Dec 5, 2022
11b339f
GPIO definitions
thesourcerer8 Dec 5, 2022
f48abeb
Fixed User/MGMT GPIO definition
thesourcerer8 Dec 5, 2022
14e7983
New directory structure
thesourcerer8 Dec 5, 2022
47d8b87
New cells directory layout
thesourcerer8 Dec 5, 2022
8f80ebb
Scaling tool
thesourcerer8 Dec 6, 2022
0c9a959
Corrected standard cell library
thesourcerer8 Dec 6, 2022
775bdc9
New cells directory structure
thesourcerer8 Dec 6, 2022
2d58978
Added .dontuse support for standard cells
thesourcerer8 Dec 6, 2022
fac5651
Change lclayout call to only use the spice file for that cell
thesourcerer8 Dec 8, 2022
83f3c4a
Power Pins for GF180
thesourcerer8 Dec 8, 2022
d76abf2
Power pins update for GF180
thesourcerer8 Dec 8, 2022
3292b2f
Made the tools executable
thesourcerer8 Dec 8, 2022
9d4c427
Fixed wrong variable name
thesourcerer8 Dec 11, 2022
d073d61
Added a maximum limit for designs
thesourcerer8 Dec 12, 2022
939247b
Added automatic rescaling for GDS
thesourcerer8 Dec 18, 2022
48dce4d
Added GF180 and Sky130 support for the Caravel IO
thesourcerer8 Dec 18, 2022
95050b3
Added counters for *.cell and *.svg files
thesourcerer8 Dec 18, 2022
d6723e1
Adding a new dummy characterization engine to please yosys
thesourcerer8 Dec 19, 2022
43ff6cb
Adding README generator, added documentation, ...
thesourcerer8 Dec 19, 2022
def439c
Libraries added
thesourcerer8 Dec 19, 2022
3ae83ab
Overridable PDK_ROOT
thesourcerer8 Dec 19, 2022
8443385
Fixed DRC issues, removed unnecessary layers
thesourcerer8 Dec 20, 2022
ace35fc
Environment variable support added
thesourcerer8 Dec 20, 2022
082b031
Warning and explanation for changed GDS files added
thesourcerer8 Dec 20, 2022
5a1d87c
Adding wildcards back in
thesourcerer8 Dec 20, 2022
0f7cd30
Including the project cells, somehow the VERILOG files dont seem to be
thesourcerer8 Dec 20, 2022
36c6c83
Input/Output confusion
thesourcerer8 Dec 20, 2022
a909cb0
New config file with environment parameters for Caravel
thesourcerer8 Dec 20, 2022
48b2953
Changed Caravel Config Filename
thesourcerer8 Dec 20, 2022
fc7a665
Adding Inverter cell
thesourcerer8 Dec 20, 2022
ec25316
Removed old Sky130 file
thesourcerer8 Dec 20, 2022
95239a4
Added new file types to cleaning
thesourcerer8 Dec 20, 2022
5c07c02
Scaling correction
thesourcerer8 Dec 20, 2022
9b08195
Removed Min-Area rule for Metal2 since those are false positives for
thesourcerer8 Dec 22, 2022
3c85b0f
Added verbosity
thesourcerer8 Dec 22, 2022
8dad813
New bisecting tool for finding errors in many changed lines to the te…
thesourcerer8 Dec 22, 2022
66120bb
Improved variable handling for supporting PDKs
thesourcerer8 Dec 22, 2022
a396607
Rearranged some steps to avoid unnecessary steps that cost time
thesourcerer8 Dec 22, 2022
a7a76d8
Made it executable
thesourcerer8 Dec 22, 2022
52f3532
Various changes to DRC rules, based on the DRC results from magic
thesourcerer8 Dec 22, 2022
7f6be0c
More verbose for executed commands
thesourcerer8 Dec 22, 2022
309c0e1
Adding tool to display the grid usage
thesourcerer8 Dec 22, 2022
a5862a2
Added multiple-cell support
thesourcerer8 Dec 23, 2022
6fb082c
Added x support
thesourcerer8 Dec 23, 2022
be46078
Added support for the new debug-routing-graph of lclayout
thesourcerer8 Dec 23, 2022
06467aa
Adding MCW_ROOT for simulation
thesourcerer8 Dec 23, 2022
e509358
Made it run on Sky130
thesourcerer8 Dec 23, 2022
e48aa0e
Do not delete essential cells anymore
thesourcerer8 Dec 23, 2022
35940a6
Proper sizing of the gates
thesourcerer8 Dec 23, 2022
34bedec
Adding automatic verification support
thesourcerer8 Dec 24, 2022
e343ee3
Trying to make the test successful
thesourcerer8 Dec 24, 2022
318fd50
Adding testbench for Caravel
thesourcerer8 Dec 24, 2022
b4bc326
Adding CELL generators for missing cells and for essential cells
thesourcerer8 Dec 24, 2022
9a71d93
Remove min_area for metal2
thesourcerer8 Dec 24, 2022
fca27fd
Moved code out of the loop
thesourcerer8 Dec 24, 2022
6c33f0a
HIGH-Z support for sequential cells
thesourcerer8 Dec 24, 2022
5a22ea5
Adding truthtable support
thesourcerer8 Dec 24, 2022
8613f26
Create LICENSE
thesourcerer8 Jan 7, 2023
77aac99
Adding routing grid debugging
thesourcerer8 Jan 7, 2023
2ccf9fb
Merge remote-tracking branch 'refs/remotes/origin/master'
thesourcerer8 Jan 7, 2023
383da1d
New conversion tool
thesourcerer8 Feb 15, 2023
0fb5b39
Fixed the via1 mapping, now it works
thesourcerer8 Feb 15, 2023
045c7e4
Adding siliwiz to the flow
thesourcerer8 Feb 15, 2023
3e8dc1e
Adding KLayout home variable
thesourcerer8 Feb 19, 2023
a984644
Fix DRC issues with Vias near the power rails, hopefully no sideeffects
thesourcerer8 Apr 12, 2023
2b9bef8
Cleaning up DRC tcl files
thesourcerer8 Apr 12, 2023
853638a
Adding DRC Style support
thesourcerer8 Apr 12, 2023
4a4ce06
Adding via cost displaying
thesourcerer8 Apr 12, 2023
ffe5cc4
Adding ERROR logfile visualisation tool
thesourcerer8 Apr 12, 2023
247c106
Changing default DRC style to full
thesourcerer8 Apr 12, 2023
f28e8d8
Correctly filling in resistances, using vertical poly routing to avoid
thesourcerer8 Apr 12, 2023
b7966fd
Finalizing the buildreport for distribution
thesourcerer8 May 4, 2023
7ded173
Removed errors for unavailable files
thesourcerer8 May 10, 2023
2035468
Switched demoboard from bounding box to abutment
thesourcerer8 May 10, 2023
2efdb6c
Added nowindow to be safe
thesourcerer8 May 10, 2023
171a1f9
Made it work without a X-Server
thesourcerer8 May 10, 2023
ec01dbd
Making it work without a X-Server
thesourcerer8 May 10, 2023
86816cc
Added another output message for easing flow debugging
thesourcerer8 May 10, 2023
ee4b671
Fixed permission
thesourcerer8 May 10, 2023
9266744
Removing the wrong -nowindow option
thesourcerer8 May 10, 2023
bbf1b6b
Better checkmark
thesourcerer8 Jun 23, 2023
9cf352d
Update README.md
thesourcerer8 Jul 24, 2023
f2c5b67
Adding documentation
thesourcerer8 Dec 9, 2023
06d9eef
Merge branch 'master' of github.com:thesourcerer8/StdCellLib
thesourcerer8 Dec 9, 2023
56ac54b
Rename tool
thesourcerer8 Dec 9, 2023
4b31abf
Improved Verilog format for multiple outputs
thesourcerer8 Dec 10, 2023
82d6a32
Added rules for truthtables
thesourcerer8 Dec 10, 2023
3043ca3
Moved to gf180mcuD
thesourcerer8 Dec 10, 2023
825a8f2
Tech file improvements
thesourcerer8 Dec 10, 2023
3638f12
New Caravel configuration for Sky130
thesourcerer8 Dec 10, 2023
f018f83
Improved the cell selection
thesourcerer8 Dec 10, 2023
69b4493
Added warnings for empty truthtables
thesourcerer8 Dec 10, 2023
156cd3a
Updating to newer Tapeout configuration
thesourcerer8 Dec 10, 2023
a42c08a
Adding CharLib 1.0 support
thesourcerer8 Dec 11, 2023
7b47b85
Improving the Liberty functions
thesourcerer8 Dec 11, 2023
cabc0cd
Upgrading support for CharLib 1.0
thesourcerer8 Dec 11, 2023
357e31b
Making it executable
thesourcerer8 Dec 11, 2023
ff40bcd
Fixed the config.json/config.tcl confusion
thesourcerer8 Dec 11, 2023
19fad96
Fixed the commas
thesourcerer8 Dec 11, 2023
447d2c6
Fixed the EXTRA_LEFS
thesourcerer8 Dec 11, 2023
75a99de
Assigned unused IOs
thesourcerer8 Dec 11, 2023
22777d8
We dont need to remove the newlines anymore
thesourcerer8 Dec 11, 2023
0266808
Adding charter target
thesourcerer8 Dec 11, 2023
31f07d5
More die space for the IOs
thesourcerer8 Dec 11, 2023
e049678
More diespace for the IOs
thesourcerer8 Dec 11, 2023
29ad309
Modularized the SPICE PDK definitions
thesourcerer8 Dec 11, 2023
9690b07
Added a welcome message
thesourcerer8 Dec 11, 2023
7365184
Replacing the Tech directory with a symlink
thesourcerer8 Apr 9, 2024
581e90a
Adding symlink, does it work?
thesourcerer8 Apr 9, 2024
64c3585
Tools installation
thesourcerer8 Apr 9, 2024
36ef251
Adding documentation
thesourcerer8 Apr 20, 2024
7e56009
Track variations calculation
thesourcerer8 Apr 21, 2024
7651271
Adding spice file definitions. These are the modified files from
thesourcerer8 Apr 21, 2024
6e15f6d
Fixed DRC rules for via/contact overlap
thesourcerer8 Apr 23, 2024
05ba41b
Adding variants for 3.3V, 5V, 6V, 10V
thesourcerer8 Apr 26, 2024
2a49791
Addingt topological truth table for a Topology vs. Synthesis check
thesourcerer8 Apr 26, 2024
ea85f5d
Generating YAML for single cells
thesourcerer8 Apr 26, 2024
d00bbe7
Environment variables
thesourcerer8 Apr 26, 2024
0466821
Moving the DRC Fixing TCL code to a seperate file
thesourcerer8 May 2, 2024
c4a11c4
Making the Verilog output Python syntax compatible too
thesourcerer8 May 2, 2024
21266d8
Skipping cells without a truthtable
thesourcerer8 May 2, 2024
2e8d125
Switched to parasitic extracted netlist
thesourcerer8 May 2, 2024
afe7f06
Removed warnings for newer magic versions - is it the correct way to …
thesourcerer8 May 2, 2024
6127453
Made it flexible for single cells and whole libraries
thesourcerer8 May 2, 2024
e32efbe
Activating charlib support
thesourcerer8 May 2, 2024
b4e3818
Activating Logging for charlib
thesourcerer8 May 2, 2024
65989ac
Fixed typo
thesourcerer8 May 2, 2024
c5ecdab
Adding usage collection for charlib
thesourcerer8 May 2, 2024
76d1918
Added some documentation
thesourcerer8 May 2, 2024
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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
StdCellLib*.tgz
9 changes: 9 additions & 0 deletions Catalog/.gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
*.mag
*.cell
*.svg
*.sp
*.pxi
!INV.cell
__pycache__
libresilicon.lib
libresilicon.lef
27 changes: 14 additions & 13 deletions Catalog/AND4.cell
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
.DESCRIPTION "a 4-input AND gate"
.SEE_ALSO "NAND3 - a 3-input Not-AND (or NAND) gate"
.ORDER "Gate Drain Source MOSFET"
A Y vdd pmos
B Y vdd pmos
C Y vdd pmos
D Y vdd pmos
Y Z vdd pmos
A Y 2 nmos
B 2 4 nmos
C 4 6 nmos
D 6 gnd nmos
Y Z gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B C D
.outputs Z
.ORDER "MOSFET Gate Drain Source"
pmos A Y vdd
pmos B Y vdd
pmos C Y vdd
pmos D Y vdd
pmos Y Z vdd
nmos A Y 1
nmos B 1 2
nmos C 2 3
nmos D 3 gnd
nmos Y Z gnd
17 changes: 8 additions & 9 deletions Catalog/AOI21.cell
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
.DESCRIPTION "a 2-1-input AND-OR-Invert gate"
.SEE_ALSO "AOI21 - a 2-1-input AND-OR-Invert gate"
.ORDER "Gate Drain Source MOSFET"
A Y 1 pmos
B 1 vdd pmos
B1 1 vdd pmos
A Y gnd nmos
B Y 2 nmos
B1 2 gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A A1
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y vdd
pmos A1 Y vdd
nmos A Y 1
nmos A1 1 gnd
20 changes: 11 additions & 9 deletions Catalog/AOI31.cell
Original file line number Diff line number Diff line change
@@ -1,11 +1,13 @@
.DESCRIPTION "a 3-1-input AND-OR-Invert gate"
.SEE_ALSO "AOI31 - a 3-1-input AND-OR-Invert gate"
.ORDER "Gate Drain Source MOSFET"
A Y 1 pmos
B 1 vdd pmos
B1 1 vdd pmos
B2 1 vdd pmos
A Y gnd nmos
B Y 2 nmos
B1 2 3 nmos
B2 3 gnd nmos
.inputs A B B1 B2
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y 1
pmos B 1 vdd
pmos B1 1 vdd
pmos B2 1 vdd
nmos A Y gnd
nmos B Y 2
nmos B1 2 3
nmos B2 3 gnd
71 changes: 68 additions & 3 deletions Catalog/GNUmakefile
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ DATE := $(shell date +%Y%m%d)
# project tools

POPCORN ?= ../Tools/tcl/popcorn
CELLS = INV.cell NAND2.cell NAND3.cell AND4.cell NOR2.cell NOR3.cell OR4.cell
CELLS = INV.cell NAND2.cell NAND3.cell AND4.cell NOR2.cell NOR3.cell OR4.cell AOI21.cell OAI21.cell
LIMIT = 4

# ----------------------------------------------------------------
Expand All @@ -79,13 +79,34 @@ help:
.PHONY: clean
clean:
# $(RM) *.aux *.idx *.log *.toc *.out
$(RM) AND4.cell NAND2.cell NAND3.cell NOR2.cell NOR3.cell OR4.cell
$(RM) *.mag *.svg

# ----------------------------------------------------------------
# DOCUMENTATION TARGETS
# ----------------------------------------------------------------

.PHONY: catalog
catalog: $(CELLS)
catalog: $(CELLS) libresilicon.sp libresilicon.lef libresilicon.lib qflow demoboard.mag doc/StdCellLib.pdf

libresilicon.sp: *.cell ../Tech/librecell_tech.py ../Tools/perl/cell2spice.pl ../Tools/perl/librecells.pl ../Tech/transistor.sp
../Tools/perl/cell2spice.pl
../Tools/perl/librecells.pl

demoboard.mag: *.cell libresilicon.sp
perl ../Tools/perl/demoboard.pl >demoboard.mag

libresilicon.lef: *.cell libresilicon.sp
../Tools/perl/lefgen.pl outputlib/*.lef >libresilicon.lef

libresilicon.lib: *.cell libresilicon.sp
../Tools/perl/libgen.pl >libresilicon.lib

.PHONY: qflow
qflow: libresilicon.lef libresilicon.lib
mkdir -p /usr/local/share/qflow/tech/ls050
cp libresilicon.lef /usr/local/share/qflow/tech/ls050/ls050_stdcells.lef
cp libresilicon.lib /usr/local/share/qflow/tech/ls050/ls05_stdcells.lib

AND4.cell: NAND3.cell
$(POPCORN) -l $(LIMIT) -n nand -c $@ -b $(LIMIT) $<
Expand All @@ -96,12 +117,56 @@ NAND2.cell: INV.cell
NAND3.cell: NAND2.cell
$(POPCORN) -l $(LIMIT) -n nand -c $@ $<

AOI21.cell: INV.cell
$(POPCORN) -l $(LIMIT) -n aoi -c $@ $<

OAI21.cell: INV.cell
$(POPCORN) -l $(LIMIT) -n oai -c $@ $<

NOR2.cell: INV.cell
$(POPCORN) -l $(LIMIT) -n nor -c $@ $<

NOR3.cell: NOR2.cell
$(POPCORN) -l $(LIMIT) -n nor -c $@ $<

OR4.cell: NOR3.cell
$(POPCORN) -l $(LIMIT) -n nor -b $(LIMIT) -c $@ $<
$(POPCORN) -l $(LIMIT) -n nor -c $@ -b $(LIMIT) $<

doc/StdCellLib.pdf: *.cell libresilicon.sp
doc/docu.sh

.PHONY: importQflow
importQflow:
../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/gscl45nm/gscl45nm.sp
../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu018/osu018_stdcells.sp
../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu035/osu035_stdcells.sp
../Tools/perl/spice2cell.pl /usr/local/share/qflow/tech/osu050/osu050_stdcells.sp
../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu018/osu018_stdcells.sp
../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu035/osu035_stdcells.sp
../Tools/perl/spice2cell.pl /usr/share/qflow/tech/osu050/osu050_stdcells.sp

mags=$(wildcard *.mag)
svgs=$(mags:.mag=.svg)

.PHONY: svg
svg: $(svgs)

test:
lctime --debug --liberty libresilicon.lib \
--include ../Tech/libresilicon.m \
--spice INV.sp \
--cell INV \
--output INV.lib

test2:
/usr/local/bin/lctime --debug --liberty ~/FreePDK45/osu_soc/lib/files/gscl45nm.lib \
--include ~/FreePDK45/osu_soc/lib/files/gpdk45nm.m \
--spice ~/FreePDK45/osu_soc/lib/source/netlists/AND2X1.pex.netlist \
--cell AND2X1 \
--output /tmp/and2x1.lib
libertyviz -l libresilicon.lib --cell INV --pin Y --related-pin A --table cell_rise

%.svg:
perl ../Tools/perl/mag2svg.pl $@


2 changes: 1 addition & 1 deletion Catalog/INV.cell
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
a Not (or Inverter) gate
.DESCRIPTION a Not (or Inverter) gate
.cell INV
.inputs A
.outputs Y
Expand Down
15 changes: 8 additions & 7 deletions Catalog/NAND2.cell
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
.DESCRIPTION "a 2-input Not-AND (or NAND) gate"
.SEE_ALSO "NAND3 - a 3-input Not-AND (or NAND) gate"
.ORDER "Gate Drain Source MOSFET"
A Y vdd pmos
B Y vdd pmos
A Y 2 nmos
B 2 gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y vdd
pmos B Y vdd
nmos A Y 1
nmos B 1 gnd
19 changes: 9 additions & 10 deletions Catalog/NAND3.cell
Original file line number Diff line number Diff line change
@@ -1,11 +1,10 @@
a 3-input Not-AND (or NAND) gate
.cell NAND3
.inputs C B A
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B C
.outputs Y
pmos C Y vdd vdd 1 1 1
pmos B Y vdd vdd 1 2 1
pmos A Y vdd vdd 1 3 1
nmos A Y 2 gnd 1 1 -1
nmos B 2 4 gnd 2 1 -2
nmos C 4 gnd gnd 3 1 -3
.end
.ORDER "MOSFET Gate Drain Source"
pmos A Y vdd
pmos B Y vdd
pmos C Y vdd
nmos A Y 1
nmos B 1 2
nmos C 2 gnd
15 changes: 8 additions & 7 deletions Catalog/NOR2.cell
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
.DESCRIPTION "a 2-input Not-OR (or NOR) gate"
.SEE_ALSO "NOR3 - a 3-input Not-OR (or NOR) gate"
.ORDER "Gate Drain Source MOSFET"
A Y 1 pmos
B 1 vdd pmos
A Y gnd nmos
B Y gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y 1
pmos B 1 vdd
nmos A Y gnd
nmos B Y gnd
19 changes: 10 additions & 9 deletions Catalog/NOR3.cell
Original file line number Diff line number Diff line change
@@ -1,9 +1,10 @@
.DESCRIPTION "a 3-input Not-OR (or NOR) gate"
.SEE_ALSO "NOR2 - a 2-input Not-OR (or NOR) gate"
.ORDER "Gate Drain Source MOSFET"
A Y 1 pmos
B 1 3 pmos
C 3 vdd pmos
A Y gnd nmos
B Y gnd nmos
C Y gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B C
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y 1
pmos B 1 2
pmos C 2 vdd
nmos A Y gnd
nmos B Y gnd
nmos C Y gnd
17 changes: 8 additions & 9 deletions Catalog/OAI21.cell
Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
.DESCRIPTION "a 2-1-input OR-AND-Invert gate"
.SEE_ALSO "OAI21 - a 2-1-input OR-AND-Invert gate"
.ORDER "Gate Drain Source MOSFET"
A Y vdd pmos
B Y 1 pmos
B1 1 vdd pmos
A Y 2 nmos
B 2 gnd nmos
B1 2 gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A A1
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y 1
pmos A1 1 vdd
nmos A Y gnd
nmos A1 Y gnd
20 changes: 11 additions & 9 deletions Catalog/OAI31.cell
Original file line number Diff line number Diff line change
@@ -1,11 +1,13 @@
.DESCRIPTION "a 3-1-input OR-AND-Invert gate"
.SEE_ALSO "OAI31 - a 3-1-input OR-AND-Invert gate"
.ORDER "Gate Drain Source MOSFET"
A Y vdd pmos
B Y 1 pmos
B1 1 3 pmos
B2 3 vdd pmos
A Y 2 nmos
B 2 gnd nmos
B1 2 gnd nmos
B2 2 gnd nmos
.inputs A B B1 B2
.outputs Y
.ORDER "MOSFET Gate Drain Source"
pmos A Y vdd
pmos B Y 1
pmos B1 1 3
pmos B2 3 vdd
nmos A Y 2
nmos B 2 gnd
nmos B1 2 gnd
nmos B2 2 gnd
27 changes: 14 additions & 13 deletions Catalog/OR4.cell
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
.DESCRIPTION "a 4-input OR gate"
.SEE_ALSO "NOR3 - a 3-input Not-OR (or NOR) gate"
.ORDER "Gate Drain Source MOSFET"
A Y 1 pmos
B 1 3 pmos
C 3 5 pmos
D 5 vdd pmos
Y Z vdd pmos
A Y gnd nmos
B Y gnd nmos
C Y gnd nmos
D Y gnd nmos
Y Z gnd nmos
.AUTOGENERATED by Popcorn Tcl Script
.inputs A B C D
.outputs Z
.ORDER "MOSFET Gate Drain Source"
pmos A Y 1
pmos B 1 2
pmos C 2 3
pmos D 3 vdd
pmos Y Z vdd
nmos A Y gnd
nmos B Y gnd
nmos C Y gnd
nmos D Y gnd
nmos Y Z gnd
8 changes: 8 additions & 0 deletions Catalog/doc/GNUmakefile
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
all:
./docu.sh

clean:
rm -f *_schematic.tex cells.tex
rm -f *.aux *.idx *.log *.toc *.pdf *.png *.svg *_svg.tex
killall -q pdflatex || true

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