It might be nice to have optional emulation of the VeeR MRAC RISC-V CSR: https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/memory-map.html#region-access-control-register-mrac

I think this would be best implemented as a RootBus wrapper, that takes an inner RootBus that it delegates certain reads and writes to.

At least as far as we should honor two aspects:

• If a region of the memory map is set to side effect, then we allow 32-bit level access to the correct word always (but disallow non-aligned access to 8-bit or 16-bit) that is passed through to the inner RootBus.
• If a region is set to cachable, then the outer RootBus accepts any 8, 16, or 32-bit access with any alignment, but always does 64-bit access to the inner RootBus (translated as two 32-bit accesses)

Notably, I would expect two consequences of this:

1. Non-aligned access to a memory should fail if it is set to side-effect
2. If side effect is not turned on correctly for the mailbox, then its lock will probably not work (since the user locking register is adjacent to another register).

However, I also fear that enabling MRAC emulation might break a lot of things, so maybe we should leave it off by default.