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[style] migrate scalafmt.conf and reformat the world
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6 files changed

+50
-52
lines changed

6 files changed

+50
-52
lines changed

‎templates/chisel/.scalafmt.conf‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,21 +2,19 @@ version = "3.7.15"
22
runner.dialect = scala213
33

44
maxColumn = 120
5-
align = most
6-
continuationIndent.defnSite = 2
5+
align.preset = most
6+
indent.defnSite = 2
77
assumeStandardLibraryStripMargin = true
88
docstrings.style = SpaceAsterisk
99
lineEndings = preserve
1010
includeCurlyBraceInSelectChains = false
1111
danglingParentheses.preset = true
1212

13-
align.tokens."+" = [
14-
{
15-
code = ":"
16-
}
17-
]
13+
align.tokens."+" = [{
14+
code = ":"
15+
}]
1816

19-
newlines.beforeCurlyLambdaParams = never
17+
newlines.beforeCurlyLambdaParams = "never"
2018
newlines.alwaysBeforeMultilineDef = false
2119
newlines.implicitParamListModifierForce = [before]
2220

‎templates/chisel/elaborator/src/GCD.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ object GCDMain extends SerializableModuleElaborator {
1616

1717
@main
1818
case class GCDParameterMain(
19-
@arg(name = "width") width: Int,
19+
@arg(name = "width") width: Int,
2020
@arg(name = "useAsyncReset") useAsyncReset: Boolean) {
2121
require(width > 0, "width must be a non-negative integer")
2222
require(chisel3.util.isPow2(width), "width must be a power of 2")

‎templates/chisel/elaborator/src/GCDTestBench.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ object GCDTestBenchMain extends SerializableModuleElaborator {
2020
@arg(name = "testVerbatimParameter") testVerbatimParameter: TestVerbatimParameterMain,
2121
@arg(name = "gcdParameter") gcdParameter: GCDParameterMain,
2222
@arg(name = "timeout") timeout: Int,
23-
@arg(name = "testSize") testSize: Int) {
23+
@arg(name = "testSize") testSize: Int) {
2424
def convert: GCDTestBenchParameter = GCDTestBenchParameter(
2525
testVerbatimParameter.convert,
2626
gcdParameter.convert,
@@ -34,7 +34,7 @@ object GCDTestBenchMain extends SerializableModuleElaborator {
3434
@arg(name = "initFunctionName") initFunctionName: String,
3535
@arg(name = "dumpFunctionName") dumpFunctionName: String,
3636
@arg(name = "clockFlipTick") clockFlipTick: Int,
37-
@arg(name = "resetFlipTick") resetFlipTick: Int) {
37+
@arg(name = "resetFlipTick") resetFlipTick: Int) {
3838
def convert: TestVerbatimParameter = TestVerbatimParameter(
3939
useAsyncReset: Boolean,
4040
initFunctionName: String,

‎templates/chisel/gcd/src/GCD.scala‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -26,23 +26,23 @@ class GCDProbe(parameter: GCDParameter) extends Bundle {
2626
/** Metadata of [[GCD]]. */
2727
@instantiable
2828
class GCDOM(parameter: GCDParameter) extends Class {
29-
val width: Property[Int] = IO(Output(Property[Int]()))
29+
val width: Property[Int] = IO(Output(Property[Int]()))
3030
val useAsyncReset: Property[Boolean] = IO(Output(Property[Boolean]()))
31-
width := Property(parameter.width)
31+
width := Property(parameter.width)
3232
useAsyncReset := Property(parameter.useAsyncReset)
3333
}
3434

3535
/** Interface of [[GCD]]. */
3636
class GCDInterface(parameter: GCDParameter) extends Bundle {
37-
val clock = Input(Clock())
38-
val reset = Input(if (parameter.useAsyncReset) AsyncReset() else Bool())
39-
val input = Flipped(DecoupledIO(new Bundle {
37+
val clock = Input(Clock())
38+
val reset = Input(if (parameter.useAsyncReset) AsyncReset() else Bool())
39+
val input = Flipped(DecoupledIO(new Bundle {
4040
val x = UInt(parameter.width.W)
4141
val y = UInt(parameter.width.W)
4242
}))
4343
val output = Valid(UInt(parameter.width.W))
44-
val probe = Output(Probe(new GCDProbe(parameter), layers.Verification))
45-
val om = Output(Property[AnyClassType]())
44+
val probe = Output(Probe(new GCDProbe(parameter), layers.Verification))
45+
val om = Output(Property[AnyClassType]())
4646
}
4747

4848
/** Hardware Implementation of GCD */
@@ -59,18 +59,18 @@ class GCD(val parameter: GCDParameter)
5959
// Block X-state propagation
6060
val y: UInt = RegInit(chiselTypeOf(io.input.bits.x), 0.U)
6161
val startupFlag = RegInit(false.B)
62-
val busy = y =/= 0.U
62+
val busy = y =/= 0.U
6363

6464
when(x > y) { x := x - y }.otherwise { y := y - x }
6565

6666
when(io.input.fire) {
67-
x := io.input.bits.x
68-
y := io.input.bits.y
67+
x := io.input.bits.x
68+
y := io.input.bits.y
6969
startupFlag := true.B
7070
}
7171

72-
io.input.ready := !busy
73-
io.output.bits := x
72+
io.input.ready := !busy
73+
io.output.bits := x
7474
io.output.valid := startupFlag && !busy
7575

7676
// Assign Probe

‎templates/chisel/gcd/src/GCDFormal.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ case class GCDFormalParameter(gcdParameter: GCDParameter) extends SerializableMo
2424

2525
@instantiable
2626
class GCDFormalOM(parameter: GCDFormalParameter) extends Class {
27-
val gcd = IO(Output(Property[AnyClassType]()))
27+
val gcd = IO(Output(Property[AnyClassType]()))
2828
@public
2929
val gcdIn = IO(Input(Property[AnyClassType]()))
3030
gcd := gcdIn
@@ -37,7 +37,7 @@ class GCDFormalInterface(parameter: GCDFormalParameter) extends Bundle {
3737
val x = UInt(parameter.gcdParameter.width.W)
3838
val y = UInt(parameter.gcdParameter.width.W)
3939
}))
40-
val om = Output(Property[AnyClassType]())
40+
val om = Output(Property[AnyClassType]())
4141
}
4242

4343
@instantiable
@@ -46,13 +46,13 @@ class GCDFormal(val parameter: GCDFormalParameter)
4646
with SerializableModule[GCDFormalParameter]
4747
with ImplicitClock
4848
with ImplicitReset {
49-
override protected def implicitClock: Clock = io.clock
50-
override protected def implicitReset: Reset = io.reset
49+
override protected def implicitClock: Clock = io.clock
50+
override protected def implicitReset: Reset = io.reset
5151
// Instantiate DUT.
52-
val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter))
52+
val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter))
5353
// Instantiate OM
5454
val omInstance = Instantiate(new GCDFormalOM(parameter))
55-
io.om := omInstance.getPropertyReference.asAnyClassType
55+
io.om := omInstance.getPropertyReference.asAnyClassType
5656
omInstance.gcdIn := dut.io.om
5757

5858
dut.io.clock := implicitClock
@@ -66,7 +66,7 @@ class GCDFormal(val parameter: GCDFormalParameter)
6666
val outputNotFire: Sequence = !dut.io.output.valid
6767
val inputNotValid: Sequence = dut.io.input.ready && !dut.io.input.valid
6868

69-
dut.io.input.bits := io.input.bits
69+
dut.io.input.bits := io.input.bits
7070
dut.io.input.valid := io.input.valid
7171

7272
AssumeProperty(

‎templates/chisel/gcd/src/GCDTestBench.scala‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ case class GCDTestBenchParameter(
3333

3434
@instantiable
3535
class GCDTestBenchOM(parameter: GCDTestBenchParameter) extends Class {
36-
val gcd = IO(Output(Property[AnyClassType]()))
36+
val gcd = IO(Output(Property[AnyClassType]()))
3737
@public
3838
val gcdIn = IO(Input(Property[AnyClassType]()))
3939
gcd := gcdIn
@@ -48,18 +48,18 @@ class GCDTestBench(val parameter: GCDTestBenchParameter)
4848
extends FixedIORawModule(new GCDTestBenchInterface(parameter))
4949
with SerializableModule[GCDTestBenchParameter]
5050
with ImplicitClock
51-
with ImplicitReset {
52-
override protected def implicitClock: Clock = verbatim.io.clock
53-
override protected def implicitReset: Reset = verbatim.io.reset
51+
with ImplicitReset {
52+
override protected def implicitClock: Clock = verbatim.io.clock
53+
override protected def implicitReset: Reset = verbatim.io.reset
5454
// Instantiate Drivers
55-
val verbatim: Instance[TestVerbatim] = Instantiate(
55+
val verbatim: Instance[TestVerbatim] = Instantiate(
5656
new TestVerbatim(parameter.testVerbatimParameter)
5757
)
5858
// Instantiate DUT.
59-
val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter))
59+
val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter))
6060
// Instantiate OM
6161
val omInstance = Instantiate(new GCDTestBenchOM(parameter))
62-
io.om := omInstance.getPropertyReference.asAnyClassType
62+
io.om := omInstance.getPropertyReference.asAnyClassType
6363
omInstance.gcdIn := dut.io.om
6464

6565
dut.io.clock := implicitClock
@@ -70,13 +70,13 @@ class GCDTestBench(val parameter: GCDTestBenchParameter)
7070
simulationTime := simulationTime + 1.U
7171
// For each timeout ticks, check it
7272
val (_, callWatchdog) = Counter(true.B, parameter.timeout / 2)
73-
val watchdogCode = RawUnclockedNonVoidFunctionCall("gcd_watchdog", UInt(8.W))(callWatchdog)
73+
val watchdogCode = RawUnclockedNonVoidFunctionCall("gcd_watchdog", UInt(8.W))(callWatchdog)
7474
when(watchdogCode =/= 0.U) {
7575
stop(cf"""{"event":"SimulationStop","reason": ${watchdogCode},"cycle":${simulationTime}}\n""")
7676
}
7777
class TestPayload extends Bundle {
78-
val x = UInt(parameter.gcdParameter.width.W)
79-
val y = UInt(parameter.gcdParameter.width.W)
78+
val x = UInt(parameter.gcdParameter.width.W)
79+
val y = UInt(parameter.gcdParameter.width.W)
8080
val result = UInt(parameter.gcdParameter.width.W)
8181
}
8282
val request =
@@ -86,10 +86,10 @@ class GCDTestBench(val parameter: GCDTestBenchParameter)
8686
)
8787
when(dut.io.input.ready) {
8888
dut.io.input.valid := request.valid
89-
dut.io.input.bits := request.bits
89+
dut.io.input.bits := request.bits
9090
}.otherwise {
9191
dut.io.input.valid := false.B;
92-
dut.io.input.bits := DontCare;
92+
dut.io.input.bits := DontCare;
9393
}
9494

9595
// LTL Checker
@@ -98,7 +98,7 @@ class GCDTestBench(val parameter: GCDTestBenchParameter)
9898
val inputNotFire: Sequence = !dut.io.input.fire
9999
val outputFire: Sequence = dut.io.output.valid
100100
val outputNotFire: Sequence = !dut.io.output.valid
101-
val lastRequestResult: UInt = RegEnable(request.bits.result, dut.io.input.fire)
101+
val lastRequestResult: UInt = RegEnable(request.bits.result, dut.io.input.fire)
102102
val checkRight: Sequence = lastRequestResult === dut.io.output.bits
103103
val inputNotValid: Sequence = dut.io.input.ready && !dut.io.input.valid
104104

@@ -140,19 +140,19 @@ case class TestVerbatimParameter(
140140
@instantiable
141141
class TestVerbatimOM(parameter: TestVerbatimParameter) extends Class {
142142
val useAsyncReset: Property[Boolean] = IO(Output(Property[Boolean]()))
143-
val initFunctionName: Property[String] = IO(Output(Property[String]()))
144-
val dumpFunctionName: Property[String] = IO(Output(Property[String]()))
145-
val clockFlipTick: Property[Int] = IO(Output(Property[Int]()))
146-
val resetFlipTick: Property[Int] = IO(Output(Property[Int]()))
147-
val gcd = IO(Output(Property[AnyClassType]()))
143+
val initFunctionName: Property[String] = IO(Output(Property[String]()))
144+
val dumpFunctionName: Property[String] = IO(Output(Property[String]()))
145+
val clockFlipTick: Property[Int] = IO(Output(Property[Int]()))
146+
val resetFlipTick: Property[Int] = IO(Output(Property[Int]()))
147+
val gcd = IO(Output(Property[AnyClassType]()))
148148
@public
149149
val gcdIn = IO(Input(Property[AnyClassType]()))
150-
gcd := gcdIn
151-
useAsyncReset := Property(parameter.useAsyncReset)
150+
gcd := gcdIn
151+
useAsyncReset := Property(parameter.useAsyncReset)
152152
initFunctionName := Property(parameter.initFunctionName)
153153
dumpFunctionName := Property(parameter.dumpFunctionName)
154-
clockFlipTick := Property(parameter.clockFlipTick)
155-
resetFlipTick := Property(parameter.resetFlipTick)
154+
clockFlipTick := Property(parameter.clockFlipTick)
155+
resetFlipTick := Property(parameter.resetFlipTick)
156156
}
157157

158158
/** Test blackbox for clockgen, wave dump and extra testbench-only codes. */

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