From 8e3bf6498cc45e148c60dcb63f38fbd9a4060d2a Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 11 Jul 2024 13:37:33 +0200 Subject: [PATCH 01/12] run: fix disabling the `c` extension This commit fixes the way that the `c` extension is disabled, i.e. removed from the arch ISA string. Without this change, for GCC versions where Zicsr and Zifencei constitute separate extensions, the following ISA string: rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs Would be changed to (note incorrect `_zisr` vs correct `_zicsr`): rv32im_zisr_zifenei_zba_zbb_zb_zbs Instead of the expected: rv32im_zicsr_zifencei_zba_zbb_zbc_zbs Signed-off-by: Filip Kokosinski --- run.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/run.py b/run.py index ac323177..a775ecce 100644 --- a/run.py +++ b/run.py @@ -446,7 +446,12 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd): if 'gen_opts' in test: # Disable compressed instruction if re.search('disable_compressed_instr', test['gen_opts']): - test_isa = re.sub("c", "", test_isa) + # Note that this substitution assumes the cannonical order + # of extensions, i.e. that extensions with preceding + # underscores will be provided after all letter extensions. + # This assumption should hold true, as this is a + # requirement enforced by e.g. gcc + test_isa = re.sub(r"(rv.+?)c", r"\1", test_isa) # If march/mabi is not defined in the test gcc_opts, use the default # setting from the command line. if not re.search('march', cmd): From ec43dcf100d36207ed55b003258fb5ed896c2129 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Fri, 12 Jul 2024 10:31:54 +0200 Subject: [PATCH 02/12] scripts/lib: increase the deafult timeout to 1 hour Signed-off-by: Filip Kokosinski --- scripts/lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/lib.py b/scripts/lib.py index ef9744da..a12cbc08 100644 --- a/scripts/lib.py +++ b/scripts/lib.py @@ -88,7 +88,7 @@ def get_env_var(var, debug_cmd=None): return val -def run_cmd(cmd, timeout_s=999, exit_on_error=1, check_return_code=True, +def run_cmd(cmd, timeout_s=3600, exit_on_error=1, check_return_code=True, debug_cmd=None): """Run a command and return output From f6fcdc2b624b59117948f2ddbb47e470b1f7173d Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Fri, 21 Jun 2024 11:46:51 +0200 Subject: [PATCH 03/12] allow specifying privilege modes for simulation --- run.py | 13 +++++++++---- yaml/iss.yaml | 4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/run.py b/run.py index a775ecce..e973cc22 100644 --- a/run.py +++ b/run.py @@ -124,13 +124,14 @@ def get_generator_cmd(simulator, simulator_yaml, cov, exp, debug_cmd): sys.exit(RET_FAIL) -def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd): +def parse_iss_yaml(iss, iss_yaml, isa, priv, setting_dir, debug_cmd): """Parse ISS YAML to get the simulation command Args: iss : target ISS used to look up in ISS YAML iss_yaml : ISS configuration file in YAML format isa : ISA variant passed to the ISS + priv: : privilege modes setting_dir : Generator setting directory debug_cmd : Produce the debug cmd log without running @@ -169,6 +170,7 @@ def parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd): cmd = re.sub("\", variant, cmd) else: cmd = re.sub("\", isa, cmd) + cmd = re.sub("\", priv, cmd) cmd = re.sub("\", scripts_dir, cmd) cmd = re.sub("\", yaml_dir, cmd) return cmd @@ -650,7 +652,7 @@ def run_c_from_dir(c_test_dir, iss_yaml, isa, mabi, gcc_opts, iss, def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts, - isa, setting_dir, timeout_s, debug_cmd): + isa, priv, setting_dir, timeout_s, debug_cmd): """Run ISS simulation with the generated test program Args: @@ -660,13 +662,14 @@ def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts, iss_yaml : ISS configuration file in YAML format iss_opts : ISS command line options isa : ISA variant passed to the ISS + priv : privilege modes setting_dir : Generator setting directory timeout_s : Timeout limit in seconds debug_cmd : Produce the debug cmd log without running """ for iss in iss_list.split(","): log_dir = ("{}/{}_sim".format(output_dir, iss)) - base_cmd = parse_iss_yaml(iss, iss_yaml, isa, setting_dir, debug_cmd) + base_cmd = parse_iss_yaml(iss, iss_yaml, isa, priv, setting_dir, debug_cmd) logging.info("{} sim log dir: {}".format(iss, log_dir)) run_cmd_output(["mkdir", "-p", log_dir]) for test in test_list: @@ -823,6 +826,8 @@ def parse_args(cwd): command is not specified") parser.add_argument("--isa", type=str, default="", help="RISC-V ISA subset") + parser.add_argument("--priv", type=str, default="", + help="RISC-V privilege modes enabled in simulation [su]") parser.add_argument("-m", "--mabi", type=str, default="", help="mabi used for compilation", dest="mabi") parser.add_argument("--gen_timeout", type=int, default=360, @@ -1156,7 +1161,7 @@ def main(): if args.steps == "all" or re.match(".*iss_sim.*", args.steps): iss_sim(matched_list, output_dir, args.iss, args.iss_yaml, args.iss_opts, - args.isa, args.core_setting_dir, args.iss_timeout, + args.isa, args.priv, args.core_setting_dir, args.iss_timeout, args.debug) # Compare ISS simulation result diff --git a/yaml/iss.yaml b/yaml/iss.yaml index ecf3224a..502e1137 100644 --- a/yaml/iss.yaml +++ b/yaml/iss.yaml @@ -15,7 +15,7 @@ - iss: spike path_var: SPIKE_PATH cmd: > - /spike --log-commits --isa= --misaligned -l + /spike --log-commits --isa= --priv=m --misaligned -l - iss: ovpsim path_var: OVPSIM_PATH @@ -35,7 +35,7 @@ - iss: whisper path_var: WHISPER_ISS cmd: > - --log --xlen --isa --configfile /whisper.json --iccmrw + --log --xlen --isa --configfile /whisper.json --iccmrw - iss: renode path_var: RENODE_PATH From 15c80f10ee1eadcf8da3caef62e5e0ea26e63444 Mon Sep 17 00:00:00 2001 From: Mateusz Karlic Date: Wed, 21 Aug 2024 14:39:57 +0200 Subject: [PATCH 04/12] Pass custom params to ISS Signed-off-by: Mateusz Karlic --- run.py | 1 + 1 file changed, 1 insertion(+) diff --git a/run.py b/run.py index e973cc22..5f364fcf 100644 --- a/run.py +++ b/run.py @@ -670,6 +670,7 @@ def iss_sim(test_list, output_dir, iss_list, iss_yaml, iss_opts, for iss in iss_list.split(","): log_dir = ("{}/{}_sim".format(output_dir, iss)) base_cmd = parse_iss_yaml(iss, iss_yaml, isa, priv, setting_dir, debug_cmd) + base_cmd += iss_opts logging.info("{} sim log dir: {}".format(iss, log_dir)) run_cmd_output(["mkdir", "-p", log_dir]) for test in test_list: From 7a76cf35a7fdea4c126433c47b03064295e5c719 Mon Sep 17 00:00:00 2001 From: Mateusz Karlic Date: Wed, 21 Aug 2024 14:40:13 +0200 Subject: [PATCH 05/12] renode_wrapper: Make CPU type configurable Signed-off-by: Mateusz Karlic --- scripts/renode_wrapper.py | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/scripts/renode_wrapper.py b/scripts/renode_wrapper.py index 4f56d582..6e91c278 100644 --- a/scripts/renode_wrapper.py +++ b/scripts/renode_wrapper.py @@ -10,11 +10,11 @@ memory: Memory.MappedMemory @ sysbus 0x80000000 size: {mem} -cpu: CPU.RiscV32 @ sysbus +cpu: CPU.{cpu_type} @ sysbus cpuType: "{isa}" timeProvider: clint hartId: 0 - allowUnalignedAccesses: true + {additional_cpu_parameters} clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 [0,1] -> cpu@[3,7] @@ -77,6 +77,20 @@ def main(): default="0x100000", help="Memory size", ) + parser.add_argument( + "--cpu-type", + type=str, + default="Riscv32", + help="Renode CPU type", + ) + # Some CPUs might not expose these parameters as configurable + # allow the testing software to ignore/override them if needed + parser.add_argument( + "--additional-cpu-parameters", + type=str, + default="allowUnalignedAccesses: true", + help="Additional CPU parameters", + ) args = parser.parse_args() @@ -93,6 +107,8 @@ def main(): "resc": resc, "log": args.log, "mem": args.mem_size, + "cpu_type": args.cpu_type, + "additional_cpu_parameters": args.additional_cpu_parameters, } # Render REPL template From 962250463d30b0be9fdb1002eb6fe2bbc96981ec Mon Sep 17 00:00:00 2001 From: Mateusz Karlic Date: Fri, 23 Aug 2024 09:03:28 +0200 Subject: [PATCH 06/12] renode_wrapper: Add configurable priv levels --- scripts/renode_wrapper.py | 18 ++++++++++++++++++ yaml/iss.yaml | 2 +- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/scripts/renode_wrapper.py b/scripts/renode_wrapper.py index 6e91c278..16c097f4 100644 --- a/scripts/renode_wrapper.py +++ b/scripts/renode_wrapper.py @@ -14,6 +14,7 @@ cpuType: "{isa}" timeProvider: clint hartId: 0 + {priv_levels} {additional_cpu_parameters} clint: IRQControllers.CoreLevelInterruptor @ sysbus 0x02000000 @@ -83,6 +84,12 @@ def main(): default="Riscv32", help="Renode CPU type", ) + parser.add_argument( + "--priv", + type=str, + default="", + help="Supported privilege levels", + ) # Some CPUs might not expose these parameters as configurable # allow the testing software to ignore/override them if needed parser.add_argument( @@ -99,6 +106,16 @@ def main(): repl = os.path.join(tmpdir, "riscv.repl") resc = os.path.join(tmpdir, "riscv.resc") + priv_levels = "" + if args.priv: + priv_levels += "privilegeLevels: PrivilegeLevels." + if "m" in args.priv: + priv_levels += "Machine" + if "s" in args.priv: + priv_levels += "Supervisor" + if "u" in args.priv: + priv_levels += "User" + params = { "renode": args.renode, "isa": args.isa, @@ -108,6 +125,7 @@ def main(): "log": args.log, "mem": args.mem_size, "cpu_type": args.cpu_type, + "priv_levels": priv_levels, "additional_cpu_parameters": args.additional_cpu_parameters, } diff --git a/yaml/iss.yaml b/yaml/iss.yaml index 502e1137..fd1d92e1 100644 --- a/yaml/iss.yaml +++ b/yaml/iss.yaml @@ -40,4 +40,4 @@ - iss: renode path_var: RENODE_PATH cmd: > - python3 /renode_wrapper.py --renode "" --elf --isa --mem-size 0x80000000 + python3 /renode_wrapper.py --renode "" --elf --isa --priv=m --mem-size 0x80000000 From 9a6587a6a351feb668c0252e3278b47358fc5e87 Mon Sep 17 00:00:00 2001 From: Mateusz Karlic Date: Fri, 23 Aug 2024 09:08:19 +0200 Subject: [PATCH 07/12] iss.yaml: Remove 'm' hack --- yaml/iss.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/yaml/iss.yaml b/yaml/iss.yaml index fd1d92e1..1167d7fd 100644 --- a/yaml/iss.yaml +++ b/yaml/iss.yaml @@ -15,7 +15,7 @@ - iss: spike path_var: SPIKE_PATH cmd: > - /spike --log-commits --isa= --priv=m --misaligned -l + /spike --log-commits --isa= --priv= --misaligned -l - iss: ovpsim path_var: OVPSIM_PATH @@ -40,4 +40,4 @@ - iss: renode path_var: RENODE_PATH cmd: > - python3 /renode_wrapper.py --renode "" --elf --isa --priv=m --mem-size 0x80000000 + python3 /renode_wrapper.py --renode "" --elf --isa --priv= --mem-size 0x80000000 From 2c319b805fd1a5fa19b9f481362fe71d8d003f60 Mon Sep 17 00:00:00 2001 From: Mateusz Karlic Date: Wed, 28 Aug 2024 11:59:57 +0200 Subject: [PATCH 08/12] instr_trace_compare: Add additional mismatch print Signed-off-by: Mateusz Karlic --- scripts/instr_trace_compare.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/instr_trace_compare.py b/scripts/instr_trace_compare.py index b0fd3e88..61566538 100644 --- a/scripts/instr_trace_compare.py +++ b/scripts/instr_trace_compare.py @@ -125,6 +125,8 @@ def compare_trace_csv(csv1, csv2, name1, name2, log, instr_trace_2[trace_2_index].gpr, gpr_val_2) if gpr_state_change_2 == 1: + fd.write("Mismatch[{}]:\n[{}] {} : {}\n".format( + mismatch_cnt, trace_1_index, name1,trace.get_trace_string())) fd.write("{} instructions left in trace {}\n".format( len(instr_trace_2) - trace_2_index, name2)) mismatch_cnt += len(instr_trace_2) - trace_2_index From 68d6777599747ef9a4252a12b26181fd74d57804 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Wed, 5 Feb 2025 13:19:38 +0100 Subject: [PATCH 09/12] workflows: Update upload-artifacts to v4 Signed-off-by: Wiktoria Kuna --- .github/workflows/build-spike.yml | 2 +- .github/workflows/run-tests.yml | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/.github/workflows/build-spike.yml b/.github/workflows/build-spike.yml index 442e825e..59fbfffb 100644 --- a/.github/workflows/build-spike.yml +++ b/.github/workflows/build-spike.yml @@ -36,7 +36,7 @@ jobs: key: ${{ env.cache_name }}_${{ env.cache_date }} restore-keys: ${{ env.cache_name }}_ - - name: Install prerequisities + - name: Install prerequisites if: ${{ steps.cache.outputs.cache-hit != 'true' }} run: | sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \ diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml index dd93d0cf..e0128d4d 100644 --- a/.github/workflows/run-tests.yml +++ b/.github/workflows/run-tests.yml @@ -27,7 +27,7 @@ jobs: name: Prepare files' hash run: | echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\ -f1 | sha256sum | cut -d\ -f1)" | tee -a $GITHUB_OUTPUT - + generate-code: runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] @@ -39,7 +39,7 @@ jobs: test: ${{ fromJSON(needs.generate-config.outputs.test-types) }} version: [ uvm ] include: - - test: riscv_arithmetic_basic_test + - test: riscv_arithmetic_basic_test version: pyflow env: GHA_EXTERNAL_DISK: additional-tools @@ -89,9 +89,10 @@ jobs: --isa $RISCV_TARGET --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log - name: Upload Artifacts - uses: actions/upload-artifact@v3 + uses: actions/upload-artifact@v4 if: always() with: + name: generate_code_${{ matrix.test }}_${{ matrix.version }} path: | test/asm_test/*.S @@ -174,9 +175,10 @@ jobs: --isa $RISCV_TARGET --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log - name: Upload Artifacts - uses: actions/upload-artifact@v3 + uses: actions/upload-artifact@v4 if: always() with: + name: run_tests_log_${{ matrix.test }}_${{ matrix.version }} path: | test/asm_test/*.log test/*.log From 24794088632250ee5e39ed54558aee541d4700a7 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Wed, 5 Feb 2025 15:25:22 +0100 Subject: [PATCH 10/12] workflows: Preserve errors when generating config Signed-off-by: Wiktoria Kuna --- .github/workflows/run-tests.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml index e0128d4d..640e966b 100644 --- a/.github/workflows/run-tests.yml +++ b/.github/workflows/run-tests.yml @@ -22,11 +22,13 @@ jobs: name: Prepare test types run: | python3 -m pip install pyyaml - echo "tests=$(python3 .github/scripts/parse_testlist.py $RISCV_TARGET)" | tee -a $GITHUB_OUTPUT + python3 .github/scripts/parse_testlist.py $RISCV_TARGET > tests.list + echo "tests=$(cat tests.list)" | tee -a $GITHUB_OUTPUT - id: hash name: Prepare files' hash run: | - echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\ -f1 | sha256sum | cut -d\ -f1)" | tee -a $GITHUB_OUTPUT + sha256sum **/*.sv **/*.py **/*.yaml > file.hash + echo "files-hash=$(cat file.hash | cut -d\ -f1 | sha256sum | cut -d\ -f1)" | tee -a $GITHUB_OUTPUT generate-code: From 6f8e566e3417ce79c43cbacb4e5c89f5fd49c693 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Thu, 6 Feb 2025 13:05:38 +0100 Subject: [PATCH 11/12] workflows: Update RISCV toolchain & add 'Z' ext Some of the 'I' ext instructions were once moved to separate Zicsr and Zifencei extensions. For newer toolchains the 'Z' extensions need to be explicitly requested in '-march'. Signed-off-by: Wiktoria Kuna --- .github/workflows/run-tests.yml | 9 ++++++++- run.py | 26 +++++++++++++------------- 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml index 640e966b..1bfca1db 100644 --- a/.github/workflows/run-tests.yml +++ b/.github/workflows/run-tests.yml @@ -119,7 +119,14 @@ jobs: - uses: actions/checkout@v4 - name: Install dependencies - run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler + run: sudo apt-get -qqy update && sudo apt-get -qqy install device-tree-compiler + + - name: Install cross-compiler + shell: bash + run: | + echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null + sudo apt -qqy update && sudo apt -qqy --no-install-recommends install gcc-riscv64-unknown-elf + riscv64-unknown-elf-gcc --version - name: Setup python # python dependencies cannot be properly downloaded with new versions of python diff --git a/run.py b/run.py index 5f364fcf..4097c9f6 100644 --- a/run.py +++ b/run.py @@ -827,7 +827,7 @@ def parse_args(cwd): command is not specified") parser.add_argument("--isa", type=str, default="", help="RISC-V ISA subset") - parser.add_argument("--priv", type=str, default="", + parser.add_argument("--priv", type=str, default="m", help="RISC-V privilege modes enabled in simulation [su]") parser.add_argument("-m", "--mabi", type=str, default="", help="mabi used for compilation", dest="mabi") @@ -951,40 +951,40 @@ def load_config(args, cwd): args.core_setting_dir = cwd + "/target/" + args.target if args.target == "rv32imc": args.mabi = "ilp32" - args.isa = "rv32imc" + args.isa = "rv32imc_zicsr_zifencei" elif args.target == "rv32imafdc": args.mabi = "ilp32" - args.isa = "rv32imafdc" + args.isa = "rv32imafdc_zicsr_zifencei" elif args.target == "rv32imc_sv32": args.mabi = "ilp32" - args.isa = "rv32imc" + args.isa = "rv32imc_zicsr_zifencei" elif args.target == "multi_harts": args.mabi = "ilp32" - args.isa = "rv32gc" + args.isa = "rv32gc_zicsr_zifencei" elif args.target == "rv32imcb": args.mabi = "ilp32" - args.isa = "rv32imcb" + args.isa = "rv32imcb_zicsr_zifencei" elif args.target == "rv32i": args.mabi = "ilp32" - args.isa = "rv32i" + args.isa = "rv32i_zicsr_zifencei" elif args.target == "rv64imc": args.mabi = "lp64" - args.isa = "rv64imc" + args.isa = "rv64imc_zicsr_zifencei" elif args.target == "rv64imcb": args.mabi = "lp64" - args.isa = "rv64imcb" + args.isa = "rv64imcb_zicsr_zifencei" elif args.target == "rv64gc": args.mabi = "lp64" - args.isa = "rv64gc" + args.isa = "rv64gc_zicsr_zifencei" elif args.target == "rv64gcv": args.mabi = "lp64" - args.isa = "rv64gcv" + args.isa = "rv64gcv_zicsr_zifencei" elif args.target == "ml": args.mabi = "lp64" - args.isa = "rv64imc" + args.isa = "rv64imc_zicsr_zifencei" elif args.target == "rv64imafdc": args.mabi = "lp64" - args.isa = "rv64imafdc" + args.isa = "rv64imafdc_zicsr_zifencei" else: sys.exit("Unsupported pre-defined target: {}".format(args.target)) else: From 4bf494fd1f2e8ebba63131ea9dce2e2021f5c573 Mon Sep 17 00:00:00 2001 From: Wiktoria Kuna Date: Thu, 6 Feb 2025 13:18:27 +0100 Subject: [PATCH 12/12] workflows: Fix path to run-tests artifats Signed-off-by: Wiktoria Kuna --- .github/workflows/run-tests.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml index 1bfca1db..7858a706 100644 --- a/.github/workflows/run-tests.yml +++ b/.github/workflows/run-tests.yml @@ -189,5 +189,5 @@ jobs: with: name: run_tests_log_${{ matrix.test }}_${{ matrix.version }} path: | - test/asm_test/*.log test/*.log + test/**/${{ matrix.test }}*.log