From 071d737f9950a3db6c48c73df28a18ea7bcdae9f Mon Sep 17 00:00:00 2001
From: mszelwiga <mszelwiga@internships.antmicro.com>
Date: Tue, 19 Nov 2024 12:13:05 +0100
Subject: [PATCH] Add alias write_ilang -> write_rtlil and update Yosys version

---
 CMakeLists.txt                           |  3 ++-
 src/Makefile                             |  2 +-
 src/frontends/systemverilog/Build.mk     |  3 ++-
 src/frontends/systemverilog/Makefile.inc |  2 ++
 src/mods/yosys_ast/Makefile.inc          |  3 +++
 src/mods/yosys_ast/synlig_write_ilang.cc | 24 ++++++++++++++++++++++++
 third_party/yosys                        |  2 +-
 7 files changed, 35 insertions(+), 4 deletions(-)
 create mode 100644 src/mods/yosys_ast/synlig_write_ilang.cc

diff --git a/CMakeLists.txt b/CMakeLists.txt
index c395cdad3..311e73024 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -263,7 +263,8 @@ set(synlig_SRC
     ${PROJECT_SOURCE_DIR}/src/frontends/systemverilog/uhdm_common_frontend.cc
     ${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_const2ast.cc
     ${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_edif.cc
-    ${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_simplify.cc)
+    ${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_simplify.cc
+    ${PROJECT_SOURCE_DIR}/src/mods/yosys_ast/synlig_write_ilang.cc)
 
 add_library(synlig SHARED ${synlig_SRC})
 
diff --git a/src/Makefile b/src/Makefile
index d7ca5712e..a9054dd7e 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -18,7 +18,7 @@ CONFIG := none
 # CONFIG := gcc
 
 # --- add synlig cxxflags --- #
-CXXFLAGS += -DSYNLIG_STANDALONE_BINARY -I $(SYNLIG_SRC)/frontends/*/ -I $(SYNLIG_SRC)/mods/* -I $(SYNLIG_SRC)/utils
+CXXFLAGS += -DSYNLIG_STANDALONE_BINARY -I $(SYNLIG_SRC)/utils
 
 # --- add static option --- #
 CXXFLAGS += -static
diff --git a/src/frontends/systemverilog/Build.mk b/src/frontends/systemverilog/Build.mk
index 2832f1fce..be9ea8fa7 100644
--- a/src/frontends/systemverilog/Build.mk
+++ b/src/frontends/systemverilog/Build.mk
@@ -16,7 +16,8 @@ ${ts}.sources := \
 	${${ts}.src_dir}uhdm_surelog_ast_frontend.cc \
 	${${ts}.mod_dir}synlig_const2ast.cc \
 	${${ts}.mod_dir}synlig_edif.cc \
-	${${ts}.mod_dir}synlig_simplify.cc
+	${${ts}.mod_dir}synlig_simplify.cc \
+	${${ts}.mod_dir}synlig_write_ilang.cc
 
 define ${ts}.env =
 export PKG_CONFIG_PATH=$(call ShQuote,${$(call GetTargetStructName,surelog).output_vars.PKG_CONFIG_PATH}$(if ${PKG_CONFIG_PATH},:${PKG_CONFIG_PATH}))
diff --git a/src/frontends/systemverilog/Makefile.inc b/src/frontends/systemverilog/Makefile.inc
index b5f129743..492c0460a 100644
--- a/src/frontends/systemverilog/Makefile.inc
+++ b/src/frontends/systemverilog/Makefile.inc
@@ -1,4 +1,6 @@
 
+CXXFLAGS += -I $(SYNLIG_SRC)/frontends/systemverilog
+
 SYNLIG_OBJS += frontends/systemverilog/uhdm_ast.o
 SYNLIG_OBJS += frontends/systemverilog/uhdm_ast_frontend.o
 SYNLIG_OBJS += frontends/systemverilog/uhdm_common_frontend.o
diff --git a/src/mods/yosys_ast/Makefile.inc b/src/mods/yosys_ast/Makefile.inc
index c35e90145..c4808f6d3 100644
--- a/src/mods/yosys_ast/Makefile.inc
+++ b/src/mods/yosys_ast/Makefile.inc
@@ -1,4 +1,7 @@
 
+CXXFLAGS += -I $(SYNLIG_SRC)/mods/yosys_ast
+
 SYNLIG_OBJS += mods/yosys_ast/synlig_const2ast.o
 SYNLIG_OBJS += mods/yosys_ast/synlig_edif.o
 SYNLIG_OBJS += mods/yosys_ast/synlig_simplify.o
+SYNLIG_OBJS += mods/yosys_ast/synlig_write_ilang.o
diff --git a/src/mods/yosys_ast/synlig_write_ilang.cc b/src/mods/yosys_ast/synlig_write_ilang.cc
new file mode 100644
index 000000000..b797ba090
--- /dev/null
+++ b/src/mods/yosys_ast/synlig_write_ilang.cc
@@ -0,0 +1,24 @@
+#include "kernel/yosys.h"
+
+namespace Synlig
+{
+
+using namespace ::Yosys;
+struct WriteIlangAlias : public Pass {
+    WriteIlangAlias() : Pass("write_ilang", "alias for write_rtlil pass") {}
+    void help() override
+    {
+        log_warning("write_ilang pass is an alias for write_rtlil pass.\n\n");
+        run_pass("help write_rtlil");
+    }
+    void execute(std::vector<std::string> args, RTLIL::Design *design) override
+    {
+        log_warning("write_ilang pass is an alias for write_rtlil pass.\n\n");
+        std::string cmd = "write_rtlil";
+        for (int i = 1; i < args.size(); i++)
+            cmd += " " + args[i];
+        run_pass(cmd, design);
+    }
+} WriteIlangAliasPass;
+
+} // namespace Synlig
diff --git a/third_party/yosys b/third_party/yosys
index cef87cc17..b89bd027a 160000
--- a/third_party/yosys
+++ b/third_party/yosys
@@ -1 +1 @@
-Subproject commit cef87cc179dcc45d742cfcd73d5378acb3f4068e
+Subproject commit b89bd027a069dc93a6eab82dd55217c733797f33