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kamilrakoczykamilrakoczy
authored
Update outdated naming (#2686)
This PR updates naming to match `synlig`.
2 parents b65b286 + 9186b02 commit 90f3a82

18 files changed

+53
-52
lines changed

Diff for: ‎src/frontends/systemverilog/uhdm_ast.cc

+10-9
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ extern bool sv_mode;
3030
}
3131
YOSYS_NAMESPACE_END
3232

33-
namespace systemverilog_plugin
33+
namespace Synlig
3434
{
3535

3636
using namespace ::Yosys;
@@ -75,7 +75,7 @@ static IdString enum_struct_item;
7575
/*static*/ const IdString &UhdmAst::low_high_bound() { return attr_id::low_high_bound; }
7676
/*static*/ const IdString &UhdmAst::is_elaborated_module() { return attr_id::is_elaborated_module; }
7777

78-
#define MAKE_INTERNAL_ID(X) IdString("$systemverilog_plugin$" #X)
78+
#define MAKE_INTERNAL_ID(X) IdString("$synlig$" #X)
7979

8080
void attr_id_init()
8181
{
@@ -88,6 +88,7 @@ void attr_id_init()
8888

8989
// Register IdStrings. Can't be done statically, as the IdString class uses resources created during Yosys initialization which happens after
9090
// static initialization of the plugin when everything is statically linked.
91+
// This applies only to Synlig compiled as plugin.
9192
attr_id::partial = MAKE_INTERNAL_ID(partial);
9293
attr_id::packed_ranges = MAKE_INTERNAL_ID(packed_ranges);
9394
attr_id::unpacked_ranges = MAKE_INTERNAL_ID(unpacked_ranges);
@@ -149,7 +150,7 @@ static void delete_attribute(AST::AstNode *node, const IdString &attribute)
149150
}
150151
}
151152

152-
// Delete all attributes that belong to the SV plugin.
153+
// Delete all attributes that belong to the Synlig.
153154
// The attributes beloning to Yosys are *not* deleted here.
154155
static void delete_internal_attributes(AST::AstNode *node)
155156
{
@@ -1371,7 +1372,7 @@ void resolve_children_reparent(AST::AstNode *current_node)
13711372
}
13721373

13731374
// A wrapper for Yosys simplify function.
1374-
// Simplifies AST constructs specific to this plugin to a form understandable by Yosys' simplify and then calls the latter if necessary.
1375+
// Simplifies AST constructs specific to Synlig to a form understandable by Yosys' simplify and then calls the latter if necessary.
13751376
// Since simplify from Yosys has been forked to this codebase, all new code should be added there instead.
13761377
static void simplify_sv(AST::AstNode *current_node, AST::AstNode *parent_node)
13771378
{
@@ -1836,7 +1837,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
18361837
}
18371838
// handle vpiBinStrVal, vpiDecStrVal and vpiHexStrVal
18381839
if (val_str.find('\'') != std::string::npos) {
1839-
return ::systemverilog_plugin::synlig_const2ast(std::move(val_str), caseType, false);
1840+
return ::Synlig::synlig_const2ast(std::move(val_str), caseType, false);
18401841
} else {
18411842
auto size = vpi_get(vpiSize, obj_h);
18421843
std::string size_str;
@@ -1852,7 +1853,7 @@ AST::AstNode *UhdmAst::process_value(vpiHandle obj_h)
18521853
size_str = "1";
18531854
}
18541855
}
1855-
auto c = ::systemverilog_plugin::synlig_const2ast(size_str + strValType + val_str, caseType, false);
1856+
auto c = ::Synlig::synlig_const2ast(size_str + strValType + val_str, caseType, false);
18561857
if (size <= 0) {
18571858
// unsized unbased const
18581859
c->is_unsized = true;
@@ -2914,7 +2915,7 @@ void UhdmAst::process_enum_typespec()
29142915
}
29152916
if (current_node->str.empty()) {
29162917
// anonymous typespec
2917-
std::string typedef_name = "$systemverilog_plugin$anonymous_enum" + std::to_string(shared.next_anonymous_enum_typedef_id());
2918+
std::string typedef_name = "$synlig$anonymous_enum" + std::to_string(shared.next_anonymous_enum_typedef_id());
29182919
current_node->str = typedef_name;
29192920
uhdmast_assert(shared.current_top_node != nullptr);
29202921
move_type_to_new_typedef(shared.current_top_node, current_node);
@@ -3993,7 +3994,7 @@ void UhdmAst::process_stream_op()
39933994
// Get a prefix for internal identifiers.
39943995
const auto stream_op_id = shared.next_loop_id();
39953996
const auto make_id_str = [stream_op_id](const char *suffix) {
3996-
return std::string("$systemverilog_plugin$stream_op_") + std::to_string(stream_op_id) + "_" + suffix;
3997+
return std::string("$synlig$stream_op_") + std::to_string(stream_op_id) + "_" + suffix;
39973998
};
39983999

39994000
if (is_proc_ctx) {
@@ -5771,4 +5772,4 @@ void UhdmAst::report_error(const char *format, ...) const
57715772
}
57725773
}
57735774

5774-
} // namespace systemverilog_plugin
5775+
} // namespace Synlig

Diff for: ‎src/frontends/systemverilog/uhdm_ast.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
#include <memory>
1010
#include <uhdm/uhdm.h>
1111

12-
namespace systemverilog_plugin
12+
namespace Synlig
1313
{
1414

1515
class AstNodeBuilder;
@@ -330,6 +330,6 @@ class AstNodeBuilder
330330
operator std::unique_ptr<AstNode>() { return std::move(node); }
331331
};
332332

333-
} // namespace systemverilog_plugin
333+
} // namespace Synlig
334334

335335
#endif

Diff for: ‎src/frontends/systemverilog/uhdm_ast_frontend.cc

+2-2
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
#include "uhdm/vpi_visitor.h" // visit_object
2222
#include "uhdm_common_frontend.h"
2323

24-
namespace systemverilog_plugin
24+
namespace Synlig
2525
{
2626

2727
using namespace ::Yosys;
@@ -60,4 +60,4 @@ struct UhdmAstFrontend : public UhdmCommonFrontend {
6060
void call_log_header(RTLIL::Design *design) override { log_header(design, "Executing UHDM frontend.\n"); }
6161
} UhdmAstFrontend;
6262

63-
} // namespace systemverilog_plugin
63+
} // namespace Synlig

Diff for: ‎src/frontends/systemverilog/uhdm_ast_shared.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include <uhdm/vpi_user.h>
1313
#include <unordered_map>
1414

15-
namespace systemverilog_plugin
15+
namespace Synlig
1616
{
1717

1818
class UhdmAstShared
@@ -106,6 +106,6 @@ class UhdmAstShared
106106
std::unordered_map<std::string, std::unordered_map<const UHDM::enum_typespec *, std::string>> anonymous_enums;
107107
};
108108

109-
} // namespace systemverilog_plugin
109+
} // namespace Synlig
110110

111111
#endif

Diff for: ‎src/frontends/systemverilog/uhdm_common_frontend.cc

+2-2
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, boo
3535
} // namespace Yosys
3636
#endif
3737

38-
namespace systemverilog_plugin
38+
namespace Synlig
3939
{
4040

4141
using namespace ::Yosys;
@@ -194,4 +194,4 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
194194
}
195195
}
196196

197-
} // namespace systemverilog_plugin
197+
} // namespace Synlig

Diff for: ‎src/frontends/systemverilog/uhdm_common_frontend.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
#include <type_traits>
2727
#include <vector>
2828

29-
namespace systemverilog_plugin
29+
namespace Synlig
3030
{
3131

3232
// FIXME (mglb): temporary fix to support UHDM both before and after the following change:
@@ -57,4 +57,4 @@ struct UhdmCommonFrontend : public ::Yosys::Frontend {
5757
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, ::Yosys::RTLIL::Design *design);
5858
};
5959

60-
} // namespace systemverilog_plugin
60+
} // namespace Synlig

Diff for: ‎src/frontends/systemverilog/uhdm_surelog_ast_frontend.cc

+2-2
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@
4040
#include "uhdm/uhdm-version.h" // UHDM_VERSION define
4141
#include "uhdm/vpi_visitor.h" // visit_object
4242

43-
namespace systemverilog_plugin
43+
namespace Synlig
4444
{
4545

4646
using namespace ::Yosys;
@@ -399,4 +399,4 @@ struct SystemVerilogDefines : public Pass {
399399
}
400400
} SystemVerilogDefines;
401401

402-
} // namespace systemverilog_plugin
402+
} // namespace Synlig

Diff for: ‎src/frontends/systemverilog/utils/memory.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#include <cassert>
55
#include <utility>
66

7-
namespace systemverilog_plugin
7+
namespace Synlig
88
{
99

1010
// `std::default_delete` equivalent for any range of pointers, e.g. `std::vector<Object *>`.
@@ -190,6 +190,6 @@ inline unique_resource<Resource, Deleter> make_unique_resource(Tn &&...arg_n)
190190
return unique_resource<Resource, Deleter>(Resource(std::forward<Tn>(arg_n)...));
191191
}
192192

193-
} // namespace systemverilog_plugin
193+
} // namespace Synlig
194194

195195
#endif // SYSTEMVERILOG_PLUGIN_UTILS_MEMORY_H_

Diff for: ‎src/mods/yosys_ast/README

+4-4
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,14 @@ Copied files, their sources, changes & notes:
99
- Changes:
1010
- C++ includes adapted to not rely on `verilog_frontend.h` file.
1111
- Removed Yosys namespace; `const2ast()` has been placed inside
12-
`systemverilog_plugin` namespace to avoid conflicts with the symbol from
12+
`Synlig` namespace to avoid conflicts with the symbol from
1313
Yosys when statically linking.
1414
- Renamed to synlig_const2ast.cc to prevent GDB breakpoint aliasing from one
1515
file to the other original file
1616
- synlig_simplify.cc: yosys/frontends/ast/simplify.cc (rev. ceef00c)
17-
- The file is a part of Yosys AST frontend. It has been placed in the plugin,
17+
- The file is a part of Yosys AST frontend. It has been placed in Synlig,
1818
as in some cases we need to adjust it to support certain functionalities
19-
in the plugin. Since it is included now in the plugin, we can skip caling
19+
in Synlig. Since it is included now in the plugin, we can skip caling
2020
the original Yosys' simplify() during AST preparation. The original Yosys'
2121
simplify() is only called in uhdmcommonfrontend.cc when Yosys' process()
2222
is called, after having AST done.
@@ -36,4 +36,4 @@ Non-copied files placed here for interfacing purposes:
3636

3737
- const2ast.h
3838
- simplify.h
39-
- edif.h
39+
- edif.h

Diff for: ‎src/mods/yosys_ast/synlig_const2ast.cc

+1-1
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ static void synlig_strtobin(std::vector<RTLIL::State> &data, const char *str, in
153153
}
154154

155155
// convert the Verilog code for a constant to an AST node
156-
AstNode *systemverilog_plugin::synlig_const2ast(std::string code, char case_type, bool warn_z)
156+
AstNode *Synlig::synlig_const2ast(std::string code, char case_type, bool warn_z)
157157
{
158158
if (warn_z) {
159159
AstNode *ret = synlig_const2ast(code, case_type);

Diff for: ‎src/mods/yosys_ast/synlig_const2ast.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
#include "frontends/ast/ast.h"
55
#include <string>
66

7-
namespace systemverilog_plugin
7+
namespace Synlig
88
{
99
// this function converts a Verilog constant to an AST_CONSTANT node
1010
Yosys::AST::AstNode *synlig_const2ast(std::string code, char case_type = 0, bool warn_z = false);
11-
} // namespace systemverilog_plugin
11+
} // namespace Synlig
1212

1313
#endif // SYSTEMVERILOG_PLUGIN_CONST2AST_H

Diff for: ‎src/mods/yosys_ast/synlig_edif.cc

+2-2
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
#include "kernel/sigtools.h"
2828
#include <string>
2929

30-
namespace systemverilog_plugin
30+
namespace Synlig
3131
{
3232

3333
using namespace ::Yosys;
@@ -618,4 +618,4 @@ void register_synlig_edif_backend()
618618
seb->init_register();
619619
}
620620

621-
} // namespace systemverilog_plugin
621+
} // namespace Synlig

Diff for: ‎src/mods/yosys_ast/synlig_edif.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
namespace systemverilog_plugin
1+
namespace Synlig
22
{
33
void register_synlig_edif_backend();
44
}

Diff for: ‎src/mods/yosys_ast/synlig_simplify.cc

+5-5
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ extern bool sv_mode;
4545
}
4646
YOSYS_NAMESPACE_END
4747

48-
namespace systemverilog_plugin
48+
namespace Synlig
4949
{
5050

5151
using namespace ::Yosys;
@@ -2579,7 +2579,7 @@ bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zer
25792579
int source_width = ast_node->children[0]->id2ast->range_left - ast_node->children[0]->id2ast->range_right + 1;
25802580
int source_offset = ast_node->children[0]->id2ast->range_right;
25812581
int result_width = 1;
2582-
Yosys::AST::AstNode *member_node = systemverilog_plugin::synlig_get_struct_member(ast_node->children[0]);
2582+
Yosys::AST::AstNode *member_node = Synlig::synlig_get_struct_member(ast_node->children[0]);
25832583
if (member_node) {
25842584
// Clamp chunk to range of member within struct/union.
25852585
log_assert(!source_offset && !ast_node->children[0]->id2ast->range_swapped);
@@ -3359,7 +3359,7 @@ skip_dynamic_range_lvalue_expansion:;
33593359
buf->str.c_str());
33603360

33613361
// Check for item in packed struct / union
3362-
Yosys::AST::AstNode *item_node = systemverilog_plugin::synlig_get_struct_member(buf);
3362+
Yosys::AST::AstNode *item_node = Synlig::synlig_get_struct_member(buf);
33633363
if (id_ast->type == Yosys::AST::AST_WIRE && item_node) {
33643364
// The dimension of the original array expression is saved in the 'integer' field
33653365
dim += buf->integer;
@@ -4082,7 +4082,7 @@ replace_fcall_later:;
40824082
tmp_range_left = (param_width + 2 * param_offset) - ast_node->children[0]->range_right - 1;
40834083
tmp_range_right = (param_width + 2 * param_offset) - ast_node->children[0]->range_left - 1;
40844084
}
4085-
Yosys::AST::AstNode *member_node = systemverilog_plugin::synlig_get_struct_member(ast_node);
4085+
Yosys::AST::AstNode *member_node = Synlig::synlig_get_struct_member(ast_node);
40864086
int chunk_offset = member_node ? member_node->range_right : 0;
40874087
log_assert(!(chunk_offset && param_upto));
40884088
for (int i = tmp_range_right; i <= tmp_range_left; i++) {
@@ -4478,4 +4478,4 @@ replace_fcall_later:;
44784478
return did_something;
44794479
}
44804480

4481-
} // namespace systemverilog_plugin
4481+
} // namespace Synlig

Diff for: ‎src/mods/yosys_ast/synlig_simplify.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
#include "frontends/ast/ast.h"
22

3-
namespace systemverilog_plugin
3+
namespace Synlig
44
{
55
using ys_size_type = int; // Makes it easy to change if changed upstream.
66
bool synlig_simplify(Yosys::AST::AstNode *ast_node, bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint,
77
bool in_param);
88
void synlig_expand_genblock(Yosys::AST::AstNode *current_node, std::string prefix, bool only_resolve_scope);
9-
} // namespace systemverilog_plugin
9+
} // namespace Synlig

Diff for: ‎tests/formal/README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ A table below presents example for [results.py](results.py) script generated on
4040
| FAIL | 23 | formally not equivalent |
4141
| SKIP | 4 | not executed |
4242
| YOSYS_READ_FAIL | 58 | yosys couldn't read design |
43-
| PLUGIN_READ_FAIL | 4 | synlig couldn't read design |
43+
| SYNLIG_READ_FAIL | 4 | synlig couldn't read design |
4444
| EMPTY_MODULE | 5 | synlig or yosys produced empty module |
4545
| UNMATCHED_MODULE | 13 | different module names or count was produced |
4646
|NOTHING_TO_COMPARE | 6 | there is nothing to compare in designs |

Diff for: ‎tests/formal/results.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
"FAIL": "formally not equivalent",
1313
"SKIP": "not executed",
1414
"YOSYS_READ_FAIL": "yosys couldn't read design",
15-
"PLUGIN_READ_FAIL": "synlig couldn't read design",
15+
"SYNLIG_READ_FAIL": "synlig couldn't read design",
1616
"EMPTY_MODULE": "synlig or yosys produced empty module",
1717
"UNMATCHED_MODULE": "different module names or count was produced",
1818
"NOTHING_TO_COMPARE": "there is nothing to compare in designs",
@@ -70,7 +70,7 @@ def main():
7070
expected_result = performed_tests_summary[test]["expected_result"]
7171
performed_result = performed_tests_summary[test]["result"]
7272
if expected_result != performed_result:
73-
if not (expected_result == "READ_FAIL" and performed_result in {"YOSYS_READ_FAIL", "PLUGIN_READ_FAIL"}):
73+
if not (expected_result == "READ_FAIL" and performed_result in {"YOSYS_READ_FAIL", "SYNLIG_READ_FAIL"}):
7474
results_different_then_expected.append((
7575
test,
7676
performed_result,

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