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Introduce a compatibility layer for Yosys::AST::process (#2357)
This uses a weak symbol which allows us to build and link with Yosys before and after the API change. Ref: #2300
2 parents fe8f61f + e5358ed commit d844d8d

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+47
-5
lines changed

2 files changed

+47
-5
lines changed

Diff for: frontends/systemverilog/compat_symbols.cc

+17
Original file line numberDiff line numberDiff line change
@@ -8,4 +8,21 @@ YOSYS_NAMESPACE_BEGIN
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#include "kernel/constids.inc"
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#undef X
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#ifdef __linux__
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namespace AST
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{
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extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
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bool, bool, bool);
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void __attribute__((weak))
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process(RTLIL::Design *design, AST::AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
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bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires,
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bool nooverwrite, bool overwrite, bool defer, bool autowire)
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{
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process(design, ast, false, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, nolatches, nomeminit, nomem2reg, mem2reg,
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noblackbox, lib, nowb, noopt, icells, pwires, nooverwrite, overwrite, defer, autowire);
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}
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} // namespace AST
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#endif
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YOSYS_NAMESPACE_END

Diff for: frontends/systemverilog/uhdm_common_frontend.cc

+30-5
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,20 @@
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#include "uhdm_common_frontend.h"
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#include "synlig_edif.h"
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#ifdef __linux__
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namespace Yosys
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{
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using AST::AstNode;
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using RTLIL::Design;
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namespace AST
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{
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extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
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bool, bool);
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} // namespace AST
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} // namespace Yosys
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#endif
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namespace systemverilog_plugin
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{
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@@ -145,14 +159,25 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
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AST::set_line_num = &set_line_num;
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AST::get_line_num = &get_line_num;
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bool dont_redefine = false;
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bool default_nettype_wire = true;
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AST::AstNode *current_ast = parse(filename);
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if (current_ast) {
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AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false,
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false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire);
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Yosys::AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil,
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false, // nolatches
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false, // nomeminit
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false, // nomem2reg
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false, // mem2reg
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false, // noblackbox
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false, // lib
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false, // nowb
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false, // noopt
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false, // icells
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false, // pwires
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false, // nooverwrite
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false, // overwrite
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defer, // defer
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true // autowire
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);
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delete current_ast;
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}
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}

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