[rtl] support zvk

Author: Lucas-Wye

configgen/generated/blastoise.json

@@ -167,7 +167,8 @@
           ]
         ]
       ],
-      "zvbbModuleParameters": []
+      "zvbbModuleParameters": [],
+      "zvkModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"

configgen/generated/machamp.json

@@ -151,7 +151,8 @@
         ]
       ],
       "floatModuleParameters": [],
-      "zvbbModuleParameters": []
+      "zvbbModuleParameters": [],
+      "zvkModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"

configgen/generated/psyduck.json

@@ -4,7 +4,8 @@
     "dLen": 256,
     "extensions": [
       "Zve32f",
-      "Zvbb"
+      "Zvbb",
+      "Zvk"
     ],
     "t1customInstructions": [],
     "vrfBankSize": 1,
@@ -184,6 +185,23 @@
             3
           ]
         ]
+      ],
+      "zvkModuleParameters": [
+        [
+          {
+            "parameter": {
+              "datapathWidth": 32,
+              "latency": 3
+            },
+            "generator": "org.chipsalliance.t1.rtl.LaneZvk"
+          },
+          [
+            0,
+            1,
+            2,
+            3
+          ]
+        ]
       ]
     }
   },

configgen/generated/sandslash.json

@@ -151,7 +151,8 @@
         ]
       ],
       "floatModuleParameters": [],
-      "zvbbModuleParameters": []
+      "zvbbModuleParameters": [],
+      "zvkModuleParameters": []
     }
   },
   "generator": "org.chipsalliance.t1.rtl.T1"

configgen/src/Main.scala

@@ -100,14 +100,15 @@ object Main {
             Seq(0, 1, 2, 3))),
         floatModuleParameters =
           Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))),
-        zvbbModuleParameters = Seq()
+        zvbbModuleParameters = Seq(),
+        zvkModuleParameters = Seq(),
       )
     )
     if (doEmit) param.emit(targetFile)
     param
   }
 
-  // DLEN256 VLEN256;   FP; VRF p0rw,p1rw bank1; LSU bank8  beatbyte 8; Zvbb
+  // DLEN256 VLEN256;   FP; VRF p0rw,p1rw bank1; LSU bank8  beatbyte 8; Zvbb; Zvk
   @main def psyduck(
     @arg(name = "target-file", short = 't') targetFile:             os.Path,
     @arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true
@@ -117,7 +118,7 @@ object Main {
     val param = T1Parameter(
       vLen,
       dLen,
-      extensions = Seq("Zve32f", "Zvbb"),
+      extensions = Seq("Zve32f", "Zvbb", "Zvk"),
       t1customInstructions = Nil,
       vrfBankSize = 1,
       vrfRamType = RamType.p0rwp1rw,
@@ -151,7 +152,9 @@ object Main {
         floatModuleParameters =
           Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))),
         zvbbModuleParameters =
-          Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3)))
+          Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3))),
+        zvkModuleParameters =
+          Seq((SerializableModuleGenerator(classOf[LaneZvk], LaneZvkParam(32, 3)), Seq(0, 1, 2, 3))),
       )
     )
     if (doEmit) param.emit(targetFile)
@@ -201,7 +204,8 @@ object Main {
             ),
             Seq(0, 1, 2, 3))),
         floatModuleParameters = Seq(),
-        zvbbModuleParameters = Seq() // TODO
+        zvbbModuleParameters = Seq(),
+        zvkModuleParameters = Seq(),
       )
     )
     if (doEmit) param.emit(targetFile)
@@ -251,7 +255,8 @@ object Main {
             ),
             Seq(0, 1, 2, 3))),
         floatModuleParameters = Seq(),
-        zvbbModuleParameters = Seq() // TODO
+        zvbbModuleParameters = Seq(),
+        zvkModuleParameters = Seq(),
       )
     )
     if (doEmit) param.emit(targetFile)

ipemu/src/TestBench.scala

@@ -253,7 +253,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
         laneProbes.flatMap(laneProbe =>
           laneProbe.slots.map(slot => slot.writeTag === tag.U && slot.writeQueueEnq && slot.writeMask.orR)
         ) ++ laneProbes.flatMap(laneProbe =>
-          laneProbe.crossWriteProbe.map(cp => cp.bits.writeTag === tag.U && cp.valid && cp.bits.writeMask.orR)
+          laneProbe.crossWriteProbe.map(cp => cp.bits.writeTag === tag.U && cp.valid && cp.bits.writeMask.orR) // TODO: zvkCrossWriteProbe
         ) ++
           // vrf write from lsu
           lsuProbe.slots.map(slot => slot.dataInstruction === tag.U && slot.writeValid && slot.dataMask.orR) ++

t1/src/Bundles.scala

@@ -621,6 +621,7 @@ class ExecutionUnitRecord(parameter: LaneParameter)(isLastSlot: Boolean) extends
   val executeIndex: Bool = Bool()
   val source: Vec[UInt] = Vec(3, UInt(parameter.datapathWidth.W))
   val crossReadSource: Option[UInt] = Option.when(isLastSlot)(UInt((parameter.datapathWidth * 2).W))
+  val zvkCrossReadSource: Option[UInt] = Option.when(isLastSlot && parameter.zvkEnable)(UInt((parameter.datapathWidth * 4).W))
   /** groupCounter need use to update `Lane.maskFormatResultForGroup` */
   val groupCounter: UInt = UInt(parameter.groupNumberBits.W)
   val sSendResponse: Option[Bool] = Option.when(isLastSlot)(Bool())
@@ -725,4 +726,4 @@ class T1Retire(xLen: Int) extends Bundle {
   val rd:  ValidIO[T1RdRetire] = Valid(new T1RdRetire(xLen))
   val csr: ValidIO[T1CSRRetire] = Valid(new T1CSRRetire)
   val mem: ValidIO[EmptyBundle] = Valid(new EmptyBundle)
-}
+}