From 22428c1337071327aa6760bd3d9da58c1ca1cf63 Mon Sep 17 00:00:00 2001
From: unlsycn <unlsycn@unlsycn.com>
Date: Fri, 29 Nov 2024 16:32:16 +0000
Subject: [PATCH] use HasExtModuleInline

---
 t1/src/SRAM.scala | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/t1/src/SRAM.scala b/t1/src/SRAM.scala
index de80e31a3..35fc84930 100644
--- a/t1/src/SRAM.scala
+++ b/t1/src/SRAM.scala
@@ -11,8 +11,11 @@ import chisel3.util.{log2Ceil, MemoryFile, SRAMDescription, SRAMInterface}
 import firrtl.transforms.BlackBoxInlineAnno
 import chisel3.experimental.ChiselAnnotation
 import chisel3.experimental.hierarchy.core.Hierarchy.HierarchyBaseModuleExtensions
+import chisel3.util.HasExtModuleInline
 
-class SRAMBlackbox(parameter: CIRCTSRAMParameter) extends FixedIOExtModule(new CIRCTSRAMInterface(parameter)) { self =>
+class SRAMBlackbox(parameter: CIRCTSRAMParameter)
+    extends FixedIOExtModule(new CIRCTSRAMInterface(parameter))
+    with HasExtModuleInline { self =>
 
   private val verilogInterface: String =
     (Seq.tabulate(parameter.write)(idx =>
@@ -112,19 +115,14 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter) extends FixedIOExtModule(new C
 
   override def desiredName = parameter.moduleName
 
-  chisel3.experimental.annotate(
-    new ChiselAnnotation {
-      def toFirrtl = new BlackBoxInlineAnno(
-        self.toNamed,
-        parameter.moduleName,
-        s"""module ${parameter.moduleName}(
-           |${verilogInterface}
-           |);
-           |${logic}
-           |endmodule
-           |""".stripMargin
-      )
-    }
+  setInline(
+    desiredName,
+    s"""module ${parameter.moduleName}(
+       |${verilogInterface}
+       |);
+       |${logic}
+       |endmodule
+       |""".stripMargin
   )
 }